ehci-hcd.c 31 KB

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  1. /*
  2. * Copyright (c) 2000-2004 by David Brownell
  3. *
  4. * This program is free software; you can redistribute it and/or modify it
  5. * under the terms of the GNU General Public License as published by the
  6. * Free Software Foundation; either version 2 of the License, or (at your
  7. * option) any later version.
  8. *
  9. * This program is distributed in the hope that it will be useful, but
  10. * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  11. * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  12. * for more details.
  13. *
  14. * You should have received a copy of the GNU General Public License
  15. * along with this program; if not, write to the Free Software Foundation,
  16. * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  17. */
  18. #include <linux/module.h>
  19. #include <linux/pci.h>
  20. #include <linux/dmapool.h>
  21. #include <linux/kernel.h>
  22. #include <linux/delay.h>
  23. #include <linux/ioport.h>
  24. #include <linux/sched.h>
  25. #include <linux/slab.h>
  26. #include <linux/vmalloc.h>
  27. #include <linux/errno.h>
  28. #include <linux/init.h>
  29. #include <linux/timer.h>
  30. #include <linux/list.h>
  31. #include <linux/interrupt.h>
  32. #include <linux/reboot.h>
  33. #include <linux/usb.h>
  34. #include <linux/moduleparam.h>
  35. #include <linux/dma-mapping.h>
  36. #include <linux/debugfs.h>
  37. #include "../core/hcd.h"
  38. #include <asm/byteorder.h>
  39. #include <asm/io.h>
  40. #include <asm/irq.h>
  41. #include <asm/system.h>
  42. #include <asm/unaligned.h>
  43. /*-------------------------------------------------------------------------*/
  44. /*
  45. * EHCI hc_driver implementation ... experimental, incomplete.
  46. * Based on the final 1.0 register interface specification.
  47. *
  48. * USB 2.0 shows up in upcoming www.pcmcia.org technology.
  49. * First was PCMCIA, like ISA; then CardBus, which is PCI.
  50. * Next comes "CardBay", using USB 2.0 signals.
  51. *
  52. * Contains additional contributions by Brad Hards, Rory Bolt, and others.
  53. * Special thanks to Intel and VIA for providing host controllers to
  54. * test this driver on, and Cypress (including In-System Design) for
  55. * providing early devices for those host controllers to talk to!
  56. */
  57. #define DRIVER_AUTHOR "David Brownell"
  58. #define DRIVER_DESC "USB 2.0 'Enhanced' Host Controller (EHCI) Driver"
  59. static const char hcd_name [] = "ehci_hcd";
  60. #undef VERBOSE_DEBUG
  61. #undef EHCI_URB_TRACE
  62. #ifdef DEBUG
  63. #define EHCI_STATS
  64. #endif
  65. /* magic numbers that can affect system performance */
  66. #define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */
  67. #define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */
  68. #define EHCI_TUNE_RL_TT 0
  69. #define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */
  70. #define EHCI_TUNE_MULT_TT 1
  71. #define EHCI_TUNE_FLS 2 /* (small) 256 frame schedule */
  72. #define EHCI_IAA_MSECS 10 /* arbitrary */
  73. #define EHCI_IO_JIFFIES (HZ/10) /* io watchdog > irq_thresh */
  74. #define EHCI_ASYNC_JIFFIES (HZ/20) /* async idle timeout */
  75. #define EHCI_SHRINK_FRAMES 5 /* async qh unlink delay */
  76. /* Initial IRQ latency: faster than hw default */
  77. static int log2_irq_thresh = 0; // 0 to 6
  78. module_param (log2_irq_thresh, int, S_IRUGO);
  79. MODULE_PARM_DESC (log2_irq_thresh, "log2 IRQ latency, 1-64 microframes");
  80. /* initial park setting: slower than hw default */
  81. static unsigned park = 0;
  82. module_param (park, uint, S_IRUGO);
  83. MODULE_PARM_DESC (park, "park setting; 1-3 back-to-back async packets");
  84. /* for flakey hardware, ignore overcurrent indicators */
  85. static int ignore_oc = 0;
  86. module_param (ignore_oc, bool, S_IRUGO);
  87. MODULE_PARM_DESC (ignore_oc, "ignore bogus hardware overcurrent indications");
  88. #define INTR_MASK (STS_IAA | STS_FATAL | STS_PCD | STS_ERR | STS_INT)
  89. /*-------------------------------------------------------------------------*/
  90. #include "ehci.h"
  91. #include "ehci-dbg.c"
  92. /*-------------------------------------------------------------------------*/
  93. /*
  94. * handshake - spin reading hc until handshake completes or fails
  95. * @ptr: address of hc register to be read
  96. * @mask: bits to look at in result of read
  97. * @done: value of those bits when handshake succeeds
  98. * @usec: timeout in microseconds
  99. *
  100. * Returns negative errno, or zero on success
  101. *
  102. * Success happens when the "mask" bits have the specified value (hardware
  103. * handshake done). There are two failure modes: "usec" have passed (major
  104. * hardware flakeout), or the register reads as all-ones (hardware removed).
  105. *
  106. * That last failure should_only happen in cases like physical cardbus eject
  107. * before driver shutdown. But it also seems to be caused by bugs in cardbus
  108. * bridge shutdown: shutting down the bridge before the devices using it.
  109. */
  110. static int handshake (struct ehci_hcd *ehci, void __iomem *ptr,
  111. u32 mask, u32 done, int usec)
  112. {
  113. u32 result;
  114. do {
  115. result = ehci_readl(ehci, ptr);
  116. if (result == ~(u32)0) /* card removed */
  117. return -ENODEV;
  118. result &= mask;
  119. if (result == done)
  120. return 0;
  121. udelay (1);
  122. usec--;
  123. } while (usec > 0);
  124. return -ETIMEDOUT;
  125. }
  126. /* force HC to halt state from unknown (EHCI spec section 2.3) */
  127. static int ehci_halt (struct ehci_hcd *ehci)
  128. {
  129. u32 temp = ehci_readl(ehci, &ehci->regs->status);
  130. /* disable any irqs left enabled by previous code */
  131. ehci_writel(ehci, 0, &ehci->regs->intr_enable);
  132. if ((temp & STS_HALT) != 0)
  133. return 0;
  134. temp = ehci_readl(ehci, &ehci->regs->command);
  135. temp &= ~CMD_RUN;
  136. ehci_writel(ehci, temp, &ehci->regs->command);
  137. return handshake (ehci, &ehci->regs->status,
  138. STS_HALT, STS_HALT, 16 * 125);
  139. }
  140. static int handshake_on_error_set_halt(struct ehci_hcd *ehci, void __iomem *ptr,
  141. u32 mask, u32 done, int usec)
  142. {
  143. int error;
  144. error = handshake(ehci, ptr, mask, done, usec);
  145. if (error) {
  146. ehci_halt(ehci);
  147. ehci_to_hcd(ehci)->state = HC_STATE_HALT;
  148. ehci_err(ehci, "force halt; handhake %p %08x %08x -> %d\n",
  149. ptr, mask, done, error);
  150. }
  151. return error;
  152. }
  153. /* put TDI/ARC silicon into EHCI mode */
  154. static void tdi_reset (struct ehci_hcd *ehci)
  155. {
  156. u32 __iomem *reg_ptr;
  157. u32 tmp;
  158. reg_ptr = (u32 __iomem *)(((u8 __iomem *)ehci->regs) + USBMODE);
  159. tmp = ehci_readl(ehci, reg_ptr);
  160. tmp |= USBMODE_CM_HC;
  161. /* The default byte access to MMR space is LE after
  162. * controller reset. Set the required endian mode
  163. * for transfer buffers to match the host microprocessor
  164. */
  165. if (ehci_big_endian_mmio(ehci))
  166. tmp |= USBMODE_BE;
  167. ehci_writel(ehci, tmp, reg_ptr);
  168. }
  169. /* reset a non-running (STS_HALT == 1) controller */
  170. static int ehci_reset (struct ehci_hcd *ehci)
  171. {
  172. int retval;
  173. u32 command = ehci_readl(ehci, &ehci->regs->command);
  174. command |= CMD_RESET;
  175. dbg_cmd (ehci, "reset", command);
  176. ehci_writel(ehci, command, &ehci->regs->command);
  177. ehci_to_hcd(ehci)->state = HC_STATE_HALT;
  178. ehci->next_statechange = jiffies;
  179. retval = handshake (ehci, &ehci->regs->command,
  180. CMD_RESET, 0, 250 * 1000);
  181. if (retval)
  182. return retval;
  183. if (ehci_is_TDI(ehci))
  184. tdi_reset (ehci);
  185. return retval;
  186. }
  187. /* idle the controller (from running) */
  188. static void ehci_quiesce (struct ehci_hcd *ehci)
  189. {
  190. u32 temp;
  191. #ifdef DEBUG
  192. if (!HC_IS_RUNNING (ehci_to_hcd(ehci)->state))
  193. BUG ();
  194. #endif
  195. /* wait for any schedule enables/disables to take effect */
  196. temp = ehci_readl(ehci, &ehci->regs->command) << 10;
  197. temp &= STS_ASS | STS_PSS;
  198. if (handshake_on_error_set_halt(ehci, &ehci->regs->status,
  199. STS_ASS | STS_PSS, temp, 16 * 125))
  200. return;
  201. /* then disable anything that's still active */
  202. temp = ehci_readl(ehci, &ehci->regs->command);
  203. temp &= ~(CMD_ASE | CMD_IAAD | CMD_PSE);
  204. ehci_writel(ehci, temp, &ehci->regs->command);
  205. /* hardware can take 16 microframes to turn off ... */
  206. handshake_on_error_set_halt(ehci, &ehci->regs->status,
  207. STS_ASS | STS_PSS, 0, 16 * 125);
  208. }
  209. /*-------------------------------------------------------------------------*/
  210. static void end_unlink_async(struct ehci_hcd *ehci);
  211. static void ehci_work(struct ehci_hcd *ehci);
  212. #include "ehci-hub.c"
  213. #include "ehci-mem.c"
  214. #include "ehci-q.c"
  215. #include "ehci-sched.c"
  216. /*-------------------------------------------------------------------------*/
  217. static void ehci_iaa_watchdog(unsigned long param)
  218. {
  219. struct ehci_hcd *ehci = (struct ehci_hcd *) param;
  220. unsigned long flags;
  221. spin_lock_irqsave (&ehci->lock, flags);
  222. /* Lost IAA irqs wedge things badly; seen first with a vt8235.
  223. * So we need this watchdog, but must protect it against both
  224. * (a) SMP races against real IAA firing and retriggering, and
  225. * (b) clean HC shutdown, when IAA watchdog was pending.
  226. */
  227. if (ehci->reclaim
  228. && !timer_pending(&ehci->iaa_watchdog)
  229. && HC_IS_RUNNING(ehci_to_hcd(ehci)->state)) {
  230. u32 cmd, status;
  231. /* If we get here, IAA is *REALLY* late. It's barely
  232. * conceivable that the system is so busy that CMD_IAAD
  233. * is still legitimately set, so let's be sure it's
  234. * clear before we read STS_IAA. (The HC should clear
  235. * CMD_IAAD when it sets STS_IAA.)
  236. */
  237. cmd = ehci_readl(ehci, &ehci->regs->command);
  238. if (cmd & CMD_IAAD)
  239. ehci_writel(ehci, cmd & ~CMD_IAAD,
  240. &ehci->regs->command);
  241. /* If IAA is set here it either legitimately triggered
  242. * before we cleared IAAD above (but _way_ late, so we'll
  243. * still count it as lost) ... or a silicon erratum:
  244. * - VIA seems to set IAA without triggering the IRQ;
  245. * - IAAD potentially cleared without setting IAA.
  246. */
  247. status = ehci_readl(ehci, &ehci->regs->status);
  248. if ((status & STS_IAA) || !(cmd & CMD_IAAD)) {
  249. COUNT (ehci->stats.lost_iaa);
  250. ehci_writel(ehci, STS_IAA, &ehci->regs->status);
  251. }
  252. ehci_vdbg(ehci, "IAA watchdog: status %x cmd %x\n",
  253. status, cmd);
  254. end_unlink_async(ehci);
  255. }
  256. spin_unlock_irqrestore(&ehci->lock, flags);
  257. }
  258. static void ehci_watchdog(unsigned long param)
  259. {
  260. struct ehci_hcd *ehci = (struct ehci_hcd *) param;
  261. unsigned long flags;
  262. spin_lock_irqsave(&ehci->lock, flags);
  263. /* stop async processing after it's idled a bit */
  264. if (test_bit (TIMER_ASYNC_OFF, &ehci->actions))
  265. start_unlink_async (ehci, ehci->async);
  266. /* ehci could run by timer, without IRQs ... */
  267. ehci_work (ehci);
  268. spin_unlock_irqrestore (&ehci->lock, flags);
  269. }
  270. /* On some systems, leaving remote wakeup enabled prevents system shutdown.
  271. * The firmware seems to think that powering off is a wakeup event!
  272. * This routine turns off remote wakeup and everything else, on all ports.
  273. */
  274. static void ehci_turn_off_all_ports(struct ehci_hcd *ehci)
  275. {
  276. int port = HCS_N_PORTS(ehci->hcs_params);
  277. while (port--)
  278. ehci_writel(ehci, PORT_RWC_BITS,
  279. &ehci->regs->port_status[port]);
  280. }
  281. /*
  282. * Halt HC, turn off all ports, and let the BIOS use the companion controllers.
  283. * Should be called with ehci->lock held.
  284. */
  285. static void ehci_silence_controller(struct ehci_hcd *ehci)
  286. {
  287. ehci_halt(ehci);
  288. ehci_turn_off_all_ports(ehci);
  289. /* make BIOS/etc use companion controller during reboot */
  290. ehci_writel(ehci, 0, &ehci->regs->configured_flag);
  291. /* unblock posted writes */
  292. ehci_readl(ehci, &ehci->regs->configured_flag);
  293. }
  294. /* ehci_shutdown kick in for silicon on any bus (not just pci, etc).
  295. * This forcibly disables dma and IRQs, helping kexec and other cases
  296. * where the next system software may expect clean state.
  297. */
  298. static void ehci_shutdown(struct usb_hcd *hcd)
  299. {
  300. struct ehci_hcd *ehci = hcd_to_ehci(hcd);
  301. del_timer_sync(&ehci->watchdog);
  302. del_timer_sync(&ehci->iaa_watchdog);
  303. spin_lock_irq(&ehci->lock);
  304. ehci_silence_controller(ehci);
  305. spin_unlock_irq(&ehci->lock);
  306. }
  307. static void ehci_port_power (struct ehci_hcd *ehci, int is_on)
  308. {
  309. unsigned port;
  310. if (!HCS_PPC (ehci->hcs_params))
  311. return;
  312. ehci_dbg (ehci, "...power%s ports...\n", is_on ? "up" : "down");
  313. for (port = HCS_N_PORTS (ehci->hcs_params); port > 0; )
  314. (void) ehci_hub_control(ehci_to_hcd(ehci),
  315. is_on ? SetPortFeature : ClearPortFeature,
  316. USB_PORT_FEAT_POWER,
  317. port--, NULL, 0);
  318. /* Flush those writes */
  319. ehci_readl(ehci, &ehci->regs->command);
  320. msleep(20);
  321. }
  322. /*-------------------------------------------------------------------------*/
  323. /*
  324. * ehci_work is called from some interrupts, timers, and so on.
  325. * it calls driver completion functions, after dropping ehci->lock.
  326. */
  327. static void ehci_work (struct ehci_hcd *ehci)
  328. {
  329. timer_action_done (ehci, TIMER_IO_WATCHDOG);
  330. /* another CPU may drop ehci->lock during a schedule scan while
  331. * it reports urb completions. this flag guards against bogus
  332. * attempts at re-entrant schedule scanning.
  333. */
  334. if (ehci->scanning)
  335. return;
  336. ehci->scanning = 1;
  337. scan_async (ehci);
  338. if (ehci->next_uframe != -1)
  339. scan_periodic (ehci);
  340. ehci->scanning = 0;
  341. /* the IO watchdog guards against hardware or driver bugs that
  342. * misplace IRQs, and should let us run completely without IRQs.
  343. * such lossage has been observed on both VT6202 and VT8235.
  344. */
  345. if (HC_IS_RUNNING (ehci_to_hcd(ehci)->state) &&
  346. (ehci->async->qh_next.ptr != NULL ||
  347. ehci->periodic_sched != 0))
  348. timer_action (ehci, TIMER_IO_WATCHDOG);
  349. }
  350. /*
  351. * Called when the ehci_hcd module is removed.
  352. */
  353. static void ehci_stop (struct usb_hcd *hcd)
  354. {
  355. struct ehci_hcd *ehci = hcd_to_ehci (hcd);
  356. ehci_dbg (ehci, "stop\n");
  357. /* no more interrupts ... */
  358. del_timer_sync (&ehci->watchdog);
  359. del_timer_sync(&ehci->iaa_watchdog);
  360. spin_lock_irq(&ehci->lock);
  361. if (HC_IS_RUNNING (hcd->state))
  362. ehci_quiesce (ehci);
  363. ehci_silence_controller(ehci);
  364. ehci_reset (ehci);
  365. spin_unlock_irq(&ehci->lock);
  366. remove_companion_file(ehci);
  367. remove_debug_files (ehci);
  368. /* root hub is shut down separately (first, when possible) */
  369. spin_lock_irq (&ehci->lock);
  370. if (ehci->async)
  371. ehci_work (ehci);
  372. spin_unlock_irq (&ehci->lock);
  373. ehci_mem_cleanup (ehci);
  374. #ifdef EHCI_STATS
  375. ehci_dbg (ehci, "irq normal %ld err %ld reclaim %ld (lost %ld)\n",
  376. ehci->stats.normal, ehci->stats.error, ehci->stats.reclaim,
  377. ehci->stats.lost_iaa);
  378. ehci_dbg (ehci, "complete %ld unlink %ld\n",
  379. ehci->stats.complete, ehci->stats.unlink);
  380. #endif
  381. dbg_status (ehci, "ehci_stop completed",
  382. ehci_readl(ehci, &ehci->regs->status));
  383. }
  384. /* one-time init, only for memory state */
  385. static int ehci_init(struct usb_hcd *hcd)
  386. {
  387. struct ehci_hcd *ehci = hcd_to_ehci(hcd);
  388. u32 temp;
  389. int retval;
  390. u32 hcc_params;
  391. spin_lock_init(&ehci->lock);
  392. init_timer(&ehci->watchdog);
  393. ehci->watchdog.function = ehci_watchdog;
  394. ehci->watchdog.data = (unsigned long) ehci;
  395. init_timer(&ehci->iaa_watchdog);
  396. ehci->iaa_watchdog.function = ehci_iaa_watchdog;
  397. ehci->iaa_watchdog.data = (unsigned long) ehci;
  398. /*
  399. * hw default: 1K periodic list heads, one per frame.
  400. * periodic_size can shrink by USBCMD update if hcc_params allows.
  401. */
  402. ehci->periodic_size = DEFAULT_I_TDPS;
  403. if ((retval = ehci_mem_init(ehci, GFP_KERNEL)) < 0)
  404. return retval;
  405. /* controllers may cache some of the periodic schedule ... */
  406. hcc_params = ehci_readl(ehci, &ehci->caps->hcc_params);
  407. if (HCC_ISOC_CACHE(hcc_params)) // full frame cache
  408. ehci->i_thresh = 8;
  409. else // N microframes cached
  410. ehci->i_thresh = 2 + HCC_ISOC_THRES(hcc_params);
  411. ehci->reclaim = NULL;
  412. ehci->next_uframe = -1;
  413. /*
  414. * dedicate a qh for the async ring head, since we couldn't unlink
  415. * a 'real' qh without stopping the async schedule [4.8]. use it
  416. * as the 'reclamation list head' too.
  417. * its dummy is used in hw_alt_next of many tds, to prevent the qh
  418. * from automatically advancing to the next td after short reads.
  419. */
  420. ehci->async->qh_next.qh = NULL;
  421. ehci->async->hw_next = QH_NEXT(ehci, ehci->async->qh_dma);
  422. ehci->async->hw_info1 = cpu_to_hc32(ehci, QH_HEAD);
  423. ehci->async->hw_token = cpu_to_hc32(ehci, QTD_STS_HALT);
  424. ehci->async->hw_qtd_next = EHCI_LIST_END(ehci);
  425. ehci->async->qh_state = QH_STATE_LINKED;
  426. ehci->async->hw_alt_next = QTD_NEXT(ehci, ehci->async->dummy->qtd_dma);
  427. /* clear interrupt enables, set irq latency */
  428. if (log2_irq_thresh < 0 || log2_irq_thresh > 6)
  429. log2_irq_thresh = 0;
  430. temp = 1 << (16 + log2_irq_thresh);
  431. if (HCC_CANPARK(hcc_params)) {
  432. /* HW default park == 3, on hardware that supports it (like
  433. * NVidia and ALI silicon), maximizes throughput on the async
  434. * schedule by avoiding QH fetches between transfers.
  435. *
  436. * With fast usb storage devices and NForce2, "park" seems to
  437. * make problems: throughput reduction (!), data errors...
  438. */
  439. if (park) {
  440. park = min(park, (unsigned) 3);
  441. temp |= CMD_PARK;
  442. temp |= park << 8;
  443. }
  444. ehci_dbg(ehci, "park %d\n", park);
  445. }
  446. if (HCC_PGM_FRAMELISTLEN(hcc_params)) {
  447. /* periodic schedule size can be smaller than default */
  448. temp &= ~(3 << 2);
  449. temp |= (EHCI_TUNE_FLS << 2);
  450. switch (EHCI_TUNE_FLS) {
  451. case 0: ehci->periodic_size = 1024; break;
  452. case 1: ehci->periodic_size = 512; break;
  453. case 2: ehci->periodic_size = 256; break;
  454. default: BUG();
  455. }
  456. }
  457. ehci->command = temp;
  458. return 0;
  459. }
  460. /* start HC running; it's halted, ehci_init() has been run (once) */
  461. static int ehci_run (struct usb_hcd *hcd)
  462. {
  463. struct ehci_hcd *ehci = hcd_to_ehci (hcd);
  464. int retval;
  465. u32 temp;
  466. u32 hcc_params;
  467. hcd->uses_new_polling = 1;
  468. hcd->poll_rh = 0;
  469. /* EHCI spec section 4.1 */
  470. if ((retval = ehci_reset(ehci)) != 0) {
  471. ehci_mem_cleanup(ehci);
  472. return retval;
  473. }
  474. ehci_writel(ehci, ehci->periodic_dma, &ehci->regs->frame_list);
  475. ehci_writel(ehci, (u32)ehci->async->qh_dma, &ehci->regs->async_next);
  476. /*
  477. * hcc_params controls whether ehci->regs->segment must (!!!)
  478. * be used; it constrains QH/ITD/SITD and QTD locations.
  479. * pci_pool consistent memory always uses segment zero.
  480. * streaming mappings for I/O buffers, like pci_map_single(),
  481. * can return segments above 4GB, if the device allows.
  482. *
  483. * NOTE: the dma mask is visible through dma_supported(), so
  484. * drivers can pass this info along ... like NETIF_F_HIGHDMA,
  485. * Scsi_Host.highmem_io, and so forth. It's readonly to all
  486. * host side drivers though.
  487. */
  488. hcc_params = ehci_readl(ehci, &ehci->caps->hcc_params);
  489. if (HCC_64BIT_ADDR(hcc_params)) {
  490. ehci_writel(ehci, 0, &ehci->regs->segment);
  491. #if 0
  492. // this is deeply broken on almost all architectures
  493. if (!dma_set_mask(hcd->self.controller, DMA_64BIT_MASK))
  494. ehci_info(ehci, "enabled 64bit DMA\n");
  495. #endif
  496. }
  497. // Philips, Intel, and maybe others need CMD_RUN before the
  498. // root hub will detect new devices (why?); NEC doesn't
  499. ehci->command &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET);
  500. ehci->command |= CMD_RUN;
  501. ehci_writel(ehci, ehci->command, &ehci->regs->command);
  502. dbg_cmd (ehci, "init", ehci->command);
  503. /*
  504. * Start, enabling full USB 2.0 functionality ... usb 1.1 devices
  505. * are explicitly handed to companion controller(s), so no TT is
  506. * involved with the root hub. (Except where one is integrated,
  507. * and there's no companion controller unless maybe for USB OTG.)
  508. *
  509. * Turning on the CF flag will transfer ownership of all ports
  510. * from the companions to the EHCI controller. If any of the
  511. * companions are in the middle of a port reset at the time, it
  512. * could cause trouble. Write-locking ehci_cf_port_reset_rwsem
  513. * guarantees that no resets are in progress. After we set CF,
  514. * a short delay lets the hardware catch up; new resets shouldn't
  515. * be started before the port switching actions could complete.
  516. */
  517. down_write(&ehci_cf_port_reset_rwsem);
  518. hcd->state = HC_STATE_RUNNING;
  519. ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag);
  520. ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */
  521. msleep(5);
  522. up_write(&ehci_cf_port_reset_rwsem);
  523. temp = HC_VERSION(ehci_readl(ehci, &ehci->caps->hc_capbase));
  524. ehci_info (ehci,
  525. "USB %x.%x started, EHCI %x.%02x%s\n",
  526. ((ehci->sbrn & 0xf0)>>4), (ehci->sbrn & 0x0f),
  527. temp >> 8, temp & 0xff,
  528. ignore_oc ? ", overcurrent ignored" : "");
  529. ehci_writel(ehci, INTR_MASK,
  530. &ehci->regs->intr_enable); /* Turn On Interrupts */
  531. /* GRR this is run-once init(), being done every time the HC starts.
  532. * So long as they're part of class devices, we can't do it init()
  533. * since the class device isn't created that early.
  534. */
  535. create_debug_files(ehci);
  536. create_companion_file(ehci);
  537. return 0;
  538. }
  539. /*-------------------------------------------------------------------------*/
  540. static irqreturn_t ehci_irq (struct usb_hcd *hcd)
  541. {
  542. struct ehci_hcd *ehci = hcd_to_ehci (hcd);
  543. u32 status, pcd_status = 0, cmd;
  544. int bh;
  545. spin_lock (&ehci->lock);
  546. status = ehci_readl(ehci, &ehci->regs->status);
  547. /* e.g. cardbus physical eject */
  548. if (status == ~(u32) 0) {
  549. ehci_dbg (ehci, "device removed\n");
  550. goto dead;
  551. }
  552. status &= INTR_MASK;
  553. if (!status) { /* irq sharing? */
  554. spin_unlock(&ehci->lock);
  555. return IRQ_NONE;
  556. }
  557. /* clear (just) interrupts */
  558. ehci_writel(ehci, status, &ehci->regs->status);
  559. cmd = ehci_readl(ehci, &ehci->regs->command);
  560. bh = 0;
  561. #ifdef VERBOSE_DEBUG
  562. /* unrequested/ignored: Frame List Rollover */
  563. dbg_status (ehci, "irq", status);
  564. #endif
  565. /* INT, ERR, and IAA interrupt rates can be throttled */
  566. /* normal [4.15.1.2] or error [4.15.1.1] completion */
  567. if (likely ((status & (STS_INT|STS_ERR)) != 0)) {
  568. if (likely ((status & STS_ERR) == 0))
  569. COUNT (ehci->stats.normal);
  570. else
  571. COUNT (ehci->stats.error);
  572. bh = 1;
  573. }
  574. /* complete the unlinking of some qh [4.15.2.3] */
  575. if (status & STS_IAA) {
  576. /* guard against (alleged) silicon errata */
  577. if (cmd & CMD_IAAD) {
  578. ehci_writel(ehci, cmd & ~CMD_IAAD,
  579. &ehci->regs->command);
  580. ehci_dbg(ehci, "IAA with IAAD still set?\n");
  581. }
  582. if (ehci->reclaim) {
  583. COUNT(ehci->stats.reclaim);
  584. end_unlink_async(ehci);
  585. } else
  586. ehci_dbg(ehci, "IAA with nothing to reclaim?\n");
  587. }
  588. /* remote wakeup [4.3.1] */
  589. if (status & STS_PCD) {
  590. unsigned i = HCS_N_PORTS (ehci->hcs_params);
  591. /* kick root hub later */
  592. pcd_status = status;
  593. /* resume root hub? */
  594. if (!(cmd & CMD_RUN))
  595. usb_hcd_resume_root_hub(hcd);
  596. while (i--) {
  597. int pstatus = ehci_readl(ehci,
  598. &ehci->regs->port_status [i]);
  599. if (pstatus & PORT_OWNER)
  600. continue;
  601. if (!(test_bit(i, &ehci->suspended_ports) &&
  602. ((pstatus & PORT_RESUME) ||
  603. !(pstatus & PORT_SUSPEND)) &&
  604. (pstatus & PORT_PE) &&
  605. ehci->reset_done[i] == 0))
  606. continue;
  607. /* start 20 msec resume signaling from this port,
  608. * and make khubd collect PORT_STAT_C_SUSPEND to
  609. * stop that signaling.
  610. */
  611. ehci->reset_done [i] = jiffies + msecs_to_jiffies (20);
  612. ehci_dbg (ehci, "port %d remote wakeup\n", i + 1);
  613. mod_timer(&hcd->rh_timer, ehci->reset_done[i]);
  614. }
  615. }
  616. /* PCI errors [4.15.2.4] */
  617. if (unlikely ((status & STS_FATAL) != 0)) {
  618. dbg_cmd(ehci, "fatal", cmd);
  619. dbg_status(ehci, "fatal", status);
  620. if (status & STS_HALT) {
  621. ehci_err (ehci, "fatal error\n");
  622. dead:
  623. ehci_reset (ehci);
  624. ehci_writel(ehci, 0, &ehci->regs->configured_flag);
  625. /* generic layer kills/unlinks all urbs, then
  626. * uses ehci_stop to clean up the rest
  627. */
  628. bh = 1;
  629. }
  630. }
  631. if (bh)
  632. ehci_work (ehci);
  633. spin_unlock (&ehci->lock);
  634. if (pcd_status)
  635. usb_hcd_poll_rh_status(hcd);
  636. return IRQ_HANDLED;
  637. }
  638. /*-------------------------------------------------------------------------*/
  639. /*
  640. * non-error returns are a promise to giveback() the urb later
  641. * we drop ownership so next owner (or urb unlink) can get it
  642. *
  643. * urb + dev is in hcd.self.controller.urb_list
  644. * we're queueing TDs onto software and hardware lists
  645. *
  646. * hcd-specific init for hcpriv hasn't been done yet
  647. *
  648. * NOTE: control, bulk, and interrupt share the same code to append TDs
  649. * to a (possibly active) QH, and the same QH scanning code.
  650. */
  651. static int ehci_urb_enqueue (
  652. struct usb_hcd *hcd,
  653. struct urb *urb,
  654. gfp_t mem_flags
  655. ) {
  656. struct ehci_hcd *ehci = hcd_to_ehci (hcd);
  657. struct list_head qtd_list;
  658. INIT_LIST_HEAD (&qtd_list);
  659. switch (usb_pipetype (urb->pipe)) {
  660. case PIPE_CONTROL:
  661. /* qh_completions() code doesn't handle all the fault cases
  662. * in multi-TD control transfers. Even 1KB is rare anyway.
  663. */
  664. if (urb->transfer_buffer_length > (16 * 1024))
  665. return -EMSGSIZE;
  666. /* FALLTHROUGH */
  667. /* case PIPE_BULK: */
  668. default:
  669. if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags))
  670. return -ENOMEM;
  671. return submit_async(ehci, urb, &qtd_list, mem_flags);
  672. case PIPE_INTERRUPT:
  673. if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags))
  674. return -ENOMEM;
  675. return intr_submit(ehci, urb, &qtd_list, mem_flags);
  676. case PIPE_ISOCHRONOUS:
  677. if (urb->dev->speed == USB_SPEED_HIGH)
  678. return itd_submit (ehci, urb, mem_flags);
  679. else
  680. return sitd_submit (ehci, urb, mem_flags);
  681. }
  682. }
  683. static void unlink_async (struct ehci_hcd *ehci, struct ehci_qh *qh)
  684. {
  685. /* failfast */
  686. if (!HC_IS_RUNNING(ehci_to_hcd(ehci)->state) && ehci->reclaim)
  687. end_unlink_async(ehci);
  688. /* if it's not linked then there's nothing to do */
  689. if (qh->qh_state != QH_STATE_LINKED)
  690. ;
  691. /* defer till later if busy */
  692. else if (ehci->reclaim) {
  693. struct ehci_qh *last;
  694. for (last = ehci->reclaim;
  695. last->reclaim;
  696. last = last->reclaim)
  697. continue;
  698. qh->qh_state = QH_STATE_UNLINK_WAIT;
  699. last->reclaim = qh;
  700. /* start IAA cycle */
  701. } else
  702. start_unlink_async (ehci, qh);
  703. }
  704. /* remove from hardware lists
  705. * completions normally happen asynchronously
  706. */
  707. static int ehci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
  708. {
  709. struct ehci_hcd *ehci = hcd_to_ehci (hcd);
  710. struct ehci_qh *qh;
  711. unsigned long flags;
  712. int rc;
  713. spin_lock_irqsave (&ehci->lock, flags);
  714. rc = usb_hcd_check_unlink_urb(hcd, urb, status);
  715. if (rc)
  716. goto done;
  717. switch (usb_pipetype (urb->pipe)) {
  718. // case PIPE_CONTROL:
  719. // case PIPE_BULK:
  720. default:
  721. qh = (struct ehci_qh *) urb->hcpriv;
  722. if (!qh)
  723. break;
  724. switch (qh->qh_state) {
  725. case QH_STATE_LINKED:
  726. case QH_STATE_COMPLETING:
  727. unlink_async(ehci, qh);
  728. break;
  729. case QH_STATE_UNLINK:
  730. case QH_STATE_UNLINK_WAIT:
  731. /* already started */
  732. break;
  733. case QH_STATE_IDLE:
  734. WARN_ON(1);
  735. break;
  736. }
  737. break;
  738. case PIPE_INTERRUPT:
  739. qh = (struct ehci_qh *) urb->hcpriv;
  740. if (!qh)
  741. break;
  742. switch (qh->qh_state) {
  743. case QH_STATE_LINKED:
  744. intr_deschedule (ehci, qh);
  745. /* FALL THROUGH */
  746. case QH_STATE_IDLE:
  747. qh_completions (ehci, qh);
  748. break;
  749. default:
  750. ehci_dbg (ehci, "bogus qh %p state %d\n",
  751. qh, qh->qh_state);
  752. goto done;
  753. }
  754. /* reschedule QH iff another request is queued */
  755. if (!list_empty (&qh->qtd_list)
  756. && HC_IS_RUNNING (hcd->state)) {
  757. rc = qh_schedule(ehci, qh);
  758. /* An error here likely indicates handshake failure
  759. * or no space left in the schedule. Neither fault
  760. * should happen often ...
  761. *
  762. * FIXME kill the now-dysfunctional queued urbs
  763. */
  764. if (rc != 0)
  765. ehci_err(ehci,
  766. "can't reschedule qh %p, err %d",
  767. qh, rc);
  768. }
  769. break;
  770. case PIPE_ISOCHRONOUS:
  771. // itd or sitd ...
  772. // wait till next completion, do it then.
  773. // completion irqs can wait up to 1024 msec,
  774. break;
  775. }
  776. done:
  777. spin_unlock_irqrestore (&ehci->lock, flags);
  778. return rc;
  779. }
  780. /*-------------------------------------------------------------------------*/
  781. // bulk qh holds the data toggle
  782. static void
  783. ehci_endpoint_disable (struct usb_hcd *hcd, struct usb_host_endpoint *ep)
  784. {
  785. struct ehci_hcd *ehci = hcd_to_ehci (hcd);
  786. unsigned long flags;
  787. struct ehci_qh *qh, *tmp;
  788. /* ASSERT: any requests/urbs are being unlinked */
  789. /* ASSERT: nobody can be submitting urbs for this any more */
  790. rescan:
  791. spin_lock_irqsave (&ehci->lock, flags);
  792. qh = ep->hcpriv;
  793. if (!qh)
  794. goto done;
  795. /* endpoints can be iso streams. for now, we don't
  796. * accelerate iso completions ... so spin a while.
  797. */
  798. if (qh->hw_info1 == 0) {
  799. ehci_vdbg (ehci, "iso delay\n");
  800. goto idle_timeout;
  801. }
  802. if (!HC_IS_RUNNING (hcd->state))
  803. qh->qh_state = QH_STATE_IDLE;
  804. switch (qh->qh_state) {
  805. case QH_STATE_LINKED:
  806. for (tmp = ehci->async->qh_next.qh;
  807. tmp && tmp != qh;
  808. tmp = tmp->qh_next.qh)
  809. continue;
  810. /* periodic qh self-unlinks on empty */
  811. if (!tmp)
  812. goto nogood;
  813. unlink_async (ehci, qh);
  814. /* FALL THROUGH */
  815. case QH_STATE_UNLINK: /* wait for hw to finish? */
  816. case QH_STATE_UNLINK_WAIT:
  817. idle_timeout:
  818. spin_unlock_irqrestore (&ehci->lock, flags);
  819. schedule_timeout_uninterruptible(1);
  820. goto rescan;
  821. case QH_STATE_IDLE: /* fully unlinked */
  822. if (list_empty (&qh->qtd_list)) {
  823. qh_put (qh);
  824. break;
  825. }
  826. /* else FALL THROUGH */
  827. default:
  828. nogood:
  829. /* caller was supposed to have unlinked any requests;
  830. * that's not our job. just leak this memory.
  831. */
  832. ehci_err (ehci, "qh %p (#%02x) state %d%s\n",
  833. qh, ep->desc.bEndpointAddress, qh->qh_state,
  834. list_empty (&qh->qtd_list) ? "" : "(has tds)");
  835. break;
  836. }
  837. ep->hcpriv = NULL;
  838. done:
  839. spin_unlock_irqrestore (&ehci->lock, flags);
  840. return;
  841. }
  842. static int ehci_get_frame (struct usb_hcd *hcd)
  843. {
  844. struct ehci_hcd *ehci = hcd_to_ehci (hcd);
  845. return (ehci_readl(ehci, &ehci->regs->frame_index) >> 3) %
  846. ehci->periodic_size;
  847. }
  848. /*-------------------------------------------------------------------------*/
  849. MODULE_DESCRIPTION(DRIVER_DESC);
  850. MODULE_AUTHOR (DRIVER_AUTHOR);
  851. MODULE_LICENSE ("GPL");
  852. #ifdef CONFIG_PCI
  853. #include "ehci-pci.c"
  854. #define PCI_DRIVER ehci_pci_driver
  855. #endif
  856. #ifdef CONFIG_USB_EHCI_FSL
  857. #include "ehci-fsl.c"
  858. #define PLATFORM_DRIVER ehci_fsl_driver
  859. #endif
  860. #ifdef CONFIG_SOC_AU1200
  861. #include "ehci-au1xxx.c"
  862. #define PLATFORM_DRIVER ehci_hcd_au1xxx_driver
  863. #endif
  864. #ifdef CONFIG_PPC_PS3
  865. #include "ehci-ps3.c"
  866. #define PS3_SYSTEM_BUS_DRIVER ps3_ehci_driver
  867. #endif
  868. #ifdef CONFIG_USB_EHCI_HCD_PPC_OF
  869. #include "ehci-ppc-of.c"
  870. #define OF_PLATFORM_DRIVER ehci_hcd_ppc_of_driver
  871. #endif
  872. #ifdef CONFIG_PLAT_ORION
  873. #include "ehci-orion.c"
  874. #define PLATFORM_DRIVER ehci_orion_driver
  875. #endif
  876. #ifdef CONFIG_ARCH_IXP4XX
  877. #include "ehci-ixp4xx.c"
  878. #define PLATFORM_DRIVER ixp4xx_ehci_driver
  879. #endif
  880. #if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER) && \
  881. !defined(PS3_SYSTEM_BUS_DRIVER) && !defined(OF_PLATFORM_DRIVER)
  882. #error "missing bus glue for ehci-hcd"
  883. #endif
  884. static int __init ehci_hcd_init(void)
  885. {
  886. int retval = 0;
  887. if (usb_disabled())
  888. return -ENODEV;
  889. printk(KERN_INFO "%s: " DRIVER_DESC "\n", hcd_name);
  890. set_bit(USB_EHCI_LOADED, &usb_hcds_loaded);
  891. if (test_bit(USB_UHCI_LOADED, &usb_hcds_loaded) ||
  892. test_bit(USB_OHCI_LOADED, &usb_hcds_loaded))
  893. printk(KERN_WARNING "Warning! ehci_hcd should always be loaded"
  894. " before uhci_hcd and ohci_hcd, not after\n");
  895. pr_debug("%s: block sizes: qh %Zd qtd %Zd itd %Zd sitd %Zd\n",
  896. hcd_name,
  897. sizeof(struct ehci_qh), sizeof(struct ehci_qtd),
  898. sizeof(struct ehci_itd), sizeof(struct ehci_sitd));
  899. #ifdef DEBUG
  900. ehci_debug_root = debugfs_create_dir("ehci", NULL);
  901. if (!ehci_debug_root) {
  902. retval = -ENOENT;
  903. goto err_debug;
  904. }
  905. #endif
  906. #ifdef PLATFORM_DRIVER
  907. retval = platform_driver_register(&PLATFORM_DRIVER);
  908. if (retval < 0)
  909. goto clean0;
  910. #endif
  911. #ifdef PCI_DRIVER
  912. retval = pci_register_driver(&PCI_DRIVER);
  913. if (retval < 0)
  914. goto clean1;
  915. #endif
  916. #ifdef PS3_SYSTEM_BUS_DRIVER
  917. retval = ps3_ehci_driver_register(&PS3_SYSTEM_BUS_DRIVER);
  918. if (retval < 0)
  919. goto clean2;
  920. #endif
  921. #ifdef OF_PLATFORM_DRIVER
  922. retval = of_register_platform_driver(&OF_PLATFORM_DRIVER);
  923. if (retval < 0)
  924. goto clean3;
  925. #endif
  926. return retval;
  927. #ifdef OF_PLATFORM_DRIVER
  928. /* of_unregister_platform_driver(&OF_PLATFORM_DRIVER); */
  929. clean3:
  930. #endif
  931. #ifdef PS3_SYSTEM_BUS_DRIVER
  932. ps3_ehci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER);
  933. clean2:
  934. #endif
  935. #ifdef PCI_DRIVER
  936. pci_unregister_driver(&PCI_DRIVER);
  937. clean1:
  938. #endif
  939. #ifdef PLATFORM_DRIVER
  940. platform_driver_unregister(&PLATFORM_DRIVER);
  941. clean0:
  942. #endif
  943. #ifdef DEBUG
  944. debugfs_remove(ehci_debug_root);
  945. ehci_debug_root = NULL;
  946. #endif
  947. err_debug:
  948. clear_bit(USB_EHCI_LOADED, &usb_hcds_loaded);
  949. return retval;
  950. }
  951. module_init(ehci_hcd_init);
  952. static void __exit ehci_hcd_cleanup(void)
  953. {
  954. #ifdef OF_PLATFORM_DRIVER
  955. of_unregister_platform_driver(&OF_PLATFORM_DRIVER);
  956. #endif
  957. #ifdef PLATFORM_DRIVER
  958. platform_driver_unregister(&PLATFORM_DRIVER);
  959. #endif
  960. #ifdef PCI_DRIVER
  961. pci_unregister_driver(&PCI_DRIVER);
  962. #endif
  963. #ifdef PS3_SYSTEM_BUS_DRIVER
  964. ps3_ehci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER);
  965. #endif
  966. #ifdef DEBUG
  967. debugfs_remove(ehci_debug_root);
  968. #endif
  969. clear_bit(USB_EHCI_LOADED, &usb_hcds_loaded);
  970. }
  971. module_exit(ehci_hcd_cleanup);