dice.c 24 KB

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  1. /*
  2. * TC Applied Technologies Digital Interface Communications Engine driver
  3. *
  4. * Copyright (c) Clemens Ladisch <clemens@ladisch.de>
  5. * Licensed under the terms of the GNU General Public License, version 2.
  6. */
  7. #include <linux/compat.h>
  8. #include <linux/delay.h>
  9. #include <linux/device.h>
  10. #include <linux/firewire.h>
  11. #include <linux/firewire-constants.h>
  12. #include <linux/module.h>
  13. #include <linux/mod_devicetable.h>
  14. #include <linux/mutex.h>
  15. #include <linux/slab.h>
  16. #include <linux/spinlock.h>
  17. #include <linux/wait.h>
  18. #include <sound/control.h>
  19. #include <sound/core.h>
  20. #include <sound/firewire.h>
  21. #include <sound/hwdep.h>
  22. #include <sound/initval.h>
  23. #include <sound/pcm.h>
  24. #include <sound/pcm_params.h>
  25. #include "amdtp.h"
  26. #include "iso-resources.h"
  27. #include "lib.h"
  28. #include "dice-interface.h"
  29. struct dice {
  30. struct snd_card *card;
  31. struct fw_unit *unit;
  32. spinlock_t lock;
  33. struct mutex mutex;
  34. unsigned int global_offset;
  35. unsigned int rx_offset;
  36. struct fw_address_handler notification_handler;
  37. int owner_generation;
  38. int dev_lock_count; /* > 0 driver, < 0 userspace */
  39. bool dev_lock_changed;
  40. bool global_enabled;
  41. wait_queue_head_t hwdep_wait;
  42. u32 notification_bits;
  43. struct snd_pcm_substream *pcm;
  44. struct fw_iso_resources resources;
  45. struct amdtp_out_stream stream;
  46. };
  47. MODULE_DESCRIPTION("DICE driver");
  48. MODULE_AUTHOR("Clemens Ladisch <clemens@ladisch.de>");
  49. MODULE_LICENSE("GPL v2");
  50. static const unsigned int dice_rates[] = {
  51. [0] = 32000,
  52. [1] = 44100,
  53. [2] = 48000,
  54. [3] = 88200,
  55. [4] = 96000,
  56. [5] = 176400,
  57. [6] = 192000,
  58. };
  59. static void dice_lock_changed(struct dice *dice)
  60. {
  61. dice->dev_lock_changed = true;
  62. wake_up(&dice->hwdep_wait);
  63. }
  64. static int dice_try_lock(struct dice *dice)
  65. {
  66. int err;
  67. spin_lock_irq(&dice->lock);
  68. if (dice->dev_lock_count < 0) {
  69. err = -EBUSY;
  70. goto out;
  71. }
  72. if (dice->dev_lock_count++ == 0)
  73. dice_lock_changed(dice);
  74. err = 0;
  75. out:
  76. spin_unlock_irq(&dice->lock);
  77. return err;
  78. }
  79. static void dice_unlock(struct dice *dice)
  80. {
  81. spin_lock_irq(&dice->lock);
  82. if (WARN_ON(dice->dev_lock_count <= 0))
  83. goto out;
  84. if (--dice->dev_lock_count == 0)
  85. dice_lock_changed(dice);
  86. out:
  87. spin_unlock_irq(&dice->lock);
  88. }
  89. static inline u64 global_address(struct dice *dice, unsigned int offset)
  90. {
  91. return DICE_PRIVATE_SPACE + dice->global_offset + offset;
  92. }
  93. // TODO: rx index
  94. static inline u64 rx_address(struct dice *dice, unsigned int offset)
  95. {
  96. return DICE_PRIVATE_SPACE + dice->rx_offset + offset;
  97. }
  98. static int dice_owner_set(struct dice *dice)
  99. {
  100. struct fw_device *device = fw_parent_device(dice->unit);
  101. __be64 *buffer;
  102. int err, errors = 0;
  103. buffer = kmalloc(2 * 8, GFP_KERNEL);
  104. if (!buffer)
  105. return -ENOMEM;
  106. for (;;) {
  107. buffer[0] = cpu_to_be64(OWNER_NO_OWNER);
  108. buffer[1] = cpu_to_be64(
  109. ((u64)device->card->node_id << OWNER_NODE_SHIFT) |
  110. dice->notification_handler.offset);
  111. dice->owner_generation = device->generation;
  112. smp_rmb(); /* node_id vs. generation */
  113. err = snd_fw_transaction(dice->unit,
  114. TCODE_LOCK_COMPARE_SWAP,
  115. global_address(dice, GLOBAL_OWNER),
  116. buffer, 2 * 8,
  117. FW_FIXED_GENERATION |
  118. dice->owner_generation);
  119. if (err == 0) {
  120. if (buffer[0] != cpu_to_be64(OWNER_NO_OWNER)) {
  121. dev_err(&dice->unit->device,
  122. "device is already in use\n");
  123. err = -EBUSY;
  124. }
  125. break;
  126. }
  127. if (err != -EAGAIN || ++errors >= 3)
  128. break;
  129. msleep(20);
  130. }
  131. kfree(buffer);
  132. return err;
  133. }
  134. static int dice_owner_update(struct dice *dice)
  135. {
  136. struct fw_device *device = fw_parent_device(dice->unit);
  137. __be64 *buffer;
  138. int err;
  139. if (dice->owner_generation == -1)
  140. return 0;
  141. buffer = kmalloc(2 * 8, GFP_KERNEL);
  142. if (!buffer)
  143. return -ENOMEM;
  144. buffer[0] = cpu_to_be64(OWNER_NO_OWNER);
  145. buffer[1] = cpu_to_be64(
  146. ((u64)device->card->node_id << OWNER_NODE_SHIFT) |
  147. dice->notification_handler.offset);
  148. dice->owner_generation = device->generation;
  149. smp_rmb(); /* node_id vs. generation */
  150. err = snd_fw_transaction(dice->unit, TCODE_LOCK_COMPARE_SWAP,
  151. global_address(dice, GLOBAL_OWNER),
  152. buffer, 2 * 8,
  153. FW_FIXED_GENERATION | dice->owner_generation);
  154. if (err == 0) {
  155. if (buffer[0] != cpu_to_be64(OWNER_NO_OWNER)) {
  156. dev_err(&dice->unit->device,
  157. "device is already in use\n");
  158. err = -EBUSY;
  159. }
  160. } else if (err == -EAGAIN) {
  161. err = 0; /* try again later */
  162. }
  163. kfree(buffer);
  164. if (err < 0)
  165. dice->owner_generation = -1;
  166. return err;
  167. }
  168. static void dice_owner_clear(struct dice *dice)
  169. {
  170. struct fw_device *device = fw_parent_device(dice->unit);
  171. __be64 *buffer;
  172. buffer = kmalloc(2 * 8, GFP_KERNEL);
  173. if (!buffer)
  174. return;
  175. buffer[0] = cpu_to_be64(
  176. ((u64)device->card->node_id << OWNER_NODE_SHIFT) |
  177. dice->notification_handler.offset);
  178. buffer[1] = cpu_to_be64(OWNER_NO_OWNER);
  179. snd_fw_transaction(dice->unit, TCODE_LOCK_COMPARE_SWAP,
  180. global_address(dice, GLOBAL_OWNER),
  181. buffer, 2 * 8, FW_QUIET |
  182. FW_FIXED_GENERATION | dice->owner_generation);
  183. kfree(buffer);
  184. dice->owner_generation = -1;
  185. }
  186. static int dice_enable_set(struct dice *dice)
  187. {
  188. __be32 value;
  189. int err;
  190. value = cpu_to_be32(1);
  191. err = snd_fw_transaction(dice->unit, TCODE_WRITE_QUADLET_REQUEST,
  192. global_address(dice, GLOBAL_ENABLE),
  193. &value, 4,
  194. FW_FIXED_GENERATION | dice->owner_generation);
  195. if (err < 0)
  196. return err;
  197. dice->global_enabled = true;
  198. return 0;
  199. }
  200. static void dice_enable_clear(struct dice *dice)
  201. {
  202. __be32 value;
  203. if (!dice->global_enabled)
  204. return;
  205. value = 0;
  206. snd_fw_transaction(dice->unit, TCODE_WRITE_QUADLET_REQUEST,
  207. global_address(dice, GLOBAL_ENABLE),
  208. &value, 4, FW_QUIET |
  209. FW_FIXED_GENERATION | dice->owner_generation);
  210. dice->global_enabled = false;
  211. }
  212. static void dice_notification(struct fw_card *card, struct fw_request *request,
  213. int tcode, int destination, int source,
  214. int generation, unsigned long long offset,
  215. void *data, size_t length, void *callback_data)
  216. {
  217. struct dice *dice = callback_data;
  218. unsigned long flags;
  219. if (tcode != TCODE_WRITE_QUADLET_REQUEST) {
  220. fw_send_response(card, request, RCODE_TYPE_ERROR);
  221. return;
  222. }
  223. if ((offset & 3) != 0) {
  224. fw_send_response(card, request, RCODE_ADDRESS_ERROR);
  225. return;
  226. }
  227. spin_lock_irqsave(&dice->lock, flags);
  228. dice->notification_bits |= be32_to_cpup(data);
  229. spin_unlock_irqrestore(&dice->lock, flags);
  230. fw_send_response(card, request, RCODE_COMPLETE);
  231. wake_up(&dice->hwdep_wait);
  232. }
  233. static int dice_open(struct snd_pcm_substream *substream)
  234. {
  235. static const struct snd_pcm_hardware hardware = {
  236. .info = SNDRV_PCM_INFO_MMAP |
  237. SNDRV_PCM_INFO_MMAP_VALID |
  238. SNDRV_PCM_INFO_BATCH |
  239. SNDRV_PCM_INFO_INTERLEAVED |
  240. SNDRV_PCM_INFO_BLOCK_TRANSFER,
  241. .formats = AMDTP_OUT_PCM_FORMAT_BITS,
  242. .buffer_bytes_max = 16 * 1024 * 1024,
  243. .period_bytes_min = 1,
  244. .period_bytes_max = UINT_MAX,
  245. .periods_min = 1,
  246. .periods_max = UINT_MAX,
  247. };
  248. struct dice *dice = substream->private_data;
  249. struct snd_pcm_runtime *runtime = substream->runtime;
  250. __be32 clock_sel, data[2];
  251. unsigned int rate_index, number_audio, number_midi;
  252. int err;
  253. err = dice_try_lock(dice);
  254. if (err < 0)
  255. goto error;
  256. err = snd_fw_transaction(dice->unit, TCODE_READ_QUADLET_REQUEST,
  257. global_address(dice, GLOBAL_CLOCK_SELECT),
  258. &clock_sel, 4, 0);
  259. if (err < 0)
  260. goto err_lock;
  261. rate_index = (be32_to_cpu(clock_sel) & CLOCK_RATE_MASK)
  262. >> CLOCK_RATE_SHIFT;
  263. if (rate_index >= ARRAY_SIZE(dice_rates)) {
  264. err = -ENXIO;
  265. goto err_lock;
  266. }
  267. err = snd_fw_transaction(dice->unit, TCODE_READ_BLOCK_REQUEST,
  268. rx_address(dice, RX_NUMBER_AUDIO),
  269. data, 2 * 4, 0);
  270. if (err < 0)
  271. goto err_lock;
  272. number_audio = be32_to_cpu(data[0]);
  273. number_midi = be32_to_cpu(data[1]);
  274. runtime->hw = hardware;
  275. runtime->hw.rates = snd_pcm_rate_to_rate_bit(dice_rates[rate_index]);
  276. snd_pcm_limit_hw_rates(runtime);
  277. runtime->hw.channels_min = number_audio;
  278. runtime->hw.channels_max = number_audio;
  279. amdtp_out_stream_set_parameters(&dice->stream, dice_rates[rate_index],
  280. number_audio, number_midi);
  281. err = snd_pcm_hw_constraint_step(runtime, 0,
  282. SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
  283. amdtp_syt_intervals[rate_index]);
  284. if (err < 0)
  285. goto err_lock;
  286. err = snd_pcm_hw_constraint_step(runtime, 0,
  287. SNDRV_PCM_HW_PARAM_BUFFER_SIZE,
  288. amdtp_syt_intervals[rate_index]);
  289. if (err < 0)
  290. goto err_lock;
  291. err = snd_pcm_hw_constraint_minmax(runtime,
  292. SNDRV_PCM_HW_PARAM_PERIOD_TIME,
  293. 5000, 8192000);
  294. if (err < 0)
  295. goto err_lock;
  296. err = snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
  297. if (err < 0)
  298. goto err_lock;
  299. return 0;
  300. err_lock:
  301. dice_unlock(dice);
  302. error:
  303. return err;
  304. }
  305. static int dice_close(struct snd_pcm_substream *substream)
  306. {
  307. struct dice *dice = substream->private_data;
  308. dice_unlock(dice);
  309. return 0;
  310. }
  311. static int dice_stream_start_packets(struct dice *dice)
  312. {
  313. int err;
  314. if (amdtp_out_stream_running(&dice->stream))
  315. return 0;
  316. err = amdtp_out_stream_start(&dice->stream, dice->resources.channel,
  317. fw_parent_device(dice->unit)->max_speed);
  318. if (err < 0)
  319. return err;
  320. err = dice_enable_set(dice);
  321. if (err < 0) {
  322. amdtp_out_stream_stop(&dice->stream);
  323. return err;
  324. }
  325. return 0;
  326. }
  327. static int dice_stream_start(struct dice *dice)
  328. {
  329. __be32 channel;
  330. int err;
  331. if (!dice->resources.allocated) {
  332. err = fw_iso_resources_allocate(&dice->resources,
  333. amdtp_out_stream_get_max_payload(&dice->stream),
  334. fw_parent_device(dice->unit)->max_speed);
  335. if (err < 0)
  336. goto error;
  337. channel = cpu_to_be32(dice->resources.channel);
  338. err = snd_fw_transaction(dice->unit,
  339. TCODE_WRITE_QUADLET_REQUEST,
  340. rx_address(dice, RX_ISOCHRONOUS),
  341. &channel, 4, 0);
  342. if (err < 0)
  343. goto err_resources;
  344. }
  345. err = dice_stream_start_packets(dice);
  346. if (err < 0)
  347. goto err_rx_channel;
  348. return 0;
  349. err_rx_channel:
  350. channel = cpu_to_be32((u32)-1);
  351. snd_fw_transaction(dice->unit, TCODE_WRITE_QUADLET_REQUEST,
  352. rx_address(dice, RX_ISOCHRONOUS), &channel, 4, 0);
  353. err_resources:
  354. fw_iso_resources_free(&dice->resources);
  355. error:
  356. return err;
  357. }
  358. static void dice_stream_stop_packets(struct dice *dice)
  359. {
  360. if (amdtp_out_stream_running(&dice->stream)) {
  361. dice_enable_clear(dice);
  362. amdtp_out_stream_stop(&dice->stream);
  363. }
  364. }
  365. static void dice_stream_stop(struct dice *dice)
  366. {
  367. __be32 channel;
  368. dice_stream_stop_packets(dice);
  369. if (!dice->resources.allocated)
  370. return;
  371. channel = cpu_to_be32((u32)-1);
  372. snd_fw_transaction(dice->unit, TCODE_WRITE_QUADLET_REQUEST,
  373. rx_address(dice, RX_ISOCHRONOUS), &channel, 4, 0);
  374. fw_iso_resources_free(&dice->resources);
  375. }
  376. static int dice_hw_params(struct snd_pcm_substream *substream,
  377. struct snd_pcm_hw_params *hw_params)
  378. {
  379. struct dice *dice = substream->private_data;
  380. int err;
  381. mutex_lock(&dice->mutex);
  382. dice_stream_stop(dice);
  383. mutex_unlock(&dice->mutex);
  384. err = snd_pcm_lib_alloc_vmalloc_buffer(substream,
  385. params_buffer_bytes(hw_params));
  386. if (err < 0)
  387. goto error;
  388. amdtp_out_stream_set_pcm_format(&dice->stream,
  389. params_format(hw_params));
  390. return 0;
  391. error:
  392. return err;
  393. }
  394. static int dice_hw_free(struct snd_pcm_substream *substream)
  395. {
  396. struct dice *dice = substream->private_data;
  397. mutex_lock(&dice->mutex);
  398. dice_stream_stop(dice);
  399. mutex_unlock(&dice->mutex);
  400. return snd_pcm_lib_free_vmalloc_buffer(substream);
  401. }
  402. static int dice_prepare(struct snd_pcm_substream *substream)
  403. {
  404. struct dice *dice = substream->private_data;
  405. int err;
  406. mutex_lock(&dice->mutex);
  407. if (amdtp_out_streaming_error(&dice->stream))
  408. dice_stream_stop_packets(dice);
  409. err = dice_stream_start(dice);
  410. if (err < 0) {
  411. mutex_unlock(&dice->mutex);
  412. return err;
  413. }
  414. mutex_unlock(&dice->mutex);
  415. amdtp_out_stream_pcm_prepare(&dice->stream);
  416. return 0;
  417. }
  418. static int dice_trigger(struct snd_pcm_substream *substream, int cmd)
  419. {
  420. struct dice *dice = substream->private_data;
  421. struct snd_pcm_substream *pcm;
  422. switch (cmd) {
  423. case SNDRV_PCM_TRIGGER_START:
  424. pcm = substream;
  425. break;
  426. case SNDRV_PCM_TRIGGER_STOP:
  427. pcm = NULL;
  428. break;
  429. default:
  430. return -EINVAL;
  431. }
  432. amdtp_out_stream_pcm_trigger(&dice->stream, pcm);
  433. return 0;
  434. }
  435. static snd_pcm_uframes_t dice_pointer(struct snd_pcm_substream *substream)
  436. {
  437. struct dice *dice = substream->private_data;
  438. return amdtp_out_stream_pcm_pointer(&dice->stream);
  439. }
  440. static int dice_create_pcm(struct dice *dice)
  441. {
  442. static struct snd_pcm_ops ops = {
  443. .open = dice_open,
  444. .close = dice_close,
  445. .ioctl = snd_pcm_lib_ioctl,
  446. .hw_params = dice_hw_params,
  447. .hw_free = dice_hw_free,
  448. .prepare = dice_prepare,
  449. .trigger = dice_trigger,
  450. .pointer = dice_pointer,
  451. .page = snd_pcm_lib_get_vmalloc_page,
  452. .mmap = snd_pcm_lib_mmap_vmalloc,
  453. };
  454. struct snd_pcm *pcm;
  455. int err;
  456. err = snd_pcm_new(dice->card, "DICE", 0, 1, 0, &pcm);
  457. if (err < 0)
  458. return err;
  459. pcm->private_data = dice;
  460. strcpy(pcm->name, dice->card->shortname);
  461. dice->pcm = pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream;
  462. dice->pcm->ops = &ops;
  463. return 0;
  464. }
  465. static long dice_hwdep_read(struct snd_hwdep *hwdep, char __user *buf,
  466. long count, loff_t *offset)
  467. {
  468. struct dice *dice = hwdep->private_data;
  469. DEFINE_WAIT(wait);
  470. union snd_firewire_event event;
  471. spin_lock_irq(&dice->lock);
  472. while (!dice->dev_lock_changed && dice->notification_bits == 0) {
  473. prepare_to_wait(&dice->hwdep_wait, &wait, TASK_INTERRUPTIBLE);
  474. spin_unlock_irq(&dice->lock);
  475. schedule();
  476. finish_wait(&dice->hwdep_wait, &wait);
  477. if (signal_pending(current))
  478. return -ERESTARTSYS;
  479. spin_lock_irq(&dice->lock);
  480. }
  481. memset(&event, 0, sizeof(event));
  482. if (dice->dev_lock_changed) {
  483. event.lock_status.type = SNDRV_FIREWIRE_EVENT_LOCK_STATUS;
  484. event.lock_status.status = dice->dev_lock_count > 0;
  485. dice->dev_lock_changed = false;
  486. count = min(count, (long)sizeof(event.lock_status));
  487. } else {
  488. event.dice_notification.type = SNDRV_FIREWIRE_EVENT_DICE_NOTIFICATION;
  489. event.dice_notification.notification = dice->notification_bits;
  490. dice->notification_bits = 0;
  491. count = min(count, (long)sizeof(event.dice_notification));
  492. }
  493. spin_unlock_irq(&dice->lock);
  494. if (copy_to_user(buf, &event, count))
  495. return -EFAULT;
  496. return count;
  497. }
  498. static unsigned int dice_hwdep_poll(struct snd_hwdep *hwdep, struct file *file,
  499. poll_table *wait)
  500. {
  501. struct dice *dice = hwdep->private_data;
  502. unsigned int events;
  503. poll_wait(file, &dice->hwdep_wait, wait);
  504. spin_lock_irq(&dice->lock);
  505. if (dice->dev_lock_changed || dice->notification_bits != 0)
  506. events = POLLIN | POLLRDNORM;
  507. else
  508. events = 0;
  509. spin_unlock_irq(&dice->lock);
  510. return events;
  511. }
  512. static int dice_hwdep_get_info(struct dice *dice, void __user *arg)
  513. {
  514. struct fw_device *dev = fw_parent_device(dice->unit);
  515. struct snd_firewire_get_info info;
  516. memset(&info, 0, sizeof(info));
  517. info.type = SNDRV_FIREWIRE_TYPE_DICE;
  518. info.card = dev->card->index;
  519. *(__be32 *)&info.guid[0] = cpu_to_be32(dev->config_rom[3]);
  520. *(__be32 *)&info.guid[4] = cpu_to_be32(dev->config_rom[4]);
  521. strlcpy(info.device_name, dev_name(&dev->device),
  522. sizeof(info.device_name));
  523. if (copy_to_user(arg, &info, sizeof(info)))
  524. return -EFAULT;
  525. return 0;
  526. }
  527. static int dice_hwdep_lock(struct dice *dice)
  528. {
  529. int err;
  530. spin_lock_irq(&dice->lock);
  531. if (dice->dev_lock_count == 0) {
  532. dice->dev_lock_count = -1;
  533. err = 0;
  534. } else {
  535. err = -EBUSY;
  536. }
  537. spin_unlock_irq(&dice->lock);
  538. return err;
  539. }
  540. static int dice_hwdep_unlock(struct dice *dice)
  541. {
  542. int err;
  543. spin_lock_irq(&dice->lock);
  544. if (dice->dev_lock_count == -1) {
  545. dice->dev_lock_count = 0;
  546. err = 0;
  547. } else {
  548. err = -EBADFD;
  549. }
  550. spin_unlock_irq(&dice->lock);
  551. return err;
  552. }
  553. static int dice_hwdep_release(struct snd_hwdep *hwdep, struct file *file)
  554. {
  555. struct dice *dice = hwdep->private_data;
  556. spin_lock_irq(&dice->lock);
  557. if (dice->dev_lock_count == -1)
  558. dice->dev_lock_count = 0;
  559. spin_unlock_irq(&dice->lock);
  560. return 0;
  561. }
  562. static int dice_hwdep_ioctl(struct snd_hwdep *hwdep, struct file *file,
  563. unsigned int cmd, unsigned long arg)
  564. {
  565. struct dice *dice = hwdep->private_data;
  566. switch (cmd) {
  567. case SNDRV_FIREWIRE_IOCTL_GET_INFO:
  568. return dice_hwdep_get_info(dice, (void __user *)arg);
  569. case SNDRV_FIREWIRE_IOCTL_LOCK:
  570. return dice_hwdep_lock(dice);
  571. case SNDRV_FIREWIRE_IOCTL_UNLOCK:
  572. return dice_hwdep_unlock(dice);
  573. default:
  574. return -ENOIOCTLCMD;
  575. }
  576. }
  577. #ifdef CONFIG_COMPAT
  578. static int dice_hwdep_compat_ioctl(struct snd_hwdep *hwdep, struct file *file,
  579. unsigned int cmd, unsigned long arg)
  580. {
  581. return dice_hwdep_ioctl(hwdep, file, cmd,
  582. (unsigned long)compat_ptr(arg));
  583. }
  584. #else
  585. #define dice_hwdep_compat_ioctl NULL
  586. #endif
  587. static int dice_create_hwdep(struct dice *dice)
  588. {
  589. static const struct snd_hwdep_ops ops = {
  590. .read = dice_hwdep_read,
  591. .release = dice_hwdep_release,
  592. .poll = dice_hwdep_poll,
  593. .ioctl = dice_hwdep_ioctl,
  594. .ioctl_compat = dice_hwdep_compat_ioctl,
  595. };
  596. struct snd_hwdep *hwdep;
  597. int err;
  598. err = snd_hwdep_new(dice->card, "DICE", 0, &hwdep);
  599. if (err < 0)
  600. return err;
  601. strcpy(hwdep->name, "DICE");
  602. hwdep->iface = SNDRV_HWDEP_IFACE_FW_DICE;
  603. hwdep->ops = ops;
  604. hwdep->private_data = dice;
  605. hwdep->exclusive = true;
  606. return 0;
  607. }
  608. static void dice_card_free(struct snd_card *card)
  609. {
  610. struct dice *dice = card->private_data;
  611. amdtp_out_stream_destroy(&dice->stream);
  612. fw_core_remove_address_handler(&dice->notification_handler);
  613. mutex_destroy(&dice->mutex);
  614. }
  615. #define DICE_CATEGORY_ID 0x04
  616. static int dice_interface_check(struct fw_unit *unit)
  617. {
  618. static const int min_values[10] = {
  619. 10, 0x64 / 4,
  620. 10, 0x18 / 4,
  621. 10, 0x18 / 4,
  622. 0, 0,
  623. 0, 0,
  624. };
  625. struct fw_device *device = fw_parent_device(unit);
  626. struct fw_csr_iterator it;
  627. int key, value, vendor = -1, model = -1, err;
  628. unsigned int i;
  629. __be32 pointers[ARRAY_SIZE(min_values)];
  630. __be32 version;
  631. /*
  632. * Check that GUID and unit directory are constructed according to DICE
  633. * rules, i.e., that the specifier ID is the GUID's OUI, and that the
  634. * GUID chip ID consists of the 8-bit DICE category ID, the 10-bit
  635. * product ID, and a 22-bit serial number.
  636. */
  637. fw_csr_iterator_init(&it, unit->directory);
  638. while (fw_csr_iterator_next(&it, &key, &value)) {
  639. switch (key) {
  640. case CSR_SPECIFIER_ID:
  641. vendor = value;
  642. break;
  643. case CSR_MODEL:
  644. model = value;
  645. break;
  646. }
  647. }
  648. if (device->config_rom[3] != ((vendor << 8) | DICE_CATEGORY_ID) ||
  649. device->config_rom[4] >> 22 != model)
  650. return -ENODEV;
  651. /*
  652. * Check that the sub address spaces exist and are located inside the
  653. * private address space. The minimum values are chosen so that all
  654. * minimally required registers are included.
  655. */
  656. err = snd_fw_transaction(unit, TCODE_READ_BLOCK_REQUEST,
  657. DICE_PRIVATE_SPACE,
  658. pointers, sizeof(pointers), 0);
  659. if (err < 0)
  660. return -ENODEV;
  661. for (i = 0; i < ARRAY_SIZE(pointers); ++i) {
  662. value = be32_to_cpu(pointers[i]);
  663. if (value < min_values[i] || value >= 0x40000)
  664. return -ENODEV;
  665. }
  666. /*
  667. * Check that the implemented DICE driver specification major version
  668. * number matches.
  669. */
  670. err = snd_fw_transaction(unit, TCODE_READ_QUADLET_REQUEST,
  671. DICE_PRIVATE_SPACE +
  672. be32_to_cpu(pointers[0]) * 4 + GLOBAL_VERSION,
  673. &version, 4, 0);
  674. if (err < 0)
  675. return -ENODEV;
  676. if ((version & cpu_to_be32(0xff000000)) != cpu_to_be32(0x01000000)) {
  677. dev_err(&unit->device,
  678. "unknown DICE version: 0x%08x\n", be32_to_cpu(version));
  679. return -ENODEV;
  680. }
  681. return 0;
  682. }
  683. static int dice_init_offsets(struct dice *dice)
  684. {
  685. __be32 pointers[6];
  686. int err;
  687. err = snd_fw_transaction(dice->unit, TCODE_READ_BLOCK_REQUEST,
  688. DICE_PRIVATE_SPACE,
  689. pointers, sizeof(pointers), 0);
  690. if (err < 0)
  691. return err;
  692. dice->global_offset = be32_to_cpu(pointers[0]) * 4;
  693. dice->rx_offset = be32_to_cpu(pointers[4]) * 4;
  694. return 0;
  695. }
  696. static void dice_card_strings(struct dice *dice)
  697. {
  698. struct snd_card *card = dice->card;
  699. struct fw_device *dev = fw_parent_device(dice->unit);
  700. char vendor[32], model[32];
  701. unsigned int i;
  702. int err;
  703. strcpy(card->driver, "DICE");
  704. strcpy(card->shortname, "DICE");
  705. BUILD_BUG_ON(NICK_NAME_SIZE < sizeof(card->shortname));
  706. err = snd_fw_transaction(dice->unit, TCODE_READ_BLOCK_REQUEST,
  707. global_address(dice, GLOBAL_NICK_NAME),
  708. card->shortname, sizeof(card->shortname), 0);
  709. if (err >= 0) {
  710. /* DICE strings are returned in "always-wrong" endianness */
  711. BUILD_BUG_ON(sizeof(card->shortname) % 4 != 0);
  712. for (i = 0; i < sizeof(card->shortname); i += 4)
  713. swab32s((u32 *)&card->shortname[i]);
  714. card->shortname[sizeof(card->shortname) - 1] = '\0';
  715. }
  716. strcpy(vendor, "?");
  717. fw_csr_string(dev->config_rom + 5, CSR_VENDOR, vendor, sizeof(vendor));
  718. strcpy(model, "?");
  719. fw_csr_string(dice->unit->directory, CSR_MODEL, model, sizeof(model));
  720. snprintf(card->longname, sizeof(card->longname),
  721. "%s %s (serial %u) at %s, S%d",
  722. vendor, model, dev->config_rom[4] & 0x3fffff,
  723. dev_name(&dice->unit->device), 100 << dev->max_speed);
  724. strcpy(card->mixername, "DICE");
  725. }
  726. static int dice_probe(struct fw_unit *unit, const struct ieee1394_device_id *id)
  727. {
  728. struct snd_card *card;
  729. struct dice *dice;
  730. __be32 clock_sel;
  731. int err;
  732. err = dice_interface_check(unit);
  733. if (err < 0)
  734. return err;
  735. err = snd_card_create(-1, NULL, THIS_MODULE, sizeof(*dice), &card);
  736. if (err < 0)
  737. return err;
  738. snd_card_set_dev(card, &unit->device);
  739. dice = card->private_data;
  740. dice->card = card;
  741. spin_lock_init(&dice->lock);
  742. mutex_init(&dice->mutex);
  743. dice->unit = unit;
  744. init_waitqueue_head(&dice->hwdep_wait);
  745. err = dice_init_offsets(dice);
  746. if (err < 0)
  747. goto err_mutex;
  748. dice->notification_handler.length = 4;
  749. dice->notification_handler.address_callback = dice_notification;
  750. dice->notification_handler.callback_data = dice;
  751. err = fw_core_add_address_handler(&dice->notification_handler,
  752. &fw_high_memory_region);
  753. if (err < 0)
  754. goto err_mutex;
  755. err = fw_iso_resources_init(&dice->resources, unit);
  756. if (err < 0)
  757. goto err_notification_handler;
  758. dice->resources.channels_mask = 0x00000000ffffffffuLL;
  759. err = amdtp_out_stream_init(&dice->stream, unit,
  760. CIP_BLOCKING | CIP_HI_DUALWIRE);
  761. if (err < 0)
  762. goto err_resources;
  763. err = dice_owner_set(dice);
  764. if (err < 0)
  765. goto err_stream;
  766. card->private_free = dice_card_free;
  767. dice_card_strings(dice);
  768. err = snd_fw_transaction(unit, TCODE_READ_QUADLET_REQUEST,
  769. global_address(dice, GLOBAL_CLOCK_SELECT),
  770. &clock_sel, 4, 0);
  771. if (err < 0)
  772. goto error;
  773. clock_sel &= cpu_to_be32(~CLOCK_SOURCE_MASK);
  774. clock_sel |= cpu_to_be32(CLOCK_SOURCE_ARX1);
  775. err = snd_fw_transaction(unit, TCODE_WRITE_QUADLET_REQUEST,
  776. global_address(dice, GLOBAL_CLOCK_SELECT),
  777. &clock_sel, 4, 0);
  778. if (err < 0)
  779. goto error;
  780. err = dice_create_pcm(dice);
  781. if (err < 0)
  782. goto error;
  783. err = dice_create_hwdep(dice);
  784. if (err < 0)
  785. goto error;
  786. err = snd_card_register(card);
  787. if (err < 0)
  788. goto error;
  789. dev_set_drvdata(&unit->device, dice);
  790. return 0;
  791. err_stream:
  792. amdtp_out_stream_destroy(&dice->stream);
  793. err_resources:
  794. fw_iso_resources_destroy(&dice->resources);
  795. err_notification_handler:
  796. fw_core_remove_address_handler(&dice->notification_handler);
  797. err_mutex:
  798. mutex_destroy(&dice->mutex);
  799. error:
  800. snd_card_free(card);
  801. return err;
  802. }
  803. static void dice_remove(struct fw_unit *unit)
  804. {
  805. struct dice *dice = dev_get_drvdata(&unit->device);
  806. mutex_lock(&dice->mutex);
  807. amdtp_out_stream_pcm_abort(&dice->stream);
  808. snd_card_disconnect(dice->card);
  809. dice_stream_stop(dice);
  810. dice_owner_clear(dice);
  811. mutex_unlock(&dice->mutex);
  812. snd_card_free_when_closed(dice->card);
  813. }
  814. static void dice_bus_reset(struct fw_unit *unit)
  815. {
  816. struct dice *dice = dev_get_drvdata(&unit->device);
  817. mutex_lock(&dice->mutex);
  818. /*
  819. * On a bus reset, the DICE firmware disables streaming and then goes
  820. * off contemplating its own navel for hundreds of milliseconds before
  821. * it can react to any of our attempts to reenable streaming. This
  822. * means that we lose synchronization anyway, so we force our streams
  823. * to stop so that the application can restart them in an orderly
  824. * manner.
  825. */
  826. amdtp_out_stream_pcm_abort(&dice->stream);
  827. dice->global_enabled = false;
  828. dice_stream_stop_packets(dice);
  829. dice_owner_update(dice);
  830. fw_iso_resources_update(&dice->resources);
  831. mutex_unlock(&dice->mutex);
  832. }
  833. #define DICE_INTERFACE 0x000001
  834. static const struct ieee1394_device_id dice_id_table[] = {
  835. {
  836. .match_flags = IEEE1394_MATCH_VERSION,
  837. .version = DICE_INTERFACE,
  838. },
  839. { }
  840. };
  841. MODULE_DEVICE_TABLE(ieee1394, dice_id_table);
  842. static struct fw_driver dice_driver = {
  843. .driver = {
  844. .owner = THIS_MODULE,
  845. .name = KBUILD_MODNAME,
  846. .bus = &fw_bus_type,
  847. },
  848. .probe = dice_probe,
  849. .update = dice_bus_reset,
  850. .remove = dice_remove,
  851. .id_table = dice_id_table,
  852. };
  853. static int __init alsa_dice_init(void)
  854. {
  855. return driver_register(&dice_driver.driver);
  856. }
  857. static void __exit alsa_dice_exit(void)
  858. {
  859. driver_unregister(&dice_driver.driver);
  860. }
  861. module_init(alsa_dice_init);
  862. module_exit(alsa_dice_exit);