mpt2sas_base.c 109 KB

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  1. /*
  2. * This is the Fusion MPT base driver providing common API layer interface
  3. * for access to MPT (Message Passing Technology) firmware.
  4. *
  5. * This code is based on drivers/scsi/mpt2sas/mpt2_base.c
  6. * Copyright (C) 2007-2010 LSI Corporation
  7. * (mailto:DL-MPTFusionLinux@lsi.com)
  8. *
  9. * This program is free software; you can redistribute it and/or
  10. * modify it under the terms of the GNU General Public License
  11. * as published by the Free Software Foundation; either version 2
  12. * of the License, or (at your option) any later version.
  13. *
  14. * This program is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * NO WARRANTY
  20. * THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR
  21. * CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT
  22. * LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
  23. * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is
  24. * solely responsible for determining the appropriateness of using and
  25. * distributing the Program and assumes all risks associated with its
  26. * exercise of rights under this Agreement, including but not limited to
  27. * the risks and costs of program errors, damage to or loss of data,
  28. * programs or equipment, and unavailability or interruption of operations.
  29. * DISCLAIMER OF LIABILITY
  30. * NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY
  31. * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  32. * DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND
  33. * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
  34. * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
  35. * USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED
  36. * HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES
  37. * You should have received a copy of the GNU General Public License
  38. * along with this program; if not, write to the Free Software
  39. * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301,
  40. * USA.
  41. */
  42. #include <linux/version.h>
  43. #include <linux/kernel.h>
  44. #include <linux/module.h>
  45. #include <linux/errno.h>
  46. #include <linux/init.h>
  47. #include <linux/slab.h>
  48. #include <linux/types.h>
  49. #include <linux/pci.h>
  50. #include <linux/kdev_t.h>
  51. #include <linux/blkdev.h>
  52. #include <linux/delay.h>
  53. #include <linux/interrupt.h>
  54. #include <linux/dma-mapping.h>
  55. #include <linux/sort.h>
  56. #include <linux/io.h>
  57. #include <linux/time.h>
  58. #include <linux/aer.h>
  59. #include "mpt2sas_base.h"
  60. static MPT_CALLBACK mpt_callbacks[MPT_MAX_CALLBACKS];
  61. #define FAULT_POLLING_INTERVAL 1000 /* in milliseconds */
  62. #define MPT2SAS_MAX_REQUEST_QUEUE 600 /* maximum controller queue depth */
  63. static int max_queue_depth = -1;
  64. module_param(max_queue_depth, int, 0);
  65. MODULE_PARM_DESC(max_queue_depth, " max controller queue depth ");
  66. static int max_sgl_entries = -1;
  67. module_param(max_sgl_entries, int, 0);
  68. MODULE_PARM_DESC(max_sgl_entries, " max sg entries ");
  69. static int msix_disable = -1;
  70. module_param(msix_disable, int, 0);
  71. MODULE_PARM_DESC(msix_disable, " disable msix routed interrupts (default=0)");
  72. /* diag_buffer_enable is bitwise
  73. * bit 0 set = TRACE
  74. * bit 1 set = SNAPSHOT
  75. * bit 2 set = EXTENDED
  76. *
  77. * Either bit can be set, or both
  78. */
  79. static int diag_buffer_enable;
  80. module_param(diag_buffer_enable, int, 0);
  81. MODULE_PARM_DESC(diag_buffer_enable, " post diag buffers "
  82. "(TRACE=1/SNAPSHOT=2/EXTENDED=4/default=0)");
  83. int mpt2sas_fwfault_debug;
  84. MODULE_PARM_DESC(mpt2sas_fwfault_debug, " enable detection of firmware fault "
  85. "and halt firmware - (default=0)");
  86. static int disable_discovery = -1;
  87. module_param(disable_discovery, int, 0);
  88. MODULE_PARM_DESC(disable_discovery, " disable discovery ");
  89. /**
  90. * _scsih_set_fwfault_debug - global setting of ioc->fwfault_debug.
  91. *
  92. */
  93. static int
  94. _scsih_set_fwfault_debug(const char *val, struct kernel_param *kp)
  95. {
  96. int ret = param_set_int(val, kp);
  97. struct MPT2SAS_ADAPTER *ioc;
  98. if (ret)
  99. return ret;
  100. printk(KERN_INFO "setting fwfault_debug(%d)\n", mpt2sas_fwfault_debug);
  101. list_for_each_entry(ioc, &mpt2sas_ioc_list, list)
  102. ioc->fwfault_debug = mpt2sas_fwfault_debug;
  103. return 0;
  104. }
  105. module_param_call(mpt2sas_fwfault_debug, _scsih_set_fwfault_debug,
  106. param_get_int, &mpt2sas_fwfault_debug, 0644);
  107. /**
  108. * _base_fault_reset_work - workq handling ioc fault conditions
  109. * @work: input argument, used to derive ioc
  110. * Context: sleep.
  111. *
  112. * Return nothing.
  113. */
  114. static void
  115. _base_fault_reset_work(struct work_struct *work)
  116. {
  117. struct MPT2SAS_ADAPTER *ioc =
  118. container_of(work, struct MPT2SAS_ADAPTER, fault_reset_work.work);
  119. unsigned long flags;
  120. u32 doorbell;
  121. int rc;
  122. spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
  123. if (ioc->shost_recovery)
  124. goto rearm_timer;
  125. spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
  126. doorbell = mpt2sas_base_get_iocstate(ioc, 0);
  127. if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) {
  128. rc = mpt2sas_base_hard_reset_handler(ioc, CAN_SLEEP,
  129. FORCE_BIG_HAMMER);
  130. printk(MPT2SAS_WARN_FMT "%s: hard reset: %s\n", ioc->name,
  131. __func__, (rc == 0) ? "success" : "failed");
  132. doorbell = mpt2sas_base_get_iocstate(ioc, 0);
  133. if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT)
  134. mpt2sas_base_fault_info(ioc, doorbell &
  135. MPI2_DOORBELL_DATA_MASK);
  136. }
  137. spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
  138. rearm_timer:
  139. if (ioc->fault_reset_work_q)
  140. queue_delayed_work(ioc->fault_reset_work_q,
  141. &ioc->fault_reset_work,
  142. msecs_to_jiffies(FAULT_POLLING_INTERVAL));
  143. spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
  144. }
  145. /**
  146. * mpt2sas_base_start_watchdog - start the fault_reset_work_q
  147. * @ioc: per adapter object
  148. * Context: sleep.
  149. *
  150. * Return nothing.
  151. */
  152. void
  153. mpt2sas_base_start_watchdog(struct MPT2SAS_ADAPTER *ioc)
  154. {
  155. unsigned long flags;
  156. if (ioc->fault_reset_work_q)
  157. return;
  158. /* initialize fault polling */
  159. INIT_DELAYED_WORK(&ioc->fault_reset_work, _base_fault_reset_work);
  160. snprintf(ioc->fault_reset_work_q_name,
  161. sizeof(ioc->fault_reset_work_q_name), "poll_%d_status", ioc->id);
  162. ioc->fault_reset_work_q =
  163. create_singlethread_workqueue(ioc->fault_reset_work_q_name);
  164. if (!ioc->fault_reset_work_q) {
  165. printk(MPT2SAS_ERR_FMT "%s: failed (line=%d)\n",
  166. ioc->name, __func__, __LINE__);
  167. return;
  168. }
  169. spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
  170. if (ioc->fault_reset_work_q)
  171. queue_delayed_work(ioc->fault_reset_work_q,
  172. &ioc->fault_reset_work,
  173. msecs_to_jiffies(FAULT_POLLING_INTERVAL));
  174. spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
  175. }
  176. /**
  177. * mpt2sas_base_stop_watchdog - stop the fault_reset_work_q
  178. * @ioc: per adapter object
  179. * Context: sleep.
  180. *
  181. * Return nothing.
  182. */
  183. void
  184. mpt2sas_base_stop_watchdog(struct MPT2SAS_ADAPTER *ioc)
  185. {
  186. unsigned long flags;
  187. struct workqueue_struct *wq;
  188. spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
  189. wq = ioc->fault_reset_work_q;
  190. ioc->fault_reset_work_q = NULL;
  191. spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
  192. if (wq) {
  193. if (!cancel_delayed_work(&ioc->fault_reset_work))
  194. flush_workqueue(wq);
  195. destroy_workqueue(wq);
  196. }
  197. }
  198. /**
  199. * mpt2sas_base_fault_info - verbose translation of firmware FAULT code
  200. * @ioc: per adapter object
  201. * @fault_code: fault code
  202. *
  203. * Return nothing.
  204. */
  205. void
  206. mpt2sas_base_fault_info(struct MPT2SAS_ADAPTER *ioc , u16 fault_code)
  207. {
  208. printk(MPT2SAS_ERR_FMT "fault_state(0x%04x)!\n",
  209. ioc->name, fault_code);
  210. }
  211. /**
  212. * mpt2sas_halt_firmware - halt's mpt controller firmware
  213. * @ioc: per adapter object
  214. *
  215. * For debugging timeout related issues. Writing 0xCOFFEE00
  216. * to the doorbell register will halt controller firmware. With
  217. * the purpose to stop both driver and firmware, the enduser can
  218. * obtain a ring buffer from controller UART.
  219. */
  220. void
  221. mpt2sas_halt_firmware(struct MPT2SAS_ADAPTER *ioc)
  222. {
  223. u32 doorbell;
  224. if (!ioc->fwfault_debug)
  225. return;
  226. dump_stack();
  227. doorbell = readl(&ioc->chip->Doorbell);
  228. if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT)
  229. mpt2sas_base_fault_info(ioc , doorbell);
  230. else {
  231. writel(0xC0FFEE00, &ioc->chip->Doorbell);
  232. printk(MPT2SAS_ERR_FMT "Firmware is halted due to command "
  233. "timeout\n", ioc->name);
  234. }
  235. panic("panic in %s\n", __func__);
  236. }
  237. #ifdef CONFIG_SCSI_MPT2SAS_LOGGING
  238. /**
  239. * _base_sas_ioc_info - verbose translation of the ioc status
  240. * @ioc: per adapter object
  241. * @mpi_reply: reply mf payload returned from firmware
  242. * @request_hdr: request mf
  243. *
  244. * Return nothing.
  245. */
  246. static void
  247. _base_sas_ioc_info(struct MPT2SAS_ADAPTER *ioc, MPI2DefaultReply_t *mpi_reply,
  248. MPI2RequestHeader_t *request_hdr)
  249. {
  250. u16 ioc_status = le16_to_cpu(mpi_reply->IOCStatus) &
  251. MPI2_IOCSTATUS_MASK;
  252. char *desc = NULL;
  253. u16 frame_sz;
  254. char *func_str = NULL;
  255. /* SCSI_IO, RAID_PASS are handled from _scsih_scsi_ioc_info */
  256. if (request_hdr->Function == MPI2_FUNCTION_SCSI_IO_REQUEST ||
  257. request_hdr->Function == MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH ||
  258. request_hdr->Function == MPI2_FUNCTION_EVENT_NOTIFICATION)
  259. return;
  260. if (ioc_status == MPI2_IOCSTATUS_CONFIG_INVALID_PAGE)
  261. return;
  262. switch (ioc_status) {
  263. /****************************************************************************
  264. * Common IOCStatus values for all replies
  265. ****************************************************************************/
  266. case MPI2_IOCSTATUS_INVALID_FUNCTION:
  267. desc = "invalid function";
  268. break;
  269. case MPI2_IOCSTATUS_BUSY:
  270. desc = "busy";
  271. break;
  272. case MPI2_IOCSTATUS_INVALID_SGL:
  273. desc = "invalid sgl";
  274. break;
  275. case MPI2_IOCSTATUS_INTERNAL_ERROR:
  276. desc = "internal error";
  277. break;
  278. case MPI2_IOCSTATUS_INVALID_VPID:
  279. desc = "invalid vpid";
  280. break;
  281. case MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES:
  282. desc = "insufficient resources";
  283. break;
  284. case MPI2_IOCSTATUS_INVALID_FIELD:
  285. desc = "invalid field";
  286. break;
  287. case MPI2_IOCSTATUS_INVALID_STATE:
  288. desc = "invalid state";
  289. break;
  290. case MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED:
  291. desc = "op state not supported";
  292. break;
  293. /****************************************************************************
  294. * Config IOCStatus values
  295. ****************************************************************************/
  296. case MPI2_IOCSTATUS_CONFIG_INVALID_ACTION:
  297. desc = "config invalid action";
  298. break;
  299. case MPI2_IOCSTATUS_CONFIG_INVALID_TYPE:
  300. desc = "config invalid type";
  301. break;
  302. case MPI2_IOCSTATUS_CONFIG_INVALID_PAGE:
  303. desc = "config invalid page";
  304. break;
  305. case MPI2_IOCSTATUS_CONFIG_INVALID_DATA:
  306. desc = "config invalid data";
  307. break;
  308. case MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS:
  309. desc = "config no defaults";
  310. break;
  311. case MPI2_IOCSTATUS_CONFIG_CANT_COMMIT:
  312. desc = "config cant commit";
  313. break;
  314. /****************************************************************************
  315. * SCSI IO Reply
  316. ****************************************************************************/
  317. case MPI2_IOCSTATUS_SCSI_RECOVERED_ERROR:
  318. case MPI2_IOCSTATUS_SCSI_INVALID_DEVHANDLE:
  319. case MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE:
  320. case MPI2_IOCSTATUS_SCSI_DATA_OVERRUN:
  321. case MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN:
  322. case MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR:
  323. case MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR:
  324. case MPI2_IOCSTATUS_SCSI_TASK_TERMINATED:
  325. case MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH:
  326. case MPI2_IOCSTATUS_SCSI_TASK_MGMT_FAILED:
  327. case MPI2_IOCSTATUS_SCSI_IOC_TERMINATED:
  328. case MPI2_IOCSTATUS_SCSI_EXT_TERMINATED:
  329. break;
  330. /****************************************************************************
  331. * For use by SCSI Initiator and SCSI Target end-to-end data protection
  332. ****************************************************************************/
  333. case MPI2_IOCSTATUS_EEDP_GUARD_ERROR:
  334. desc = "eedp guard error";
  335. break;
  336. case MPI2_IOCSTATUS_EEDP_REF_TAG_ERROR:
  337. desc = "eedp ref tag error";
  338. break;
  339. case MPI2_IOCSTATUS_EEDP_APP_TAG_ERROR:
  340. desc = "eedp app tag error";
  341. break;
  342. /****************************************************************************
  343. * SCSI Target values
  344. ****************************************************************************/
  345. case MPI2_IOCSTATUS_TARGET_INVALID_IO_INDEX:
  346. desc = "target invalid io index";
  347. break;
  348. case MPI2_IOCSTATUS_TARGET_ABORTED:
  349. desc = "target aborted";
  350. break;
  351. case MPI2_IOCSTATUS_TARGET_NO_CONN_RETRYABLE:
  352. desc = "target no conn retryable";
  353. break;
  354. case MPI2_IOCSTATUS_TARGET_NO_CONNECTION:
  355. desc = "target no connection";
  356. break;
  357. case MPI2_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH:
  358. desc = "target xfer count mismatch";
  359. break;
  360. case MPI2_IOCSTATUS_TARGET_DATA_OFFSET_ERROR:
  361. desc = "target data offset error";
  362. break;
  363. case MPI2_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA:
  364. desc = "target too much write data";
  365. break;
  366. case MPI2_IOCSTATUS_TARGET_IU_TOO_SHORT:
  367. desc = "target iu too short";
  368. break;
  369. case MPI2_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT:
  370. desc = "target ack nak timeout";
  371. break;
  372. case MPI2_IOCSTATUS_TARGET_NAK_RECEIVED:
  373. desc = "target nak received";
  374. break;
  375. /****************************************************************************
  376. * Serial Attached SCSI values
  377. ****************************************************************************/
  378. case MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED:
  379. desc = "smp request failed";
  380. break;
  381. case MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN:
  382. desc = "smp data overrun";
  383. break;
  384. /****************************************************************************
  385. * Diagnostic Buffer Post / Diagnostic Release values
  386. ****************************************************************************/
  387. case MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED:
  388. desc = "diagnostic released";
  389. break;
  390. default:
  391. break;
  392. }
  393. if (!desc)
  394. return;
  395. switch (request_hdr->Function) {
  396. case MPI2_FUNCTION_CONFIG:
  397. frame_sz = sizeof(Mpi2ConfigRequest_t) + ioc->sge_size;
  398. func_str = "config_page";
  399. break;
  400. case MPI2_FUNCTION_SCSI_TASK_MGMT:
  401. frame_sz = sizeof(Mpi2SCSITaskManagementRequest_t);
  402. func_str = "task_mgmt";
  403. break;
  404. case MPI2_FUNCTION_SAS_IO_UNIT_CONTROL:
  405. frame_sz = sizeof(Mpi2SasIoUnitControlRequest_t);
  406. func_str = "sas_iounit_ctl";
  407. break;
  408. case MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR:
  409. frame_sz = sizeof(Mpi2SepRequest_t);
  410. func_str = "enclosure";
  411. break;
  412. case MPI2_FUNCTION_IOC_INIT:
  413. frame_sz = sizeof(Mpi2IOCInitRequest_t);
  414. func_str = "ioc_init";
  415. break;
  416. case MPI2_FUNCTION_PORT_ENABLE:
  417. frame_sz = sizeof(Mpi2PortEnableRequest_t);
  418. func_str = "port_enable";
  419. break;
  420. case MPI2_FUNCTION_SMP_PASSTHROUGH:
  421. frame_sz = sizeof(Mpi2SmpPassthroughRequest_t) + ioc->sge_size;
  422. func_str = "smp_passthru";
  423. break;
  424. default:
  425. frame_sz = 32;
  426. func_str = "unknown";
  427. break;
  428. }
  429. printk(MPT2SAS_WARN_FMT "ioc_status: %s(0x%04x), request(0x%p),"
  430. " (%s)\n", ioc->name, desc, ioc_status, request_hdr, func_str);
  431. _debug_dump_mf(request_hdr, frame_sz/4);
  432. }
  433. /**
  434. * _base_display_event_data - verbose translation of firmware asyn events
  435. * @ioc: per adapter object
  436. * @mpi_reply: reply mf payload returned from firmware
  437. *
  438. * Return nothing.
  439. */
  440. static void
  441. _base_display_event_data(struct MPT2SAS_ADAPTER *ioc,
  442. Mpi2EventNotificationReply_t *mpi_reply)
  443. {
  444. char *desc = NULL;
  445. u16 event;
  446. if (!(ioc->logging_level & MPT_DEBUG_EVENTS))
  447. return;
  448. event = le16_to_cpu(mpi_reply->Event);
  449. switch (event) {
  450. case MPI2_EVENT_LOG_DATA:
  451. desc = "Log Data";
  452. break;
  453. case MPI2_EVENT_STATE_CHANGE:
  454. desc = "Status Change";
  455. break;
  456. case MPI2_EVENT_HARD_RESET_RECEIVED:
  457. desc = "Hard Reset Received";
  458. break;
  459. case MPI2_EVENT_EVENT_CHANGE:
  460. desc = "Event Change";
  461. break;
  462. case MPI2_EVENT_TASK_SET_FULL:
  463. desc = "Task Set Full";
  464. break;
  465. case MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE:
  466. desc = "Device Status Change";
  467. break;
  468. case MPI2_EVENT_IR_OPERATION_STATUS:
  469. desc = "IR Operation Status";
  470. break;
  471. case MPI2_EVENT_SAS_DISCOVERY:
  472. {
  473. Mpi2EventDataSasDiscovery_t *event_data =
  474. (Mpi2EventDataSasDiscovery_t *)mpi_reply->EventData;
  475. printk(MPT2SAS_INFO_FMT "Discovery: (%s)", ioc->name,
  476. (event_data->ReasonCode == MPI2_EVENT_SAS_DISC_RC_STARTED) ?
  477. "start" : "stop");
  478. if (event_data->DiscoveryStatus)
  479. printk("discovery_status(0x%08x)",
  480. le32_to_cpu(event_data->DiscoveryStatus));
  481. printk("\n");
  482. return;
  483. }
  484. case MPI2_EVENT_SAS_BROADCAST_PRIMITIVE:
  485. desc = "SAS Broadcast Primitive";
  486. break;
  487. case MPI2_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE:
  488. desc = "SAS Init Device Status Change";
  489. break;
  490. case MPI2_EVENT_SAS_INIT_TABLE_OVERFLOW:
  491. desc = "SAS Init Table Overflow";
  492. break;
  493. case MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST:
  494. desc = "SAS Topology Change List";
  495. break;
  496. case MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE:
  497. desc = "SAS Enclosure Device Status Change";
  498. break;
  499. case MPI2_EVENT_IR_VOLUME:
  500. desc = "IR Volume";
  501. break;
  502. case MPI2_EVENT_IR_PHYSICAL_DISK:
  503. desc = "IR Physical Disk";
  504. break;
  505. case MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST:
  506. desc = "IR Configuration Change List";
  507. break;
  508. case MPI2_EVENT_LOG_ENTRY_ADDED:
  509. desc = "Log Entry Added";
  510. break;
  511. }
  512. if (!desc)
  513. return;
  514. printk(MPT2SAS_INFO_FMT "%s\n", ioc->name, desc);
  515. }
  516. #endif
  517. /**
  518. * _base_sas_log_info - verbose translation of firmware log info
  519. * @ioc: per adapter object
  520. * @log_info: log info
  521. *
  522. * Return nothing.
  523. */
  524. static void
  525. _base_sas_log_info(struct MPT2SAS_ADAPTER *ioc , u32 log_info)
  526. {
  527. union loginfo_type {
  528. u32 loginfo;
  529. struct {
  530. u32 subcode:16;
  531. u32 code:8;
  532. u32 originator:4;
  533. u32 bus_type:4;
  534. } dw;
  535. };
  536. union loginfo_type sas_loginfo;
  537. char *originator_str = NULL;
  538. sas_loginfo.loginfo = log_info;
  539. if (sas_loginfo.dw.bus_type != 3 /*SAS*/)
  540. return;
  541. /* each nexus loss loginfo */
  542. if (log_info == 0x31170000)
  543. return;
  544. /* eat the loginfos associated with task aborts */
  545. if (ioc->ignore_loginfos && (log_info == 30050000 || log_info ==
  546. 0x31140000 || log_info == 0x31130000))
  547. return;
  548. switch (sas_loginfo.dw.originator) {
  549. case 0:
  550. originator_str = "IOP";
  551. break;
  552. case 1:
  553. originator_str = "PL";
  554. break;
  555. case 2:
  556. originator_str = "IR";
  557. break;
  558. }
  559. printk(MPT2SAS_WARN_FMT "log_info(0x%08x): originator(%s), "
  560. "code(0x%02x), sub_code(0x%04x)\n", ioc->name, log_info,
  561. originator_str, sas_loginfo.dw.code,
  562. sas_loginfo.dw.subcode);
  563. }
  564. /**
  565. * _base_display_reply_info -
  566. * @ioc: per adapter object
  567. * @smid: system request message index
  568. * @msix_index: MSIX table index supplied by the OS
  569. * @reply: reply message frame(lower 32bit addr)
  570. *
  571. * Return nothing.
  572. */
  573. static void
  574. _base_display_reply_info(struct MPT2SAS_ADAPTER *ioc, u16 smid, u8 msix_index,
  575. u32 reply)
  576. {
  577. MPI2DefaultReply_t *mpi_reply;
  578. u16 ioc_status;
  579. mpi_reply = mpt2sas_base_get_reply_virt_addr(ioc, reply);
  580. ioc_status = le16_to_cpu(mpi_reply->IOCStatus);
  581. #ifdef CONFIG_SCSI_MPT2SAS_LOGGING
  582. if ((ioc_status & MPI2_IOCSTATUS_MASK) &&
  583. (ioc->logging_level & MPT_DEBUG_REPLY)) {
  584. _base_sas_ioc_info(ioc , mpi_reply,
  585. mpt2sas_base_get_msg_frame(ioc, smid));
  586. }
  587. #endif
  588. if (ioc_status & MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE)
  589. _base_sas_log_info(ioc, le32_to_cpu(mpi_reply->IOCLogInfo));
  590. }
  591. /**
  592. * mpt2sas_base_done - base internal command completion routine
  593. * @ioc: per adapter object
  594. * @smid: system request message index
  595. * @msix_index: MSIX table index supplied by the OS
  596. * @reply: reply message frame(lower 32bit addr)
  597. *
  598. * Return 1 meaning mf should be freed from _base_interrupt
  599. * 0 means the mf is freed from this function.
  600. */
  601. u8
  602. mpt2sas_base_done(struct MPT2SAS_ADAPTER *ioc, u16 smid, u8 msix_index,
  603. u32 reply)
  604. {
  605. MPI2DefaultReply_t *mpi_reply;
  606. mpi_reply = mpt2sas_base_get_reply_virt_addr(ioc, reply);
  607. if (mpi_reply && mpi_reply->Function == MPI2_FUNCTION_EVENT_ACK)
  608. return 1;
  609. if (ioc->base_cmds.status == MPT2_CMD_NOT_USED)
  610. return 1;
  611. ioc->base_cmds.status |= MPT2_CMD_COMPLETE;
  612. if (mpi_reply) {
  613. ioc->base_cmds.status |= MPT2_CMD_REPLY_VALID;
  614. memcpy(ioc->base_cmds.reply, mpi_reply, mpi_reply->MsgLength*4);
  615. }
  616. ioc->base_cmds.status &= ~MPT2_CMD_PENDING;
  617. complete(&ioc->base_cmds.done);
  618. return 1;
  619. }
  620. /**
  621. * _base_async_event - main callback handler for firmware asyn events
  622. * @ioc: per adapter object
  623. * @msix_index: MSIX table index supplied by the OS
  624. * @reply: reply message frame(lower 32bit addr)
  625. *
  626. * Return 1 meaning mf should be freed from _base_interrupt
  627. * 0 means the mf is freed from this function.
  628. */
  629. static u8
  630. _base_async_event(struct MPT2SAS_ADAPTER *ioc, u8 msix_index, u32 reply)
  631. {
  632. Mpi2EventNotificationReply_t *mpi_reply;
  633. Mpi2EventAckRequest_t *ack_request;
  634. u16 smid;
  635. mpi_reply = mpt2sas_base_get_reply_virt_addr(ioc, reply);
  636. if (!mpi_reply)
  637. return 1;
  638. if (mpi_reply->Function != MPI2_FUNCTION_EVENT_NOTIFICATION)
  639. return 1;
  640. #ifdef CONFIG_SCSI_MPT2SAS_LOGGING
  641. _base_display_event_data(ioc, mpi_reply);
  642. #endif
  643. if (!(mpi_reply->AckRequired & MPI2_EVENT_NOTIFICATION_ACK_REQUIRED))
  644. goto out;
  645. smid = mpt2sas_base_get_smid(ioc, ioc->base_cb_idx);
  646. if (!smid) {
  647. printk(MPT2SAS_ERR_FMT "%s: failed obtaining a smid\n",
  648. ioc->name, __func__);
  649. goto out;
  650. }
  651. ack_request = mpt2sas_base_get_msg_frame(ioc, smid);
  652. memset(ack_request, 0, sizeof(Mpi2EventAckRequest_t));
  653. ack_request->Function = MPI2_FUNCTION_EVENT_ACK;
  654. ack_request->Event = mpi_reply->Event;
  655. ack_request->EventContext = mpi_reply->EventContext;
  656. ack_request->VF_ID = 0; /* TODO */
  657. ack_request->VP_ID = 0;
  658. mpt2sas_base_put_smid_default(ioc, smid);
  659. out:
  660. /* scsih callback handler */
  661. mpt2sas_scsih_event_callback(ioc, msix_index, reply);
  662. /* ctl callback handler */
  663. mpt2sas_ctl_event_callback(ioc, msix_index, reply);
  664. return 1;
  665. }
  666. /**
  667. * _base_get_cb_idx - obtain the callback index
  668. * @ioc: per adapter object
  669. * @smid: system request message index
  670. *
  671. * Return callback index.
  672. */
  673. static u8
  674. _base_get_cb_idx(struct MPT2SAS_ADAPTER *ioc, u16 smid)
  675. {
  676. int i;
  677. u8 cb_idx = 0xFF;
  678. if (smid >= ioc->hi_priority_smid) {
  679. if (smid < ioc->internal_smid) {
  680. i = smid - ioc->hi_priority_smid;
  681. cb_idx = ioc->hpr_lookup[i].cb_idx;
  682. } else {
  683. i = smid - ioc->internal_smid;
  684. cb_idx = ioc->internal_lookup[i].cb_idx;
  685. }
  686. } else {
  687. i = smid - 1;
  688. cb_idx = ioc->scsi_lookup[i].cb_idx;
  689. }
  690. return cb_idx;
  691. }
  692. /**
  693. * _base_mask_interrupts - disable interrupts
  694. * @ioc: per adapter object
  695. *
  696. * Disabling ResetIRQ, Reply and Doorbell Interrupts
  697. *
  698. * Return nothing.
  699. */
  700. static void
  701. _base_mask_interrupts(struct MPT2SAS_ADAPTER *ioc)
  702. {
  703. u32 him_register;
  704. ioc->mask_interrupts = 1;
  705. him_register = readl(&ioc->chip->HostInterruptMask);
  706. him_register |= MPI2_HIM_DIM + MPI2_HIM_RIM + MPI2_HIM_RESET_IRQ_MASK;
  707. writel(him_register, &ioc->chip->HostInterruptMask);
  708. readl(&ioc->chip->HostInterruptMask);
  709. }
  710. /**
  711. * _base_unmask_interrupts - enable interrupts
  712. * @ioc: per adapter object
  713. *
  714. * Enabling only Reply Interrupts
  715. *
  716. * Return nothing.
  717. */
  718. static void
  719. _base_unmask_interrupts(struct MPT2SAS_ADAPTER *ioc)
  720. {
  721. u32 him_register;
  722. him_register = readl(&ioc->chip->HostInterruptMask);
  723. him_register &= ~MPI2_HIM_RIM;
  724. writel(him_register, &ioc->chip->HostInterruptMask);
  725. ioc->mask_interrupts = 0;
  726. }
  727. union reply_descriptor {
  728. u64 word;
  729. struct {
  730. u32 low;
  731. u32 high;
  732. } u;
  733. };
  734. /**
  735. * _base_interrupt - MPT adapter (IOC) specific interrupt handler.
  736. * @irq: irq number (not used)
  737. * @bus_id: bus identifier cookie == pointer to MPT_ADAPTER structure
  738. * @r: pt_regs pointer (not used)
  739. *
  740. * Return IRQ_HANDLE if processed, else IRQ_NONE.
  741. */
  742. static irqreturn_t
  743. _base_interrupt(int irq, void *bus_id)
  744. {
  745. union reply_descriptor rd;
  746. u32 completed_cmds;
  747. u8 request_desript_type;
  748. u16 smid;
  749. u8 cb_idx;
  750. u32 reply;
  751. u8 msix_index;
  752. struct MPT2SAS_ADAPTER *ioc = bus_id;
  753. Mpi2ReplyDescriptorsUnion_t *rpf;
  754. u8 rc;
  755. if (ioc->mask_interrupts)
  756. return IRQ_NONE;
  757. rpf = &ioc->reply_post_free[ioc->reply_post_host_index];
  758. request_desript_type = rpf->Default.ReplyFlags
  759. & MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK;
  760. if (request_desript_type == MPI2_RPY_DESCRIPT_FLAGS_UNUSED)
  761. return IRQ_NONE;
  762. completed_cmds = 0;
  763. do {
  764. rd.word = rpf->Words;
  765. if (rd.u.low == UINT_MAX || rd.u.high == UINT_MAX)
  766. goto out;
  767. reply = 0;
  768. cb_idx = 0xFF;
  769. smid = le16_to_cpu(rpf->Default.DescriptorTypeDependent1);
  770. msix_index = rpf->Default.MSIxIndex;
  771. if (request_desript_type ==
  772. MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY) {
  773. reply = le32_to_cpu
  774. (rpf->AddressReply.ReplyFrameAddress);
  775. } else if (request_desript_type ==
  776. MPI2_RPY_DESCRIPT_FLAGS_TARGET_COMMAND_BUFFER)
  777. goto next;
  778. else if (request_desript_type ==
  779. MPI2_RPY_DESCRIPT_FLAGS_TARGETASSIST_SUCCESS)
  780. goto next;
  781. if (smid)
  782. cb_idx = _base_get_cb_idx(ioc, smid);
  783. if (smid && cb_idx != 0xFF) {
  784. rc = mpt_callbacks[cb_idx](ioc, smid, msix_index,
  785. reply);
  786. if (reply)
  787. _base_display_reply_info(ioc, smid, msix_index,
  788. reply);
  789. if (rc)
  790. mpt2sas_base_free_smid(ioc, smid);
  791. }
  792. if (!smid)
  793. _base_async_event(ioc, msix_index, reply);
  794. /* reply free queue handling */
  795. if (reply) {
  796. ioc->reply_free_host_index =
  797. (ioc->reply_free_host_index ==
  798. (ioc->reply_free_queue_depth - 1)) ?
  799. 0 : ioc->reply_free_host_index + 1;
  800. ioc->reply_free[ioc->reply_free_host_index] =
  801. cpu_to_le32(reply);
  802. wmb();
  803. writel(ioc->reply_free_host_index,
  804. &ioc->chip->ReplyFreeHostIndex);
  805. }
  806. next:
  807. rpf->Words = ULLONG_MAX;
  808. ioc->reply_post_host_index = (ioc->reply_post_host_index ==
  809. (ioc->reply_post_queue_depth - 1)) ? 0 :
  810. ioc->reply_post_host_index + 1;
  811. request_desript_type =
  812. ioc->reply_post_free[ioc->reply_post_host_index].Default.
  813. ReplyFlags & MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK;
  814. completed_cmds++;
  815. if (request_desript_type == MPI2_RPY_DESCRIPT_FLAGS_UNUSED)
  816. goto out;
  817. if (!ioc->reply_post_host_index)
  818. rpf = ioc->reply_post_free;
  819. else
  820. rpf++;
  821. } while (1);
  822. out:
  823. if (!completed_cmds)
  824. return IRQ_NONE;
  825. wmb();
  826. writel(ioc->reply_post_host_index, &ioc->chip->ReplyPostHostIndex);
  827. return IRQ_HANDLED;
  828. }
  829. /**
  830. * mpt2sas_base_release_callback_handler - clear interupt callback handler
  831. * @cb_idx: callback index
  832. *
  833. * Return nothing.
  834. */
  835. void
  836. mpt2sas_base_release_callback_handler(u8 cb_idx)
  837. {
  838. mpt_callbacks[cb_idx] = NULL;
  839. }
  840. /**
  841. * mpt2sas_base_register_callback_handler - obtain index for the interrupt callback handler
  842. * @cb_func: callback function
  843. *
  844. * Returns cb_func.
  845. */
  846. u8
  847. mpt2sas_base_register_callback_handler(MPT_CALLBACK cb_func)
  848. {
  849. u8 cb_idx;
  850. for (cb_idx = MPT_MAX_CALLBACKS-1; cb_idx; cb_idx--)
  851. if (mpt_callbacks[cb_idx] == NULL)
  852. break;
  853. mpt_callbacks[cb_idx] = cb_func;
  854. return cb_idx;
  855. }
  856. /**
  857. * mpt2sas_base_initialize_callback_handler - initialize the interrupt callback handler
  858. *
  859. * Return nothing.
  860. */
  861. void
  862. mpt2sas_base_initialize_callback_handler(void)
  863. {
  864. u8 cb_idx;
  865. for (cb_idx = 0; cb_idx < MPT_MAX_CALLBACKS; cb_idx++)
  866. mpt2sas_base_release_callback_handler(cb_idx);
  867. }
  868. /**
  869. * mpt2sas_base_build_zero_len_sge - build zero length sg entry
  870. * @ioc: per adapter object
  871. * @paddr: virtual address for SGE
  872. *
  873. * Create a zero length scatter gather entry to insure the IOCs hardware has
  874. * something to use if the target device goes brain dead and tries
  875. * to send data even when none is asked for.
  876. *
  877. * Return nothing.
  878. */
  879. void
  880. mpt2sas_base_build_zero_len_sge(struct MPT2SAS_ADAPTER *ioc, void *paddr)
  881. {
  882. u32 flags_length = (u32)((MPI2_SGE_FLAGS_LAST_ELEMENT |
  883. MPI2_SGE_FLAGS_END_OF_BUFFER | MPI2_SGE_FLAGS_END_OF_LIST |
  884. MPI2_SGE_FLAGS_SIMPLE_ELEMENT) <<
  885. MPI2_SGE_FLAGS_SHIFT);
  886. ioc->base_add_sg_single(paddr, flags_length, -1);
  887. }
  888. /**
  889. * _base_add_sg_single_32 - Place a simple 32 bit SGE at address pAddr.
  890. * @paddr: virtual address for SGE
  891. * @flags_length: SGE flags and data transfer length
  892. * @dma_addr: Physical address
  893. *
  894. * Return nothing.
  895. */
  896. static void
  897. _base_add_sg_single_32(void *paddr, u32 flags_length, dma_addr_t dma_addr)
  898. {
  899. Mpi2SGESimple32_t *sgel = paddr;
  900. flags_length |= (MPI2_SGE_FLAGS_32_BIT_ADDRESSING |
  901. MPI2_SGE_FLAGS_SYSTEM_ADDRESS) << MPI2_SGE_FLAGS_SHIFT;
  902. sgel->FlagsLength = cpu_to_le32(flags_length);
  903. sgel->Address = cpu_to_le32(dma_addr);
  904. }
  905. /**
  906. * _base_add_sg_single_64 - Place a simple 64 bit SGE at address pAddr.
  907. * @paddr: virtual address for SGE
  908. * @flags_length: SGE flags and data transfer length
  909. * @dma_addr: Physical address
  910. *
  911. * Return nothing.
  912. */
  913. static void
  914. _base_add_sg_single_64(void *paddr, u32 flags_length, dma_addr_t dma_addr)
  915. {
  916. Mpi2SGESimple64_t *sgel = paddr;
  917. flags_length |= (MPI2_SGE_FLAGS_64_BIT_ADDRESSING |
  918. MPI2_SGE_FLAGS_SYSTEM_ADDRESS) << MPI2_SGE_FLAGS_SHIFT;
  919. sgel->FlagsLength = cpu_to_le32(flags_length);
  920. sgel->Address = cpu_to_le64(dma_addr);
  921. }
  922. #define convert_to_kb(x) ((x) << (PAGE_SHIFT - 10))
  923. /**
  924. * _base_config_dma_addressing - set dma addressing
  925. * @ioc: per adapter object
  926. * @pdev: PCI device struct
  927. *
  928. * Returns 0 for success, non-zero for failure.
  929. */
  930. static int
  931. _base_config_dma_addressing(struct MPT2SAS_ADAPTER *ioc, struct pci_dev *pdev)
  932. {
  933. struct sysinfo s;
  934. char *desc = NULL;
  935. if (sizeof(dma_addr_t) > 4) {
  936. const uint64_t required_mask =
  937. dma_get_required_mask(&pdev->dev);
  938. if ((required_mask > DMA_BIT_MASK(32)) && !pci_set_dma_mask(pdev,
  939. DMA_BIT_MASK(64)) && !pci_set_consistent_dma_mask(pdev,
  940. DMA_BIT_MASK(64))) {
  941. ioc->base_add_sg_single = &_base_add_sg_single_64;
  942. ioc->sge_size = sizeof(Mpi2SGESimple64_t);
  943. desc = "64";
  944. goto out;
  945. }
  946. }
  947. if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))
  948. && !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) {
  949. ioc->base_add_sg_single = &_base_add_sg_single_32;
  950. ioc->sge_size = sizeof(Mpi2SGESimple32_t);
  951. desc = "32";
  952. } else
  953. return -ENODEV;
  954. out:
  955. si_meminfo(&s);
  956. printk(MPT2SAS_INFO_FMT "%s BIT PCI BUS DMA ADDRESSING SUPPORTED, "
  957. "total mem (%ld kB)\n", ioc->name, desc, convert_to_kb(s.totalram));
  958. return 0;
  959. }
  960. /**
  961. * _base_save_msix_table - backup msix vector table
  962. * @ioc: per adapter object
  963. *
  964. * This address an errata where diag reset clears out the table
  965. */
  966. static void
  967. _base_save_msix_table(struct MPT2SAS_ADAPTER *ioc)
  968. {
  969. int i;
  970. if (!ioc->msix_enable || ioc->msix_table_backup == NULL)
  971. return;
  972. for (i = 0; i < ioc->msix_vector_count; i++)
  973. ioc->msix_table_backup[i] = ioc->msix_table[i];
  974. }
  975. /**
  976. * _base_restore_msix_table - this restores the msix vector table
  977. * @ioc: per adapter object
  978. *
  979. */
  980. static void
  981. _base_restore_msix_table(struct MPT2SAS_ADAPTER *ioc)
  982. {
  983. int i;
  984. if (!ioc->msix_enable || ioc->msix_table_backup == NULL)
  985. return;
  986. for (i = 0; i < ioc->msix_vector_count; i++)
  987. ioc->msix_table[i] = ioc->msix_table_backup[i];
  988. }
  989. /**
  990. * _base_check_enable_msix - checks MSIX capabable.
  991. * @ioc: per adapter object
  992. *
  993. * Check to see if card is capable of MSIX, and set number
  994. * of avaliable msix vectors
  995. */
  996. static int
  997. _base_check_enable_msix(struct MPT2SAS_ADAPTER *ioc)
  998. {
  999. int base;
  1000. u16 message_control;
  1001. u32 msix_table_offset;
  1002. base = pci_find_capability(ioc->pdev, PCI_CAP_ID_MSIX);
  1003. if (!base) {
  1004. dfailprintk(ioc, printk(MPT2SAS_INFO_FMT "msix not "
  1005. "supported\n", ioc->name));
  1006. return -EINVAL;
  1007. }
  1008. /* get msix vector count */
  1009. pci_read_config_word(ioc->pdev, base + 2, &message_control);
  1010. ioc->msix_vector_count = (message_control & 0x3FF) + 1;
  1011. /* get msix table */
  1012. pci_read_config_dword(ioc->pdev, base + 4, &msix_table_offset);
  1013. msix_table_offset &= 0xFFFFFFF8;
  1014. ioc->msix_table = (u32 *)((void *)ioc->chip + msix_table_offset);
  1015. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "msix is supported, "
  1016. "vector_count(%d), table_offset(0x%08x), table(%p)\n", ioc->name,
  1017. ioc->msix_vector_count, msix_table_offset, ioc->msix_table));
  1018. return 0;
  1019. }
  1020. /**
  1021. * _base_disable_msix - disables msix
  1022. * @ioc: per adapter object
  1023. *
  1024. */
  1025. static void
  1026. _base_disable_msix(struct MPT2SAS_ADAPTER *ioc)
  1027. {
  1028. if (ioc->msix_enable) {
  1029. pci_disable_msix(ioc->pdev);
  1030. kfree(ioc->msix_table_backup);
  1031. ioc->msix_table_backup = NULL;
  1032. ioc->msix_enable = 0;
  1033. }
  1034. }
  1035. /**
  1036. * _base_enable_msix - enables msix, failback to io_apic
  1037. * @ioc: per adapter object
  1038. *
  1039. */
  1040. static int
  1041. _base_enable_msix(struct MPT2SAS_ADAPTER *ioc)
  1042. {
  1043. struct msix_entry entries;
  1044. int r;
  1045. u8 try_msix = 0;
  1046. if (msix_disable == -1 || msix_disable == 0)
  1047. try_msix = 1;
  1048. if (!try_msix)
  1049. goto try_ioapic;
  1050. if (_base_check_enable_msix(ioc) != 0)
  1051. goto try_ioapic;
  1052. ioc->msix_table_backup = kcalloc(ioc->msix_vector_count,
  1053. sizeof(u32), GFP_KERNEL);
  1054. if (!ioc->msix_table_backup) {
  1055. dfailprintk(ioc, printk(MPT2SAS_INFO_FMT "allocation for "
  1056. "msix_table_backup failed!!!\n", ioc->name));
  1057. goto try_ioapic;
  1058. }
  1059. memset(&entries, 0, sizeof(struct msix_entry));
  1060. r = pci_enable_msix(ioc->pdev, &entries, 1);
  1061. if (r) {
  1062. dfailprintk(ioc, printk(MPT2SAS_INFO_FMT "pci_enable_msix "
  1063. "failed (r=%d) !!!\n", ioc->name, r));
  1064. goto try_ioapic;
  1065. }
  1066. r = request_irq(entries.vector, _base_interrupt, IRQF_SHARED,
  1067. ioc->name, ioc);
  1068. if (r) {
  1069. dfailprintk(ioc, printk(MPT2SAS_INFO_FMT "unable to allocate "
  1070. "interrupt %d !!!\n", ioc->name, entries.vector));
  1071. pci_disable_msix(ioc->pdev);
  1072. goto try_ioapic;
  1073. }
  1074. ioc->pci_irq = entries.vector;
  1075. ioc->msix_enable = 1;
  1076. return 0;
  1077. /* failback to io_apic interrupt routing */
  1078. try_ioapic:
  1079. r = request_irq(ioc->pdev->irq, _base_interrupt, IRQF_SHARED,
  1080. ioc->name, ioc);
  1081. if (r) {
  1082. printk(MPT2SAS_ERR_FMT "unable to allocate interrupt %d!\n",
  1083. ioc->name, ioc->pdev->irq);
  1084. r = -EBUSY;
  1085. goto out_fail;
  1086. }
  1087. ioc->pci_irq = ioc->pdev->irq;
  1088. return 0;
  1089. out_fail:
  1090. return r;
  1091. }
  1092. /**
  1093. * mpt2sas_base_map_resources - map in controller resources (io/irq/memap)
  1094. * @ioc: per adapter object
  1095. *
  1096. * Returns 0 for success, non-zero for failure.
  1097. */
  1098. int
  1099. mpt2sas_base_map_resources(struct MPT2SAS_ADAPTER *ioc)
  1100. {
  1101. struct pci_dev *pdev = ioc->pdev;
  1102. u32 memap_sz;
  1103. u32 pio_sz;
  1104. int i, r = 0;
  1105. u64 pio_chip = 0;
  1106. u64 chip_phys = 0;
  1107. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "%s\n",
  1108. ioc->name, __func__));
  1109. ioc->bars = pci_select_bars(pdev, IORESOURCE_MEM);
  1110. if (pci_enable_device_mem(pdev)) {
  1111. printk(MPT2SAS_WARN_FMT "pci_enable_device_mem: "
  1112. "failed\n", ioc->name);
  1113. return -ENODEV;
  1114. }
  1115. if (pci_request_selected_regions(pdev, ioc->bars,
  1116. MPT2SAS_DRIVER_NAME)) {
  1117. printk(MPT2SAS_WARN_FMT "pci_request_selected_regions: "
  1118. "failed\n", ioc->name);
  1119. r = -ENODEV;
  1120. goto out_fail;
  1121. }
  1122. /* AER (Advanced Error Reporting) hooks */
  1123. pci_enable_pcie_error_reporting(pdev);
  1124. pci_set_master(pdev);
  1125. if (_base_config_dma_addressing(ioc, pdev) != 0) {
  1126. printk(MPT2SAS_WARN_FMT "no suitable DMA mask for %s\n",
  1127. ioc->name, pci_name(pdev));
  1128. r = -ENODEV;
  1129. goto out_fail;
  1130. }
  1131. for (i = 0, memap_sz = 0, pio_sz = 0 ; i < DEVICE_COUNT_RESOURCE; i++) {
  1132. if (pci_resource_flags(pdev, i) & IORESOURCE_IO) {
  1133. if (pio_sz)
  1134. continue;
  1135. pio_chip = (u64)pci_resource_start(pdev, i);
  1136. pio_sz = pci_resource_len(pdev, i);
  1137. } else {
  1138. if (memap_sz)
  1139. continue;
  1140. /* verify memory resource is valid before using */
  1141. if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) {
  1142. ioc->chip_phys = pci_resource_start(pdev, i);
  1143. chip_phys = (u64)ioc->chip_phys;
  1144. memap_sz = pci_resource_len(pdev, i);
  1145. ioc->chip = ioremap(ioc->chip_phys, memap_sz);
  1146. if (ioc->chip == NULL) {
  1147. printk(MPT2SAS_ERR_FMT "unable to map "
  1148. "adapter memory!\n", ioc->name);
  1149. r = -EINVAL;
  1150. goto out_fail;
  1151. }
  1152. }
  1153. }
  1154. }
  1155. _base_mask_interrupts(ioc);
  1156. r = _base_enable_msix(ioc);
  1157. if (r)
  1158. goto out_fail;
  1159. printk(MPT2SAS_INFO_FMT "%s: IRQ %d\n",
  1160. ioc->name, ((ioc->msix_enable) ? "PCI-MSI-X enabled" :
  1161. "IO-APIC enabled"), ioc->pci_irq);
  1162. printk(MPT2SAS_INFO_FMT "iomem(0x%016llx), mapped(0x%p), size(%d)\n",
  1163. ioc->name, (unsigned long long)chip_phys, ioc->chip, memap_sz);
  1164. printk(MPT2SAS_INFO_FMT "ioport(0x%016llx), size(%d)\n",
  1165. ioc->name, (unsigned long long)pio_chip, pio_sz);
  1166. return 0;
  1167. out_fail:
  1168. if (ioc->chip_phys)
  1169. iounmap(ioc->chip);
  1170. ioc->chip_phys = 0;
  1171. ioc->pci_irq = -1;
  1172. pci_release_selected_regions(ioc->pdev, ioc->bars);
  1173. pci_disable_pcie_error_reporting(pdev);
  1174. pci_disable_device(pdev);
  1175. return r;
  1176. }
  1177. /**
  1178. * mpt2sas_base_get_msg_frame - obtain request mf pointer
  1179. * @ioc: per adapter object
  1180. * @smid: system request message index(smid zero is invalid)
  1181. *
  1182. * Returns virt pointer to message frame.
  1183. */
  1184. void *
  1185. mpt2sas_base_get_msg_frame(struct MPT2SAS_ADAPTER *ioc, u16 smid)
  1186. {
  1187. return (void *)(ioc->request + (smid * ioc->request_sz));
  1188. }
  1189. /**
  1190. * mpt2sas_base_get_sense_buffer - obtain a sense buffer assigned to a mf request
  1191. * @ioc: per adapter object
  1192. * @smid: system request message index
  1193. *
  1194. * Returns virt pointer to sense buffer.
  1195. */
  1196. void *
  1197. mpt2sas_base_get_sense_buffer(struct MPT2SAS_ADAPTER *ioc, u16 smid)
  1198. {
  1199. return (void *)(ioc->sense + ((smid - 1) * SCSI_SENSE_BUFFERSIZE));
  1200. }
  1201. /**
  1202. * mpt2sas_base_get_sense_buffer_dma - obtain a sense buffer assigned to a mf request
  1203. * @ioc: per adapter object
  1204. * @smid: system request message index
  1205. *
  1206. * Returns phys pointer to the low 32bit address of the sense buffer.
  1207. */
  1208. __le32
  1209. mpt2sas_base_get_sense_buffer_dma(struct MPT2SAS_ADAPTER *ioc, u16 smid)
  1210. {
  1211. return cpu_to_le32(ioc->sense_dma +
  1212. ((smid - 1) * SCSI_SENSE_BUFFERSIZE));
  1213. }
  1214. /**
  1215. * mpt2sas_base_get_reply_virt_addr - obtain reply frames virt address
  1216. * @ioc: per adapter object
  1217. * @phys_addr: lower 32 physical addr of the reply
  1218. *
  1219. * Converts 32bit lower physical addr into a virt address.
  1220. */
  1221. void *
  1222. mpt2sas_base_get_reply_virt_addr(struct MPT2SAS_ADAPTER *ioc, u32 phys_addr)
  1223. {
  1224. if (!phys_addr)
  1225. return NULL;
  1226. return ioc->reply + (phys_addr - (u32)ioc->reply_dma);
  1227. }
  1228. /**
  1229. * mpt2sas_base_get_smid - obtain a free smid from internal queue
  1230. * @ioc: per adapter object
  1231. * @cb_idx: callback index
  1232. *
  1233. * Returns smid (zero is invalid)
  1234. */
  1235. u16
  1236. mpt2sas_base_get_smid(struct MPT2SAS_ADAPTER *ioc, u8 cb_idx)
  1237. {
  1238. unsigned long flags;
  1239. struct request_tracker *request;
  1240. u16 smid;
  1241. spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
  1242. if (list_empty(&ioc->internal_free_list)) {
  1243. spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
  1244. printk(MPT2SAS_ERR_FMT "%s: smid not available\n",
  1245. ioc->name, __func__);
  1246. return 0;
  1247. }
  1248. request = list_entry(ioc->internal_free_list.next,
  1249. struct request_tracker, tracker_list);
  1250. request->cb_idx = cb_idx;
  1251. smid = request->smid;
  1252. list_del(&request->tracker_list);
  1253. spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
  1254. return smid;
  1255. }
  1256. /**
  1257. * mpt2sas_base_get_smid_scsiio - obtain a free smid from scsiio queue
  1258. * @ioc: per adapter object
  1259. * @cb_idx: callback index
  1260. * @scmd: pointer to scsi command object
  1261. *
  1262. * Returns smid (zero is invalid)
  1263. */
  1264. u16
  1265. mpt2sas_base_get_smid_scsiio(struct MPT2SAS_ADAPTER *ioc, u8 cb_idx,
  1266. struct scsi_cmnd *scmd)
  1267. {
  1268. unsigned long flags;
  1269. struct request_tracker *request;
  1270. u16 smid;
  1271. spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
  1272. if (list_empty(&ioc->free_list)) {
  1273. spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
  1274. printk(MPT2SAS_ERR_FMT "%s: smid not available\n",
  1275. ioc->name, __func__);
  1276. return 0;
  1277. }
  1278. request = list_entry(ioc->free_list.next,
  1279. struct request_tracker, tracker_list);
  1280. request->scmd = scmd;
  1281. request->cb_idx = cb_idx;
  1282. smid = request->smid;
  1283. list_del(&request->tracker_list);
  1284. spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
  1285. return smid;
  1286. }
  1287. /**
  1288. * mpt2sas_base_get_smid_hpr - obtain a free smid from hi-priority queue
  1289. * @ioc: per adapter object
  1290. * @cb_idx: callback index
  1291. *
  1292. * Returns smid (zero is invalid)
  1293. */
  1294. u16
  1295. mpt2sas_base_get_smid_hpr(struct MPT2SAS_ADAPTER *ioc, u8 cb_idx)
  1296. {
  1297. unsigned long flags;
  1298. struct request_tracker *request;
  1299. u16 smid;
  1300. spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
  1301. if (list_empty(&ioc->hpr_free_list)) {
  1302. spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
  1303. return 0;
  1304. }
  1305. request = list_entry(ioc->hpr_free_list.next,
  1306. struct request_tracker, tracker_list);
  1307. request->cb_idx = cb_idx;
  1308. smid = request->smid;
  1309. list_del(&request->tracker_list);
  1310. spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
  1311. return smid;
  1312. }
  1313. /**
  1314. * mpt2sas_base_free_smid - put smid back on free_list
  1315. * @ioc: per adapter object
  1316. * @smid: system request message index
  1317. *
  1318. * Return nothing.
  1319. */
  1320. void
  1321. mpt2sas_base_free_smid(struct MPT2SAS_ADAPTER *ioc, u16 smid)
  1322. {
  1323. unsigned long flags;
  1324. int i;
  1325. spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
  1326. if (smid >= ioc->hi_priority_smid) {
  1327. if (smid < ioc->internal_smid) {
  1328. /* hi-priority */
  1329. i = smid - ioc->hi_priority_smid;
  1330. ioc->hpr_lookup[i].cb_idx = 0xFF;
  1331. list_add_tail(&ioc->hpr_lookup[i].tracker_list,
  1332. &ioc->hpr_free_list);
  1333. } else {
  1334. /* internal queue */
  1335. i = smid - ioc->internal_smid;
  1336. ioc->internal_lookup[i].cb_idx = 0xFF;
  1337. list_add_tail(&ioc->internal_lookup[i].tracker_list,
  1338. &ioc->internal_free_list);
  1339. }
  1340. spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
  1341. return;
  1342. }
  1343. /* scsiio queue */
  1344. i = smid - 1;
  1345. ioc->scsi_lookup[i].cb_idx = 0xFF;
  1346. ioc->scsi_lookup[i].scmd = NULL;
  1347. list_add_tail(&ioc->scsi_lookup[i].tracker_list,
  1348. &ioc->free_list);
  1349. spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
  1350. /*
  1351. * See _wait_for_commands_to_complete() call with regards to this code.
  1352. */
  1353. if (ioc->shost_recovery && ioc->pending_io_count) {
  1354. if (ioc->pending_io_count == 1)
  1355. wake_up(&ioc->reset_wq);
  1356. ioc->pending_io_count--;
  1357. }
  1358. }
  1359. /**
  1360. * _base_writeq - 64 bit write to MMIO
  1361. * @ioc: per adapter object
  1362. * @b: data payload
  1363. * @addr: address in MMIO space
  1364. * @writeq_lock: spin lock
  1365. *
  1366. * Glue for handling an atomic 64 bit word to MMIO. This special handling takes
  1367. * care of 32 bit environment where its not quarenteed to send the entire word
  1368. * in one transfer.
  1369. */
  1370. #ifndef writeq
  1371. static inline void _base_writeq(__u64 b, volatile void __iomem *addr,
  1372. spinlock_t *writeq_lock)
  1373. {
  1374. unsigned long flags;
  1375. __u64 data_out = cpu_to_le64(b);
  1376. spin_lock_irqsave(writeq_lock, flags);
  1377. writel((u32)(data_out), addr);
  1378. writel((u32)(data_out >> 32), (addr + 4));
  1379. spin_unlock_irqrestore(writeq_lock, flags);
  1380. }
  1381. #else
  1382. static inline void _base_writeq(__u64 b, volatile void __iomem *addr,
  1383. spinlock_t *writeq_lock)
  1384. {
  1385. writeq(cpu_to_le64(b), addr);
  1386. }
  1387. #endif
  1388. /**
  1389. * mpt2sas_base_put_smid_scsi_io - send SCSI_IO request to firmware
  1390. * @ioc: per adapter object
  1391. * @smid: system request message index
  1392. * @handle: device handle
  1393. *
  1394. * Return nothing.
  1395. */
  1396. void
  1397. mpt2sas_base_put_smid_scsi_io(struct MPT2SAS_ADAPTER *ioc, u16 smid, u16 handle)
  1398. {
  1399. Mpi2RequestDescriptorUnion_t descriptor;
  1400. u64 *request = (u64 *)&descriptor;
  1401. descriptor.SCSIIO.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO;
  1402. descriptor.SCSIIO.MSIxIndex = 0; /* TODO */
  1403. descriptor.SCSIIO.SMID = cpu_to_le16(smid);
  1404. descriptor.SCSIIO.DevHandle = cpu_to_le16(handle);
  1405. descriptor.SCSIIO.LMID = 0;
  1406. _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
  1407. &ioc->scsi_lookup_lock);
  1408. }
  1409. /**
  1410. * mpt2sas_base_put_smid_hi_priority - send Task Managment request to firmware
  1411. * @ioc: per adapter object
  1412. * @smid: system request message index
  1413. *
  1414. * Return nothing.
  1415. */
  1416. void
  1417. mpt2sas_base_put_smid_hi_priority(struct MPT2SAS_ADAPTER *ioc, u16 smid)
  1418. {
  1419. Mpi2RequestDescriptorUnion_t descriptor;
  1420. u64 *request = (u64 *)&descriptor;
  1421. descriptor.HighPriority.RequestFlags =
  1422. MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY;
  1423. descriptor.HighPriority.MSIxIndex = 0; /* TODO */
  1424. descriptor.HighPriority.SMID = cpu_to_le16(smid);
  1425. descriptor.HighPriority.LMID = 0;
  1426. descriptor.HighPriority.Reserved1 = 0;
  1427. _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
  1428. &ioc->scsi_lookup_lock);
  1429. }
  1430. /**
  1431. * mpt2sas_base_put_smid_default - Default, primarily used for config pages
  1432. * @ioc: per adapter object
  1433. * @smid: system request message index
  1434. *
  1435. * Return nothing.
  1436. */
  1437. void
  1438. mpt2sas_base_put_smid_default(struct MPT2SAS_ADAPTER *ioc, u16 smid)
  1439. {
  1440. Mpi2RequestDescriptorUnion_t descriptor;
  1441. u64 *request = (u64 *)&descriptor;
  1442. descriptor.Default.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE;
  1443. descriptor.Default.MSIxIndex = 0; /* TODO */
  1444. descriptor.Default.SMID = cpu_to_le16(smid);
  1445. descriptor.Default.LMID = 0;
  1446. descriptor.Default.DescriptorTypeDependent = 0;
  1447. _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
  1448. &ioc->scsi_lookup_lock);
  1449. }
  1450. /**
  1451. * mpt2sas_base_put_smid_target_assist - send Target Assist/Status to firmware
  1452. * @ioc: per adapter object
  1453. * @smid: system request message index
  1454. * @io_index: value used to track the IO
  1455. *
  1456. * Return nothing.
  1457. */
  1458. void
  1459. mpt2sas_base_put_smid_target_assist(struct MPT2SAS_ADAPTER *ioc, u16 smid,
  1460. u16 io_index)
  1461. {
  1462. Mpi2RequestDescriptorUnion_t descriptor;
  1463. u64 *request = (u64 *)&descriptor;
  1464. descriptor.SCSITarget.RequestFlags =
  1465. MPI2_REQ_DESCRIPT_FLAGS_SCSI_TARGET;
  1466. descriptor.SCSITarget.MSIxIndex = 0; /* TODO */
  1467. descriptor.SCSITarget.SMID = cpu_to_le16(smid);
  1468. descriptor.SCSITarget.LMID = 0;
  1469. descriptor.SCSITarget.IoIndex = cpu_to_le16(io_index);
  1470. _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
  1471. &ioc->scsi_lookup_lock);
  1472. }
  1473. /**
  1474. * _base_display_dell_branding - Disply branding string
  1475. * @ioc: per adapter object
  1476. *
  1477. * Return nothing.
  1478. */
  1479. static void
  1480. _base_display_dell_branding(struct MPT2SAS_ADAPTER *ioc)
  1481. {
  1482. char dell_branding[MPT2SAS_DELL_BRANDING_SIZE];
  1483. if (ioc->pdev->subsystem_vendor != PCI_VENDOR_ID_DELL)
  1484. return;
  1485. memset(dell_branding, 0, MPT2SAS_DELL_BRANDING_SIZE);
  1486. switch (ioc->pdev->subsystem_device) {
  1487. case MPT2SAS_DELL_6GBPS_SAS_HBA_SSDID:
  1488. strncpy(dell_branding, MPT2SAS_DELL_6GBPS_SAS_HBA_BRANDING,
  1489. MPT2SAS_DELL_BRANDING_SIZE - 1);
  1490. break;
  1491. case MPT2SAS_DELL_PERC_H200_ADAPTER_SSDID:
  1492. strncpy(dell_branding, MPT2SAS_DELL_PERC_H200_ADAPTER_BRANDING,
  1493. MPT2SAS_DELL_BRANDING_SIZE - 1);
  1494. break;
  1495. case MPT2SAS_DELL_PERC_H200_INTEGRATED_SSDID:
  1496. strncpy(dell_branding,
  1497. MPT2SAS_DELL_PERC_H200_INTEGRATED_BRANDING,
  1498. MPT2SAS_DELL_BRANDING_SIZE - 1);
  1499. break;
  1500. case MPT2SAS_DELL_PERC_H200_MODULAR_SSDID:
  1501. strncpy(dell_branding,
  1502. MPT2SAS_DELL_PERC_H200_MODULAR_BRANDING,
  1503. MPT2SAS_DELL_BRANDING_SIZE - 1);
  1504. break;
  1505. case MPT2SAS_DELL_PERC_H200_EMBEDDED_SSDID:
  1506. strncpy(dell_branding,
  1507. MPT2SAS_DELL_PERC_H200_EMBEDDED_BRANDING,
  1508. MPT2SAS_DELL_BRANDING_SIZE - 1);
  1509. break;
  1510. case MPT2SAS_DELL_PERC_H200_SSDID:
  1511. strncpy(dell_branding, MPT2SAS_DELL_PERC_H200_BRANDING,
  1512. MPT2SAS_DELL_BRANDING_SIZE - 1);
  1513. break;
  1514. case MPT2SAS_DELL_6GBPS_SAS_SSDID:
  1515. strncpy(dell_branding, MPT2SAS_DELL_6GBPS_SAS_BRANDING,
  1516. MPT2SAS_DELL_BRANDING_SIZE - 1);
  1517. break;
  1518. default:
  1519. sprintf(dell_branding, "0x%4X", ioc->pdev->subsystem_device);
  1520. break;
  1521. }
  1522. printk(MPT2SAS_INFO_FMT "%s: Vendor(0x%04X), Device(0x%04X),"
  1523. " SSVID(0x%04X), SSDID(0x%04X)\n", ioc->name, dell_branding,
  1524. ioc->pdev->vendor, ioc->pdev->device, ioc->pdev->subsystem_vendor,
  1525. ioc->pdev->subsystem_device);
  1526. }
  1527. /**
  1528. * _base_display_ioc_capabilities - Disply IOC's capabilities.
  1529. * @ioc: per adapter object
  1530. *
  1531. * Return nothing.
  1532. */
  1533. static void
  1534. _base_display_ioc_capabilities(struct MPT2SAS_ADAPTER *ioc)
  1535. {
  1536. int i = 0;
  1537. char desc[16];
  1538. u8 revision;
  1539. u32 iounit_pg1_flags;
  1540. pci_read_config_byte(ioc->pdev, PCI_CLASS_REVISION, &revision);
  1541. strncpy(desc, ioc->manu_pg0.ChipName, 16);
  1542. printk(MPT2SAS_INFO_FMT "%s: FWVersion(%02d.%02d.%02d.%02d), "
  1543. "ChipRevision(0x%02x), BiosVersion(%02d.%02d.%02d.%02d)\n",
  1544. ioc->name, desc,
  1545. (ioc->facts.FWVersion.Word & 0xFF000000) >> 24,
  1546. (ioc->facts.FWVersion.Word & 0x00FF0000) >> 16,
  1547. (ioc->facts.FWVersion.Word & 0x0000FF00) >> 8,
  1548. ioc->facts.FWVersion.Word & 0x000000FF,
  1549. revision,
  1550. (ioc->bios_pg3.BiosVersion & 0xFF000000) >> 24,
  1551. (ioc->bios_pg3.BiosVersion & 0x00FF0000) >> 16,
  1552. (ioc->bios_pg3.BiosVersion & 0x0000FF00) >> 8,
  1553. ioc->bios_pg3.BiosVersion & 0x000000FF);
  1554. _base_display_dell_branding(ioc);
  1555. printk(MPT2SAS_INFO_FMT "Protocol=(", ioc->name);
  1556. if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_SCSI_INITIATOR) {
  1557. printk("Initiator");
  1558. i++;
  1559. }
  1560. if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_SCSI_TARGET) {
  1561. printk("%sTarget", i ? "," : "");
  1562. i++;
  1563. }
  1564. i = 0;
  1565. printk("), ");
  1566. printk("Capabilities=(");
  1567. if (ioc->facts.IOCCapabilities &
  1568. MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID) {
  1569. printk("Raid");
  1570. i++;
  1571. }
  1572. if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_TLR) {
  1573. printk("%sTLR", i ? "," : "");
  1574. i++;
  1575. }
  1576. if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_MULTICAST) {
  1577. printk("%sMulticast", i ? "," : "");
  1578. i++;
  1579. }
  1580. if (ioc->facts.IOCCapabilities &
  1581. MPI2_IOCFACTS_CAPABILITY_BIDIRECTIONAL_TARGET) {
  1582. printk("%sBIDI Target", i ? "," : "");
  1583. i++;
  1584. }
  1585. if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_EEDP) {
  1586. printk("%sEEDP", i ? "," : "");
  1587. i++;
  1588. }
  1589. if (ioc->facts.IOCCapabilities &
  1590. MPI2_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER) {
  1591. printk("%sSnapshot Buffer", i ? "," : "");
  1592. i++;
  1593. }
  1594. if (ioc->facts.IOCCapabilities &
  1595. MPI2_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER) {
  1596. printk("%sDiag Trace Buffer", i ? "," : "");
  1597. i++;
  1598. }
  1599. if (ioc->facts.IOCCapabilities &
  1600. MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER) {
  1601. printk(KERN_INFO "%sDiag Extended Buffer", i ? "," : "");
  1602. i++;
  1603. }
  1604. if (ioc->facts.IOCCapabilities &
  1605. MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING) {
  1606. printk("%sTask Set Full", i ? "," : "");
  1607. i++;
  1608. }
  1609. iounit_pg1_flags = le32_to_cpu(ioc->iounit_pg1.Flags);
  1610. if (!(iounit_pg1_flags & MPI2_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE)) {
  1611. printk("%sNCQ", i ? "," : "");
  1612. i++;
  1613. }
  1614. printk(")\n");
  1615. }
  1616. /**
  1617. * _base_static_config_pages - static start of day config pages
  1618. * @ioc: per adapter object
  1619. *
  1620. * Return nothing.
  1621. */
  1622. static void
  1623. _base_static_config_pages(struct MPT2SAS_ADAPTER *ioc)
  1624. {
  1625. Mpi2ConfigReply_t mpi_reply;
  1626. u32 iounit_pg1_flags;
  1627. mpt2sas_config_get_manufacturing_pg0(ioc, &mpi_reply, &ioc->manu_pg0);
  1628. if (ioc->ir_firmware)
  1629. mpt2sas_config_get_manufacturing_pg10(ioc, &mpi_reply,
  1630. &ioc->manu_pg10);
  1631. mpt2sas_config_get_bios_pg2(ioc, &mpi_reply, &ioc->bios_pg2);
  1632. mpt2sas_config_get_bios_pg3(ioc, &mpi_reply, &ioc->bios_pg3);
  1633. mpt2sas_config_get_ioc_pg8(ioc, &mpi_reply, &ioc->ioc_pg8);
  1634. mpt2sas_config_get_iounit_pg0(ioc, &mpi_reply, &ioc->iounit_pg0);
  1635. mpt2sas_config_get_iounit_pg1(ioc, &mpi_reply, &ioc->iounit_pg1);
  1636. _base_display_ioc_capabilities(ioc);
  1637. /*
  1638. * Enable task_set_full handling in iounit_pg1 when the
  1639. * facts capabilities indicate that its supported.
  1640. */
  1641. iounit_pg1_flags = le32_to_cpu(ioc->iounit_pg1.Flags);
  1642. if ((ioc->facts.IOCCapabilities &
  1643. MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING))
  1644. iounit_pg1_flags &=
  1645. ~MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING;
  1646. else
  1647. iounit_pg1_flags |=
  1648. MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING;
  1649. ioc->iounit_pg1.Flags = cpu_to_le32(iounit_pg1_flags);
  1650. mpt2sas_config_set_iounit_pg1(ioc, &mpi_reply, &ioc->iounit_pg1);
  1651. }
  1652. /**
  1653. * _base_release_memory_pools - release memory
  1654. * @ioc: per adapter object
  1655. *
  1656. * Free memory allocated from _base_allocate_memory_pools.
  1657. *
  1658. * Return nothing.
  1659. */
  1660. static void
  1661. _base_release_memory_pools(struct MPT2SAS_ADAPTER *ioc)
  1662. {
  1663. dexitprintk(ioc, printk(MPT2SAS_INFO_FMT "%s\n", ioc->name,
  1664. __func__));
  1665. if (ioc->request) {
  1666. pci_free_consistent(ioc->pdev, ioc->request_dma_sz,
  1667. ioc->request, ioc->request_dma);
  1668. dexitprintk(ioc, printk(MPT2SAS_INFO_FMT "request_pool(0x%p)"
  1669. ": free\n", ioc->name, ioc->request));
  1670. ioc->request = NULL;
  1671. }
  1672. if (ioc->sense) {
  1673. pci_pool_free(ioc->sense_dma_pool, ioc->sense, ioc->sense_dma);
  1674. if (ioc->sense_dma_pool)
  1675. pci_pool_destroy(ioc->sense_dma_pool);
  1676. dexitprintk(ioc, printk(MPT2SAS_INFO_FMT "sense_pool(0x%p)"
  1677. ": free\n", ioc->name, ioc->sense));
  1678. ioc->sense = NULL;
  1679. }
  1680. if (ioc->reply) {
  1681. pci_pool_free(ioc->reply_dma_pool, ioc->reply, ioc->reply_dma);
  1682. if (ioc->reply_dma_pool)
  1683. pci_pool_destroy(ioc->reply_dma_pool);
  1684. dexitprintk(ioc, printk(MPT2SAS_INFO_FMT "reply_pool(0x%p)"
  1685. ": free\n", ioc->name, ioc->reply));
  1686. ioc->reply = NULL;
  1687. }
  1688. if (ioc->reply_free) {
  1689. pci_pool_free(ioc->reply_free_dma_pool, ioc->reply_free,
  1690. ioc->reply_free_dma);
  1691. if (ioc->reply_free_dma_pool)
  1692. pci_pool_destroy(ioc->reply_free_dma_pool);
  1693. dexitprintk(ioc, printk(MPT2SAS_INFO_FMT "reply_free_pool"
  1694. "(0x%p): free\n", ioc->name, ioc->reply_free));
  1695. ioc->reply_free = NULL;
  1696. }
  1697. if (ioc->reply_post_free) {
  1698. pci_pool_free(ioc->reply_post_free_dma_pool,
  1699. ioc->reply_post_free, ioc->reply_post_free_dma);
  1700. if (ioc->reply_post_free_dma_pool)
  1701. pci_pool_destroy(ioc->reply_post_free_dma_pool);
  1702. dexitprintk(ioc, printk(MPT2SAS_INFO_FMT
  1703. "reply_post_free_pool(0x%p): free\n", ioc->name,
  1704. ioc->reply_post_free));
  1705. ioc->reply_post_free = NULL;
  1706. }
  1707. if (ioc->config_page) {
  1708. dexitprintk(ioc, printk(MPT2SAS_INFO_FMT
  1709. "config_page(0x%p): free\n", ioc->name,
  1710. ioc->config_page));
  1711. pci_free_consistent(ioc->pdev, ioc->config_page_sz,
  1712. ioc->config_page, ioc->config_page_dma);
  1713. }
  1714. if (ioc->scsi_lookup) {
  1715. free_pages((ulong)ioc->scsi_lookup, ioc->scsi_lookup_pages);
  1716. ioc->scsi_lookup = NULL;
  1717. }
  1718. kfree(ioc->hpr_lookup);
  1719. kfree(ioc->internal_lookup);
  1720. }
  1721. /**
  1722. * _base_allocate_memory_pools - allocate start of day memory pools
  1723. * @ioc: per adapter object
  1724. * @sleep_flag: CAN_SLEEP or NO_SLEEP
  1725. *
  1726. * Returns 0 success, anything else error
  1727. */
  1728. static int
  1729. _base_allocate_memory_pools(struct MPT2SAS_ADAPTER *ioc, int sleep_flag)
  1730. {
  1731. Mpi2IOCFactsReply_t *facts;
  1732. u32 queue_size, queue_diff;
  1733. u16 max_sge_elements;
  1734. u16 num_of_reply_frames;
  1735. u16 chains_needed_per_io;
  1736. u32 sz, total_sz;
  1737. u32 retry_sz;
  1738. u16 max_request_credit;
  1739. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "%s\n", ioc->name,
  1740. __func__));
  1741. retry_sz = 0;
  1742. facts = &ioc->facts;
  1743. /* command line tunables for max sgl entries */
  1744. if (max_sgl_entries != -1) {
  1745. ioc->shost->sg_tablesize = (max_sgl_entries <
  1746. MPT2SAS_SG_DEPTH) ? max_sgl_entries :
  1747. MPT2SAS_SG_DEPTH;
  1748. } else {
  1749. ioc->shost->sg_tablesize = MPT2SAS_SG_DEPTH;
  1750. }
  1751. /* command line tunables for max controller queue depth */
  1752. if (max_queue_depth != -1) {
  1753. max_request_credit = (max_queue_depth < facts->RequestCredit)
  1754. ? max_queue_depth : facts->RequestCredit;
  1755. } else {
  1756. max_request_credit = (facts->RequestCredit >
  1757. MPT2SAS_MAX_REQUEST_QUEUE) ? MPT2SAS_MAX_REQUEST_QUEUE :
  1758. facts->RequestCredit;
  1759. }
  1760. ioc->hba_queue_depth = max_request_credit;
  1761. ioc->hi_priority_depth = facts->HighPriorityCredit;
  1762. ioc->internal_depth = ioc->hi_priority_depth + 5;
  1763. /* request frame size */
  1764. ioc->request_sz = facts->IOCRequestFrameSize * 4;
  1765. /* reply frame size */
  1766. ioc->reply_sz = facts->ReplyFrameSize * 4;
  1767. retry_allocation:
  1768. total_sz = 0;
  1769. /* calculate number of sg elements left over in the 1st frame */
  1770. max_sge_elements = ioc->request_sz - ((sizeof(Mpi2SCSIIORequest_t) -
  1771. sizeof(Mpi2SGEIOUnion_t)) + ioc->sge_size);
  1772. ioc->max_sges_in_main_message = max_sge_elements/ioc->sge_size;
  1773. /* now do the same for a chain buffer */
  1774. max_sge_elements = ioc->request_sz - ioc->sge_size;
  1775. ioc->max_sges_in_chain_message = max_sge_elements/ioc->sge_size;
  1776. ioc->chain_offset_value_for_main_message =
  1777. ((sizeof(Mpi2SCSIIORequest_t) - sizeof(Mpi2SGEIOUnion_t)) +
  1778. (ioc->max_sges_in_chain_message * ioc->sge_size)) / 4;
  1779. /*
  1780. * MPT2SAS_SG_DEPTH = CONFIG_FUSION_MAX_SGE
  1781. */
  1782. chains_needed_per_io = ((ioc->shost->sg_tablesize -
  1783. ioc->max_sges_in_main_message)/ioc->max_sges_in_chain_message)
  1784. + 1;
  1785. if (chains_needed_per_io > facts->MaxChainDepth) {
  1786. chains_needed_per_io = facts->MaxChainDepth;
  1787. ioc->shost->sg_tablesize = min_t(u16,
  1788. ioc->max_sges_in_main_message + (ioc->max_sges_in_chain_message
  1789. * chains_needed_per_io), ioc->shost->sg_tablesize);
  1790. }
  1791. ioc->chains_needed_per_io = chains_needed_per_io;
  1792. /* reply free queue sizing - taking into account for events */
  1793. num_of_reply_frames = ioc->hba_queue_depth + 32;
  1794. /* number of replies frames can't be a multiple of 16 */
  1795. /* decrease number of reply frames by 1 */
  1796. if (!(num_of_reply_frames % 16))
  1797. num_of_reply_frames--;
  1798. /* calculate number of reply free queue entries
  1799. * (must be multiple of 16)
  1800. */
  1801. /* (we know reply_free_queue_depth is not a multiple of 16) */
  1802. queue_size = num_of_reply_frames;
  1803. queue_size += 16 - (queue_size % 16);
  1804. ioc->reply_free_queue_depth = queue_size;
  1805. /* reply descriptor post queue sizing */
  1806. /* this size should be the number of request frames + number of reply
  1807. * frames
  1808. */
  1809. queue_size = ioc->hba_queue_depth + num_of_reply_frames + 1;
  1810. /* round up to 16 byte boundary */
  1811. if (queue_size % 16)
  1812. queue_size += 16 - (queue_size % 16);
  1813. /* check against IOC maximum reply post queue depth */
  1814. if (queue_size > facts->MaxReplyDescriptorPostQueueDepth) {
  1815. queue_diff = queue_size -
  1816. facts->MaxReplyDescriptorPostQueueDepth;
  1817. /* round queue_diff up to multiple of 16 */
  1818. if (queue_diff % 16)
  1819. queue_diff += 16 - (queue_diff % 16);
  1820. /* adjust hba_queue_depth, reply_free_queue_depth,
  1821. * and queue_size
  1822. */
  1823. ioc->hba_queue_depth -= queue_diff;
  1824. ioc->reply_free_queue_depth -= queue_diff;
  1825. queue_size -= queue_diff;
  1826. }
  1827. ioc->reply_post_queue_depth = queue_size;
  1828. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "scatter gather: "
  1829. "sge_in_main_msg(%d), sge_per_chain(%d), sge_per_io(%d), "
  1830. "chains_per_io(%d)\n", ioc->name, ioc->max_sges_in_main_message,
  1831. ioc->max_sges_in_chain_message, ioc->shost->sg_tablesize,
  1832. ioc->chains_needed_per_io));
  1833. ioc->scsiio_depth = ioc->hba_queue_depth -
  1834. ioc->hi_priority_depth - ioc->internal_depth;
  1835. /* set the scsi host can_queue depth
  1836. * with some internal commands that could be outstanding
  1837. */
  1838. ioc->shost->can_queue = ioc->scsiio_depth - (2);
  1839. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "scsi host: "
  1840. "can_queue depth (%d)\n", ioc->name, ioc->shost->can_queue));
  1841. /* contiguous pool for request and chains, 16 byte align, one extra "
  1842. * "frame for smid=0
  1843. */
  1844. ioc->chain_depth = ioc->chains_needed_per_io * ioc->scsiio_depth;
  1845. sz = ((ioc->scsiio_depth + 1 + ioc->chain_depth) * ioc->request_sz);
  1846. /* hi-priority queue */
  1847. sz += (ioc->hi_priority_depth * ioc->request_sz);
  1848. /* internal queue */
  1849. sz += (ioc->internal_depth * ioc->request_sz);
  1850. ioc->request_dma_sz = sz;
  1851. ioc->request = pci_alloc_consistent(ioc->pdev, sz, &ioc->request_dma);
  1852. if (!ioc->request) {
  1853. printk(MPT2SAS_ERR_FMT "request pool: pci_alloc_consistent "
  1854. "failed: hba_depth(%d), chains_per_io(%d), frame_sz(%d), "
  1855. "total(%d kB)\n", ioc->name, ioc->hba_queue_depth,
  1856. ioc->chains_needed_per_io, ioc->request_sz, sz/1024);
  1857. if (ioc->scsiio_depth < MPT2SAS_SAS_QUEUE_DEPTH)
  1858. goto out;
  1859. retry_sz += 64;
  1860. ioc->hba_queue_depth = max_request_credit - retry_sz;
  1861. goto retry_allocation;
  1862. }
  1863. if (retry_sz)
  1864. printk(MPT2SAS_ERR_FMT "request pool: pci_alloc_consistent "
  1865. "succeed: hba_depth(%d), chains_per_io(%d), frame_sz(%d), "
  1866. "total(%d kb)\n", ioc->name, ioc->hba_queue_depth,
  1867. ioc->chains_needed_per_io, ioc->request_sz, sz/1024);
  1868. /* hi-priority queue */
  1869. ioc->hi_priority = ioc->request + ((ioc->scsiio_depth + 1) *
  1870. ioc->request_sz);
  1871. ioc->hi_priority_dma = ioc->request_dma + ((ioc->scsiio_depth + 1) *
  1872. ioc->request_sz);
  1873. /* internal queue */
  1874. ioc->internal = ioc->hi_priority + (ioc->hi_priority_depth *
  1875. ioc->request_sz);
  1876. ioc->internal_dma = ioc->hi_priority_dma + (ioc->hi_priority_depth *
  1877. ioc->request_sz);
  1878. ioc->chain = ioc->internal + (ioc->internal_depth *
  1879. ioc->request_sz);
  1880. ioc->chain_dma = ioc->internal_dma + (ioc->internal_depth *
  1881. ioc->request_sz);
  1882. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "request pool(0x%p): "
  1883. "depth(%d), frame_size(%d), pool_size(%d kB)\n", ioc->name,
  1884. ioc->request, ioc->hba_queue_depth, ioc->request_sz,
  1885. (ioc->hba_queue_depth * ioc->request_sz)/1024));
  1886. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "chain pool(0x%p): depth"
  1887. "(%d), frame_size(%d), pool_size(%d kB)\n", ioc->name, ioc->chain,
  1888. ioc->chain_depth, ioc->request_sz, ((ioc->chain_depth *
  1889. ioc->request_sz))/1024));
  1890. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "request pool: dma(0x%llx)\n",
  1891. ioc->name, (unsigned long long) ioc->request_dma));
  1892. total_sz += sz;
  1893. sz = ioc->scsiio_depth * sizeof(struct request_tracker);
  1894. ioc->scsi_lookup_pages = get_order(sz);
  1895. ioc->scsi_lookup = (struct request_tracker *)__get_free_pages(
  1896. GFP_KERNEL, ioc->scsi_lookup_pages);
  1897. if (!ioc->scsi_lookup) {
  1898. printk(MPT2SAS_ERR_FMT "scsi_lookup: get_free_pages failed, "
  1899. "sz(%d)\n", ioc->name, (int)sz);
  1900. goto out;
  1901. }
  1902. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "scsiio(0x%p): "
  1903. "depth(%d)\n", ioc->name, ioc->request,
  1904. ioc->scsiio_depth));
  1905. /* initialize hi-priority queue smid's */
  1906. ioc->hpr_lookup = kcalloc(ioc->hi_priority_depth,
  1907. sizeof(struct request_tracker), GFP_KERNEL);
  1908. if (!ioc->hpr_lookup) {
  1909. printk(MPT2SAS_ERR_FMT "hpr_lookup: kcalloc failed\n",
  1910. ioc->name);
  1911. goto out;
  1912. }
  1913. ioc->hi_priority_smid = ioc->scsiio_depth + 1;
  1914. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "hi_priority(0x%p): "
  1915. "depth(%d), start smid(%d)\n", ioc->name, ioc->hi_priority,
  1916. ioc->hi_priority_depth, ioc->hi_priority_smid));
  1917. /* initialize internal queue smid's */
  1918. ioc->internal_lookup = kcalloc(ioc->internal_depth,
  1919. sizeof(struct request_tracker), GFP_KERNEL);
  1920. if (!ioc->internal_lookup) {
  1921. printk(MPT2SAS_ERR_FMT "internal_lookup: kcalloc failed\n",
  1922. ioc->name);
  1923. goto out;
  1924. }
  1925. ioc->internal_smid = ioc->hi_priority_smid + ioc->hi_priority_depth;
  1926. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "internal(0x%p): "
  1927. "depth(%d), start smid(%d)\n", ioc->name, ioc->internal,
  1928. ioc->internal_depth, ioc->internal_smid));
  1929. /* sense buffers, 4 byte align */
  1930. sz = ioc->scsiio_depth * SCSI_SENSE_BUFFERSIZE;
  1931. ioc->sense_dma_pool = pci_pool_create("sense pool", ioc->pdev, sz, 4,
  1932. 0);
  1933. if (!ioc->sense_dma_pool) {
  1934. printk(MPT2SAS_ERR_FMT "sense pool: pci_pool_create failed\n",
  1935. ioc->name);
  1936. goto out;
  1937. }
  1938. ioc->sense = pci_pool_alloc(ioc->sense_dma_pool , GFP_KERNEL,
  1939. &ioc->sense_dma);
  1940. if (!ioc->sense) {
  1941. printk(MPT2SAS_ERR_FMT "sense pool: pci_pool_alloc failed\n",
  1942. ioc->name);
  1943. goto out;
  1944. }
  1945. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT
  1946. "sense pool(0x%p): depth(%d), element_size(%d), pool_size"
  1947. "(%d kB)\n", ioc->name, ioc->sense, ioc->scsiio_depth,
  1948. SCSI_SENSE_BUFFERSIZE, sz/1024));
  1949. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "sense_dma(0x%llx)\n",
  1950. ioc->name, (unsigned long long)ioc->sense_dma));
  1951. total_sz += sz;
  1952. /* reply pool, 4 byte align */
  1953. sz = ioc->reply_free_queue_depth * ioc->reply_sz;
  1954. ioc->reply_dma_pool = pci_pool_create("reply pool", ioc->pdev, sz, 4,
  1955. 0);
  1956. if (!ioc->reply_dma_pool) {
  1957. printk(MPT2SAS_ERR_FMT "reply pool: pci_pool_create failed\n",
  1958. ioc->name);
  1959. goto out;
  1960. }
  1961. ioc->reply = pci_pool_alloc(ioc->reply_dma_pool , GFP_KERNEL,
  1962. &ioc->reply_dma);
  1963. if (!ioc->reply) {
  1964. printk(MPT2SAS_ERR_FMT "reply pool: pci_pool_alloc failed\n",
  1965. ioc->name);
  1966. goto out;
  1967. }
  1968. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "reply pool(0x%p): depth"
  1969. "(%d), frame_size(%d), pool_size(%d kB)\n", ioc->name, ioc->reply,
  1970. ioc->reply_free_queue_depth, ioc->reply_sz, sz/1024));
  1971. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "reply_dma(0x%llx)\n",
  1972. ioc->name, (unsigned long long)ioc->reply_dma));
  1973. total_sz += sz;
  1974. /* reply free queue, 16 byte align */
  1975. sz = ioc->reply_free_queue_depth * 4;
  1976. ioc->reply_free_dma_pool = pci_pool_create("reply_free pool",
  1977. ioc->pdev, sz, 16, 0);
  1978. if (!ioc->reply_free_dma_pool) {
  1979. printk(MPT2SAS_ERR_FMT "reply_free pool: pci_pool_create "
  1980. "failed\n", ioc->name);
  1981. goto out;
  1982. }
  1983. ioc->reply_free = pci_pool_alloc(ioc->reply_free_dma_pool , GFP_KERNEL,
  1984. &ioc->reply_free_dma);
  1985. if (!ioc->reply_free) {
  1986. printk(MPT2SAS_ERR_FMT "reply_free pool: pci_pool_alloc "
  1987. "failed\n", ioc->name);
  1988. goto out;
  1989. }
  1990. memset(ioc->reply_free, 0, sz);
  1991. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "reply_free pool(0x%p): "
  1992. "depth(%d), element_size(%d), pool_size(%d kB)\n", ioc->name,
  1993. ioc->reply_free, ioc->reply_free_queue_depth, 4, sz/1024));
  1994. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "reply_free_dma"
  1995. "(0x%llx)\n", ioc->name, (unsigned long long)ioc->reply_free_dma));
  1996. total_sz += sz;
  1997. /* reply post queue, 16 byte align */
  1998. sz = ioc->reply_post_queue_depth * sizeof(Mpi2DefaultReplyDescriptor_t);
  1999. ioc->reply_post_free_dma_pool = pci_pool_create("reply_post_free pool",
  2000. ioc->pdev, sz, 16, 0);
  2001. if (!ioc->reply_post_free_dma_pool) {
  2002. printk(MPT2SAS_ERR_FMT "reply_post_free pool: pci_pool_create "
  2003. "failed\n", ioc->name);
  2004. goto out;
  2005. }
  2006. ioc->reply_post_free = pci_pool_alloc(ioc->reply_post_free_dma_pool ,
  2007. GFP_KERNEL, &ioc->reply_post_free_dma);
  2008. if (!ioc->reply_post_free) {
  2009. printk(MPT2SAS_ERR_FMT "reply_post_free pool: pci_pool_alloc "
  2010. "failed\n", ioc->name);
  2011. goto out;
  2012. }
  2013. memset(ioc->reply_post_free, 0, sz);
  2014. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "reply post free pool"
  2015. "(0x%p): depth(%d), element_size(%d), pool_size(%d kB)\n",
  2016. ioc->name, ioc->reply_post_free, ioc->reply_post_queue_depth, 8,
  2017. sz/1024));
  2018. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "reply_post_free_dma = "
  2019. "(0x%llx)\n", ioc->name, (unsigned long long)
  2020. ioc->reply_post_free_dma));
  2021. total_sz += sz;
  2022. ioc->config_page_sz = 512;
  2023. ioc->config_page = pci_alloc_consistent(ioc->pdev,
  2024. ioc->config_page_sz, &ioc->config_page_dma);
  2025. if (!ioc->config_page) {
  2026. printk(MPT2SAS_ERR_FMT "config page: pci_pool_alloc "
  2027. "failed\n", ioc->name);
  2028. goto out;
  2029. }
  2030. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "config page(0x%p): size"
  2031. "(%d)\n", ioc->name, ioc->config_page, ioc->config_page_sz));
  2032. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "config_page_dma"
  2033. "(0x%llx)\n", ioc->name, (unsigned long long)ioc->config_page_dma));
  2034. total_sz += ioc->config_page_sz;
  2035. printk(MPT2SAS_INFO_FMT "Allocated physical memory: size(%d kB)\n",
  2036. ioc->name, total_sz/1024);
  2037. printk(MPT2SAS_INFO_FMT "Current Controller Queue Depth(%d), "
  2038. "Max Controller Queue Depth(%d)\n",
  2039. ioc->name, ioc->shost->can_queue, facts->RequestCredit);
  2040. printk(MPT2SAS_INFO_FMT "Scatter Gather Elements per IO(%d)\n",
  2041. ioc->name, ioc->shost->sg_tablesize);
  2042. return 0;
  2043. out:
  2044. _base_release_memory_pools(ioc);
  2045. return -ENOMEM;
  2046. }
  2047. /**
  2048. * mpt2sas_base_get_iocstate - Get the current state of a MPT adapter.
  2049. * @ioc: Pointer to MPT_ADAPTER structure
  2050. * @cooked: Request raw or cooked IOC state
  2051. *
  2052. * Returns all IOC Doorbell register bits if cooked==0, else just the
  2053. * Doorbell bits in MPI_IOC_STATE_MASK.
  2054. */
  2055. u32
  2056. mpt2sas_base_get_iocstate(struct MPT2SAS_ADAPTER *ioc, int cooked)
  2057. {
  2058. u32 s, sc;
  2059. s = readl(&ioc->chip->Doorbell);
  2060. sc = s & MPI2_IOC_STATE_MASK;
  2061. return cooked ? sc : s;
  2062. }
  2063. /**
  2064. * _base_wait_on_iocstate - waiting on a particular ioc state
  2065. * @ioc_state: controller state { READY, OPERATIONAL, or RESET }
  2066. * @timeout: timeout in second
  2067. * @sleep_flag: CAN_SLEEP or NO_SLEEP
  2068. *
  2069. * Returns 0 for success, non-zero for failure.
  2070. */
  2071. static int
  2072. _base_wait_on_iocstate(struct MPT2SAS_ADAPTER *ioc, u32 ioc_state, int timeout,
  2073. int sleep_flag)
  2074. {
  2075. u32 count, cntdn;
  2076. u32 current_state;
  2077. count = 0;
  2078. cntdn = (sleep_flag == CAN_SLEEP) ? 1000*timeout : 2000*timeout;
  2079. do {
  2080. current_state = mpt2sas_base_get_iocstate(ioc, 1);
  2081. if (current_state == ioc_state)
  2082. return 0;
  2083. if (count && current_state == MPI2_IOC_STATE_FAULT)
  2084. break;
  2085. if (sleep_flag == CAN_SLEEP)
  2086. msleep(1);
  2087. else
  2088. udelay(500);
  2089. count++;
  2090. } while (--cntdn);
  2091. return current_state;
  2092. }
  2093. /**
  2094. * _base_wait_for_doorbell_int - waiting for controller interrupt(generated by
  2095. * a write to the doorbell)
  2096. * @ioc: per adapter object
  2097. * @timeout: timeout in second
  2098. * @sleep_flag: CAN_SLEEP or NO_SLEEP
  2099. *
  2100. * Returns 0 for success, non-zero for failure.
  2101. *
  2102. * Notes: MPI2_HIS_IOC2SYS_DB_STATUS - set to one when IOC writes to doorbell.
  2103. */
  2104. static int
  2105. _base_wait_for_doorbell_int(struct MPT2SAS_ADAPTER *ioc, int timeout,
  2106. int sleep_flag)
  2107. {
  2108. u32 cntdn, count;
  2109. u32 int_status;
  2110. count = 0;
  2111. cntdn = (sleep_flag == CAN_SLEEP) ? 1000*timeout : 2000*timeout;
  2112. do {
  2113. int_status = readl(&ioc->chip->HostInterruptStatus);
  2114. if (int_status & MPI2_HIS_IOC2SYS_DB_STATUS) {
  2115. dhsprintk(ioc, printk(MPT2SAS_INFO_FMT "%s: "
  2116. "successfull count(%d), timeout(%d)\n", ioc->name,
  2117. __func__, count, timeout));
  2118. return 0;
  2119. }
  2120. if (sleep_flag == CAN_SLEEP)
  2121. msleep(1);
  2122. else
  2123. udelay(500);
  2124. count++;
  2125. } while (--cntdn);
  2126. printk(MPT2SAS_ERR_FMT "%s: failed due to timeout count(%d), "
  2127. "int_status(%x)!\n", ioc->name, __func__, count, int_status);
  2128. return -EFAULT;
  2129. }
  2130. /**
  2131. * _base_wait_for_doorbell_ack - waiting for controller to read the doorbell.
  2132. * @ioc: per adapter object
  2133. * @timeout: timeout in second
  2134. * @sleep_flag: CAN_SLEEP or NO_SLEEP
  2135. *
  2136. * Returns 0 for success, non-zero for failure.
  2137. *
  2138. * Notes: MPI2_HIS_SYS2IOC_DB_STATUS - set to one when host writes to
  2139. * doorbell.
  2140. */
  2141. static int
  2142. _base_wait_for_doorbell_ack(struct MPT2SAS_ADAPTER *ioc, int timeout,
  2143. int sleep_flag)
  2144. {
  2145. u32 cntdn, count;
  2146. u32 int_status;
  2147. u32 doorbell;
  2148. count = 0;
  2149. cntdn = (sleep_flag == CAN_SLEEP) ? 1000*timeout : 2000*timeout;
  2150. do {
  2151. int_status = readl(&ioc->chip->HostInterruptStatus);
  2152. if (!(int_status & MPI2_HIS_SYS2IOC_DB_STATUS)) {
  2153. dhsprintk(ioc, printk(MPT2SAS_INFO_FMT "%s: "
  2154. "successfull count(%d), timeout(%d)\n", ioc->name,
  2155. __func__, count, timeout));
  2156. return 0;
  2157. } else if (int_status & MPI2_HIS_IOC2SYS_DB_STATUS) {
  2158. doorbell = readl(&ioc->chip->Doorbell);
  2159. if ((doorbell & MPI2_IOC_STATE_MASK) ==
  2160. MPI2_IOC_STATE_FAULT) {
  2161. mpt2sas_base_fault_info(ioc , doorbell);
  2162. return -EFAULT;
  2163. }
  2164. } else if (int_status == 0xFFFFFFFF)
  2165. goto out;
  2166. if (sleep_flag == CAN_SLEEP)
  2167. msleep(1);
  2168. else
  2169. udelay(500);
  2170. count++;
  2171. } while (--cntdn);
  2172. out:
  2173. printk(MPT2SAS_ERR_FMT "%s: failed due to timeout count(%d), "
  2174. "int_status(%x)!\n", ioc->name, __func__, count, int_status);
  2175. return -EFAULT;
  2176. }
  2177. /**
  2178. * _base_wait_for_doorbell_not_used - waiting for doorbell to not be in use
  2179. * @ioc: per adapter object
  2180. * @timeout: timeout in second
  2181. * @sleep_flag: CAN_SLEEP or NO_SLEEP
  2182. *
  2183. * Returns 0 for success, non-zero for failure.
  2184. *
  2185. */
  2186. static int
  2187. _base_wait_for_doorbell_not_used(struct MPT2SAS_ADAPTER *ioc, int timeout,
  2188. int sleep_flag)
  2189. {
  2190. u32 cntdn, count;
  2191. u32 doorbell_reg;
  2192. count = 0;
  2193. cntdn = (sleep_flag == CAN_SLEEP) ? 1000*timeout : 2000*timeout;
  2194. do {
  2195. doorbell_reg = readl(&ioc->chip->Doorbell);
  2196. if (!(doorbell_reg & MPI2_DOORBELL_USED)) {
  2197. dhsprintk(ioc, printk(MPT2SAS_INFO_FMT "%s: "
  2198. "successfull count(%d), timeout(%d)\n", ioc->name,
  2199. __func__, count, timeout));
  2200. return 0;
  2201. }
  2202. if (sleep_flag == CAN_SLEEP)
  2203. msleep(1);
  2204. else
  2205. udelay(500);
  2206. count++;
  2207. } while (--cntdn);
  2208. printk(MPT2SAS_ERR_FMT "%s: failed due to timeout count(%d), "
  2209. "doorbell_reg(%x)!\n", ioc->name, __func__, count, doorbell_reg);
  2210. return -EFAULT;
  2211. }
  2212. /**
  2213. * _base_send_ioc_reset - send doorbell reset
  2214. * @ioc: per adapter object
  2215. * @reset_type: currently only supports: MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET
  2216. * @timeout: timeout in second
  2217. * @sleep_flag: CAN_SLEEP or NO_SLEEP
  2218. *
  2219. * Returns 0 for success, non-zero for failure.
  2220. */
  2221. static int
  2222. _base_send_ioc_reset(struct MPT2SAS_ADAPTER *ioc, u8 reset_type, int timeout,
  2223. int sleep_flag)
  2224. {
  2225. u32 ioc_state;
  2226. int r = 0;
  2227. if (reset_type != MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET) {
  2228. printk(MPT2SAS_ERR_FMT "%s: unknown reset_type\n",
  2229. ioc->name, __func__);
  2230. return -EFAULT;
  2231. }
  2232. if (!(ioc->facts.IOCCapabilities &
  2233. MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY))
  2234. return -EFAULT;
  2235. printk(MPT2SAS_INFO_FMT "sending message unit reset !!\n", ioc->name);
  2236. writel(reset_type << MPI2_DOORBELL_FUNCTION_SHIFT,
  2237. &ioc->chip->Doorbell);
  2238. if ((_base_wait_for_doorbell_ack(ioc, 15, sleep_flag))) {
  2239. r = -EFAULT;
  2240. goto out;
  2241. }
  2242. ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY,
  2243. timeout, sleep_flag);
  2244. if (ioc_state) {
  2245. printk(MPT2SAS_ERR_FMT "%s: failed going to ready state "
  2246. " (ioc_state=0x%x)\n", ioc->name, __func__, ioc_state);
  2247. r = -EFAULT;
  2248. goto out;
  2249. }
  2250. out:
  2251. printk(MPT2SAS_INFO_FMT "message unit reset: %s\n",
  2252. ioc->name, ((r == 0) ? "SUCCESS" : "FAILED"));
  2253. return r;
  2254. }
  2255. /**
  2256. * _base_handshake_req_reply_wait - send request thru doorbell interface
  2257. * @ioc: per adapter object
  2258. * @request_bytes: request length
  2259. * @request: pointer having request payload
  2260. * @reply_bytes: reply length
  2261. * @reply: pointer to reply payload
  2262. * @timeout: timeout in second
  2263. * @sleep_flag: CAN_SLEEP or NO_SLEEP
  2264. *
  2265. * Returns 0 for success, non-zero for failure.
  2266. */
  2267. static int
  2268. _base_handshake_req_reply_wait(struct MPT2SAS_ADAPTER *ioc, int request_bytes,
  2269. u32 *request, int reply_bytes, u16 *reply, int timeout, int sleep_flag)
  2270. {
  2271. MPI2DefaultReply_t *default_reply = (MPI2DefaultReply_t *)reply;
  2272. int i;
  2273. u8 failed;
  2274. u16 dummy;
  2275. u32 *mfp;
  2276. /* make sure doorbell is not in use */
  2277. if ((readl(&ioc->chip->Doorbell) & MPI2_DOORBELL_USED)) {
  2278. printk(MPT2SAS_ERR_FMT "doorbell is in use "
  2279. " (line=%d)\n", ioc->name, __LINE__);
  2280. return -EFAULT;
  2281. }
  2282. /* clear pending doorbell interrupts from previous state changes */
  2283. if (readl(&ioc->chip->HostInterruptStatus) &
  2284. MPI2_HIS_IOC2SYS_DB_STATUS)
  2285. writel(0, &ioc->chip->HostInterruptStatus);
  2286. /* send message to ioc */
  2287. writel(((MPI2_FUNCTION_HANDSHAKE<<MPI2_DOORBELL_FUNCTION_SHIFT) |
  2288. ((request_bytes/4)<<MPI2_DOORBELL_ADD_DWORDS_SHIFT)),
  2289. &ioc->chip->Doorbell);
  2290. if ((_base_wait_for_doorbell_int(ioc, 5, NO_SLEEP))) {
  2291. printk(MPT2SAS_ERR_FMT "doorbell handshake "
  2292. "int failed (line=%d)\n", ioc->name, __LINE__);
  2293. return -EFAULT;
  2294. }
  2295. writel(0, &ioc->chip->HostInterruptStatus);
  2296. if ((_base_wait_for_doorbell_ack(ioc, 5, sleep_flag))) {
  2297. printk(MPT2SAS_ERR_FMT "doorbell handshake "
  2298. "ack failed (line=%d)\n", ioc->name, __LINE__);
  2299. return -EFAULT;
  2300. }
  2301. /* send message 32-bits at a time */
  2302. for (i = 0, failed = 0; i < request_bytes/4 && !failed; i++) {
  2303. writel(cpu_to_le32(request[i]), &ioc->chip->Doorbell);
  2304. if ((_base_wait_for_doorbell_ack(ioc, 5, sleep_flag)))
  2305. failed = 1;
  2306. }
  2307. if (failed) {
  2308. printk(MPT2SAS_ERR_FMT "doorbell handshake "
  2309. "sending request failed (line=%d)\n", ioc->name, __LINE__);
  2310. return -EFAULT;
  2311. }
  2312. /* now wait for the reply */
  2313. if ((_base_wait_for_doorbell_int(ioc, timeout, sleep_flag))) {
  2314. printk(MPT2SAS_ERR_FMT "doorbell handshake "
  2315. "int failed (line=%d)\n", ioc->name, __LINE__);
  2316. return -EFAULT;
  2317. }
  2318. /* read the first two 16-bits, it gives the total length of the reply */
  2319. reply[0] = le16_to_cpu(readl(&ioc->chip->Doorbell)
  2320. & MPI2_DOORBELL_DATA_MASK);
  2321. writel(0, &ioc->chip->HostInterruptStatus);
  2322. if ((_base_wait_for_doorbell_int(ioc, 5, sleep_flag))) {
  2323. printk(MPT2SAS_ERR_FMT "doorbell handshake "
  2324. "int failed (line=%d)\n", ioc->name, __LINE__);
  2325. return -EFAULT;
  2326. }
  2327. reply[1] = le16_to_cpu(readl(&ioc->chip->Doorbell)
  2328. & MPI2_DOORBELL_DATA_MASK);
  2329. writel(0, &ioc->chip->HostInterruptStatus);
  2330. for (i = 2; i < default_reply->MsgLength * 2; i++) {
  2331. if ((_base_wait_for_doorbell_int(ioc, 5, sleep_flag))) {
  2332. printk(MPT2SAS_ERR_FMT "doorbell "
  2333. "handshake int failed (line=%d)\n", ioc->name,
  2334. __LINE__);
  2335. return -EFAULT;
  2336. }
  2337. if (i >= reply_bytes/2) /* overflow case */
  2338. dummy = readl(&ioc->chip->Doorbell);
  2339. else
  2340. reply[i] = le16_to_cpu(readl(&ioc->chip->Doorbell)
  2341. & MPI2_DOORBELL_DATA_MASK);
  2342. writel(0, &ioc->chip->HostInterruptStatus);
  2343. }
  2344. _base_wait_for_doorbell_int(ioc, 5, sleep_flag);
  2345. if (_base_wait_for_doorbell_not_used(ioc, 5, sleep_flag) != 0) {
  2346. dhsprintk(ioc, printk(MPT2SAS_INFO_FMT "doorbell is in use "
  2347. " (line=%d)\n", ioc->name, __LINE__));
  2348. }
  2349. writel(0, &ioc->chip->HostInterruptStatus);
  2350. if (ioc->logging_level & MPT_DEBUG_INIT) {
  2351. mfp = (u32 *)reply;
  2352. printk(KERN_INFO "\toffset:data\n");
  2353. for (i = 0; i < reply_bytes/4; i++)
  2354. printk(KERN_INFO "\t[0x%02x]:%08x\n", i*4,
  2355. le32_to_cpu(mfp[i]));
  2356. }
  2357. return 0;
  2358. }
  2359. /**
  2360. * mpt2sas_base_sas_iounit_control - send sas iounit control to FW
  2361. * @ioc: per adapter object
  2362. * @mpi_reply: the reply payload from FW
  2363. * @mpi_request: the request payload sent to FW
  2364. *
  2365. * The SAS IO Unit Control Request message allows the host to perform low-level
  2366. * operations, such as resets on the PHYs of the IO Unit, also allows the host
  2367. * to obtain the IOC assigned device handles for a device if it has other
  2368. * identifying information about the device, in addition allows the host to
  2369. * remove IOC resources associated with the device.
  2370. *
  2371. * Returns 0 for success, non-zero for failure.
  2372. */
  2373. int
  2374. mpt2sas_base_sas_iounit_control(struct MPT2SAS_ADAPTER *ioc,
  2375. Mpi2SasIoUnitControlReply_t *mpi_reply,
  2376. Mpi2SasIoUnitControlRequest_t *mpi_request)
  2377. {
  2378. u16 smid;
  2379. u32 ioc_state;
  2380. unsigned long timeleft;
  2381. u8 issue_reset;
  2382. int rc;
  2383. void *request;
  2384. u16 wait_state_count;
  2385. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "%s\n", ioc->name,
  2386. __func__));
  2387. mutex_lock(&ioc->base_cmds.mutex);
  2388. if (ioc->base_cmds.status != MPT2_CMD_NOT_USED) {
  2389. printk(MPT2SAS_ERR_FMT "%s: base_cmd in use\n",
  2390. ioc->name, __func__);
  2391. rc = -EAGAIN;
  2392. goto out;
  2393. }
  2394. wait_state_count = 0;
  2395. ioc_state = mpt2sas_base_get_iocstate(ioc, 1);
  2396. while (ioc_state != MPI2_IOC_STATE_OPERATIONAL) {
  2397. if (wait_state_count++ == 10) {
  2398. printk(MPT2SAS_ERR_FMT
  2399. "%s: failed due to ioc not operational\n",
  2400. ioc->name, __func__);
  2401. rc = -EFAULT;
  2402. goto out;
  2403. }
  2404. ssleep(1);
  2405. ioc_state = mpt2sas_base_get_iocstate(ioc, 1);
  2406. printk(MPT2SAS_INFO_FMT "%s: waiting for "
  2407. "operational state(count=%d)\n", ioc->name,
  2408. __func__, wait_state_count);
  2409. }
  2410. smid = mpt2sas_base_get_smid(ioc, ioc->base_cb_idx);
  2411. if (!smid) {
  2412. printk(MPT2SAS_ERR_FMT "%s: failed obtaining a smid\n",
  2413. ioc->name, __func__);
  2414. rc = -EAGAIN;
  2415. goto out;
  2416. }
  2417. rc = 0;
  2418. ioc->base_cmds.status = MPT2_CMD_PENDING;
  2419. request = mpt2sas_base_get_msg_frame(ioc, smid);
  2420. ioc->base_cmds.smid = smid;
  2421. memcpy(request, mpi_request, sizeof(Mpi2SasIoUnitControlRequest_t));
  2422. if (mpi_request->Operation == MPI2_SAS_OP_PHY_HARD_RESET ||
  2423. mpi_request->Operation == MPI2_SAS_OP_PHY_LINK_RESET)
  2424. ioc->ioc_link_reset_in_progress = 1;
  2425. mpt2sas_base_put_smid_default(ioc, smid);
  2426. init_completion(&ioc->base_cmds.done);
  2427. timeleft = wait_for_completion_timeout(&ioc->base_cmds.done,
  2428. msecs_to_jiffies(10000));
  2429. if ((mpi_request->Operation == MPI2_SAS_OP_PHY_HARD_RESET ||
  2430. mpi_request->Operation == MPI2_SAS_OP_PHY_LINK_RESET) &&
  2431. ioc->ioc_link_reset_in_progress)
  2432. ioc->ioc_link_reset_in_progress = 0;
  2433. if (!(ioc->base_cmds.status & MPT2_CMD_COMPLETE)) {
  2434. printk(MPT2SAS_ERR_FMT "%s: timeout\n",
  2435. ioc->name, __func__);
  2436. _debug_dump_mf(mpi_request,
  2437. sizeof(Mpi2SasIoUnitControlRequest_t)/4);
  2438. if (!(ioc->base_cmds.status & MPT2_CMD_RESET))
  2439. issue_reset = 1;
  2440. goto issue_host_reset;
  2441. }
  2442. if (ioc->base_cmds.status & MPT2_CMD_REPLY_VALID)
  2443. memcpy(mpi_reply, ioc->base_cmds.reply,
  2444. sizeof(Mpi2SasIoUnitControlReply_t));
  2445. else
  2446. memset(mpi_reply, 0, sizeof(Mpi2SasIoUnitControlReply_t));
  2447. ioc->base_cmds.status = MPT2_CMD_NOT_USED;
  2448. goto out;
  2449. issue_host_reset:
  2450. if (issue_reset)
  2451. mpt2sas_base_hard_reset_handler(ioc, CAN_SLEEP,
  2452. FORCE_BIG_HAMMER);
  2453. ioc->base_cmds.status = MPT2_CMD_NOT_USED;
  2454. rc = -EFAULT;
  2455. out:
  2456. mutex_unlock(&ioc->base_cmds.mutex);
  2457. return rc;
  2458. }
  2459. /**
  2460. * mpt2sas_base_scsi_enclosure_processor - sending request to sep device
  2461. * @ioc: per adapter object
  2462. * @mpi_reply: the reply payload from FW
  2463. * @mpi_request: the request payload sent to FW
  2464. *
  2465. * The SCSI Enclosure Processor request message causes the IOC to
  2466. * communicate with SES devices to control LED status signals.
  2467. *
  2468. * Returns 0 for success, non-zero for failure.
  2469. */
  2470. int
  2471. mpt2sas_base_scsi_enclosure_processor(struct MPT2SAS_ADAPTER *ioc,
  2472. Mpi2SepReply_t *mpi_reply, Mpi2SepRequest_t *mpi_request)
  2473. {
  2474. u16 smid;
  2475. u32 ioc_state;
  2476. unsigned long timeleft;
  2477. u8 issue_reset;
  2478. int rc;
  2479. void *request;
  2480. u16 wait_state_count;
  2481. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "%s\n", ioc->name,
  2482. __func__));
  2483. mutex_lock(&ioc->base_cmds.mutex);
  2484. if (ioc->base_cmds.status != MPT2_CMD_NOT_USED) {
  2485. printk(MPT2SAS_ERR_FMT "%s: base_cmd in use\n",
  2486. ioc->name, __func__);
  2487. rc = -EAGAIN;
  2488. goto out;
  2489. }
  2490. wait_state_count = 0;
  2491. ioc_state = mpt2sas_base_get_iocstate(ioc, 1);
  2492. while (ioc_state != MPI2_IOC_STATE_OPERATIONAL) {
  2493. if (wait_state_count++ == 10) {
  2494. printk(MPT2SAS_ERR_FMT
  2495. "%s: failed due to ioc not operational\n",
  2496. ioc->name, __func__);
  2497. rc = -EFAULT;
  2498. goto out;
  2499. }
  2500. ssleep(1);
  2501. ioc_state = mpt2sas_base_get_iocstate(ioc, 1);
  2502. printk(MPT2SAS_INFO_FMT "%s: waiting for "
  2503. "operational state(count=%d)\n", ioc->name,
  2504. __func__, wait_state_count);
  2505. }
  2506. smid = mpt2sas_base_get_smid(ioc, ioc->base_cb_idx);
  2507. if (!smid) {
  2508. printk(MPT2SAS_ERR_FMT "%s: failed obtaining a smid\n",
  2509. ioc->name, __func__);
  2510. rc = -EAGAIN;
  2511. goto out;
  2512. }
  2513. rc = 0;
  2514. ioc->base_cmds.status = MPT2_CMD_PENDING;
  2515. request = mpt2sas_base_get_msg_frame(ioc, smid);
  2516. ioc->base_cmds.smid = smid;
  2517. memcpy(request, mpi_request, sizeof(Mpi2SepReply_t));
  2518. mpt2sas_base_put_smid_default(ioc, smid);
  2519. init_completion(&ioc->base_cmds.done);
  2520. timeleft = wait_for_completion_timeout(&ioc->base_cmds.done,
  2521. msecs_to_jiffies(10000));
  2522. if (!(ioc->base_cmds.status & MPT2_CMD_COMPLETE)) {
  2523. printk(MPT2SAS_ERR_FMT "%s: timeout\n",
  2524. ioc->name, __func__);
  2525. _debug_dump_mf(mpi_request,
  2526. sizeof(Mpi2SepRequest_t)/4);
  2527. if (!(ioc->base_cmds.status & MPT2_CMD_RESET))
  2528. issue_reset = 1;
  2529. goto issue_host_reset;
  2530. }
  2531. if (ioc->base_cmds.status & MPT2_CMD_REPLY_VALID)
  2532. memcpy(mpi_reply, ioc->base_cmds.reply,
  2533. sizeof(Mpi2SepReply_t));
  2534. else
  2535. memset(mpi_reply, 0, sizeof(Mpi2SepReply_t));
  2536. ioc->base_cmds.status = MPT2_CMD_NOT_USED;
  2537. goto out;
  2538. issue_host_reset:
  2539. if (issue_reset)
  2540. mpt2sas_base_hard_reset_handler(ioc, CAN_SLEEP,
  2541. FORCE_BIG_HAMMER);
  2542. ioc->base_cmds.status = MPT2_CMD_NOT_USED;
  2543. rc = -EFAULT;
  2544. out:
  2545. mutex_unlock(&ioc->base_cmds.mutex);
  2546. return rc;
  2547. }
  2548. /**
  2549. * _base_get_port_facts - obtain port facts reply and save in ioc
  2550. * @ioc: per adapter object
  2551. * @sleep_flag: CAN_SLEEP or NO_SLEEP
  2552. *
  2553. * Returns 0 for success, non-zero for failure.
  2554. */
  2555. static int
  2556. _base_get_port_facts(struct MPT2SAS_ADAPTER *ioc, int port, int sleep_flag)
  2557. {
  2558. Mpi2PortFactsRequest_t mpi_request;
  2559. Mpi2PortFactsReply_t mpi_reply, *pfacts;
  2560. int mpi_reply_sz, mpi_request_sz, r;
  2561. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "%s\n", ioc->name,
  2562. __func__));
  2563. mpi_reply_sz = sizeof(Mpi2PortFactsReply_t);
  2564. mpi_request_sz = sizeof(Mpi2PortFactsRequest_t);
  2565. memset(&mpi_request, 0, mpi_request_sz);
  2566. mpi_request.Function = MPI2_FUNCTION_PORT_FACTS;
  2567. mpi_request.PortNumber = port;
  2568. r = _base_handshake_req_reply_wait(ioc, mpi_request_sz,
  2569. (u32 *)&mpi_request, mpi_reply_sz, (u16 *)&mpi_reply, 5, CAN_SLEEP);
  2570. if (r != 0) {
  2571. printk(MPT2SAS_ERR_FMT "%s: handshake failed (r=%d)\n",
  2572. ioc->name, __func__, r);
  2573. return r;
  2574. }
  2575. pfacts = &ioc->pfacts[port];
  2576. memset(pfacts, 0, sizeof(Mpi2PortFactsReply_t));
  2577. pfacts->PortNumber = mpi_reply.PortNumber;
  2578. pfacts->VP_ID = mpi_reply.VP_ID;
  2579. pfacts->VF_ID = mpi_reply.VF_ID;
  2580. pfacts->MaxPostedCmdBuffers =
  2581. le16_to_cpu(mpi_reply.MaxPostedCmdBuffers);
  2582. return 0;
  2583. }
  2584. /**
  2585. * _base_get_ioc_facts - obtain ioc facts reply and save in ioc
  2586. * @ioc: per adapter object
  2587. * @sleep_flag: CAN_SLEEP or NO_SLEEP
  2588. *
  2589. * Returns 0 for success, non-zero for failure.
  2590. */
  2591. static int
  2592. _base_get_ioc_facts(struct MPT2SAS_ADAPTER *ioc, int sleep_flag)
  2593. {
  2594. Mpi2IOCFactsRequest_t mpi_request;
  2595. Mpi2IOCFactsReply_t mpi_reply, *facts;
  2596. int mpi_reply_sz, mpi_request_sz, r;
  2597. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "%s\n", ioc->name,
  2598. __func__));
  2599. mpi_reply_sz = sizeof(Mpi2IOCFactsReply_t);
  2600. mpi_request_sz = sizeof(Mpi2IOCFactsRequest_t);
  2601. memset(&mpi_request, 0, mpi_request_sz);
  2602. mpi_request.Function = MPI2_FUNCTION_IOC_FACTS;
  2603. r = _base_handshake_req_reply_wait(ioc, mpi_request_sz,
  2604. (u32 *)&mpi_request, mpi_reply_sz, (u16 *)&mpi_reply, 5, CAN_SLEEP);
  2605. if (r != 0) {
  2606. printk(MPT2SAS_ERR_FMT "%s: handshake failed (r=%d)\n",
  2607. ioc->name, __func__, r);
  2608. return r;
  2609. }
  2610. facts = &ioc->facts;
  2611. memset(facts, 0, sizeof(Mpi2IOCFactsReply_t));
  2612. facts->MsgVersion = le16_to_cpu(mpi_reply.MsgVersion);
  2613. facts->HeaderVersion = le16_to_cpu(mpi_reply.HeaderVersion);
  2614. facts->VP_ID = mpi_reply.VP_ID;
  2615. facts->VF_ID = mpi_reply.VF_ID;
  2616. facts->IOCExceptions = le16_to_cpu(mpi_reply.IOCExceptions);
  2617. facts->MaxChainDepth = mpi_reply.MaxChainDepth;
  2618. facts->WhoInit = mpi_reply.WhoInit;
  2619. facts->NumberOfPorts = mpi_reply.NumberOfPorts;
  2620. facts->RequestCredit = le16_to_cpu(mpi_reply.RequestCredit);
  2621. facts->MaxReplyDescriptorPostQueueDepth =
  2622. le16_to_cpu(mpi_reply.MaxReplyDescriptorPostQueueDepth);
  2623. facts->ProductID = le16_to_cpu(mpi_reply.ProductID);
  2624. facts->IOCCapabilities = le32_to_cpu(mpi_reply.IOCCapabilities);
  2625. if ((facts->IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID))
  2626. ioc->ir_firmware = 1;
  2627. facts->FWVersion.Word = le32_to_cpu(mpi_reply.FWVersion.Word);
  2628. facts->IOCRequestFrameSize =
  2629. le16_to_cpu(mpi_reply.IOCRequestFrameSize);
  2630. facts->MaxInitiators = le16_to_cpu(mpi_reply.MaxInitiators);
  2631. facts->MaxTargets = le16_to_cpu(mpi_reply.MaxTargets);
  2632. ioc->shost->max_id = -1;
  2633. facts->MaxSasExpanders = le16_to_cpu(mpi_reply.MaxSasExpanders);
  2634. facts->MaxEnclosures = le16_to_cpu(mpi_reply.MaxEnclosures);
  2635. facts->ProtocolFlags = le16_to_cpu(mpi_reply.ProtocolFlags);
  2636. facts->HighPriorityCredit =
  2637. le16_to_cpu(mpi_reply.HighPriorityCredit);
  2638. facts->ReplyFrameSize = mpi_reply.ReplyFrameSize;
  2639. facts->MaxDevHandle = le16_to_cpu(mpi_reply.MaxDevHandle);
  2640. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "hba queue depth(%d), "
  2641. "max chains per io(%d)\n", ioc->name, facts->RequestCredit,
  2642. facts->MaxChainDepth));
  2643. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "request frame size(%d), "
  2644. "reply frame size(%d)\n", ioc->name,
  2645. facts->IOCRequestFrameSize * 4, facts->ReplyFrameSize * 4));
  2646. return 0;
  2647. }
  2648. /**
  2649. * _base_send_ioc_init - send ioc_init to firmware
  2650. * @ioc: per adapter object
  2651. * @sleep_flag: CAN_SLEEP or NO_SLEEP
  2652. *
  2653. * Returns 0 for success, non-zero for failure.
  2654. */
  2655. static int
  2656. _base_send_ioc_init(struct MPT2SAS_ADAPTER *ioc, int sleep_flag)
  2657. {
  2658. Mpi2IOCInitRequest_t mpi_request;
  2659. Mpi2IOCInitReply_t mpi_reply;
  2660. int r;
  2661. struct timeval current_time;
  2662. u16 ioc_status;
  2663. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "%s\n", ioc->name,
  2664. __func__));
  2665. memset(&mpi_request, 0, sizeof(Mpi2IOCInitRequest_t));
  2666. mpi_request.Function = MPI2_FUNCTION_IOC_INIT;
  2667. mpi_request.WhoInit = MPI2_WHOINIT_HOST_DRIVER;
  2668. mpi_request.VF_ID = 0; /* TODO */
  2669. mpi_request.VP_ID = 0;
  2670. mpi_request.MsgVersion = cpu_to_le16(MPI2_VERSION);
  2671. mpi_request.HeaderVersion = cpu_to_le16(MPI2_HEADER_VERSION);
  2672. /* In MPI Revision I (0xA), the SystemReplyFrameSize(offset 0x18) was
  2673. * removed and made reserved. For those with older firmware will need
  2674. * this fix. It was decided that the Reply and Request frame sizes are
  2675. * the same.
  2676. */
  2677. if ((ioc->facts.HeaderVersion >> 8) < 0xA) {
  2678. mpi_request.Reserved7 = cpu_to_le16(ioc->reply_sz);
  2679. /* mpi_request.SystemReplyFrameSize =
  2680. * cpu_to_le16(ioc->reply_sz);
  2681. */
  2682. }
  2683. mpi_request.SystemRequestFrameSize = cpu_to_le16(ioc->request_sz/4);
  2684. mpi_request.ReplyDescriptorPostQueueDepth =
  2685. cpu_to_le16(ioc->reply_post_queue_depth);
  2686. mpi_request.ReplyFreeQueueDepth =
  2687. cpu_to_le16(ioc->reply_free_queue_depth);
  2688. #if BITS_PER_LONG > 32
  2689. mpi_request.SenseBufferAddressHigh =
  2690. cpu_to_le32(ioc->sense_dma >> 32);
  2691. mpi_request.SystemReplyAddressHigh =
  2692. cpu_to_le32(ioc->reply_dma >> 32);
  2693. mpi_request.SystemRequestFrameBaseAddress =
  2694. cpu_to_le64(ioc->request_dma);
  2695. mpi_request.ReplyFreeQueueAddress =
  2696. cpu_to_le64(ioc->reply_free_dma);
  2697. mpi_request.ReplyDescriptorPostQueueAddress =
  2698. cpu_to_le64(ioc->reply_post_free_dma);
  2699. #else
  2700. mpi_request.SystemRequestFrameBaseAddress =
  2701. cpu_to_le32(ioc->request_dma);
  2702. mpi_request.ReplyFreeQueueAddress =
  2703. cpu_to_le32(ioc->reply_free_dma);
  2704. mpi_request.ReplyDescriptorPostQueueAddress =
  2705. cpu_to_le32(ioc->reply_post_free_dma);
  2706. #endif
  2707. /* This time stamp specifies number of milliseconds
  2708. * since epoch ~ midnight January 1, 1970.
  2709. */
  2710. do_gettimeofday(&current_time);
  2711. mpi_request.TimeStamp = cpu_to_le64((u64)current_time.tv_sec * 1000 +
  2712. (current_time.tv_usec / 1000));
  2713. if (ioc->logging_level & MPT_DEBUG_INIT) {
  2714. u32 *mfp;
  2715. int i;
  2716. mfp = (u32 *)&mpi_request;
  2717. printk(KERN_INFO "\toffset:data\n");
  2718. for (i = 0; i < sizeof(Mpi2IOCInitRequest_t)/4; i++)
  2719. printk(KERN_INFO "\t[0x%02x]:%08x\n", i*4,
  2720. le32_to_cpu(mfp[i]));
  2721. }
  2722. r = _base_handshake_req_reply_wait(ioc,
  2723. sizeof(Mpi2IOCInitRequest_t), (u32 *)&mpi_request,
  2724. sizeof(Mpi2IOCInitReply_t), (u16 *)&mpi_reply, 10,
  2725. sleep_flag);
  2726. if (r != 0) {
  2727. printk(MPT2SAS_ERR_FMT "%s: handshake failed (r=%d)\n",
  2728. ioc->name, __func__, r);
  2729. return r;
  2730. }
  2731. ioc_status = le16_to_cpu(mpi_reply.IOCStatus) & MPI2_IOCSTATUS_MASK;
  2732. if (ioc_status != MPI2_IOCSTATUS_SUCCESS ||
  2733. mpi_reply.IOCLogInfo) {
  2734. printk(MPT2SAS_ERR_FMT "%s: failed\n", ioc->name, __func__);
  2735. r = -EIO;
  2736. }
  2737. return 0;
  2738. }
  2739. /**
  2740. * _base_send_port_enable - send port_enable(discovery stuff) to firmware
  2741. * @ioc: per adapter object
  2742. * @sleep_flag: CAN_SLEEP or NO_SLEEP
  2743. *
  2744. * Returns 0 for success, non-zero for failure.
  2745. */
  2746. static int
  2747. _base_send_port_enable(struct MPT2SAS_ADAPTER *ioc, int sleep_flag)
  2748. {
  2749. Mpi2PortEnableRequest_t *mpi_request;
  2750. u32 ioc_state;
  2751. unsigned long timeleft;
  2752. int r = 0;
  2753. u16 smid;
  2754. printk(MPT2SAS_INFO_FMT "sending port enable !!\n", ioc->name);
  2755. if (ioc->base_cmds.status & MPT2_CMD_PENDING) {
  2756. printk(MPT2SAS_ERR_FMT "%s: internal command already in use\n",
  2757. ioc->name, __func__);
  2758. return -EAGAIN;
  2759. }
  2760. smid = mpt2sas_base_get_smid(ioc, ioc->base_cb_idx);
  2761. if (!smid) {
  2762. printk(MPT2SAS_ERR_FMT "%s: failed obtaining a smid\n",
  2763. ioc->name, __func__);
  2764. return -EAGAIN;
  2765. }
  2766. ioc->base_cmds.status = MPT2_CMD_PENDING;
  2767. mpi_request = mpt2sas_base_get_msg_frame(ioc, smid);
  2768. ioc->base_cmds.smid = smid;
  2769. memset(mpi_request, 0, sizeof(Mpi2PortEnableRequest_t));
  2770. mpi_request->Function = MPI2_FUNCTION_PORT_ENABLE;
  2771. mpi_request->VF_ID = 0; /* TODO */
  2772. mpi_request->VP_ID = 0;
  2773. mpt2sas_base_put_smid_default(ioc, smid);
  2774. init_completion(&ioc->base_cmds.done);
  2775. timeleft = wait_for_completion_timeout(&ioc->base_cmds.done,
  2776. 300*HZ);
  2777. if (!(ioc->base_cmds.status & MPT2_CMD_COMPLETE)) {
  2778. printk(MPT2SAS_ERR_FMT "%s: timeout\n",
  2779. ioc->name, __func__);
  2780. _debug_dump_mf(mpi_request,
  2781. sizeof(Mpi2PortEnableRequest_t)/4);
  2782. if (ioc->base_cmds.status & MPT2_CMD_RESET)
  2783. r = -EFAULT;
  2784. else
  2785. r = -ETIME;
  2786. goto out;
  2787. } else
  2788. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "%s: complete\n",
  2789. ioc->name, __func__));
  2790. ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_OPERATIONAL,
  2791. 60, sleep_flag);
  2792. if (ioc_state) {
  2793. printk(MPT2SAS_ERR_FMT "%s: failed going to operational state "
  2794. " (ioc_state=0x%x)\n", ioc->name, __func__, ioc_state);
  2795. r = -EFAULT;
  2796. }
  2797. out:
  2798. ioc->base_cmds.status = MPT2_CMD_NOT_USED;
  2799. printk(MPT2SAS_INFO_FMT "port enable: %s\n",
  2800. ioc->name, ((r == 0) ? "SUCCESS" : "FAILED"));
  2801. return r;
  2802. }
  2803. /**
  2804. * _base_unmask_events - turn on notification for this event
  2805. * @ioc: per adapter object
  2806. * @event: firmware event
  2807. *
  2808. * The mask is stored in ioc->event_masks.
  2809. */
  2810. static void
  2811. _base_unmask_events(struct MPT2SAS_ADAPTER *ioc, u16 event)
  2812. {
  2813. u32 desired_event;
  2814. if (event >= 128)
  2815. return;
  2816. desired_event = (1 << (event % 32));
  2817. if (event < 32)
  2818. ioc->event_masks[0] &= ~desired_event;
  2819. else if (event < 64)
  2820. ioc->event_masks[1] &= ~desired_event;
  2821. else if (event < 96)
  2822. ioc->event_masks[2] &= ~desired_event;
  2823. else if (event < 128)
  2824. ioc->event_masks[3] &= ~desired_event;
  2825. }
  2826. /**
  2827. * _base_event_notification - send event notification
  2828. * @ioc: per adapter object
  2829. * @sleep_flag: CAN_SLEEP or NO_SLEEP
  2830. *
  2831. * Returns 0 for success, non-zero for failure.
  2832. */
  2833. static int
  2834. _base_event_notification(struct MPT2SAS_ADAPTER *ioc, int sleep_flag)
  2835. {
  2836. Mpi2EventNotificationRequest_t *mpi_request;
  2837. unsigned long timeleft;
  2838. u16 smid;
  2839. int r = 0;
  2840. int i;
  2841. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "%s\n", ioc->name,
  2842. __func__));
  2843. if (ioc->base_cmds.status & MPT2_CMD_PENDING) {
  2844. printk(MPT2SAS_ERR_FMT "%s: internal command already in use\n",
  2845. ioc->name, __func__);
  2846. return -EAGAIN;
  2847. }
  2848. smid = mpt2sas_base_get_smid(ioc, ioc->base_cb_idx);
  2849. if (!smid) {
  2850. printk(MPT2SAS_ERR_FMT "%s: failed obtaining a smid\n",
  2851. ioc->name, __func__);
  2852. return -EAGAIN;
  2853. }
  2854. ioc->base_cmds.status = MPT2_CMD_PENDING;
  2855. mpi_request = mpt2sas_base_get_msg_frame(ioc, smid);
  2856. ioc->base_cmds.smid = smid;
  2857. memset(mpi_request, 0, sizeof(Mpi2EventNotificationRequest_t));
  2858. mpi_request->Function = MPI2_FUNCTION_EVENT_NOTIFICATION;
  2859. mpi_request->VF_ID = 0; /* TODO */
  2860. mpi_request->VP_ID = 0;
  2861. for (i = 0; i < MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++)
  2862. mpi_request->EventMasks[i] =
  2863. cpu_to_le32(ioc->event_masks[i]);
  2864. mpt2sas_base_put_smid_default(ioc, smid);
  2865. init_completion(&ioc->base_cmds.done);
  2866. timeleft = wait_for_completion_timeout(&ioc->base_cmds.done, 30*HZ);
  2867. if (!(ioc->base_cmds.status & MPT2_CMD_COMPLETE)) {
  2868. printk(MPT2SAS_ERR_FMT "%s: timeout\n",
  2869. ioc->name, __func__);
  2870. _debug_dump_mf(mpi_request,
  2871. sizeof(Mpi2EventNotificationRequest_t)/4);
  2872. if (ioc->base_cmds.status & MPT2_CMD_RESET)
  2873. r = -EFAULT;
  2874. else
  2875. r = -ETIME;
  2876. } else
  2877. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "%s: complete\n",
  2878. ioc->name, __func__));
  2879. ioc->base_cmds.status = MPT2_CMD_NOT_USED;
  2880. return r;
  2881. }
  2882. /**
  2883. * mpt2sas_base_validate_event_type - validating event types
  2884. * @ioc: per adapter object
  2885. * @event: firmware event
  2886. *
  2887. * This will turn on firmware event notification when application
  2888. * ask for that event. We don't mask events that are already enabled.
  2889. */
  2890. void
  2891. mpt2sas_base_validate_event_type(struct MPT2SAS_ADAPTER *ioc, u32 *event_type)
  2892. {
  2893. int i, j;
  2894. u32 event_mask, desired_event;
  2895. u8 send_update_to_fw;
  2896. for (i = 0, send_update_to_fw = 0; i <
  2897. MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++) {
  2898. event_mask = ~event_type[i];
  2899. desired_event = 1;
  2900. for (j = 0; j < 32; j++) {
  2901. if (!(event_mask & desired_event) &&
  2902. (ioc->event_masks[i] & desired_event)) {
  2903. ioc->event_masks[i] &= ~desired_event;
  2904. send_update_to_fw = 1;
  2905. }
  2906. desired_event = (desired_event << 1);
  2907. }
  2908. }
  2909. if (!send_update_to_fw)
  2910. return;
  2911. mutex_lock(&ioc->base_cmds.mutex);
  2912. _base_event_notification(ioc, CAN_SLEEP);
  2913. mutex_unlock(&ioc->base_cmds.mutex);
  2914. }
  2915. /**
  2916. * _base_diag_reset - the "big hammer" start of day reset
  2917. * @ioc: per adapter object
  2918. * @sleep_flag: CAN_SLEEP or NO_SLEEP
  2919. *
  2920. * Returns 0 for success, non-zero for failure.
  2921. */
  2922. static int
  2923. _base_diag_reset(struct MPT2SAS_ADAPTER *ioc, int sleep_flag)
  2924. {
  2925. u32 host_diagnostic;
  2926. u32 ioc_state;
  2927. u32 count;
  2928. u32 hcb_size;
  2929. printk(MPT2SAS_INFO_FMT "sending diag reset !!\n", ioc->name);
  2930. _base_save_msix_table(ioc);
  2931. drsprintk(ioc, printk(MPT2SAS_INFO_FMT "clear interrupts\n",
  2932. ioc->name));
  2933. count = 0;
  2934. do {
  2935. /* Write magic sequence to WriteSequence register
  2936. * Loop until in diagnostic mode
  2937. */
  2938. drsprintk(ioc, printk(MPT2SAS_INFO_FMT "write magic "
  2939. "sequence\n", ioc->name));
  2940. writel(MPI2_WRSEQ_FLUSH_KEY_VALUE, &ioc->chip->WriteSequence);
  2941. writel(MPI2_WRSEQ_1ST_KEY_VALUE, &ioc->chip->WriteSequence);
  2942. writel(MPI2_WRSEQ_2ND_KEY_VALUE, &ioc->chip->WriteSequence);
  2943. writel(MPI2_WRSEQ_3RD_KEY_VALUE, &ioc->chip->WriteSequence);
  2944. writel(MPI2_WRSEQ_4TH_KEY_VALUE, &ioc->chip->WriteSequence);
  2945. writel(MPI2_WRSEQ_5TH_KEY_VALUE, &ioc->chip->WriteSequence);
  2946. writel(MPI2_WRSEQ_6TH_KEY_VALUE, &ioc->chip->WriteSequence);
  2947. /* wait 100 msec */
  2948. if (sleep_flag == CAN_SLEEP)
  2949. msleep(100);
  2950. else
  2951. mdelay(100);
  2952. if (count++ > 20)
  2953. goto out;
  2954. host_diagnostic = readl(&ioc->chip->HostDiagnostic);
  2955. drsprintk(ioc, printk(MPT2SAS_INFO_FMT "wrote magic "
  2956. "sequence: count(%d), host_diagnostic(0x%08x)\n",
  2957. ioc->name, count, host_diagnostic));
  2958. } while ((host_diagnostic & MPI2_DIAG_DIAG_WRITE_ENABLE) == 0);
  2959. hcb_size = readl(&ioc->chip->HCBSize);
  2960. drsprintk(ioc, printk(MPT2SAS_INFO_FMT "diag reset: issued\n",
  2961. ioc->name));
  2962. writel(host_diagnostic | MPI2_DIAG_RESET_ADAPTER,
  2963. &ioc->chip->HostDiagnostic);
  2964. /* don't access any registers for 50 milliseconds */
  2965. msleep(50);
  2966. /* 300 second max wait */
  2967. for (count = 0; count < 3000000 ; count++) {
  2968. host_diagnostic = readl(&ioc->chip->HostDiagnostic);
  2969. if (host_diagnostic == 0xFFFFFFFF)
  2970. goto out;
  2971. if (!(host_diagnostic & MPI2_DIAG_RESET_ADAPTER))
  2972. break;
  2973. /* wait 100 msec */
  2974. if (sleep_flag == CAN_SLEEP)
  2975. msleep(1);
  2976. else
  2977. mdelay(1);
  2978. }
  2979. if (host_diagnostic & MPI2_DIAG_HCB_MODE) {
  2980. drsprintk(ioc, printk(MPT2SAS_INFO_FMT "restart the adapter "
  2981. "assuming the HCB Address points to good F/W\n",
  2982. ioc->name));
  2983. host_diagnostic &= ~MPI2_DIAG_BOOT_DEVICE_SELECT_MASK;
  2984. host_diagnostic |= MPI2_DIAG_BOOT_DEVICE_SELECT_HCDW;
  2985. writel(host_diagnostic, &ioc->chip->HostDiagnostic);
  2986. drsprintk(ioc, printk(MPT2SAS_INFO_FMT
  2987. "re-enable the HCDW\n", ioc->name));
  2988. writel(hcb_size | MPI2_HCB_SIZE_HCB_ENABLE,
  2989. &ioc->chip->HCBSize);
  2990. }
  2991. drsprintk(ioc, printk(MPT2SAS_INFO_FMT "restart the adapter\n",
  2992. ioc->name));
  2993. writel(host_diagnostic & ~MPI2_DIAG_HOLD_IOC_RESET,
  2994. &ioc->chip->HostDiagnostic);
  2995. drsprintk(ioc, printk(MPT2SAS_INFO_FMT "disable writes to the "
  2996. "diagnostic register\n", ioc->name));
  2997. writel(MPI2_WRSEQ_FLUSH_KEY_VALUE, &ioc->chip->WriteSequence);
  2998. drsprintk(ioc, printk(MPT2SAS_INFO_FMT "Wait for FW to go to the "
  2999. "READY state\n", ioc->name));
  3000. ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY, 20,
  3001. sleep_flag);
  3002. if (ioc_state) {
  3003. printk(MPT2SAS_ERR_FMT "%s: failed going to ready state "
  3004. " (ioc_state=0x%x)\n", ioc->name, __func__, ioc_state);
  3005. goto out;
  3006. }
  3007. _base_restore_msix_table(ioc);
  3008. printk(MPT2SAS_INFO_FMT "diag reset: SUCCESS\n", ioc->name);
  3009. return 0;
  3010. out:
  3011. printk(MPT2SAS_ERR_FMT "diag reset: FAILED\n", ioc->name);
  3012. return -EFAULT;
  3013. }
  3014. /**
  3015. * _base_make_ioc_ready - put controller in READY state
  3016. * @ioc: per adapter object
  3017. * @sleep_flag: CAN_SLEEP or NO_SLEEP
  3018. * @type: FORCE_BIG_HAMMER or SOFT_RESET
  3019. *
  3020. * Returns 0 for success, non-zero for failure.
  3021. */
  3022. static int
  3023. _base_make_ioc_ready(struct MPT2SAS_ADAPTER *ioc, int sleep_flag,
  3024. enum reset_type type)
  3025. {
  3026. u32 ioc_state;
  3027. int rc;
  3028. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "%s\n", ioc->name,
  3029. __func__));
  3030. ioc_state = mpt2sas_base_get_iocstate(ioc, 0);
  3031. dhsprintk(ioc, printk(MPT2SAS_INFO_FMT "%s: ioc_state(0x%08x)\n",
  3032. ioc->name, __func__, ioc_state));
  3033. if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_READY)
  3034. return 0;
  3035. if (ioc_state & MPI2_DOORBELL_USED) {
  3036. dhsprintk(ioc, printk(MPT2SAS_INFO_FMT "unexpected doorbell "
  3037. "active!\n", ioc->name));
  3038. goto issue_diag_reset;
  3039. }
  3040. if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) {
  3041. mpt2sas_base_fault_info(ioc, ioc_state &
  3042. MPI2_DOORBELL_DATA_MASK);
  3043. goto issue_diag_reset;
  3044. }
  3045. if (type == FORCE_BIG_HAMMER)
  3046. goto issue_diag_reset;
  3047. if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_OPERATIONAL)
  3048. if (!(_base_send_ioc_reset(ioc,
  3049. MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET, 15, CAN_SLEEP))) {
  3050. ioc->ioc_reset_count++;
  3051. return 0;
  3052. }
  3053. issue_diag_reset:
  3054. rc = _base_diag_reset(ioc, CAN_SLEEP);
  3055. ioc->ioc_reset_count++;
  3056. return rc;
  3057. }
  3058. /**
  3059. * _base_make_ioc_operational - put controller in OPERATIONAL state
  3060. * @ioc: per adapter object
  3061. * @sleep_flag: CAN_SLEEP or NO_SLEEP
  3062. *
  3063. * Returns 0 for success, non-zero for failure.
  3064. */
  3065. static int
  3066. _base_make_ioc_operational(struct MPT2SAS_ADAPTER *ioc, int sleep_flag)
  3067. {
  3068. int r, i;
  3069. unsigned long flags;
  3070. u32 reply_address;
  3071. u16 smid;
  3072. struct _tr_list *delayed_tr, *delayed_tr_next;
  3073. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "%s\n", ioc->name,
  3074. __func__));
  3075. /* clean the delayed target reset list */
  3076. list_for_each_entry_safe(delayed_tr, delayed_tr_next,
  3077. &ioc->delayed_tr_list, list) {
  3078. list_del(&delayed_tr->list);
  3079. kfree(delayed_tr);
  3080. }
  3081. /* initialize the scsi lookup free list */
  3082. spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
  3083. INIT_LIST_HEAD(&ioc->free_list);
  3084. smid = 1;
  3085. for (i = 0; i < ioc->scsiio_depth; i++, smid++) {
  3086. ioc->scsi_lookup[i].cb_idx = 0xFF;
  3087. ioc->scsi_lookup[i].smid = smid;
  3088. ioc->scsi_lookup[i].scmd = NULL;
  3089. list_add_tail(&ioc->scsi_lookup[i].tracker_list,
  3090. &ioc->free_list);
  3091. }
  3092. /* hi-priority queue */
  3093. INIT_LIST_HEAD(&ioc->hpr_free_list);
  3094. smid = ioc->hi_priority_smid;
  3095. for (i = 0; i < ioc->hi_priority_depth; i++, smid++) {
  3096. ioc->hpr_lookup[i].cb_idx = 0xFF;
  3097. ioc->hpr_lookup[i].smid = smid;
  3098. list_add_tail(&ioc->hpr_lookup[i].tracker_list,
  3099. &ioc->hpr_free_list);
  3100. }
  3101. /* internal queue */
  3102. INIT_LIST_HEAD(&ioc->internal_free_list);
  3103. smid = ioc->internal_smid;
  3104. for (i = 0; i < ioc->internal_depth; i++, smid++) {
  3105. ioc->internal_lookup[i].cb_idx = 0xFF;
  3106. ioc->internal_lookup[i].smid = smid;
  3107. list_add_tail(&ioc->internal_lookup[i].tracker_list,
  3108. &ioc->internal_free_list);
  3109. }
  3110. spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
  3111. /* initialize Reply Free Queue */
  3112. for (i = 0, reply_address = (u32)ioc->reply_dma ;
  3113. i < ioc->reply_free_queue_depth ; i++, reply_address +=
  3114. ioc->reply_sz)
  3115. ioc->reply_free[i] = cpu_to_le32(reply_address);
  3116. /* initialize Reply Post Free Queue */
  3117. for (i = 0; i < ioc->reply_post_queue_depth; i++)
  3118. ioc->reply_post_free[i].Words = ULLONG_MAX;
  3119. r = _base_send_ioc_init(ioc, sleep_flag);
  3120. if (r)
  3121. return r;
  3122. /* initialize the index's */
  3123. ioc->reply_free_host_index = ioc->reply_free_queue_depth - 1;
  3124. ioc->reply_post_host_index = 0;
  3125. writel(ioc->reply_free_host_index, &ioc->chip->ReplyFreeHostIndex);
  3126. writel(0, &ioc->chip->ReplyPostHostIndex);
  3127. _base_unmask_interrupts(ioc);
  3128. r = _base_event_notification(ioc, sleep_flag);
  3129. if (r)
  3130. return r;
  3131. if (sleep_flag == CAN_SLEEP)
  3132. _base_static_config_pages(ioc);
  3133. if (ioc->wait_for_port_enable_to_complete) {
  3134. if (diag_buffer_enable != 0)
  3135. mpt2sas_enable_diag_buffer(ioc, diag_buffer_enable);
  3136. if (disable_discovery > 0)
  3137. return r;
  3138. }
  3139. r = _base_send_port_enable(ioc, sleep_flag);
  3140. if (r)
  3141. return r;
  3142. return r;
  3143. }
  3144. /**
  3145. * mpt2sas_base_free_resources - free resources controller resources (io/irq/memap)
  3146. * @ioc: per adapter object
  3147. *
  3148. * Return nothing.
  3149. */
  3150. void
  3151. mpt2sas_base_free_resources(struct MPT2SAS_ADAPTER *ioc)
  3152. {
  3153. struct pci_dev *pdev = ioc->pdev;
  3154. dexitprintk(ioc, printk(MPT2SAS_INFO_FMT "%s\n", ioc->name,
  3155. __func__));
  3156. _base_mask_interrupts(ioc);
  3157. ioc->shost_recovery = 1;
  3158. _base_make_ioc_ready(ioc, CAN_SLEEP, SOFT_RESET);
  3159. ioc->shost_recovery = 0;
  3160. if (ioc->pci_irq) {
  3161. synchronize_irq(pdev->irq);
  3162. free_irq(ioc->pci_irq, ioc);
  3163. }
  3164. _base_disable_msix(ioc);
  3165. if (ioc->chip_phys)
  3166. iounmap(ioc->chip);
  3167. ioc->pci_irq = -1;
  3168. ioc->chip_phys = 0;
  3169. pci_release_selected_regions(ioc->pdev, ioc->bars);
  3170. pci_disable_pcie_error_reporting(pdev);
  3171. pci_disable_device(pdev);
  3172. return;
  3173. }
  3174. /**
  3175. * mpt2sas_base_attach - attach controller instance
  3176. * @ioc: per adapter object
  3177. *
  3178. * Returns 0 for success, non-zero for failure.
  3179. */
  3180. int
  3181. mpt2sas_base_attach(struct MPT2SAS_ADAPTER *ioc)
  3182. {
  3183. int r, i;
  3184. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "%s\n", ioc->name,
  3185. __func__));
  3186. r = mpt2sas_base_map_resources(ioc);
  3187. if (r)
  3188. return r;
  3189. pci_set_drvdata(ioc->pdev, ioc->shost);
  3190. r = _base_get_ioc_facts(ioc, CAN_SLEEP);
  3191. if (r)
  3192. goto out_free_resources;
  3193. r = _base_make_ioc_ready(ioc, CAN_SLEEP, SOFT_RESET);
  3194. if (r)
  3195. goto out_free_resources;
  3196. ioc->pfacts = kcalloc(ioc->facts.NumberOfPorts,
  3197. sizeof(Mpi2PortFactsReply_t), GFP_KERNEL);
  3198. if (!ioc->pfacts) {
  3199. r = -ENOMEM;
  3200. goto out_free_resources;
  3201. }
  3202. for (i = 0 ; i < ioc->facts.NumberOfPorts; i++) {
  3203. r = _base_get_port_facts(ioc, i, CAN_SLEEP);
  3204. if (r)
  3205. goto out_free_resources;
  3206. }
  3207. r = _base_allocate_memory_pools(ioc, CAN_SLEEP);
  3208. if (r)
  3209. goto out_free_resources;
  3210. init_waitqueue_head(&ioc->reset_wq);
  3211. ioc->fwfault_debug = mpt2sas_fwfault_debug;
  3212. /* base internal command bits */
  3213. mutex_init(&ioc->base_cmds.mutex);
  3214. ioc->base_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
  3215. ioc->base_cmds.status = MPT2_CMD_NOT_USED;
  3216. /* transport internal command bits */
  3217. ioc->transport_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
  3218. ioc->transport_cmds.status = MPT2_CMD_NOT_USED;
  3219. mutex_init(&ioc->transport_cmds.mutex);
  3220. /* scsih internal command bits */
  3221. ioc->scsih_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
  3222. ioc->scsih_cmds.status = MPT2_CMD_NOT_USED;
  3223. mutex_init(&ioc->scsih_cmds.mutex);
  3224. /* task management internal command bits */
  3225. ioc->tm_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
  3226. ioc->tm_cmds.status = MPT2_CMD_NOT_USED;
  3227. mutex_init(&ioc->tm_cmds.mutex);
  3228. /* config page internal command bits */
  3229. ioc->config_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
  3230. ioc->config_cmds.status = MPT2_CMD_NOT_USED;
  3231. mutex_init(&ioc->config_cmds.mutex);
  3232. /* ctl module internal command bits */
  3233. ioc->ctl_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
  3234. ioc->ctl_cmds.status = MPT2_CMD_NOT_USED;
  3235. mutex_init(&ioc->ctl_cmds.mutex);
  3236. if (!ioc->base_cmds.reply || !ioc->transport_cmds.reply ||
  3237. !ioc->scsih_cmds.reply || !ioc->tm_cmds.reply ||
  3238. !ioc->config_cmds.reply || !ioc->ctl_cmds.reply) {
  3239. r = -ENOMEM;
  3240. goto out_free_resources;
  3241. }
  3242. init_completion(&ioc->shost_recovery_done);
  3243. for (i = 0; i < MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++)
  3244. ioc->event_masks[i] = -1;
  3245. /* here we enable the events we care about */
  3246. _base_unmask_events(ioc, MPI2_EVENT_SAS_DISCOVERY);
  3247. _base_unmask_events(ioc, MPI2_EVENT_SAS_BROADCAST_PRIMITIVE);
  3248. _base_unmask_events(ioc, MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST);
  3249. _base_unmask_events(ioc, MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE);
  3250. _base_unmask_events(ioc, MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE);
  3251. _base_unmask_events(ioc, MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST);
  3252. _base_unmask_events(ioc, MPI2_EVENT_IR_VOLUME);
  3253. _base_unmask_events(ioc, MPI2_EVENT_IR_PHYSICAL_DISK);
  3254. _base_unmask_events(ioc, MPI2_EVENT_IR_OPERATION_STATUS);
  3255. _base_unmask_events(ioc, MPI2_EVENT_TASK_SET_FULL);
  3256. _base_unmask_events(ioc, MPI2_EVENT_LOG_ENTRY_ADDED);
  3257. r = _base_make_ioc_operational(ioc, CAN_SLEEP);
  3258. if (r)
  3259. goto out_free_resources;
  3260. mpt2sas_base_start_watchdog(ioc);
  3261. return 0;
  3262. out_free_resources:
  3263. ioc->remove_host = 1;
  3264. mpt2sas_base_free_resources(ioc);
  3265. _base_release_memory_pools(ioc);
  3266. pci_set_drvdata(ioc->pdev, NULL);
  3267. kfree(ioc->tm_cmds.reply);
  3268. kfree(ioc->transport_cmds.reply);
  3269. kfree(ioc->scsih_cmds.reply);
  3270. kfree(ioc->config_cmds.reply);
  3271. kfree(ioc->base_cmds.reply);
  3272. kfree(ioc->ctl_cmds.reply);
  3273. kfree(ioc->pfacts);
  3274. ioc->ctl_cmds.reply = NULL;
  3275. ioc->base_cmds.reply = NULL;
  3276. ioc->tm_cmds.reply = NULL;
  3277. ioc->scsih_cmds.reply = NULL;
  3278. ioc->transport_cmds.reply = NULL;
  3279. ioc->config_cmds.reply = NULL;
  3280. ioc->pfacts = NULL;
  3281. return r;
  3282. }
  3283. /**
  3284. * mpt2sas_base_detach - remove controller instance
  3285. * @ioc: per adapter object
  3286. *
  3287. * Return nothing.
  3288. */
  3289. void
  3290. mpt2sas_base_detach(struct MPT2SAS_ADAPTER *ioc)
  3291. {
  3292. dexitprintk(ioc, printk(MPT2SAS_INFO_FMT "%s\n", ioc->name,
  3293. __func__));
  3294. mpt2sas_base_stop_watchdog(ioc);
  3295. mpt2sas_base_free_resources(ioc);
  3296. _base_release_memory_pools(ioc);
  3297. pci_set_drvdata(ioc->pdev, NULL);
  3298. kfree(ioc->pfacts);
  3299. kfree(ioc->ctl_cmds.reply);
  3300. kfree(ioc->base_cmds.reply);
  3301. kfree(ioc->tm_cmds.reply);
  3302. kfree(ioc->transport_cmds.reply);
  3303. kfree(ioc->scsih_cmds.reply);
  3304. kfree(ioc->config_cmds.reply);
  3305. }
  3306. /**
  3307. * _base_reset_handler - reset callback handler (for base)
  3308. * @ioc: per adapter object
  3309. * @reset_phase: phase
  3310. *
  3311. * The handler for doing any required cleanup or initialization.
  3312. *
  3313. * The reset phase can be MPT2_IOC_PRE_RESET, MPT2_IOC_AFTER_RESET,
  3314. * MPT2_IOC_DONE_RESET
  3315. *
  3316. * Return nothing.
  3317. */
  3318. static void
  3319. _base_reset_handler(struct MPT2SAS_ADAPTER *ioc, int reset_phase)
  3320. {
  3321. switch (reset_phase) {
  3322. case MPT2_IOC_PRE_RESET:
  3323. dtmprintk(ioc, printk(MPT2SAS_INFO_FMT "%s: "
  3324. "MPT2_IOC_PRE_RESET\n", ioc->name, __func__));
  3325. break;
  3326. case MPT2_IOC_AFTER_RESET:
  3327. dtmprintk(ioc, printk(MPT2SAS_INFO_FMT "%s: "
  3328. "MPT2_IOC_AFTER_RESET\n", ioc->name, __func__));
  3329. if (ioc->transport_cmds.status & MPT2_CMD_PENDING) {
  3330. ioc->transport_cmds.status |= MPT2_CMD_RESET;
  3331. mpt2sas_base_free_smid(ioc, ioc->transport_cmds.smid);
  3332. complete(&ioc->transport_cmds.done);
  3333. }
  3334. if (ioc->base_cmds.status & MPT2_CMD_PENDING) {
  3335. ioc->base_cmds.status |= MPT2_CMD_RESET;
  3336. mpt2sas_base_free_smid(ioc, ioc->base_cmds.smid);
  3337. complete(&ioc->base_cmds.done);
  3338. }
  3339. if (ioc->config_cmds.status & MPT2_CMD_PENDING) {
  3340. ioc->config_cmds.status |= MPT2_CMD_RESET;
  3341. mpt2sas_base_free_smid(ioc, ioc->config_cmds.smid);
  3342. ioc->config_cmds.smid = USHRT_MAX;
  3343. complete(&ioc->config_cmds.done);
  3344. }
  3345. break;
  3346. case MPT2_IOC_DONE_RESET:
  3347. dtmprintk(ioc, printk(MPT2SAS_INFO_FMT "%s: "
  3348. "MPT2_IOC_DONE_RESET\n", ioc->name, __func__));
  3349. break;
  3350. }
  3351. mpt2sas_scsih_reset_handler(ioc, reset_phase);
  3352. mpt2sas_ctl_reset_handler(ioc, reset_phase);
  3353. }
  3354. /**
  3355. * _wait_for_commands_to_complete - reset controller
  3356. * @ioc: Pointer to MPT_ADAPTER structure
  3357. * @sleep_flag: CAN_SLEEP or NO_SLEEP
  3358. *
  3359. * This function waiting(3s) for all pending commands to complete
  3360. * prior to putting controller in reset.
  3361. */
  3362. static void
  3363. _wait_for_commands_to_complete(struct MPT2SAS_ADAPTER *ioc, int sleep_flag)
  3364. {
  3365. u32 ioc_state;
  3366. unsigned long flags;
  3367. u16 i;
  3368. ioc->pending_io_count = 0;
  3369. if (sleep_flag != CAN_SLEEP)
  3370. return;
  3371. ioc_state = mpt2sas_base_get_iocstate(ioc, 0);
  3372. if ((ioc_state & MPI2_IOC_STATE_MASK) != MPI2_IOC_STATE_OPERATIONAL)
  3373. return;
  3374. /* pending command count */
  3375. spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
  3376. for (i = 0; i < ioc->scsiio_depth; i++)
  3377. if (ioc->scsi_lookup[i].cb_idx != 0xFF)
  3378. ioc->pending_io_count++;
  3379. spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
  3380. if (!ioc->pending_io_count)
  3381. return;
  3382. /* wait for pending commands to complete */
  3383. wait_event_timeout(ioc->reset_wq, ioc->pending_io_count == 0, 10 * HZ);
  3384. }
  3385. /**
  3386. * mpt2sas_base_hard_reset_handler - reset controller
  3387. * @ioc: Pointer to MPT_ADAPTER structure
  3388. * @sleep_flag: CAN_SLEEP or NO_SLEEP
  3389. * @type: FORCE_BIG_HAMMER or SOFT_RESET
  3390. *
  3391. * Returns 0 for success, non-zero for failure.
  3392. */
  3393. int
  3394. mpt2sas_base_hard_reset_handler(struct MPT2SAS_ADAPTER *ioc, int sleep_flag,
  3395. enum reset_type type)
  3396. {
  3397. int r;
  3398. unsigned long flags;
  3399. dtmprintk(ioc, printk(MPT2SAS_INFO_FMT "%s: enter\n", ioc->name,
  3400. __func__));
  3401. if (mpt2sas_fwfault_debug)
  3402. mpt2sas_halt_firmware(ioc);
  3403. /* TODO - What we really should be doing is pulling
  3404. * out all the code associated with NO_SLEEP; its never used.
  3405. * That is legacy code from mpt fusion driver, ported over.
  3406. * I will leave this BUG_ON here for now till its been resolved.
  3407. */
  3408. BUG_ON(sleep_flag == NO_SLEEP);
  3409. /* wait for an active reset in progress to complete */
  3410. if (!mutex_trylock(&ioc->reset_in_progress_mutex)) {
  3411. do {
  3412. ssleep(1);
  3413. } while (ioc->shost_recovery == 1);
  3414. dtmprintk(ioc, printk(MPT2SAS_INFO_FMT "%s: exit\n", ioc->name,
  3415. __func__));
  3416. return ioc->ioc_reset_in_progress_status;
  3417. }
  3418. spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
  3419. ioc->shost_recovery = 1;
  3420. spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
  3421. _base_reset_handler(ioc, MPT2_IOC_PRE_RESET);
  3422. _wait_for_commands_to_complete(ioc, sleep_flag);
  3423. _base_mask_interrupts(ioc);
  3424. r = _base_make_ioc_ready(ioc, sleep_flag, type);
  3425. if (r)
  3426. goto out;
  3427. _base_reset_handler(ioc, MPT2_IOC_AFTER_RESET);
  3428. r = _base_make_ioc_operational(ioc, sleep_flag);
  3429. if (!r)
  3430. _base_reset_handler(ioc, MPT2_IOC_DONE_RESET);
  3431. out:
  3432. dtmprintk(ioc, printk(MPT2SAS_INFO_FMT "%s: %s\n",
  3433. ioc->name, __func__, ((r == 0) ? "SUCCESS" : "FAILED")));
  3434. spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
  3435. ioc->ioc_reset_in_progress_status = r;
  3436. ioc->shost_recovery = 0;
  3437. complete(&ioc->shost_recovery_done);
  3438. spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
  3439. mutex_unlock(&ioc->reset_in_progress_mutex);
  3440. dtmprintk(ioc, printk(MPT2SAS_INFO_FMT "%s: exit\n", ioc->name,
  3441. __func__));
  3442. return r;
  3443. }