intel_crt.c 21 KB

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  1. /*
  2. * Copyright © 2006-2007 Intel Corporation
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice (including the next
  12. * paragraph) shall be included in all copies or substantial portions of the
  13. * Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  18. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21. * DEALINGS IN THE SOFTWARE.
  22. *
  23. * Authors:
  24. * Eric Anholt <eric@anholt.net>
  25. */
  26. #include <linux/dmi.h>
  27. #include <linux/i2c.h>
  28. #include <linux/slab.h>
  29. #include <drm/drmP.h>
  30. #include <drm/drm_crtc.h>
  31. #include <drm/drm_crtc_helper.h>
  32. #include <drm/drm_edid.h>
  33. #include "intel_drv.h"
  34. #include <drm/i915_drm.h>
  35. #include "i915_drv.h"
  36. /* Here's the desired hotplug mode */
  37. #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 | \
  38. ADPA_CRT_HOTPLUG_WARMUP_10MS | \
  39. ADPA_CRT_HOTPLUG_SAMPLE_4S | \
  40. ADPA_CRT_HOTPLUG_VOLTAGE_50 | \
  41. ADPA_CRT_HOTPLUG_VOLREF_325MV | \
  42. ADPA_CRT_HOTPLUG_ENABLE)
  43. struct intel_crt {
  44. struct intel_encoder base;
  45. bool force_hotplug_required;
  46. u32 adpa_reg;
  47. };
  48. static struct intel_crt *intel_attached_crt(struct drm_connector *connector)
  49. {
  50. return container_of(intel_attached_encoder(connector),
  51. struct intel_crt, base);
  52. }
  53. static struct intel_crt *intel_encoder_to_crt(struct intel_encoder *encoder)
  54. {
  55. return container_of(encoder, struct intel_crt, base);
  56. }
  57. static bool intel_crt_get_hw_state(struct intel_encoder *encoder,
  58. enum pipe *pipe)
  59. {
  60. struct drm_device *dev = encoder->base.dev;
  61. struct drm_i915_private *dev_priv = dev->dev_private;
  62. struct intel_crt *crt = intel_encoder_to_crt(encoder);
  63. u32 tmp;
  64. tmp = I915_READ(crt->adpa_reg);
  65. if (!(tmp & ADPA_DAC_ENABLE))
  66. return false;
  67. if (HAS_PCH_CPT(dev))
  68. *pipe = PORT_TO_PIPE_CPT(tmp);
  69. else
  70. *pipe = PORT_TO_PIPE(tmp);
  71. return true;
  72. }
  73. static void intel_disable_crt(struct intel_encoder *encoder)
  74. {
  75. struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
  76. struct intel_crt *crt = intel_encoder_to_crt(encoder);
  77. u32 temp;
  78. temp = I915_READ(crt->adpa_reg);
  79. temp &= ~(ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE);
  80. temp &= ~ADPA_DAC_ENABLE;
  81. I915_WRITE(crt->adpa_reg, temp);
  82. }
  83. static void intel_enable_crt(struct intel_encoder *encoder)
  84. {
  85. struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
  86. struct intel_crt *crt = intel_encoder_to_crt(encoder);
  87. u32 temp;
  88. temp = I915_READ(crt->adpa_reg);
  89. temp |= ADPA_DAC_ENABLE;
  90. I915_WRITE(crt->adpa_reg, temp);
  91. }
  92. /* Note: The caller is required to filter out dpms modes not supported by the
  93. * platform. */
  94. static void intel_crt_set_dpms(struct intel_encoder *encoder, int mode)
  95. {
  96. struct drm_device *dev = encoder->base.dev;
  97. struct drm_i915_private *dev_priv = dev->dev_private;
  98. struct intel_crt *crt = intel_encoder_to_crt(encoder);
  99. u32 temp;
  100. temp = I915_READ(crt->adpa_reg);
  101. temp &= ~(ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE);
  102. temp &= ~ADPA_DAC_ENABLE;
  103. switch (mode) {
  104. case DRM_MODE_DPMS_ON:
  105. temp |= ADPA_DAC_ENABLE;
  106. break;
  107. case DRM_MODE_DPMS_STANDBY:
  108. temp |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE;
  109. break;
  110. case DRM_MODE_DPMS_SUSPEND:
  111. temp |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE;
  112. break;
  113. case DRM_MODE_DPMS_OFF:
  114. temp |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE;
  115. break;
  116. }
  117. I915_WRITE(crt->adpa_reg, temp);
  118. }
  119. static void intel_crt_dpms(struct drm_connector *connector, int mode)
  120. {
  121. struct drm_device *dev = connector->dev;
  122. struct intel_encoder *encoder = intel_attached_encoder(connector);
  123. struct drm_crtc *crtc;
  124. int old_dpms;
  125. /* PCH platforms and VLV only support on/off. */
  126. if (INTEL_INFO(dev)->gen < 5 && mode != DRM_MODE_DPMS_ON)
  127. mode = DRM_MODE_DPMS_OFF;
  128. if (mode == connector->dpms)
  129. return;
  130. old_dpms = connector->dpms;
  131. connector->dpms = mode;
  132. /* Only need to change hw state when actually enabled */
  133. crtc = encoder->base.crtc;
  134. if (!crtc) {
  135. encoder->connectors_active = false;
  136. return;
  137. }
  138. /* We need the pipe to run for anything but OFF. */
  139. if (mode == DRM_MODE_DPMS_OFF)
  140. encoder->connectors_active = false;
  141. else
  142. encoder->connectors_active = true;
  143. if (mode < old_dpms) {
  144. /* From off to on, enable the pipe first. */
  145. intel_crtc_update_dpms(crtc);
  146. intel_crt_set_dpms(encoder, mode);
  147. } else {
  148. intel_crt_set_dpms(encoder, mode);
  149. intel_crtc_update_dpms(crtc);
  150. }
  151. intel_modeset_check_state(connector->dev);
  152. }
  153. static int intel_crt_mode_valid(struct drm_connector *connector,
  154. struct drm_display_mode *mode)
  155. {
  156. struct drm_device *dev = connector->dev;
  157. int max_clock = 0;
  158. if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
  159. return MODE_NO_DBLESCAN;
  160. if (mode->clock < 25000)
  161. return MODE_CLOCK_LOW;
  162. if (IS_GEN2(dev))
  163. max_clock = 350000;
  164. else
  165. max_clock = 400000;
  166. if (mode->clock > max_clock)
  167. return MODE_CLOCK_HIGH;
  168. return MODE_OK;
  169. }
  170. static bool intel_crt_mode_fixup(struct drm_encoder *encoder,
  171. const struct drm_display_mode *mode,
  172. struct drm_display_mode *adjusted_mode)
  173. {
  174. return true;
  175. }
  176. static void intel_crt_mode_set(struct drm_encoder *encoder,
  177. struct drm_display_mode *mode,
  178. struct drm_display_mode *adjusted_mode)
  179. {
  180. struct drm_device *dev = encoder->dev;
  181. struct drm_crtc *crtc = encoder->crtc;
  182. struct intel_crt *crt =
  183. intel_encoder_to_crt(to_intel_encoder(encoder));
  184. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  185. struct drm_i915_private *dev_priv = dev->dev_private;
  186. u32 adpa;
  187. if (HAS_PCH_SPLIT(dev))
  188. adpa = ADPA_HOTPLUG_BITS;
  189. else
  190. adpa = 0;
  191. if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
  192. adpa |= ADPA_HSYNC_ACTIVE_HIGH;
  193. if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
  194. adpa |= ADPA_VSYNC_ACTIVE_HIGH;
  195. /* For CPT allow 3 pipe config, for others just use A or B */
  196. if (HAS_PCH_LPT(dev))
  197. ; /* Those bits don't exist here */
  198. else if (HAS_PCH_CPT(dev))
  199. adpa |= PORT_TRANS_SEL_CPT(intel_crtc->pipe);
  200. else if (intel_crtc->pipe == 0)
  201. adpa |= ADPA_PIPE_A_SELECT;
  202. else
  203. adpa |= ADPA_PIPE_B_SELECT;
  204. if (!HAS_PCH_SPLIT(dev))
  205. I915_WRITE(BCLRPAT(intel_crtc->pipe), 0);
  206. I915_WRITE(crt->adpa_reg, adpa);
  207. }
  208. static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector)
  209. {
  210. struct drm_device *dev = connector->dev;
  211. struct intel_crt *crt = intel_attached_crt(connector);
  212. struct drm_i915_private *dev_priv = dev->dev_private;
  213. u32 adpa;
  214. bool ret;
  215. /* The first time through, trigger an explicit detection cycle */
  216. if (crt->force_hotplug_required) {
  217. bool turn_off_dac = HAS_PCH_SPLIT(dev);
  218. u32 save_adpa;
  219. crt->force_hotplug_required = 0;
  220. save_adpa = adpa = I915_READ(PCH_ADPA);
  221. DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
  222. adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
  223. if (turn_off_dac)
  224. adpa &= ~ADPA_DAC_ENABLE;
  225. I915_WRITE(PCH_ADPA, adpa);
  226. if (wait_for((I915_READ(PCH_ADPA) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0,
  227. 1000))
  228. DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");
  229. if (turn_off_dac) {
  230. I915_WRITE(PCH_ADPA, save_adpa);
  231. POSTING_READ(PCH_ADPA);
  232. }
  233. }
  234. /* Check the status to see if both blue and green are on now */
  235. adpa = I915_READ(PCH_ADPA);
  236. if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
  237. ret = true;
  238. else
  239. ret = false;
  240. DRM_DEBUG_KMS("ironlake hotplug adpa=0x%x, result %d\n", adpa, ret);
  241. return ret;
  242. }
  243. static bool valleyview_crt_detect_hotplug(struct drm_connector *connector)
  244. {
  245. struct drm_device *dev = connector->dev;
  246. struct drm_i915_private *dev_priv = dev->dev_private;
  247. u32 adpa;
  248. bool ret;
  249. u32 save_adpa;
  250. save_adpa = adpa = I915_READ(ADPA);
  251. DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
  252. adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
  253. I915_WRITE(ADPA, adpa);
  254. if (wait_for((I915_READ(ADPA) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0,
  255. 1000)) {
  256. DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");
  257. I915_WRITE(ADPA, save_adpa);
  258. }
  259. /* Check the status to see if both blue and green are on now */
  260. adpa = I915_READ(ADPA);
  261. if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
  262. ret = true;
  263. else
  264. ret = false;
  265. DRM_DEBUG_KMS("valleyview hotplug adpa=0x%x, result %d\n", adpa, ret);
  266. /* FIXME: debug force function and remove */
  267. ret = true;
  268. return ret;
  269. }
  270. /**
  271. * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect CRT presence.
  272. *
  273. * Not for i915G/i915GM
  274. *
  275. * \return true if CRT is connected.
  276. * \return false if CRT is disconnected.
  277. */
  278. static bool intel_crt_detect_hotplug(struct drm_connector *connector)
  279. {
  280. struct drm_device *dev = connector->dev;
  281. struct drm_i915_private *dev_priv = dev->dev_private;
  282. u32 hotplug_en, orig, stat;
  283. bool ret = false;
  284. int i, tries = 0;
  285. if (HAS_PCH_SPLIT(dev))
  286. return intel_ironlake_crt_detect_hotplug(connector);
  287. if (IS_VALLEYVIEW(dev))
  288. return valleyview_crt_detect_hotplug(connector);
  289. /*
  290. * On 4 series desktop, CRT detect sequence need to be done twice
  291. * to get a reliable result.
  292. */
  293. if (IS_G4X(dev) && !IS_GM45(dev))
  294. tries = 2;
  295. else
  296. tries = 1;
  297. hotplug_en = orig = I915_READ(PORT_HOTPLUG_EN);
  298. hotplug_en |= CRT_HOTPLUG_FORCE_DETECT;
  299. for (i = 0; i < tries ; i++) {
  300. /* turn on the FORCE_DETECT */
  301. I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
  302. /* wait for FORCE_DETECT to go off */
  303. if (wait_for((I915_READ(PORT_HOTPLUG_EN) &
  304. CRT_HOTPLUG_FORCE_DETECT) == 0,
  305. 1000))
  306. DRM_DEBUG_KMS("timed out waiting for FORCE_DETECT to go off");
  307. }
  308. stat = I915_READ(PORT_HOTPLUG_STAT);
  309. if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE)
  310. ret = true;
  311. /* clear the interrupt we just generated, if any */
  312. I915_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS);
  313. /* and put the bits back */
  314. I915_WRITE(PORT_HOTPLUG_EN, orig);
  315. return ret;
  316. }
  317. static struct edid *intel_crt_get_edid(struct drm_connector *connector,
  318. struct i2c_adapter *i2c)
  319. {
  320. struct edid *edid;
  321. edid = drm_get_edid(connector, i2c);
  322. if (!edid && !intel_gmbus_is_forced_bit(i2c)) {
  323. DRM_DEBUG_KMS("CRT GMBUS EDID read failed, retry using GPIO bit-banging\n");
  324. intel_gmbus_force_bit(i2c, true);
  325. edid = drm_get_edid(connector, i2c);
  326. intel_gmbus_force_bit(i2c, false);
  327. }
  328. return edid;
  329. }
  330. /* local version of intel_ddc_get_modes() to use intel_crt_get_edid() */
  331. static int intel_crt_ddc_get_modes(struct drm_connector *connector,
  332. struct i2c_adapter *adapter)
  333. {
  334. struct edid *edid;
  335. int ret;
  336. edid = intel_crt_get_edid(connector, adapter);
  337. if (!edid)
  338. return 0;
  339. ret = intel_connector_update_modes(connector, edid);
  340. kfree(edid);
  341. return ret;
  342. }
  343. static bool intel_crt_detect_ddc(struct drm_connector *connector)
  344. {
  345. struct intel_crt *crt = intel_attached_crt(connector);
  346. struct drm_i915_private *dev_priv = crt->base.base.dev->dev_private;
  347. struct edid *edid;
  348. struct i2c_adapter *i2c;
  349. BUG_ON(crt->base.type != INTEL_OUTPUT_ANALOG);
  350. i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->crt_ddc_pin);
  351. edid = intel_crt_get_edid(connector, i2c);
  352. if (edid) {
  353. bool is_digital = edid->input & DRM_EDID_INPUT_DIGITAL;
  354. /*
  355. * This may be a DVI-I connector with a shared DDC
  356. * link between analog and digital outputs, so we
  357. * have to check the EDID input spec of the attached device.
  358. */
  359. if (!is_digital) {
  360. DRM_DEBUG_KMS("CRT detected via DDC:0x50 [EDID]\n");
  361. return true;
  362. }
  363. DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [EDID reports a digital panel]\n");
  364. } else {
  365. DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [no valid EDID found]\n");
  366. }
  367. kfree(edid);
  368. return false;
  369. }
  370. static enum drm_connector_status
  371. intel_crt_load_detect(struct intel_crt *crt)
  372. {
  373. struct drm_device *dev = crt->base.base.dev;
  374. struct drm_i915_private *dev_priv = dev->dev_private;
  375. uint32_t pipe = to_intel_crtc(crt->base.base.crtc)->pipe;
  376. uint32_t save_bclrpat;
  377. uint32_t save_vtotal;
  378. uint32_t vtotal, vactive;
  379. uint32_t vsample;
  380. uint32_t vblank, vblank_start, vblank_end;
  381. uint32_t dsl;
  382. uint32_t bclrpat_reg;
  383. uint32_t vtotal_reg;
  384. uint32_t vblank_reg;
  385. uint32_t vsync_reg;
  386. uint32_t pipeconf_reg;
  387. uint32_t pipe_dsl_reg;
  388. uint8_t st00;
  389. enum drm_connector_status status;
  390. DRM_DEBUG_KMS("starting load-detect on CRT\n");
  391. bclrpat_reg = BCLRPAT(pipe);
  392. vtotal_reg = VTOTAL(pipe);
  393. vblank_reg = VBLANK(pipe);
  394. vsync_reg = VSYNC(pipe);
  395. pipeconf_reg = PIPECONF(pipe);
  396. pipe_dsl_reg = PIPEDSL(pipe);
  397. save_bclrpat = I915_READ(bclrpat_reg);
  398. save_vtotal = I915_READ(vtotal_reg);
  399. vblank = I915_READ(vblank_reg);
  400. vtotal = ((save_vtotal >> 16) & 0xfff) + 1;
  401. vactive = (save_vtotal & 0x7ff) + 1;
  402. vblank_start = (vblank & 0xfff) + 1;
  403. vblank_end = ((vblank >> 16) & 0xfff) + 1;
  404. /* Set the border color to purple. */
  405. I915_WRITE(bclrpat_reg, 0x500050);
  406. if (!IS_GEN2(dev)) {
  407. uint32_t pipeconf = I915_READ(pipeconf_reg);
  408. I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER);
  409. POSTING_READ(pipeconf_reg);
  410. /* Wait for next Vblank to substitue
  411. * border color for Color info */
  412. intel_wait_for_vblank(dev, pipe);
  413. st00 = I915_READ8(VGA_MSR_WRITE);
  414. status = ((st00 & (1 << 4)) != 0) ?
  415. connector_status_connected :
  416. connector_status_disconnected;
  417. I915_WRITE(pipeconf_reg, pipeconf);
  418. } else {
  419. bool restore_vblank = false;
  420. int count, detect;
  421. /*
  422. * If there isn't any border, add some.
  423. * Yes, this will flicker
  424. */
  425. if (vblank_start <= vactive && vblank_end >= vtotal) {
  426. uint32_t vsync = I915_READ(vsync_reg);
  427. uint32_t vsync_start = (vsync & 0xffff) + 1;
  428. vblank_start = vsync_start;
  429. I915_WRITE(vblank_reg,
  430. (vblank_start - 1) |
  431. ((vblank_end - 1) << 16));
  432. restore_vblank = true;
  433. }
  434. /* sample in the vertical border, selecting the larger one */
  435. if (vblank_start - vactive >= vtotal - vblank_end)
  436. vsample = (vblank_start + vactive) >> 1;
  437. else
  438. vsample = (vtotal + vblank_end) >> 1;
  439. /*
  440. * Wait for the border to be displayed
  441. */
  442. while (I915_READ(pipe_dsl_reg) >= vactive)
  443. ;
  444. while ((dsl = I915_READ(pipe_dsl_reg)) <= vsample)
  445. ;
  446. /*
  447. * Watch ST00 for an entire scanline
  448. */
  449. detect = 0;
  450. count = 0;
  451. do {
  452. count++;
  453. /* Read the ST00 VGA status register */
  454. st00 = I915_READ8(VGA_MSR_WRITE);
  455. if (st00 & (1 << 4))
  456. detect++;
  457. } while ((I915_READ(pipe_dsl_reg) == dsl));
  458. /* restore vblank if necessary */
  459. if (restore_vblank)
  460. I915_WRITE(vblank_reg, vblank);
  461. /*
  462. * If more than 3/4 of the scanline detected a monitor,
  463. * then it is assumed to be present. This works even on i830,
  464. * where there isn't any way to force the border color across
  465. * the screen
  466. */
  467. status = detect * 4 > count * 3 ?
  468. connector_status_connected :
  469. connector_status_disconnected;
  470. }
  471. /* Restore previous settings */
  472. I915_WRITE(bclrpat_reg, save_bclrpat);
  473. return status;
  474. }
  475. static enum drm_connector_status
  476. intel_crt_detect(struct drm_connector *connector, bool force)
  477. {
  478. struct drm_device *dev = connector->dev;
  479. struct intel_crt *crt = intel_attached_crt(connector);
  480. enum drm_connector_status status;
  481. struct intel_load_detect_pipe tmp;
  482. if (I915_HAS_HOTPLUG(dev)) {
  483. /* We can not rely on the HPD pin always being correctly wired
  484. * up, for example many KVM do not pass it through, and so
  485. * only trust an assertion that the monitor is connected.
  486. */
  487. if (intel_crt_detect_hotplug(connector)) {
  488. DRM_DEBUG_KMS("CRT detected via hotplug\n");
  489. return connector_status_connected;
  490. } else
  491. DRM_DEBUG_KMS("CRT not detected via hotplug\n");
  492. }
  493. if (intel_crt_detect_ddc(connector))
  494. return connector_status_connected;
  495. /* Load detection is broken on HPD capable machines. Whoever wants a
  496. * broken monitor (without edid) to work behind a broken kvm (that fails
  497. * to have the right resistors for HP detection) needs to fix this up.
  498. * For now just bail out. */
  499. if (I915_HAS_HOTPLUG(dev))
  500. return connector_status_disconnected;
  501. if (!force)
  502. return connector->status;
  503. /* for pre-945g platforms use load detect */
  504. if (intel_get_load_detect_pipe(connector, NULL, &tmp)) {
  505. if (intel_crt_detect_ddc(connector))
  506. status = connector_status_connected;
  507. else
  508. status = intel_crt_load_detect(crt);
  509. intel_release_load_detect_pipe(connector, &tmp);
  510. } else
  511. status = connector_status_unknown;
  512. return status;
  513. }
  514. static void intel_crt_destroy(struct drm_connector *connector)
  515. {
  516. drm_sysfs_connector_remove(connector);
  517. drm_connector_cleanup(connector);
  518. kfree(connector);
  519. }
  520. static int intel_crt_get_modes(struct drm_connector *connector)
  521. {
  522. struct drm_device *dev = connector->dev;
  523. struct drm_i915_private *dev_priv = dev->dev_private;
  524. int ret;
  525. struct i2c_adapter *i2c;
  526. i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->crt_ddc_pin);
  527. ret = intel_crt_ddc_get_modes(connector, i2c);
  528. if (ret || !IS_G4X(dev))
  529. return ret;
  530. /* Try to probe digital port for output in DVI-I -> VGA mode. */
  531. i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PORT_DPB);
  532. return intel_crt_ddc_get_modes(connector, i2c);
  533. }
  534. static int intel_crt_set_property(struct drm_connector *connector,
  535. struct drm_property *property,
  536. uint64_t value)
  537. {
  538. return 0;
  539. }
  540. static void intel_crt_reset(struct drm_connector *connector)
  541. {
  542. struct drm_device *dev = connector->dev;
  543. struct drm_i915_private *dev_priv = dev->dev_private;
  544. struct intel_crt *crt = intel_attached_crt(connector);
  545. if (HAS_PCH_SPLIT(dev)) {
  546. u32 adpa;
  547. adpa = I915_READ(PCH_ADPA);
  548. adpa &= ~ADPA_CRT_HOTPLUG_MASK;
  549. adpa |= ADPA_HOTPLUG_BITS;
  550. I915_WRITE(PCH_ADPA, adpa);
  551. POSTING_READ(PCH_ADPA);
  552. DRM_DEBUG_KMS("pch crt adpa set to 0x%x\n", adpa);
  553. crt->force_hotplug_required = 1;
  554. }
  555. }
  556. /*
  557. * Routines for controlling stuff on the analog port
  558. */
  559. static const struct drm_encoder_helper_funcs crt_encoder_funcs = {
  560. .mode_fixup = intel_crt_mode_fixup,
  561. .mode_set = intel_crt_mode_set,
  562. .disable = intel_encoder_noop,
  563. };
  564. static const struct drm_connector_funcs intel_crt_connector_funcs = {
  565. .reset = intel_crt_reset,
  566. .dpms = intel_crt_dpms,
  567. .detect = intel_crt_detect,
  568. .fill_modes = drm_helper_probe_single_connector_modes,
  569. .destroy = intel_crt_destroy,
  570. .set_property = intel_crt_set_property,
  571. };
  572. static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = {
  573. .mode_valid = intel_crt_mode_valid,
  574. .get_modes = intel_crt_get_modes,
  575. .best_encoder = intel_best_encoder,
  576. };
  577. static const struct drm_encoder_funcs intel_crt_enc_funcs = {
  578. .destroy = intel_encoder_destroy,
  579. };
  580. static int __init intel_no_crt_dmi_callback(const struct dmi_system_id *id)
  581. {
  582. DRM_INFO("Skipping CRT initialization for %s\n", id->ident);
  583. return 1;
  584. }
  585. static const struct dmi_system_id intel_no_crt[] = {
  586. {
  587. .callback = intel_no_crt_dmi_callback,
  588. .ident = "ACER ZGB",
  589. .matches = {
  590. DMI_MATCH(DMI_SYS_VENDOR, "ACER"),
  591. DMI_MATCH(DMI_PRODUCT_NAME, "ZGB"),
  592. },
  593. },
  594. { }
  595. };
  596. void intel_crt_init(struct drm_device *dev)
  597. {
  598. struct drm_connector *connector;
  599. struct intel_crt *crt;
  600. struct intel_connector *intel_connector;
  601. struct drm_i915_private *dev_priv = dev->dev_private;
  602. /* Skip machines without VGA that falsely report hotplug events */
  603. if (dmi_check_system(intel_no_crt))
  604. return;
  605. crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL);
  606. if (!crt)
  607. return;
  608. intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
  609. if (!intel_connector) {
  610. kfree(crt);
  611. return;
  612. }
  613. connector = &intel_connector->base;
  614. drm_connector_init(dev, &intel_connector->base,
  615. &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA);
  616. drm_encoder_init(dev, &crt->base.base, &intel_crt_enc_funcs,
  617. DRM_MODE_ENCODER_DAC);
  618. intel_connector_attach_encoder(intel_connector, &crt->base);
  619. crt->base.type = INTEL_OUTPUT_ANALOG;
  620. crt->base.cloneable = true;
  621. if (IS_I830(dev))
  622. crt->base.crtc_mask = (1 << 0);
  623. else
  624. crt->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
  625. if (IS_GEN2(dev))
  626. connector->interlace_allowed = 0;
  627. else
  628. connector->interlace_allowed = 1;
  629. connector->doublescan_allowed = 0;
  630. if (HAS_PCH_SPLIT(dev))
  631. crt->adpa_reg = PCH_ADPA;
  632. else if (IS_VALLEYVIEW(dev))
  633. crt->adpa_reg = VLV_ADPA;
  634. else
  635. crt->adpa_reg = ADPA;
  636. crt->base.disable = intel_disable_crt;
  637. crt->base.enable = intel_enable_crt;
  638. if (HAS_DDI(dev))
  639. crt->base.get_hw_state = intel_ddi_get_hw_state;
  640. else
  641. crt->base.get_hw_state = intel_crt_get_hw_state;
  642. intel_connector->get_hw_state = intel_connector_get_hw_state;
  643. drm_encoder_helper_add(&crt->base.base, &crt_encoder_funcs);
  644. drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs);
  645. drm_sysfs_connector_add(connector);
  646. if (I915_HAS_HOTPLUG(dev))
  647. connector->polled = DRM_CONNECTOR_POLL_HPD;
  648. else
  649. connector->polled = DRM_CONNECTOR_POLL_CONNECT;
  650. /*
  651. * Configure the automatic hotplug detection stuff
  652. */
  653. crt->force_hotplug_required = 0;
  654. dev_priv->hotplug_supported_mask |= CRT_HOTPLUG_INT_STATUS;
  655. }