i915_debugfs.c 59 KB

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  1. /*
  2. * Copyright © 2008 Intel Corporation
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice (including the next
  12. * paragraph) shall be included in all copies or substantial portions of the
  13. * Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  18. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21. * IN THE SOFTWARE.
  22. *
  23. * Authors:
  24. * Eric Anholt <eric@anholt.net>
  25. * Keith Packard <keithp@keithp.com>
  26. *
  27. */
  28. #include <linux/seq_file.h>
  29. #include <linux/debugfs.h>
  30. #include <linux/slab.h>
  31. #include <linux/export.h>
  32. #include <drm/drmP.h>
  33. #include "intel_drv.h"
  34. #include "intel_ringbuffer.h"
  35. #include <drm/i915_drm.h>
  36. #include "i915_drv.h"
  37. #define DRM_I915_RING_DEBUG 1
  38. #if defined(CONFIG_DEBUG_FS)
  39. enum {
  40. ACTIVE_LIST,
  41. INACTIVE_LIST,
  42. PINNED_LIST,
  43. };
  44. static const char *yesno(int v)
  45. {
  46. return v ? "yes" : "no";
  47. }
  48. static int i915_capabilities(struct seq_file *m, void *data)
  49. {
  50. struct drm_info_node *node = (struct drm_info_node *) m->private;
  51. struct drm_device *dev = node->minor->dev;
  52. const struct intel_device_info *info = INTEL_INFO(dev);
  53. seq_printf(m, "gen: %d\n", info->gen);
  54. seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
  55. #define DEV_INFO_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
  56. #define DEV_INFO_SEP ;
  57. DEV_INFO_FLAGS;
  58. #undef DEV_INFO_FLAG
  59. #undef DEV_INFO_SEP
  60. return 0;
  61. }
  62. static const char *get_pin_flag(struct drm_i915_gem_object *obj)
  63. {
  64. if (obj->user_pin_count > 0)
  65. return "P";
  66. else if (obj->pin_count > 0)
  67. return "p";
  68. else
  69. return " ";
  70. }
  71. static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
  72. {
  73. switch (obj->tiling_mode) {
  74. default:
  75. case I915_TILING_NONE: return " ";
  76. case I915_TILING_X: return "X";
  77. case I915_TILING_Y: return "Y";
  78. }
  79. }
  80. static const char *cache_level_str(int type)
  81. {
  82. switch (type) {
  83. case I915_CACHE_NONE: return " uncached";
  84. case I915_CACHE_LLC: return " snooped (LLC)";
  85. case I915_CACHE_LLC_MLC: return " snooped (LLC+MLC)";
  86. default: return "";
  87. }
  88. }
  89. static void
  90. describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
  91. {
  92. seq_printf(m, "%p: %s%s %8zdKiB %02x %02x %d %d %d%s%s%s",
  93. &obj->base,
  94. get_pin_flag(obj),
  95. get_tiling_flag(obj),
  96. obj->base.size / 1024,
  97. obj->base.read_domains,
  98. obj->base.write_domain,
  99. obj->last_read_seqno,
  100. obj->last_write_seqno,
  101. obj->last_fenced_seqno,
  102. cache_level_str(obj->cache_level),
  103. obj->dirty ? " dirty" : "",
  104. obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
  105. if (obj->base.name)
  106. seq_printf(m, " (name: %d)", obj->base.name);
  107. if (obj->pin_count)
  108. seq_printf(m, " (pinned x %d)", obj->pin_count);
  109. if (obj->fence_reg != I915_FENCE_REG_NONE)
  110. seq_printf(m, " (fence: %d)", obj->fence_reg);
  111. if (obj->gtt_space != NULL)
  112. seq_printf(m, " (gtt offset: %08x, size: %08x)",
  113. obj->gtt_offset, (unsigned int)obj->gtt_space->size);
  114. if (obj->stolen)
  115. seq_printf(m, " (stolen: %08lx)", obj->stolen->start);
  116. if (obj->pin_mappable || obj->fault_mappable) {
  117. char s[3], *t = s;
  118. if (obj->pin_mappable)
  119. *t++ = 'p';
  120. if (obj->fault_mappable)
  121. *t++ = 'f';
  122. *t = '\0';
  123. seq_printf(m, " (%s mappable)", s);
  124. }
  125. if (obj->ring != NULL)
  126. seq_printf(m, " (%s)", obj->ring->name);
  127. }
  128. static int i915_gem_object_list_info(struct seq_file *m, void *data)
  129. {
  130. struct drm_info_node *node = (struct drm_info_node *) m->private;
  131. uintptr_t list = (uintptr_t) node->info_ent->data;
  132. struct list_head *head;
  133. struct drm_device *dev = node->minor->dev;
  134. drm_i915_private_t *dev_priv = dev->dev_private;
  135. struct drm_i915_gem_object *obj;
  136. size_t total_obj_size, total_gtt_size;
  137. int count, ret;
  138. ret = mutex_lock_interruptible(&dev->struct_mutex);
  139. if (ret)
  140. return ret;
  141. switch (list) {
  142. case ACTIVE_LIST:
  143. seq_printf(m, "Active:\n");
  144. head = &dev_priv->mm.active_list;
  145. break;
  146. case INACTIVE_LIST:
  147. seq_printf(m, "Inactive:\n");
  148. head = &dev_priv->mm.inactive_list;
  149. break;
  150. default:
  151. mutex_unlock(&dev->struct_mutex);
  152. return -EINVAL;
  153. }
  154. total_obj_size = total_gtt_size = count = 0;
  155. list_for_each_entry(obj, head, mm_list) {
  156. seq_printf(m, " ");
  157. describe_obj(m, obj);
  158. seq_printf(m, "\n");
  159. total_obj_size += obj->base.size;
  160. total_gtt_size += obj->gtt_space->size;
  161. count++;
  162. }
  163. mutex_unlock(&dev->struct_mutex);
  164. seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
  165. count, total_obj_size, total_gtt_size);
  166. return 0;
  167. }
  168. #define count_objects(list, member) do { \
  169. list_for_each_entry(obj, list, member) { \
  170. size += obj->gtt_space->size; \
  171. ++count; \
  172. if (obj->map_and_fenceable) { \
  173. mappable_size += obj->gtt_space->size; \
  174. ++mappable_count; \
  175. } \
  176. } \
  177. } while (0)
  178. static int i915_gem_object_info(struct seq_file *m, void* data)
  179. {
  180. struct drm_info_node *node = (struct drm_info_node *) m->private;
  181. struct drm_device *dev = node->minor->dev;
  182. struct drm_i915_private *dev_priv = dev->dev_private;
  183. u32 count, mappable_count, purgeable_count;
  184. size_t size, mappable_size, purgeable_size;
  185. struct drm_i915_gem_object *obj;
  186. int ret;
  187. ret = mutex_lock_interruptible(&dev->struct_mutex);
  188. if (ret)
  189. return ret;
  190. seq_printf(m, "%u objects, %zu bytes\n",
  191. dev_priv->mm.object_count,
  192. dev_priv->mm.object_memory);
  193. size = count = mappable_size = mappable_count = 0;
  194. count_objects(&dev_priv->mm.bound_list, gtt_list);
  195. seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
  196. count, mappable_count, size, mappable_size);
  197. size = count = mappable_size = mappable_count = 0;
  198. count_objects(&dev_priv->mm.active_list, mm_list);
  199. seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n",
  200. count, mappable_count, size, mappable_size);
  201. size = count = mappable_size = mappable_count = 0;
  202. count_objects(&dev_priv->mm.inactive_list, mm_list);
  203. seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n",
  204. count, mappable_count, size, mappable_size);
  205. size = count = purgeable_size = purgeable_count = 0;
  206. list_for_each_entry(obj, &dev_priv->mm.unbound_list, gtt_list) {
  207. size += obj->base.size, ++count;
  208. if (obj->madv == I915_MADV_DONTNEED)
  209. purgeable_size += obj->base.size, ++purgeable_count;
  210. }
  211. seq_printf(m, "%u unbound objects, %zu bytes\n", count, size);
  212. size = count = mappable_size = mappable_count = 0;
  213. list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) {
  214. if (obj->fault_mappable) {
  215. size += obj->gtt_space->size;
  216. ++count;
  217. }
  218. if (obj->pin_mappable) {
  219. mappable_size += obj->gtt_space->size;
  220. ++mappable_count;
  221. }
  222. if (obj->madv == I915_MADV_DONTNEED) {
  223. purgeable_size += obj->base.size;
  224. ++purgeable_count;
  225. }
  226. }
  227. seq_printf(m, "%u purgeable objects, %zu bytes\n",
  228. purgeable_count, purgeable_size);
  229. seq_printf(m, "%u pinned mappable objects, %zu bytes\n",
  230. mappable_count, mappable_size);
  231. seq_printf(m, "%u fault mappable objects, %zu bytes\n",
  232. count, size);
  233. seq_printf(m, "%zu [%zu] gtt total\n",
  234. dev_priv->mm.gtt_total, dev_priv->mm.mappable_gtt_total);
  235. mutex_unlock(&dev->struct_mutex);
  236. return 0;
  237. }
  238. static int i915_gem_gtt_info(struct seq_file *m, void* data)
  239. {
  240. struct drm_info_node *node = (struct drm_info_node *) m->private;
  241. struct drm_device *dev = node->minor->dev;
  242. uintptr_t list = (uintptr_t) node->info_ent->data;
  243. struct drm_i915_private *dev_priv = dev->dev_private;
  244. struct drm_i915_gem_object *obj;
  245. size_t total_obj_size, total_gtt_size;
  246. int count, ret;
  247. ret = mutex_lock_interruptible(&dev->struct_mutex);
  248. if (ret)
  249. return ret;
  250. total_obj_size = total_gtt_size = count = 0;
  251. list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) {
  252. if (list == PINNED_LIST && obj->pin_count == 0)
  253. continue;
  254. seq_printf(m, " ");
  255. describe_obj(m, obj);
  256. seq_printf(m, "\n");
  257. total_obj_size += obj->base.size;
  258. total_gtt_size += obj->gtt_space->size;
  259. count++;
  260. }
  261. mutex_unlock(&dev->struct_mutex);
  262. seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
  263. count, total_obj_size, total_gtt_size);
  264. return 0;
  265. }
  266. static int i915_gem_pageflip_info(struct seq_file *m, void *data)
  267. {
  268. struct drm_info_node *node = (struct drm_info_node *) m->private;
  269. struct drm_device *dev = node->minor->dev;
  270. unsigned long flags;
  271. struct intel_crtc *crtc;
  272. list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
  273. const char pipe = pipe_name(crtc->pipe);
  274. const char plane = plane_name(crtc->plane);
  275. struct intel_unpin_work *work;
  276. spin_lock_irqsave(&dev->event_lock, flags);
  277. work = crtc->unpin_work;
  278. if (work == NULL) {
  279. seq_printf(m, "No flip due on pipe %c (plane %c)\n",
  280. pipe, plane);
  281. } else {
  282. if (!work->pending) {
  283. seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
  284. pipe, plane);
  285. } else {
  286. seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
  287. pipe, plane);
  288. }
  289. if (work->enable_stall_check)
  290. seq_printf(m, "Stall check enabled, ");
  291. else
  292. seq_printf(m, "Stall check waiting for page flip ioctl, ");
  293. seq_printf(m, "%d prepares\n", work->pending);
  294. if (work->old_fb_obj) {
  295. struct drm_i915_gem_object *obj = work->old_fb_obj;
  296. if (obj)
  297. seq_printf(m, "Old framebuffer gtt_offset 0x%08x\n", obj->gtt_offset);
  298. }
  299. if (work->pending_flip_obj) {
  300. struct drm_i915_gem_object *obj = work->pending_flip_obj;
  301. if (obj)
  302. seq_printf(m, "New framebuffer gtt_offset 0x%08x\n", obj->gtt_offset);
  303. }
  304. }
  305. spin_unlock_irqrestore(&dev->event_lock, flags);
  306. }
  307. return 0;
  308. }
  309. static int i915_gem_request_info(struct seq_file *m, void *data)
  310. {
  311. struct drm_info_node *node = (struct drm_info_node *) m->private;
  312. struct drm_device *dev = node->minor->dev;
  313. drm_i915_private_t *dev_priv = dev->dev_private;
  314. struct intel_ring_buffer *ring;
  315. struct drm_i915_gem_request *gem_request;
  316. int ret, count, i;
  317. ret = mutex_lock_interruptible(&dev->struct_mutex);
  318. if (ret)
  319. return ret;
  320. count = 0;
  321. for_each_ring(ring, dev_priv, i) {
  322. if (list_empty(&ring->request_list))
  323. continue;
  324. seq_printf(m, "%s requests:\n", ring->name);
  325. list_for_each_entry(gem_request,
  326. &ring->request_list,
  327. list) {
  328. seq_printf(m, " %d @ %d\n",
  329. gem_request->seqno,
  330. (int) (jiffies - gem_request->emitted_jiffies));
  331. }
  332. count++;
  333. }
  334. mutex_unlock(&dev->struct_mutex);
  335. if (count == 0)
  336. seq_printf(m, "No requests\n");
  337. return 0;
  338. }
  339. static void i915_ring_seqno_info(struct seq_file *m,
  340. struct intel_ring_buffer *ring)
  341. {
  342. if (ring->get_seqno) {
  343. seq_printf(m, "Current sequence (%s): %u\n",
  344. ring->name, ring->get_seqno(ring, false));
  345. }
  346. }
  347. static int i915_gem_seqno_info(struct seq_file *m, void *data)
  348. {
  349. struct drm_info_node *node = (struct drm_info_node *) m->private;
  350. struct drm_device *dev = node->minor->dev;
  351. drm_i915_private_t *dev_priv = dev->dev_private;
  352. struct intel_ring_buffer *ring;
  353. int ret, i;
  354. ret = mutex_lock_interruptible(&dev->struct_mutex);
  355. if (ret)
  356. return ret;
  357. for_each_ring(ring, dev_priv, i)
  358. i915_ring_seqno_info(m, ring);
  359. mutex_unlock(&dev->struct_mutex);
  360. return 0;
  361. }
  362. static int i915_interrupt_info(struct seq_file *m, void *data)
  363. {
  364. struct drm_info_node *node = (struct drm_info_node *) m->private;
  365. struct drm_device *dev = node->minor->dev;
  366. drm_i915_private_t *dev_priv = dev->dev_private;
  367. struct intel_ring_buffer *ring;
  368. int ret, i, pipe;
  369. ret = mutex_lock_interruptible(&dev->struct_mutex);
  370. if (ret)
  371. return ret;
  372. if (IS_VALLEYVIEW(dev)) {
  373. seq_printf(m, "Display IER:\t%08x\n",
  374. I915_READ(VLV_IER));
  375. seq_printf(m, "Display IIR:\t%08x\n",
  376. I915_READ(VLV_IIR));
  377. seq_printf(m, "Display IIR_RW:\t%08x\n",
  378. I915_READ(VLV_IIR_RW));
  379. seq_printf(m, "Display IMR:\t%08x\n",
  380. I915_READ(VLV_IMR));
  381. for_each_pipe(pipe)
  382. seq_printf(m, "Pipe %c stat:\t%08x\n",
  383. pipe_name(pipe),
  384. I915_READ(PIPESTAT(pipe)));
  385. seq_printf(m, "Master IER:\t%08x\n",
  386. I915_READ(VLV_MASTER_IER));
  387. seq_printf(m, "Render IER:\t%08x\n",
  388. I915_READ(GTIER));
  389. seq_printf(m, "Render IIR:\t%08x\n",
  390. I915_READ(GTIIR));
  391. seq_printf(m, "Render IMR:\t%08x\n",
  392. I915_READ(GTIMR));
  393. seq_printf(m, "PM IER:\t\t%08x\n",
  394. I915_READ(GEN6_PMIER));
  395. seq_printf(m, "PM IIR:\t\t%08x\n",
  396. I915_READ(GEN6_PMIIR));
  397. seq_printf(m, "PM IMR:\t\t%08x\n",
  398. I915_READ(GEN6_PMIMR));
  399. seq_printf(m, "Port hotplug:\t%08x\n",
  400. I915_READ(PORT_HOTPLUG_EN));
  401. seq_printf(m, "DPFLIPSTAT:\t%08x\n",
  402. I915_READ(VLV_DPFLIPSTAT));
  403. seq_printf(m, "DPINVGTT:\t%08x\n",
  404. I915_READ(DPINVGTT));
  405. } else if (!HAS_PCH_SPLIT(dev)) {
  406. seq_printf(m, "Interrupt enable: %08x\n",
  407. I915_READ(IER));
  408. seq_printf(m, "Interrupt identity: %08x\n",
  409. I915_READ(IIR));
  410. seq_printf(m, "Interrupt mask: %08x\n",
  411. I915_READ(IMR));
  412. for_each_pipe(pipe)
  413. seq_printf(m, "Pipe %c stat: %08x\n",
  414. pipe_name(pipe),
  415. I915_READ(PIPESTAT(pipe)));
  416. } else {
  417. seq_printf(m, "North Display Interrupt enable: %08x\n",
  418. I915_READ(DEIER));
  419. seq_printf(m, "North Display Interrupt identity: %08x\n",
  420. I915_READ(DEIIR));
  421. seq_printf(m, "North Display Interrupt mask: %08x\n",
  422. I915_READ(DEIMR));
  423. seq_printf(m, "South Display Interrupt enable: %08x\n",
  424. I915_READ(SDEIER));
  425. seq_printf(m, "South Display Interrupt identity: %08x\n",
  426. I915_READ(SDEIIR));
  427. seq_printf(m, "South Display Interrupt mask: %08x\n",
  428. I915_READ(SDEIMR));
  429. seq_printf(m, "Graphics Interrupt enable: %08x\n",
  430. I915_READ(GTIER));
  431. seq_printf(m, "Graphics Interrupt identity: %08x\n",
  432. I915_READ(GTIIR));
  433. seq_printf(m, "Graphics Interrupt mask: %08x\n",
  434. I915_READ(GTIMR));
  435. }
  436. seq_printf(m, "Interrupts received: %d\n",
  437. atomic_read(&dev_priv->irq_received));
  438. for_each_ring(ring, dev_priv, i) {
  439. if (IS_GEN6(dev) || IS_GEN7(dev)) {
  440. seq_printf(m,
  441. "Graphics Interrupt mask (%s): %08x\n",
  442. ring->name, I915_READ_IMR(ring));
  443. }
  444. i915_ring_seqno_info(m, ring);
  445. }
  446. mutex_unlock(&dev->struct_mutex);
  447. return 0;
  448. }
  449. static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
  450. {
  451. struct drm_info_node *node = (struct drm_info_node *) m->private;
  452. struct drm_device *dev = node->minor->dev;
  453. drm_i915_private_t *dev_priv = dev->dev_private;
  454. int i, ret;
  455. ret = mutex_lock_interruptible(&dev->struct_mutex);
  456. if (ret)
  457. return ret;
  458. seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
  459. seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
  460. for (i = 0; i < dev_priv->num_fence_regs; i++) {
  461. struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
  462. seq_printf(m, "Fence %d, pin count = %d, object = ",
  463. i, dev_priv->fence_regs[i].pin_count);
  464. if (obj == NULL)
  465. seq_printf(m, "unused");
  466. else
  467. describe_obj(m, obj);
  468. seq_printf(m, "\n");
  469. }
  470. mutex_unlock(&dev->struct_mutex);
  471. return 0;
  472. }
  473. static int i915_hws_info(struct seq_file *m, void *data)
  474. {
  475. struct drm_info_node *node = (struct drm_info_node *) m->private;
  476. struct drm_device *dev = node->minor->dev;
  477. drm_i915_private_t *dev_priv = dev->dev_private;
  478. struct intel_ring_buffer *ring;
  479. const u32 *hws;
  480. int i;
  481. ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
  482. hws = ring->status_page.page_addr;
  483. if (hws == NULL)
  484. return 0;
  485. for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
  486. seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
  487. i * 4,
  488. hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
  489. }
  490. return 0;
  491. }
  492. static const char *ring_str(int ring)
  493. {
  494. switch (ring) {
  495. case RCS: return "render";
  496. case VCS: return "bsd";
  497. case BCS: return "blt";
  498. default: return "";
  499. }
  500. }
  501. static const char *pin_flag(int pinned)
  502. {
  503. if (pinned > 0)
  504. return " P";
  505. else if (pinned < 0)
  506. return " p";
  507. else
  508. return "";
  509. }
  510. static const char *tiling_flag(int tiling)
  511. {
  512. switch (tiling) {
  513. default:
  514. case I915_TILING_NONE: return "";
  515. case I915_TILING_X: return " X";
  516. case I915_TILING_Y: return " Y";
  517. }
  518. }
  519. static const char *dirty_flag(int dirty)
  520. {
  521. return dirty ? " dirty" : "";
  522. }
  523. static const char *purgeable_flag(int purgeable)
  524. {
  525. return purgeable ? " purgeable" : "";
  526. }
  527. static void print_error_buffers(struct seq_file *m,
  528. const char *name,
  529. struct drm_i915_error_buffer *err,
  530. int count)
  531. {
  532. seq_printf(m, "%s [%d]:\n", name, count);
  533. while (count--) {
  534. seq_printf(m, " %08x %8u %02x %02x %x %x%s%s%s%s%s%s%s",
  535. err->gtt_offset,
  536. err->size,
  537. err->read_domains,
  538. err->write_domain,
  539. err->rseqno, err->wseqno,
  540. pin_flag(err->pinned),
  541. tiling_flag(err->tiling),
  542. dirty_flag(err->dirty),
  543. purgeable_flag(err->purgeable),
  544. err->ring != -1 ? " " : "",
  545. ring_str(err->ring),
  546. cache_level_str(err->cache_level));
  547. if (err->name)
  548. seq_printf(m, " (name: %d)", err->name);
  549. if (err->fence_reg != I915_FENCE_REG_NONE)
  550. seq_printf(m, " (fence: %d)", err->fence_reg);
  551. seq_printf(m, "\n");
  552. err++;
  553. }
  554. }
  555. static void i915_ring_error_state(struct seq_file *m,
  556. struct drm_device *dev,
  557. struct drm_i915_error_state *error,
  558. unsigned ring)
  559. {
  560. BUG_ON(ring >= I915_NUM_RINGS); /* shut up confused gcc */
  561. seq_printf(m, "%s command stream:\n", ring_str(ring));
  562. seq_printf(m, " HEAD: 0x%08x\n", error->head[ring]);
  563. seq_printf(m, " TAIL: 0x%08x\n", error->tail[ring]);
  564. seq_printf(m, " ACTHD: 0x%08x\n", error->acthd[ring]);
  565. seq_printf(m, " IPEIR: 0x%08x\n", error->ipeir[ring]);
  566. seq_printf(m, " IPEHR: 0x%08x\n", error->ipehr[ring]);
  567. seq_printf(m, " INSTDONE: 0x%08x\n", error->instdone[ring]);
  568. if (ring == RCS && INTEL_INFO(dev)->gen >= 4)
  569. seq_printf(m, " BBADDR: 0x%08llx\n", error->bbaddr);
  570. if (INTEL_INFO(dev)->gen >= 4)
  571. seq_printf(m, " INSTPS: 0x%08x\n", error->instps[ring]);
  572. seq_printf(m, " INSTPM: 0x%08x\n", error->instpm[ring]);
  573. seq_printf(m, " FADDR: 0x%08x\n", error->faddr[ring]);
  574. if (INTEL_INFO(dev)->gen >= 6) {
  575. seq_printf(m, " RC PSMI: 0x%08x\n", error->rc_psmi[ring]);
  576. seq_printf(m, " FAULT_REG: 0x%08x\n", error->fault_reg[ring]);
  577. seq_printf(m, " SYNC_0: 0x%08x [last synced 0x%08x]\n",
  578. error->semaphore_mboxes[ring][0],
  579. error->semaphore_seqno[ring][0]);
  580. seq_printf(m, " SYNC_1: 0x%08x [last synced 0x%08x]\n",
  581. error->semaphore_mboxes[ring][1],
  582. error->semaphore_seqno[ring][1]);
  583. }
  584. seq_printf(m, " seqno: 0x%08x\n", error->seqno[ring]);
  585. seq_printf(m, " waiting: %s\n", yesno(error->waiting[ring]));
  586. seq_printf(m, " ring->head: 0x%08x\n", error->cpu_ring_head[ring]);
  587. seq_printf(m, " ring->tail: 0x%08x\n", error->cpu_ring_tail[ring]);
  588. }
  589. struct i915_error_state_file_priv {
  590. struct drm_device *dev;
  591. struct drm_i915_error_state *error;
  592. };
  593. static int i915_error_state(struct seq_file *m, void *unused)
  594. {
  595. struct i915_error_state_file_priv *error_priv = m->private;
  596. struct drm_device *dev = error_priv->dev;
  597. drm_i915_private_t *dev_priv = dev->dev_private;
  598. struct drm_i915_error_state *error = error_priv->error;
  599. struct intel_ring_buffer *ring;
  600. int i, j, page, offset, elt;
  601. if (!error) {
  602. seq_printf(m, "no error state collected\n");
  603. return 0;
  604. }
  605. seq_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec,
  606. error->time.tv_usec);
  607. seq_printf(m, "PCI ID: 0x%04x\n", dev->pci_device);
  608. seq_printf(m, "EIR: 0x%08x\n", error->eir);
  609. seq_printf(m, "IER: 0x%08x\n", error->ier);
  610. seq_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er);
  611. seq_printf(m, "CCID: 0x%08x\n", error->ccid);
  612. for (i = 0; i < dev_priv->num_fence_regs; i++)
  613. seq_printf(m, " fence[%d] = %08llx\n", i, error->fence[i]);
  614. for (i = 0; i < ARRAY_SIZE(error->extra_instdone); i++)
  615. seq_printf(m, " INSTDONE_%d: 0x%08x\n", i, error->extra_instdone[i]);
  616. if (INTEL_INFO(dev)->gen >= 6) {
  617. seq_printf(m, "ERROR: 0x%08x\n", error->error);
  618. seq_printf(m, "DONE_REG: 0x%08x\n", error->done_reg);
  619. }
  620. if (INTEL_INFO(dev)->gen == 7)
  621. seq_printf(m, "ERR_INT: 0x%08x\n", error->err_int);
  622. for_each_ring(ring, dev_priv, i)
  623. i915_ring_error_state(m, dev, error, i);
  624. if (error->active_bo)
  625. print_error_buffers(m, "Active",
  626. error->active_bo,
  627. error->active_bo_count);
  628. if (error->pinned_bo)
  629. print_error_buffers(m, "Pinned",
  630. error->pinned_bo,
  631. error->pinned_bo_count);
  632. for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
  633. struct drm_i915_error_object *obj;
  634. if ((obj = error->ring[i].batchbuffer)) {
  635. seq_printf(m, "%s --- gtt_offset = 0x%08x\n",
  636. dev_priv->ring[i].name,
  637. obj->gtt_offset);
  638. offset = 0;
  639. for (page = 0; page < obj->page_count; page++) {
  640. for (elt = 0; elt < PAGE_SIZE/4; elt++) {
  641. seq_printf(m, "%08x : %08x\n", offset, obj->pages[page][elt]);
  642. offset += 4;
  643. }
  644. }
  645. }
  646. if (error->ring[i].num_requests) {
  647. seq_printf(m, "%s --- %d requests\n",
  648. dev_priv->ring[i].name,
  649. error->ring[i].num_requests);
  650. for (j = 0; j < error->ring[i].num_requests; j++) {
  651. seq_printf(m, " seqno 0x%08x, emitted %ld, tail 0x%08x\n",
  652. error->ring[i].requests[j].seqno,
  653. error->ring[i].requests[j].jiffies,
  654. error->ring[i].requests[j].tail);
  655. }
  656. }
  657. if ((obj = error->ring[i].ringbuffer)) {
  658. seq_printf(m, "%s --- ringbuffer = 0x%08x\n",
  659. dev_priv->ring[i].name,
  660. obj->gtt_offset);
  661. offset = 0;
  662. for (page = 0; page < obj->page_count; page++) {
  663. for (elt = 0; elt < PAGE_SIZE/4; elt++) {
  664. seq_printf(m, "%08x : %08x\n",
  665. offset,
  666. obj->pages[page][elt]);
  667. offset += 4;
  668. }
  669. }
  670. }
  671. }
  672. if (error->overlay)
  673. intel_overlay_print_error_state(m, error->overlay);
  674. if (error->display)
  675. intel_display_print_error_state(m, dev, error->display);
  676. return 0;
  677. }
  678. static ssize_t
  679. i915_error_state_write(struct file *filp,
  680. const char __user *ubuf,
  681. size_t cnt,
  682. loff_t *ppos)
  683. {
  684. struct seq_file *m = filp->private_data;
  685. struct i915_error_state_file_priv *error_priv = m->private;
  686. struct drm_device *dev = error_priv->dev;
  687. int ret;
  688. DRM_DEBUG_DRIVER("Resetting error state\n");
  689. ret = mutex_lock_interruptible(&dev->struct_mutex);
  690. if (ret)
  691. return ret;
  692. i915_destroy_error_state(dev);
  693. mutex_unlock(&dev->struct_mutex);
  694. return cnt;
  695. }
  696. static int i915_error_state_open(struct inode *inode, struct file *file)
  697. {
  698. struct drm_device *dev = inode->i_private;
  699. drm_i915_private_t *dev_priv = dev->dev_private;
  700. struct i915_error_state_file_priv *error_priv;
  701. unsigned long flags;
  702. error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
  703. if (!error_priv)
  704. return -ENOMEM;
  705. error_priv->dev = dev;
  706. spin_lock_irqsave(&dev_priv->error_lock, flags);
  707. error_priv->error = dev_priv->first_error;
  708. if (error_priv->error)
  709. kref_get(&error_priv->error->ref);
  710. spin_unlock_irqrestore(&dev_priv->error_lock, flags);
  711. return single_open(file, i915_error_state, error_priv);
  712. }
  713. static int i915_error_state_release(struct inode *inode, struct file *file)
  714. {
  715. struct seq_file *m = file->private_data;
  716. struct i915_error_state_file_priv *error_priv = m->private;
  717. if (error_priv->error)
  718. kref_put(&error_priv->error->ref, i915_error_state_free);
  719. kfree(error_priv);
  720. return single_release(inode, file);
  721. }
  722. static const struct file_operations i915_error_state_fops = {
  723. .owner = THIS_MODULE,
  724. .open = i915_error_state_open,
  725. .read = seq_read,
  726. .write = i915_error_state_write,
  727. .llseek = default_llseek,
  728. .release = i915_error_state_release,
  729. };
  730. static ssize_t
  731. i915_next_seqno_read(struct file *filp,
  732. char __user *ubuf,
  733. size_t max,
  734. loff_t *ppos)
  735. {
  736. struct drm_device *dev = filp->private_data;
  737. drm_i915_private_t *dev_priv = dev->dev_private;
  738. char buf[80];
  739. int len;
  740. int ret;
  741. ret = mutex_lock_interruptible(&dev->struct_mutex);
  742. if (ret)
  743. return ret;
  744. len = snprintf(buf, sizeof(buf),
  745. "next_seqno : 0x%x\n",
  746. dev_priv->next_seqno);
  747. mutex_unlock(&dev->struct_mutex);
  748. if (len > sizeof(buf))
  749. len = sizeof(buf);
  750. return simple_read_from_buffer(ubuf, max, ppos, buf, len);
  751. }
  752. static ssize_t
  753. i915_next_seqno_write(struct file *filp,
  754. const char __user *ubuf,
  755. size_t cnt,
  756. loff_t *ppos)
  757. {
  758. struct drm_device *dev = filp->private_data;
  759. drm_i915_private_t *dev_priv = dev->dev_private;
  760. char buf[20];
  761. u32 val = 1;
  762. int ret;
  763. if (cnt > 0) {
  764. if (cnt > sizeof(buf) - 1)
  765. return -EINVAL;
  766. if (copy_from_user(buf, ubuf, cnt))
  767. return -EFAULT;
  768. buf[cnt] = 0;
  769. ret = kstrtouint(buf, 0, &val);
  770. if (ret < 0)
  771. return ret;
  772. }
  773. if (val == 0)
  774. return -EINVAL;
  775. ret = mutex_lock_interruptible(&dev->struct_mutex);
  776. if (ret)
  777. return ret;
  778. if (i915_seqno_passed(val, dev_priv->next_seqno)) {
  779. dev_priv->next_seqno = val;
  780. DRM_DEBUG_DRIVER("Advancing seqno to %u\n", val);
  781. } else {
  782. ret = -EINVAL;
  783. }
  784. mutex_unlock(&dev->struct_mutex);
  785. return ret ?: cnt;
  786. }
  787. static const struct file_operations i915_next_seqno_fops = {
  788. .owner = THIS_MODULE,
  789. .open = simple_open,
  790. .read = i915_next_seqno_read,
  791. .write = i915_next_seqno_write,
  792. .llseek = default_llseek,
  793. };
  794. static int i915_rstdby_delays(struct seq_file *m, void *unused)
  795. {
  796. struct drm_info_node *node = (struct drm_info_node *) m->private;
  797. struct drm_device *dev = node->minor->dev;
  798. drm_i915_private_t *dev_priv = dev->dev_private;
  799. u16 crstanddelay;
  800. int ret;
  801. ret = mutex_lock_interruptible(&dev->struct_mutex);
  802. if (ret)
  803. return ret;
  804. crstanddelay = I915_READ16(CRSTANDVID);
  805. mutex_unlock(&dev->struct_mutex);
  806. seq_printf(m, "w/ctx: %d, w/o ctx: %d\n", (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f));
  807. return 0;
  808. }
  809. static int i915_cur_delayinfo(struct seq_file *m, void *unused)
  810. {
  811. struct drm_info_node *node = (struct drm_info_node *) m->private;
  812. struct drm_device *dev = node->minor->dev;
  813. drm_i915_private_t *dev_priv = dev->dev_private;
  814. int ret;
  815. if (IS_GEN5(dev)) {
  816. u16 rgvswctl = I915_READ16(MEMSWCTL);
  817. u16 rgvstat = I915_READ16(MEMSTAT_ILK);
  818. seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
  819. seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
  820. seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
  821. MEMSTAT_VID_SHIFT);
  822. seq_printf(m, "Current P-state: %d\n",
  823. (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
  824. } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
  825. u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
  826. u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
  827. u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
  828. u32 rpstat;
  829. u32 rpupei, rpcurup, rpprevup;
  830. u32 rpdownei, rpcurdown, rpprevdown;
  831. int max_freq;
  832. /* RPSTAT1 is in the GT power well */
  833. ret = mutex_lock_interruptible(&dev->struct_mutex);
  834. if (ret)
  835. return ret;
  836. gen6_gt_force_wake_get(dev_priv);
  837. rpstat = I915_READ(GEN6_RPSTAT1);
  838. rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
  839. rpcurup = I915_READ(GEN6_RP_CUR_UP);
  840. rpprevup = I915_READ(GEN6_RP_PREV_UP);
  841. rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
  842. rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
  843. rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
  844. gen6_gt_force_wake_put(dev_priv);
  845. mutex_unlock(&dev->struct_mutex);
  846. seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
  847. seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
  848. seq_printf(m, "Render p-state ratio: %d\n",
  849. (gt_perf_status & 0xff00) >> 8);
  850. seq_printf(m, "Render p-state VID: %d\n",
  851. gt_perf_status & 0xff);
  852. seq_printf(m, "Render p-state limit: %d\n",
  853. rp_state_limits & 0xff);
  854. seq_printf(m, "CAGF: %dMHz\n", ((rpstat & GEN6_CAGF_MASK) >>
  855. GEN6_CAGF_SHIFT) * GT_FREQUENCY_MULTIPLIER);
  856. seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
  857. GEN6_CURICONT_MASK);
  858. seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
  859. GEN6_CURBSYTAVG_MASK);
  860. seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
  861. GEN6_CURBSYTAVG_MASK);
  862. seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
  863. GEN6_CURIAVG_MASK);
  864. seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
  865. GEN6_CURBSYTAVG_MASK);
  866. seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
  867. GEN6_CURBSYTAVG_MASK);
  868. max_freq = (rp_state_cap & 0xff0000) >> 16;
  869. seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
  870. max_freq * GT_FREQUENCY_MULTIPLIER);
  871. max_freq = (rp_state_cap & 0xff00) >> 8;
  872. seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
  873. max_freq * GT_FREQUENCY_MULTIPLIER);
  874. max_freq = rp_state_cap & 0xff;
  875. seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
  876. max_freq * GT_FREQUENCY_MULTIPLIER);
  877. } else {
  878. seq_printf(m, "no P-state info available\n");
  879. }
  880. return 0;
  881. }
  882. static int i915_delayfreq_table(struct seq_file *m, void *unused)
  883. {
  884. struct drm_info_node *node = (struct drm_info_node *) m->private;
  885. struct drm_device *dev = node->minor->dev;
  886. drm_i915_private_t *dev_priv = dev->dev_private;
  887. u32 delayfreq;
  888. int ret, i;
  889. ret = mutex_lock_interruptible(&dev->struct_mutex);
  890. if (ret)
  891. return ret;
  892. for (i = 0; i < 16; i++) {
  893. delayfreq = I915_READ(PXVFREQ_BASE + i * 4);
  894. seq_printf(m, "P%02dVIDFREQ: 0x%08x (VID: %d)\n", i, delayfreq,
  895. (delayfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT);
  896. }
  897. mutex_unlock(&dev->struct_mutex);
  898. return 0;
  899. }
  900. static inline int MAP_TO_MV(int map)
  901. {
  902. return 1250 - (map * 25);
  903. }
  904. static int i915_inttoext_table(struct seq_file *m, void *unused)
  905. {
  906. struct drm_info_node *node = (struct drm_info_node *) m->private;
  907. struct drm_device *dev = node->minor->dev;
  908. drm_i915_private_t *dev_priv = dev->dev_private;
  909. u32 inttoext;
  910. int ret, i;
  911. ret = mutex_lock_interruptible(&dev->struct_mutex);
  912. if (ret)
  913. return ret;
  914. for (i = 1; i <= 32; i++) {
  915. inttoext = I915_READ(INTTOEXT_BASE_ILK + i * 4);
  916. seq_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext);
  917. }
  918. mutex_unlock(&dev->struct_mutex);
  919. return 0;
  920. }
  921. static int ironlake_drpc_info(struct seq_file *m)
  922. {
  923. struct drm_info_node *node = (struct drm_info_node *) m->private;
  924. struct drm_device *dev = node->minor->dev;
  925. drm_i915_private_t *dev_priv = dev->dev_private;
  926. u32 rgvmodectl, rstdbyctl;
  927. u16 crstandvid;
  928. int ret;
  929. ret = mutex_lock_interruptible(&dev->struct_mutex);
  930. if (ret)
  931. return ret;
  932. rgvmodectl = I915_READ(MEMMODECTL);
  933. rstdbyctl = I915_READ(RSTDBYCTL);
  934. crstandvid = I915_READ16(CRSTANDVID);
  935. mutex_unlock(&dev->struct_mutex);
  936. seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
  937. "yes" : "no");
  938. seq_printf(m, "Boost freq: %d\n",
  939. (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
  940. MEMMODE_BOOST_FREQ_SHIFT);
  941. seq_printf(m, "HW control enabled: %s\n",
  942. rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
  943. seq_printf(m, "SW control enabled: %s\n",
  944. rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
  945. seq_printf(m, "Gated voltage change: %s\n",
  946. rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
  947. seq_printf(m, "Starting frequency: P%d\n",
  948. (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
  949. seq_printf(m, "Max P-state: P%d\n",
  950. (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
  951. seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
  952. seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
  953. seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
  954. seq_printf(m, "Render standby enabled: %s\n",
  955. (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");
  956. seq_printf(m, "Current RS state: ");
  957. switch (rstdbyctl & RSX_STATUS_MASK) {
  958. case RSX_STATUS_ON:
  959. seq_printf(m, "on\n");
  960. break;
  961. case RSX_STATUS_RC1:
  962. seq_printf(m, "RC1\n");
  963. break;
  964. case RSX_STATUS_RC1E:
  965. seq_printf(m, "RC1E\n");
  966. break;
  967. case RSX_STATUS_RS1:
  968. seq_printf(m, "RS1\n");
  969. break;
  970. case RSX_STATUS_RS2:
  971. seq_printf(m, "RS2 (RC6)\n");
  972. break;
  973. case RSX_STATUS_RS3:
  974. seq_printf(m, "RC3 (RC6+)\n");
  975. break;
  976. default:
  977. seq_printf(m, "unknown\n");
  978. break;
  979. }
  980. return 0;
  981. }
  982. static int gen6_drpc_info(struct seq_file *m)
  983. {
  984. struct drm_info_node *node = (struct drm_info_node *) m->private;
  985. struct drm_device *dev = node->minor->dev;
  986. struct drm_i915_private *dev_priv = dev->dev_private;
  987. u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
  988. unsigned forcewake_count;
  989. int count=0, ret;
  990. ret = mutex_lock_interruptible(&dev->struct_mutex);
  991. if (ret)
  992. return ret;
  993. spin_lock_irq(&dev_priv->gt_lock);
  994. forcewake_count = dev_priv->forcewake_count;
  995. spin_unlock_irq(&dev_priv->gt_lock);
  996. if (forcewake_count) {
  997. seq_printf(m, "RC information inaccurate because somebody "
  998. "holds a forcewake reference \n");
  999. } else {
  1000. /* NB: we cannot use forcewake, else we read the wrong values */
  1001. while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
  1002. udelay(10);
  1003. seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
  1004. }
  1005. gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS);
  1006. trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4);
  1007. rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
  1008. rcctl1 = I915_READ(GEN6_RC_CONTROL);
  1009. mutex_unlock(&dev->struct_mutex);
  1010. mutex_lock(&dev_priv->rps.hw_lock);
  1011. sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
  1012. mutex_unlock(&dev_priv->rps.hw_lock);
  1013. seq_printf(m, "Video Turbo Mode: %s\n",
  1014. yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
  1015. seq_printf(m, "HW control enabled: %s\n",
  1016. yesno(rpmodectl1 & GEN6_RP_ENABLE));
  1017. seq_printf(m, "SW control enabled: %s\n",
  1018. yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
  1019. GEN6_RP_MEDIA_SW_MODE));
  1020. seq_printf(m, "RC1e Enabled: %s\n",
  1021. yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
  1022. seq_printf(m, "RC6 Enabled: %s\n",
  1023. yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
  1024. seq_printf(m, "Deep RC6 Enabled: %s\n",
  1025. yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
  1026. seq_printf(m, "Deepest RC6 Enabled: %s\n",
  1027. yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
  1028. seq_printf(m, "Current RC state: ");
  1029. switch (gt_core_status & GEN6_RCn_MASK) {
  1030. case GEN6_RC0:
  1031. if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
  1032. seq_printf(m, "Core Power Down\n");
  1033. else
  1034. seq_printf(m, "on\n");
  1035. break;
  1036. case GEN6_RC3:
  1037. seq_printf(m, "RC3\n");
  1038. break;
  1039. case GEN6_RC6:
  1040. seq_printf(m, "RC6\n");
  1041. break;
  1042. case GEN6_RC7:
  1043. seq_printf(m, "RC7\n");
  1044. break;
  1045. default:
  1046. seq_printf(m, "Unknown\n");
  1047. break;
  1048. }
  1049. seq_printf(m, "Core Power Down: %s\n",
  1050. yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
  1051. /* Not exactly sure what this is */
  1052. seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
  1053. I915_READ(GEN6_GT_GFX_RC6_LOCKED));
  1054. seq_printf(m, "RC6 residency since boot: %u\n",
  1055. I915_READ(GEN6_GT_GFX_RC6));
  1056. seq_printf(m, "RC6+ residency since boot: %u\n",
  1057. I915_READ(GEN6_GT_GFX_RC6p));
  1058. seq_printf(m, "RC6++ residency since boot: %u\n",
  1059. I915_READ(GEN6_GT_GFX_RC6pp));
  1060. seq_printf(m, "RC6 voltage: %dmV\n",
  1061. GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
  1062. seq_printf(m, "RC6+ voltage: %dmV\n",
  1063. GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
  1064. seq_printf(m, "RC6++ voltage: %dmV\n",
  1065. GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
  1066. return 0;
  1067. }
  1068. static int i915_drpc_info(struct seq_file *m, void *unused)
  1069. {
  1070. struct drm_info_node *node = (struct drm_info_node *) m->private;
  1071. struct drm_device *dev = node->minor->dev;
  1072. if (IS_GEN6(dev) || IS_GEN7(dev))
  1073. return gen6_drpc_info(m);
  1074. else
  1075. return ironlake_drpc_info(m);
  1076. }
  1077. static int i915_fbc_status(struct seq_file *m, void *unused)
  1078. {
  1079. struct drm_info_node *node = (struct drm_info_node *) m->private;
  1080. struct drm_device *dev = node->minor->dev;
  1081. drm_i915_private_t *dev_priv = dev->dev_private;
  1082. if (!I915_HAS_FBC(dev)) {
  1083. seq_printf(m, "FBC unsupported on this chipset\n");
  1084. return 0;
  1085. }
  1086. if (intel_fbc_enabled(dev)) {
  1087. seq_printf(m, "FBC enabled\n");
  1088. } else {
  1089. seq_printf(m, "FBC disabled: ");
  1090. switch (dev_priv->no_fbc_reason) {
  1091. case FBC_NO_OUTPUT:
  1092. seq_printf(m, "no outputs");
  1093. break;
  1094. case FBC_STOLEN_TOO_SMALL:
  1095. seq_printf(m, "not enough stolen memory");
  1096. break;
  1097. case FBC_UNSUPPORTED_MODE:
  1098. seq_printf(m, "mode not supported");
  1099. break;
  1100. case FBC_MODE_TOO_LARGE:
  1101. seq_printf(m, "mode too large");
  1102. break;
  1103. case FBC_BAD_PLANE:
  1104. seq_printf(m, "FBC unsupported on plane");
  1105. break;
  1106. case FBC_NOT_TILED:
  1107. seq_printf(m, "scanout buffer not tiled");
  1108. break;
  1109. case FBC_MULTIPLE_PIPES:
  1110. seq_printf(m, "multiple pipes are enabled");
  1111. break;
  1112. case FBC_MODULE_PARAM:
  1113. seq_printf(m, "disabled per module param (default off)");
  1114. break;
  1115. default:
  1116. seq_printf(m, "unknown reason");
  1117. }
  1118. seq_printf(m, "\n");
  1119. }
  1120. return 0;
  1121. }
  1122. static int i915_sr_status(struct seq_file *m, void *unused)
  1123. {
  1124. struct drm_info_node *node = (struct drm_info_node *) m->private;
  1125. struct drm_device *dev = node->minor->dev;
  1126. drm_i915_private_t *dev_priv = dev->dev_private;
  1127. bool sr_enabled = false;
  1128. if (HAS_PCH_SPLIT(dev))
  1129. sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
  1130. else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
  1131. sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
  1132. else if (IS_I915GM(dev))
  1133. sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
  1134. else if (IS_PINEVIEW(dev))
  1135. sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
  1136. seq_printf(m, "self-refresh: %s\n",
  1137. sr_enabled ? "enabled" : "disabled");
  1138. return 0;
  1139. }
  1140. static int i915_emon_status(struct seq_file *m, void *unused)
  1141. {
  1142. struct drm_info_node *node = (struct drm_info_node *) m->private;
  1143. struct drm_device *dev = node->minor->dev;
  1144. drm_i915_private_t *dev_priv = dev->dev_private;
  1145. unsigned long temp, chipset, gfx;
  1146. int ret;
  1147. if (!IS_GEN5(dev))
  1148. return -ENODEV;
  1149. ret = mutex_lock_interruptible(&dev->struct_mutex);
  1150. if (ret)
  1151. return ret;
  1152. temp = i915_mch_val(dev_priv);
  1153. chipset = i915_chipset_val(dev_priv);
  1154. gfx = i915_gfx_val(dev_priv);
  1155. mutex_unlock(&dev->struct_mutex);
  1156. seq_printf(m, "GMCH temp: %ld\n", temp);
  1157. seq_printf(m, "Chipset power: %ld\n", chipset);
  1158. seq_printf(m, "GFX power: %ld\n", gfx);
  1159. seq_printf(m, "Total power: %ld\n", chipset + gfx);
  1160. return 0;
  1161. }
  1162. static int i915_ring_freq_table(struct seq_file *m, void *unused)
  1163. {
  1164. struct drm_info_node *node = (struct drm_info_node *) m->private;
  1165. struct drm_device *dev = node->minor->dev;
  1166. drm_i915_private_t *dev_priv = dev->dev_private;
  1167. int ret;
  1168. int gpu_freq, ia_freq;
  1169. if (!(IS_GEN6(dev) || IS_GEN7(dev))) {
  1170. seq_printf(m, "unsupported on this chipset\n");
  1171. return 0;
  1172. }
  1173. ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
  1174. if (ret)
  1175. return ret;
  1176. seq_printf(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\n");
  1177. for (gpu_freq = dev_priv->rps.min_delay;
  1178. gpu_freq <= dev_priv->rps.max_delay;
  1179. gpu_freq++) {
  1180. ia_freq = gpu_freq;
  1181. sandybridge_pcode_read(dev_priv,
  1182. GEN6_PCODE_READ_MIN_FREQ_TABLE,
  1183. &ia_freq);
  1184. seq_printf(m, "%d\t\t%d\n", gpu_freq * GT_FREQUENCY_MULTIPLIER, ia_freq * 100);
  1185. }
  1186. mutex_unlock(&dev_priv->rps.hw_lock);
  1187. return 0;
  1188. }
  1189. static int i915_gfxec(struct seq_file *m, void *unused)
  1190. {
  1191. struct drm_info_node *node = (struct drm_info_node *) m->private;
  1192. struct drm_device *dev = node->minor->dev;
  1193. drm_i915_private_t *dev_priv = dev->dev_private;
  1194. int ret;
  1195. ret = mutex_lock_interruptible(&dev->struct_mutex);
  1196. if (ret)
  1197. return ret;
  1198. seq_printf(m, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4));
  1199. mutex_unlock(&dev->struct_mutex);
  1200. return 0;
  1201. }
  1202. static int i915_opregion(struct seq_file *m, void *unused)
  1203. {
  1204. struct drm_info_node *node = (struct drm_info_node *) m->private;
  1205. struct drm_device *dev = node->minor->dev;
  1206. drm_i915_private_t *dev_priv = dev->dev_private;
  1207. struct intel_opregion *opregion = &dev_priv->opregion;
  1208. void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL);
  1209. int ret;
  1210. if (data == NULL)
  1211. return -ENOMEM;
  1212. ret = mutex_lock_interruptible(&dev->struct_mutex);
  1213. if (ret)
  1214. goto out;
  1215. if (opregion->header) {
  1216. memcpy_fromio(data, opregion->header, OPREGION_SIZE);
  1217. seq_write(m, data, OPREGION_SIZE);
  1218. }
  1219. mutex_unlock(&dev->struct_mutex);
  1220. out:
  1221. kfree(data);
  1222. return 0;
  1223. }
  1224. static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
  1225. {
  1226. struct drm_info_node *node = (struct drm_info_node *) m->private;
  1227. struct drm_device *dev = node->minor->dev;
  1228. drm_i915_private_t *dev_priv = dev->dev_private;
  1229. struct intel_fbdev *ifbdev;
  1230. struct intel_framebuffer *fb;
  1231. int ret;
  1232. ret = mutex_lock_interruptible(&dev->mode_config.mutex);
  1233. if (ret)
  1234. return ret;
  1235. ifbdev = dev_priv->fbdev;
  1236. fb = to_intel_framebuffer(ifbdev->helper.fb);
  1237. seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, obj ",
  1238. fb->base.width,
  1239. fb->base.height,
  1240. fb->base.depth,
  1241. fb->base.bits_per_pixel);
  1242. describe_obj(m, fb->obj);
  1243. seq_printf(m, "\n");
  1244. list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) {
  1245. if (&fb->base == ifbdev->helper.fb)
  1246. continue;
  1247. seq_printf(m, "user size: %d x %d, depth %d, %d bpp, obj ",
  1248. fb->base.width,
  1249. fb->base.height,
  1250. fb->base.depth,
  1251. fb->base.bits_per_pixel);
  1252. describe_obj(m, fb->obj);
  1253. seq_printf(m, "\n");
  1254. }
  1255. mutex_unlock(&dev->mode_config.mutex);
  1256. return 0;
  1257. }
  1258. static int i915_context_status(struct seq_file *m, void *unused)
  1259. {
  1260. struct drm_info_node *node = (struct drm_info_node *) m->private;
  1261. struct drm_device *dev = node->minor->dev;
  1262. drm_i915_private_t *dev_priv = dev->dev_private;
  1263. int ret;
  1264. ret = mutex_lock_interruptible(&dev->mode_config.mutex);
  1265. if (ret)
  1266. return ret;
  1267. if (dev_priv->ips.pwrctx) {
  1268. seq_printf(m, "power context ");
  1269. describe_obj(m, dev_priv->ips.pwrctx);
  1270. seq_printf(m, "\n");
  1271. }
  1272. if (dev_priv->ips.renderctx) {
  1273. seq_printf(m, "render context ");
  1274. describe_obj(m, dev_priv->ips.renderctx);
  1275. seq_printf(m, "\n");
  1276. }
  1277. mutex_unlock(&dev->mode_config.mutex);
  1278. return 0;
  1279. }
  1280. static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data)
  1281. {
  1282. struct drm_info_node *node = (struct drm_info_node *) m->private;
  1283. struct drm_device *dev = node->minor->dev;
  1284. struct drm_i915_private *dev_priv = dev->dev_private;
  1285. unsigned forcewake_count;
  1286. spin_lock_irq(&dev_priv->gt_lock);
  1287. forcewake_count = dev_priv->forcewake_count;
  1288. spin_unlock_irq(&dev_priv->gt_lock);
  1289. seq_printf(m, "forcewake count = %u\n", forcewake_count);
  1290. return 0;
  1291. }
  1292. static const char *swizzle_string(unsigned swizzle)
  1293. {
  1294. switch(swizzle) {
  1295. case I915_BIT_6_SWIZZLE_NONE:
  1296. return "none";
  1297. case I915_BIT_6_SWIZZLE_9:
  1298. return "bit9";
  1299. case I915_BIT_6_SWIZZLE_9_10:
  1300. return "bit9/bit10";
  1301. case I915_BIT_6_SWIZZLE_9_11:
  1302. return "bit9/bit11";
  1303. case I915_BIT_6_SWIZZLE_9_10_11:
  1304. return "bit9/bit10/bit11";
  1305. case I915_BIT_6_SWIZZLE_9_17:
  1306. return "bit9/bit17";
  1307. case I915_BIT_6_SWIZZLE_9_10_17:
  1308. return "bit9/bit10/bit17";
  1309. case I915_BIT_6_SWIZZLE_UNKNOWN:
  1310. return "unkown";
  1311. }
  1312. return "bug";
  1313. }
  1314. static int i915_swizzle_info(struct seq_file *m, void *data)
  1315. {
  1316. struct drm_info_node *node = (struct drm_info_node *) m->private;
  1317. struct drm_device *dev = node->minor->dev;
  1318. struct drm_i915_private *dev_priv = dev->dev_private;
  1319. int ret;
  1320. ret = mutex_lock_interruptible(&dev->struct_mutex);
  1321. if (ret)
  1322. return ret;
  1323. seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
  1324. swizzle_string(dev_priv->mm.bit_6_swizzle_x));
  1325. seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
  1326. swizzle_string(dev_priv->mm.bit_6_swizzle_y));
  1327. if (IS_GEN3(dev) || IS_GEN4(dev)) {
  1328. seq_printf(m, "DDC = 0x%08x\n",
  1329. I915_READ(DCC));
  1330. seq_printf(m, "C0DRB3 = 0x%04x\n",
  1331. I915_READ16(C0DRB3));
  1332. seq_printf(m, "C1DRB3 = 0x%04x\n",
  1333. I915_READ16(C1DRB3));
  1334. } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
  1335. seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
  1336. I915_READ(MAD_DIMM_C0));
  1337. seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
  1338. I915_READ(MAD_DIMM_C1));
  1339. seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
  1340. I915_READ(MAD_DIMM_C2));
  1341. seq_printf(m, "TILECTL = 0x%08x\n",
  1342. I915_READ(TILECTL));
  1343. seq_printf(m, "ARB_MODE = 0x%08x\n",
  1344. I915_READ(ARB_MODE));
  1345. seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
  1346. I915_READ(DISP_ARB_CTL));
  1347. }
  1348. mutex_unlock(&dev->struct_mutex);
  1349. return 0;
  1350. }
  1351. static int i915_ppgtt_info(struct seq_file *m, void *data)
  1352. {
  1353. struct drm_info_node *node = (struct drm_info_node *) m->private;
  1354. struct drm_device *dev = node->minor->dev;
  1355. struct drm_i915_private *dev_priv = dev->dev_private;
  1356. struct intel_ring_buffer *ring;
  1357. int i, ret;
  1358. ret = mutex_lock_interruptible(&dev->struct_mutex);
  1359. if (ret)
  1360. return ret;
  1361. if (INTEL_INFO(dev)->gen == 6)
  1362. seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
  1363. for_each_ring(ring, dev_priv, i) {
  1364. seq_printf(m, "%s\n", ring->name);
  1365. if (INTEL_INFO(dev)->gen == 7)
  1366. seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
  1367. seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
  1368. seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
  1369. seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
  1370. }
  1371. if (dev_priv->mm.aliasing_ppgtt) {
  1372. struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
  1373. seq_printf(m, "aliasing PPGTT:\n");
  1374. seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset);
  1375. }
  1376. seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
  1377. mutex_unlock(&dev->struct_mutex);
  1378. return 0;
  1379. }
  1380. static int i915_dpio_info(struct seq_file *m, void *data)
  1381. {
  1382. struct drm_info_node *node = (struct drm_info_node *) m->private;
  1383. struct drm_device *dev = node->minor->dev;
  1384. struct drm_i915_private *dev_priv = dev->dev_private;
  1385. int ret;
  1386. if (!IS_VALLEYVIEW(dev)) {
  1387. seq_printf(m, "unsupported\n");
  1388. return 0;
  1389. }
  1390. ret = mutex_lock_interruptible(&dev->mode_config.mutex);
  1391. if (ret)
  1392. return ret;
  1393. seq_printf(m, "DPIO_CTL: 0x%08x\n", I915_READ(DPIO_CTL));
  1394. seq_printf(m, "DPIO_DIV_A: 0x%08x\n",
  1395. intel_dpio_read(dev_priv, _DPIO_DIV_A));
  1396. seq_printf(m, "DPIO_DIV_B: 0x%08x\n",
  1397. intel_dpio_read(dev_priv, _DPIO_DIV_B));
  1398. seq_printf(m, "DPIO_REFSFR_A: 0x%08x\n",
  1399. intel_dpio_read(dev_priv, _DPIO_REFSFR_A));
  1400. seq_printf(m, "DPIO_REFSFR_B: 0x%08x\n",
  1401. intel_dpio_read(dev_priv, _DPIO_REFSFR_B));
  1402. seq_printf(m, "DPIO_CORE_CLK_A: 0x%08x\n",
  1403. intel_dpio_read(dev_priv, _DPIO_CORE_CLK_A));
  1404. seq_printf(m, "DPIO_CORE_CLK_B: 0x%08x\n",
  1405. intel_dpio_read(dev_priv, _DPIO_CORE_CLK_B));
  1406. seq_printf(m, "DPIO_LFP_COEFF_A: 0x%08x\n",
  1407. intel_dpio_read(dev_priv, _DPIO_LFP_COEFF_A));
  1408. seq_printf(m, "DPIO_LFP_COEFF_B: 0x%08x\n",
  1409. intel_dpio_read(dev_priv, _DPIO_LFP_COEFF_B));
  1410. seq_printf(m, "DPIO_FASTCLK_DISABLE: 0x%08x\n",
  1411. intel_dpio_read(dev_priv, DPIO_FASTCLK_DISABLE));
  1412. mutex_unlock(&dev->mode_config.mutex);
  1413. return 0;
  1414. }
  1415. static ssize_t
  1416. i915_wedged_read(struct file *filp,
  1417. char __user *ubuf,
  1418. size_t max,
  1419. loff_t *ppos)
  1420. {
  1421. struct drm_device *dev = filp->private_data;
  1422. drm_i915_private_t *dev_priv = dev->dev_private;
  1423. char buf[80];
  1424. int len;
  1425. len = snprintf(buf, sizeof(buf),
  1426. "wedged : %d\n",
  1427. atomic_read(&dev_priv->mm.wedged));
  1428. if (len > sizeof(buf))
  1429. len = sizeof(buf);
  1430. return simple_read_from_buffer(ubuf, max, ppos, buf, len);
  1431. }
  1432. static ssize_t
  1433. i915_wedged_write(struct file *filp,
  1434. const char __user *ubuf,
  1435. size_t cnt,
  1436. loff_t *ppos)
  1437. {
  1438. struct drm_device *dev = filp->private_data;
  1439. char buf[20];
  1440. int val = 1;
  1441. if (cnt > 0) {
  1442. if (cnt > sizeof(buf) - 1)
  1443. return -EINVAL;
  1444. if (copy_from_user(buf, ubuf, cnt))
  1445. return -EFAULT;
  1446. buf[cnt] = 0;
  1447. val = simple_strtoul(buf, NULL, 0);
  1448. }
  1449. DRM_INFO("Manually setting wedged to %d\n", val);
  1450. i915_handle_error(dev, val);
  1451. return cnt;
  1452. }
  1453. static const struct file_operations i915_wedged_fops = {
  1454. .owner = THIS_MODULE,
  1455. .open = simple_open,
  1456. .read = i915_wedged_read,
  1457. .write = i915_wedged_write,
  1458. .llseek = default_llseek,
  1459. };
  1460. static ssize_t
  1461. i915_ring_stop_read(struct file *filp,
  1462. char __user *ubuf,
  1463. size_t max,
  1464. loff_t *ppos)
  1465. {
  1466. struct drm_device *dev = filp->private_data;
  1467. drm_i915_private_t *dev_priv = dev->dev_private;
  1468. char buf[20];
  1469. int len;
  1470. len = snprintf(buf, sizeof(buf),
  1471. "0x%08x\n", dev_priv->stop_rings);
  1472. if (len > sizeof(buf))
  1473. len = sizeof(buf);
  1474. return simple_read_from_buffer(ubuf, max, ppos, buf, len);
  1475. }
  1476. static ssize_t
  1477. i915_ring_stop_write(struct file *filp,
  1478. const char __user *ubuf,
  1479. size_t cnt,
  1480. loff_t *ppos)
  1481. {
  1482. struct drm_device *dev = filp->private_data;
  1483. struct drm_i915_private *dev_priv = dev->dev_private;
  1484. char buf[20];
  1485. int val = 0, ret;
  1486. if (cnt > 0) {
  1487. if (cnt > sizeof(buf) - 1)
  1488. return -EINVAL;
  1489. if (copy_from_user(buf, ubuf, cnt))
  1490. return -EFAULT;
  1491. buf[cnt] = 0;
  1492. val = simple_strtoul(buf, NULL, 0);
  1493. }
  1494. DRM_DEBUG_DRIVER("Stopping rings 0x%08x\n", val);
  1495. ret = mutex_lock_interruptible(&dev->struct_mutex);
  1496. if (ret)
  1497. return ret;
  1498. dev_priv->stop_rings = val;
  1499. mutex_unlock(&dev->struct_mutex);
  1500. return cnt;
  1501. }
  1502. static const struct file_operations i915_ring_stop_fops = {
  1503. .owner = THIS_MODULE,
  1504. .open = simple_open,
  1505. .read = i915_ring_stop_read,
  1506. .write = i915_ring_stop_write,
  1507. .llseek = default_llseek,
  1508. };
  1509. static ssize_t
  1510. i915_max_freq_read(struct file *filp,
  1511. char __user *ubuf,
  1512. size_t max,
  1513. loff_t *ppos)
  1514. {
  1515. struct drm_device *dev = filp->private_data;
  1516. drm_i915_private_t *dev_priv = dev->dev_private;
  1517. char buf[80];
  1518. int len, ret;
  1519. if (!(IS_GEN6(dev) || IS_GEN7(dev)))
  1520. return -ENODEV;
  1521. ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
  1522. if (ret)
  1523. return ret;
  1524. len = snprintf(buf, sizeof(buf),
  1525. "max freq: %d\n", dev_priv->rps.max_delay * GT_FREQUENCY_MULTIPLIER);
  1526. mutex_unlock(&dev_priv->rps.hw_lock);
  1527. if (len > sizeof(buf))
  1528. len = sizeof(buf);
  1529. return simple_read_from_buffer(ubuf, max, ppos, buf, len);
  1530. }
  1531. static ssize_t
  1532. i915_max_freq_write(struct file *filp,
  1533. const char __user *ubuf,
  1534. size_t cnt,
  1535. loff_t *ppos)
  1536. {
  1537. struct drm_device *dev = filp->private_data;
  1538. struct drm_i915_private *dev_priv = dev->dev_private;
  1539. char buf[20];
  1540. int val = 1, ret;
  1541. if (!(IS_GEN6(dev) || IS_GEN7(dev)))
  1542. return -ENODEV;
  1543. if (cnt > 0) {
  1544. if (cnt > sizeof(buf) - 1)
  1545. return -EINVAL;
  1546. if (copy_from_user(buf, ubuf, cnt))
  1547. return -EFAULT;
  1548. buf[cnt] = 0;
  1549. val = simple_strtoul(buf, NULL, 0);
  1550. }
  1551. DRM_DEBUG_DRIVER("Manually setting max freq to %d\n", val);
  1552. ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
  1553. if (ret)
  1554. return ret;
  1555. /*
  1556. * Turbo will still be enabled, but won't go above the set value.
  1557. */
  1558. dev_priv->rps.max_delay = val / GT_FREQUENCY_MULTIPLIER;
  1559. gen6_set_rps(dev, val / GT_FREQUENCY_MULTIPLIER);
  1560. mutex_unlock(&dev_priv->rps.hw_lock);
  1561. return cnt;
  1562. }
  1563. static const struct file_operations i915_max_freq_fops = {
  1564. .owner = THIS_MODULE,
  1565. .open = simple_open,
  1566. .read = i915_max_freq_read,
  1567. .write = i915_max_freq_write,
  1568. .llseek = default_llseek,
  1569. };
  1570. static ssize_t
  1571. i915_min_freq_read(struct file *filp, char __user *ubuf, size_t max,
  1572. loff_t *ppos)
  1573. {
  1574. struct drm_device *dev = filp->private_data;
  1575. drm_i915_private_t *dev_priv = dev->dev_private;
  1576. char buf[80];
  1577. int len, ret;
  1578. if (!(IS_GEN6(dev) || IS_GEN7(dev)))
  1579. return -ENODEV;
  1580. ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
  1581. if (ret)
  1582. return ret;
  1583. len = snprintf(buf, sizeof(buf),
  1584. "min freq: %d\n", dev_priv->rps.min_delay * GT_FREQUENCY_MULTIPLIER);
  1585. mutex_unlock(&dev_priv->rps.hw_lock);
  1586. if (len > sizeof(buf))
  1587. len = sizeof(buf);
  1588. return simple_read_from_buffer(ubuf, max, ppos, buf, len);
  1589. }
  1590. static ssize_t
  1591. i915_min_freq_write(struct file *filp, const char __user *ubuf, size_t cnt,
  1592. loff_t *ppos)
  1593. {
  1594. struct drm_device *dev = filp->private_data;
  1595. struct drm_i915_private *dev_priv = dev->dev_private;
  1596. char buf[20];
  1597. int val = 1, ret;
  1598. if (!(IS_GEN6(dev) || IS_GEN7(dev)))
  1599. return -ENODEV;
  1600. if (cnt > 0) {
  1601. if (cnt > sizeof(buf) - 1)
  1602. return -EINVAL;
  1603. if (copy_from_user(buf, ubuf, cnt))
  1604. return -EFAULT;
  1605. buf[cnt] = 0;
  1606. val = simple_strtoul(buf, NULL, 0);
  1607. }
  1608. DRM_DEBUG_DRIVER("Manually setting min freq to %d\n", val);
  1609. ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
  1610. if (ret)
  1611. return ret;
  1612. /*
  1613. * Turbo will still be enabled, but won't go below the set value.
  1614. */
  1615. dev_priv->rps.min_delay = val / GT_FREQUENCY_MULTIPLIER;
  1616. gen6_set_rps(dev, val / GT_FREQUENCY_MULTIPLIER);
  1617. mutex_unlock(&dev_priv->rps.hw_lock);
  1618. return cnt;
  1619. }
  1620. static const struct file_operations i915_min_freq_fops = {
  1621. .owner = THIS_MODULE,
  1622. .open = simple_open,
  1623. .read = i915_min_freq_read,
  1624. .write = i915_min_freq_write,
  1625. .llseek = default_llseek,
  1626. };
  1627. static ssize_t
  1628. i915_cache_sharing_read(struct file *filp,
  1629. char __user *ubuf,
  1630. size_t max,
  1631. loff_t *ppos)
  1632. {
  1633. struct drm_device *dev = filp->private_data;
  1634. drm_i915_private_t *dev_priv = dev->dev_private;
  1635. char buf[80];
  1636. u32 snpcr;
  1637. int len, ret;
  1638. if (!(IS_GEN6(dev) || IS_GEN7(dev)))
  1639. return -ENODEV;
  1640. ret = mutex_lock_interruptible(&dev->struct_mutex);
  1641. if (ret)
  1642. return ret;
  1643. snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
  1644. mutex_unlock(&dev_priv->dev->struct_mutex);
  1645. len = snprintf(buf, sizeof(buf),
  1646. "%d\n", (snpcr & GEN6_MBC_SNPCR_MASK) >>
  1647. GEN6_MBC_SNPCR_SHIFT);
  1648. if (len > sizeof(buf))
  1649. len = sizeof(buf);
  1650. return simple_read_from_buffer(ubuf, max, ppos, buf, len);
  1651. }
  1652. static ssize_t
  1653. i915_cache_sharing_write(struct file *filp,
  1654. const char __user *ubuf,
  1655. size_t cnt,
  1656. loff_t *ppos)
  1657. {
  1658. struct drm_device *dev = filp->private_data;
  1659. struct drm_i915_private *dev_priv = dev->dev_private;
  1660. char buf[20];
  1661. u32 snpcr;
  1662. int val = 1;
  1663. if (!(IS_GEN6(dev) || IS_GEN7(dev)))
  1664. return -ENODEV;
  1665. if (cnt > 0) {
  1666. if (cnt > sizeof(buf) - 1)
  1667. return -EINVAL;
  1668. if (copy_from_user(buf, ubuf, cnt))
  1669. return -EFAULT;
  1670. buf[cnt] = 0;
  1671. val = simple_strtoul(buf, NULL, 0);
  1672. }
  1673. if (val < 0 || val > 3)
  1674. return -EINVAL;
  1675. DRM_DEBUG_DRIVER("Manually setting uncore sharing to %d\n", val);
  1676. /* Update the cache sharing policy here as well */
  1677. snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
  1678. snpcr &= ~GEN6_MBC_SNPCR_MASK;
  1679. snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
  1680. I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
  1681. return cnt;
  1682. }
  1683. static const struct file_operations i915_cache_sharing_fops = {
  1684. .owner = THIS_MODULE,
  1685. .open = simple_open,
  1686. .read = i915_cache_sharing_read,
  1687. .write = i915_cache_sharing_write,
  1688. .llseek = default_llseek,
  1689. };
  1690. /* As the drm_debugfs_init() routines are called before dev->dev_private is
  1691. * allocated we need to hook into the minor for release. */
  1692. static int
  1693. drm_add_fake_info_node(struct drm_minor *minor,
  1694. struct dentry *ent,
  1695. const void *key)
  1696. {
  1697. struct drm_info_node *node;
  1698. node = kmalloc(sizeof(struct drm_info_node), GFP_KERNEL);
  1699. if (node == NULL) {
  1700. debugfs_remove(ent);
  1701. return -ENOMEM;
  1702. }
  1703. node->minor = minor;
  1704. node->dent = ent;
  1705. node->info_ent = (void *) key;
  1706. mutex_lock(&minor->debugfs_lock);
  1707. list_add(&node->list, &minor->debugfs_list);
  1708. mutex_unlock(&minor->debugfs_lock);
  1709. return 0;
  1710. }
  1711. static int i915_forcewake_open(struct inode *inode, struct file *file)
  1712. {
  1713. struct drm_device *dev = inode->i_private;
  1714. struct drm_i915_private *dev_priv = dev->dev_private;
  1715. if (INTEL_INFO(dev)->gen < 6)
  1716. return 0;
  1717. gen6_gt_force_wake_get(dev_priv);
  1718. return 0;
  1719. }
  1720. static int i915_forcewake_release(struct inode *inode, struct file *file)
  1721. {
  1722. struct drm_device *dev = inode->i_private;
  1723. struct drm_i915_private *dev_priv = dev->dev_private;
  1724. if (INTEL_INFO(dev)->gen < 6)
  1725. return 0;
  1726. gen6_gt_force_wake_put(dev_priv);
  1727. return 0;
  1728. }
  1729. static const struct file_operations i915_forcewake_fops = {
  1730. .owner = THIS_MODULE,
  1731. .open = i915_forcewake_open,
  1732. .release = i915_forcewake_release,
  1733. };
  1734. static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
  1735. {
  1736. struct drm_device *dev = minor->dev;
  1737. struct dentry *ent;
  1738. ent = debugfs_create_file("i915_forcewake_user",
  1739. S_IRUSR,
  1740. root, dev,
  1741. &i915_forcewake_fops);
  1742. if (IS_ERR(ent))
  1743. return PTR_ERR(ent);
  1744. return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
  1745. }
  1746. static int i915_debugfs_create(struct dentry *root,
  1747. struct drm_minor *minor,
  1748. const char *name,
  1749. const struct file_operations *fops)
  1750. {
  1751. struct drm_device *dev = minor->dev;
  1752. struct dentry *ent;
  1753. ent = debugfs_create_file(name,
  1754. S_IRUGO | S_IWUSR,
  1755. root, dev,
  1756. fops);
  1757. if (IS_ERR(ent))
  1758. return PTR_ERR(ent);
  1759. return drm_add_fake_info_node(minor, ent, fops);
  1760. }
  1761. static struct drm_info_list i915_debugfs_list[] = {
  1762. {"i915_capabilities", i915_capabilities, 0},
  1763. {"i915_gem_objects", i915_gem_object_info, 0},
  1764. {"i915_gem_gtt", i915_gem_gtt_info, 0},
  1765. {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
  1766. {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
  1767. {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
  1768. {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
  1769. {"i915_gem_request", i915_gem_request_info, 0},
  1770. {"i915_gem_seqno", i915_gem_seqno_info, 0},
  1771. {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
  1772. {"i915_gem_interrupt", i915_interrupt_info, 0},
  1773. {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
  1774. {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
  1775. {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
  1776. {"i915_rstdby_delays", i915_rstdby_delays, 0},
  1777. {"i915_cur_delayinfo", i915_cur_delayinfo, 0},
  1778. {"i915_delayfreq_table", i915_delayfreq_table, 0},
  1779. {"i915_inttoext_table", i915_inttoext_table, 0},
  1780. {"i915_drpc_info", i915_drpc_info, 0},
  1781. {"i915_emon_status", i915_emon_status, 0},
  1782. {"i915_ring_freq_table", i915_ring_freq_table, 0},
  1783. {"i915_gfxec", i915_gfxec, 0},
  1784. {"i915_fbc_status", i915_fbc_status, 0},
  1785. {"i915_sr_status", i915_sr_status, 0},
  1786. {"i915_opregion", i915_opregion, 0},
  1787. {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
  1788. {"i915_context_status", i915_context_status, 0},
  1789. {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0},
  1790. {"i915_swizzle_info", i915_swizzle_info, 0},
  1791. {"i915_ppgtt_info", i915_ppgtt_info, 0},
  1792. {"i915_dpio", i915_dpio_info, 0},
  1793. };
  1794. #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
  1795. int i915_debugfs_init(struct drm_minor *minor)
  1796. {
  1797. int ret;
  1798. ret = i915_debugfs_create(minor->debugfs_root, minor,
  1799. "i915_wedged",
  1800. &i915_wedged_fops);
  1801. if (ret)
  1802. return ret;
  1803. ret = i915_forcewake_create(minor->debugfs_root, minor);
  1804. if (ret)
  1805. return ret;
  1806. ret = i915_debugfs_create(minor->debugfs_root, minor,
  1807. "i915_max_freq",
  1808. &i915_max_freq_fops);
  1809. if (ret)
  1810. return ret;
  1811. ret = i915_debugfs_create(minor->debugfs_root, minor,
  1812. "i915_min_freq",
  1813. &i915_min_freq_fops);
  1814. if (ret)
  1815. return ret;
  1816. ret = i915_debugfs_create(minor->debugfs_root, minor,
  1817. "i915_cache_sharing",
  1818. &i915_cache_sharing_fops);
  1819. if (ret)
  1820. return ret;
  1821. ret = i915_debugfs_create(minor->debugfs_root, minor,
  1822. "i915_ring_stop",
  1823. &i915_ring_stop_fops);
  1824. if (ret)
  1825. return ret;
  1826. ret = i915_debugfs_create(minor->debugfs_root, minor,
  1827. "i915_error_state",
  1828. &i915_error_state_fops);
  1829. if (ret)
  1830. return ret;
  1831. ret = i915_debugfs_create(minor->debugfs_root, minor,
  1832. "i915_next_seqno",
  1833. &i915_next_seqno_fops);
  1834. if (ret)
  1835. return ret;
  1836. return drm_debugfs_create_files(i915_debugfs_list,
  1837. I915_DEBUGFS_ENTRIES,
  1838. minor->debugfs_root, minor);
  1839. }
  1840. void i915_debugfs_cleanup(struct drm_minor *minor)
  1841. {
  1842. drm_debugfs_remove_files(i915_debugfs_list,
  1843. I915_DEBUGFS_ENTRIES, minor);
  1844. drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
  1845. 1, minor);
  1846. drm_debugfs_remove_files((struct drm_info_list *) &i915_wedged_fops,
  1847. 1, minor);
  1848. drm_debugfs_remove_files((struct drm_info_list *) &i915_max_freq_fops,
  1849. 1, minor);
  1850. drm_debugfs_remove_files((struct drm_info_list *) &i915_min_freq_fops,
  1851. 1, minor);
  1852. drm_debugfs_remove_files((struct drm_info_list *) &i915_cache_sharing_fops,
  1853. 1, minor);
  1854. drm_debugfs_remove_files((struct drm_info_list *) &i915_ring_stop_fops,
  1855. 1, minor);
  1856. drm_debugfs_remove_files((struct drm_info_list *) &i915_error_state_fops,
  1857. 1, minor);
  1858. drm_debugfs_remove_files((struct drm_info_list *) &i915_next_seqno_fops,
  1859. 1, minor);
  1860. }
  1861. #endif /* CONFIG_DEBUG_FS */