wm8962.c 51 KB

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  1. /*
  2. * wm8962.c -- WM8962 ALSA SoC Audio driver
  3. *
  4. * Copyright 2010 Wolfson Microelectronics plc
  5. *
  6. * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
  7. *
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License version 2 as
  11. * published by the Free Software Foundation.
  12. */
  13. #include <linux/module.h>
  14. #include <linux/moduleparam.h>
  15. #include <linux/init.h>
  16. #include <linux/delay.h>
  17. #include <linux/pm.h>
  18. #include <linux/gcd.h>
  19. #include <linux/i2c.h>
  20. #include <linux/input.h>
  21. #include <linux/platform_device.h>
  22. #include <linux/regulator/consumer.h>
  23. #include <linux/slab.h>
  24. #include <linux/workqueue.h>
  25. #include <sound/core.h>
  26. #include <sound/pcm.h>
  27. #include <sound/pcm_params.h>
  28. #include <sound/soc.h>
  29. #include <sound/soc-dapm.h>
  30. #include <sound/initval.h>
  31. #include <sound/tlv.h>
  32. #include <sound/wm8962.h>
  33. #include "wm8962.h"
  34. #define WM8962_NUM_SUPPLIES 8
  35. static const char *wm8962_supply_names[WM8962_NUM_SUPPLIES] = {
  36. "DCVDD",
  37. "DBVDD",
  38. "AVDD",
  39. "CPVDD",
  40. "MICVDD",
  41. "PLLVDD",
  42. "SPKVDD1",
  43. "SPKVDD2",
  44. };
  45. /* codec private data */
  46. struct wm8962_priv {
  47. struct snd_soc_codec *codec;
  48. u16 reg_cache[WM8962_MAX_REGISTER + 1];
  49. int sysclk;
  50. int sysclk_rate;
  51. int bclk; /* Desired BCLK */
  52. int lrclk;
  53. int fll_src;
  54. int fll_fref;
  55. int fll_fout;
  56. struct regulator_bulk_data supplies[WM8962_NUM_SUPPLIES];
  57. struct notifier_block disable_nb[WM8962_NUM_SUPPLIES];
  58. #if defined(CONFIG_INPUT) || defined(CONFIG_INPUT_MODULE)
  59. struct input_dev *beep;
  60. struct work_struct beep_work;
  61. int beep_rate;
  62. #endif
  63. };
  64. /* We can't use the same notifier block for more than one supply and
  65. * there's no way I can see to get from a callback to the caller
  66. * except container_of().
  67. */
  68. #define WM8962_REGULATOR_EVENT(n) \
  69. static int wm8962_regulator_event_##n(struct notifier_block *nb, \
  70. unsigned long event, void *data) \
  71. { \
  72. struct wm8962_priv *wm8962 = container_of(nb, struct wm8962_priv, \
  73. disable_nb[n]); \
  74. if (event & REGULATOR_EVENT_DISABLE) { \
  75. wm8962->codec->cache_sync = 1; \
  76. } \
  77. return 0; \
  78. }
  79. WM8962_REGULATOR_EVENT(0)
  80. WM8962_REGULATOR_EVENT(1)
  81. WM8962_REGULATOR_EVENT(2)
  82. WM8962_REGULATOR_EVENT(3)
  83. WM8962_REGULATOR_EVENT(4)
  84. WM8962_REGULATOR_EVENT(5)
  85. WM8962_REGULATOR_EVENT(6)
  86. WM8962_REGULATOR_EVENT(7)
  87. static int wm8962_volatile_register(unsigned int reg)
  88. {
  89. if (wm8962_reg_access[reg].vol)
  90. return 1;
  91. else
  92. return 0;
  93. }
  94. static int wm8962_readable_register(unsigned int reg)
  95. {
  96. if (wm8962_reg_access[reg].read)
  97. return 1;
  98. else
  99. return 0;
  100. }
  101. static int wm8962_reset(struct snd_soc_codec *codec)
  102. {
  103. return snd_soc_write(codec, WM8962_SOFTWARE_RESET, 0);
  104. }
  105. static const DECLARE_TLV_DB_SCALE(inpga_tlv, -2325, 75, 0);
  106. static const DECLARE_TLV_DB_SCALE(mixin_tlv, -1500, 300, 0);
  107. static const unsigned int mixinpga_tlv[] = {
  108. TLV_DB_RANGE_HEAD(7),
  109. 0, 1, TLV_DB_SCALE_ITEM(0, 600, 0),
  110. 2, 2, TLV_DB_SCALE_ITEM(1300, 1300, 0),
  111. 3, 4, TLV_DB_SCALE_ITEM(1800, 200, 0),
  112. 5, 5, TLV_DB_SCALE_ITEM(2400, 0, 0),
  113. 6, 7, TLV_DB_SCALE_ITEM(2700, 300, 0),
  114. };
  115. static const DECLARE_TLV_DB_SCALE(beep_tlv, -9600, 600, 1);
  116. static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
  117. static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
  118. static const DECLARE_TLV_DB_SCALE(inmix_tlv, -600, 600, 0);
  119. static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0);
  120. static const DECLARE_TLV_DB_SCALE(out_tlv, -12100, 100, 1);
  121. static const DECLARE_TLV_DB_SCALE(hp_tlv, -700, 100, 0);
  122. static const unsigned int classd_tlv[] = {
  123. TLV_DB_RANGE_HEAD(7),
  124. 0, 6, TLV_DB_SCALE_ITEM(0, 150, 0),
  125. 7, 7, TLV_DB_SCALE_ITEM(1200, 0, 0),
  126. };
  127. /* The VU bits for the headphones are in a different register to the mute
  128. * bits and only take effect on the PGA if it is actually powered.
  129. */
  130. static int wm8962_put_hp_sw(struct snd_kcontrol *kcontrol,
  131. struct snd_ctl_elem_value *ucontrol)
  132. {
  133. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  134. struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
  135. u16 *reg_cache = wm8962->reg_cache;
  136. int ret;
  137. /* Apply the update (if any) */
  138. ret = snd_soc_put_volsw(kcontrol, ucontrol);
  139. if (ret == 0)
  140. return 0;
  141. /* If the left PGA is enabled hit that VU bit... */
  142. if (reg_cache[WM8962_PWR_MGMT_2] & WM8962_HPOUTL_PGA_ENA)
  143. return snd_soc_write(codec, WM8962_HPOUTL_VOLUME,
  144. reg_cache[WM8962_HPOUTL_VOLUME]);
  145. /* ...otherwise the right. The VU is stereo. */
  146. if (reg_cache[WM8962_PWR_MGMT_2] & WM8962_HPOUTR_PGA_ENA)
  147. return snd_soc_write(codec, WM8962_HPOUTR_VOLUME,
  148. reg_cache[WM8962_HPOUTR_VOLUME]);
  149. return 0;
  150. }
  151. /* The VU bits for the speakers are in a different register to the mute
  152. * bits and only take effect on the PGA if it is actually powered.
  153. */
  154. static int wm8962_put_spk_sw(struct snd_kcontrol *kcontrol,
  155. struct snd_ctl_elem_value *ucontrol)
  156. {
  157. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  158. struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
  159. u16 *reg_cache = wm8962->reg_cache;
  160. int ret;
  161. /* Apply the update (if any) */
  162. ret = snd_soc_put_volsw(kcontrol, ucontrol);
  163. if (ret == 0)
  164. return 0;
  165. /* If the left PGA is enabled hit that VU bit... */
  166. if (reg_cache[WM8962_PWR_MGMT_2] & WM8962_SPKOUTL_PGA_ENA)
  167. return snd_soc_write(codec, WM8962_SPKOUTL_VOLUME,
  168. reg_cache[WM8962_SPKOUTL_VOLUME]);
  169. /* ...otherwise the right. The VU is stereo. */
  170. if (reg_cache[WM8962_PWR_MGMT_2] & WM8962_SPKOUTR_PGA_ENA)
  171. return snd_soc_write(codec, WM8962_SPKOUTR_VOLUME,
  172. reg_cache[WM8962_SPKOUTR_VOLUME]);
  173. return 0;
  174. }
  175. static const struct snd_kcontrol_new wm8962_snd_controls[] = {
  176. SOC_DOUBLE("Input Mixer Switch", WM8962_INPUT_MIXER_CONTROL_1, 3, 2, 1, 1),
  177. SOC_SINGLE_TLV("MIXINL IN2L Volume", WM8962_LEFT_INPUT_MIXER_VOLUME, 6, 7, 0,
  178. mixin_tlv),
  179. SOC_SINGLE_TLV("MIXINL PGA Volume", WM8962_LEFT_INPUT_MIXER_VOLUME, 3, 7, 0,
  180. mixinpga_tlv),
  181. SOC_SINGLE_TLV("MIXINL IN3L Volume", WM8962_LEFT_INPUT_MIXER_VOLUME, 0, 7, 0,
  182. mixin_tlv),
  183. SOC_SINGLE_TLV("MIXINR IN2R Volume", WM8962_RIGHT_INPUT_MIXER_VOLUME, 6, 7, 0,
  184. mixin_tlv),
  185. SOC_SINGLE_TLV("MIXINR PGA Volume", WM8962_RIGHT_INPUT_MIXER_VOLUME, 3, 7, 0,
  186. mixinpga_tlv),
  187. SOC_SINGLE_TLV("MIXINR IN3R Volume", WM8962_RIGHT_INPUT_MIXER_VOLUME, 0, 7, 0,
  188. mixin_tlv),
  189. SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8962_LEFT_ADC_VOLUME,
  190. WM8962_RIGHT_ADC_VOLUME, 1, 127, 0, digital_tlv),
  191. SOC_DOUBLE_R_TLV("Capture Volume", WM8962_LEFT_INPUT_VOLUME,
  192. WM8962_RIGHT_INPUT_VOLUME, 0, 63, 0, inpga_tlv),
  193. SOC_DOUBLE_R("Capture Switch", WM8962_LEFT_INPUT_VOLUME,
  194. WM8962_RIGHT_INPUT_VOLUME, 7, 1, 1),
  195. SOC_DOUBLE_R("Capture ZC Switch", WM8962_LEFT_INPUT_VOLUME,
  196. WM8962_RIGHT_INPUT_VOLUME, 6, 1, 1),
  197. SOC_DOUBLE_R_TLV("Sidetone Volume", WM8962_DAC_DSP_MIXING_1,
  198. WM8962_DAC_DSP_MIXING_2, 4, 12, 0, st_tlv),
  199. SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8962_LEFT_DAC_VOLUME,
  200. WM8962_RIGHT_DAC_VOLUME, 1, 127, 0, digital_tlv),
  201. SOC_SINGLE("DAC High Performance Switch", WM8962_ADC_DAC_CONTROL_2, 0, 1, 0),
  202. SOC_SINGLE("ADC High Performance Switch", WM8962_ADDITIONAL_CONTROL_1,
  203. 5, 1, 0),
  204. SOC_SINGLE_TLV("Beep Volume", WM8962_BEEP_GENERATOR_1, 4, 15, 0, beep_tlv),
  205. SOC_DOUBLE_R_TLV("Headphone Volume", WM8962_HPOUTL_VOLUME,
  206. WM8962_HPOUTR_VOLUME, 0, 127, 0, out_tlv),
  207. SOC_DOUBLE_EXT("Headphone Switch", WM8962_PWR_MGMT_2, 1, 0, 1, 1,
  208. snd_soc_get_volsw, wm8962_put_hp_sw),
  209. SOC_DOUBLE_R("Headphone ZC Switch", WM8962_HPOUTL_VOLUME, WM8962_HPOUTR_VOLUME,
  210. 7, 1, 0),
  211. SOC_DOUBLE_TLV("Headphone Aux Volume", WM8962_ANALOGUE_HP_2, 3, 6, 7, 0,
  212. hp_tlv),
  213. SOC_DOUBLE_R("Headphone Mixer Switch", WM8962_HEADPHONE_MIXER_3,
  214. WM8962_HEADPHONE_MIXER_4, 8, 1, 1),
  215. SOC_SINGLE_TLV("HPMIXL IN4L Volume", WM8962_HEADPHONE_MIXER_3,
  216. 3, 7, 0, bypass_tlv),
  217. SOC_SINGLE_TLV("HPMIXL IN4R Volume", WM8962_HEADPHONE_MIXER_3,
  218. 0, 7, 0, bypass_tlv),
  219. SOC_SINGLE_TLV("HPMIXL MIXINL Volume", WM8962_HEADPHONE_MIXER_3,
  220. 7, 1, 1, inmix_tlv),
  221. SOC_SINGLE_TLV("HPMIXL MIXINR Volume", WM8962_HEADPHONE_MIXER_3,
  222. 6, 1, 1, inmix_tlv),
  223. SOC_SINGLE_TLV("HPMIXR IN4L Volume", WM8962_HEADPHONE_MIXER_4,
  224. 3, 7, 0, bypass_tlv),
  225. SOC_SINGLE_TLV("HPMIXR IN4R Volume", WM8962_HEADPHONE_MIXER_4,
  226. 0, 7, 0, bypass_tlv),
  227. SOC_SINGLE_TLV("HPMIXR MIXINL Volume", WM8962_HEADPHONE_MIXER_4,
  228. 7, 1, 1, inmix_tlv),
  229. SOC_SINGLE_TLV("HPMIXR MIXINR Volume", WM8962_HEADPHONE_MIXER_4,
  230. 6, 1, 1, inmix_tlv),
  231. SOC_SINGLE_TLV("Speaker Boost Volume", WM8962_CLASS_D_CONTROL_2, 0, 7, 0,
  232. classd_tlv),
  233. };
  234. static const struct snd_kcontrol_new wm8962_spk_mono_controls[] = {
  235. SOC_SINGLE_TLV("Speaker Volume", WM8962_SPKOUTL_VOLUME, 0, 127, 0, out_tlv),
  236. SOC_SINGLE_EXT("Speaker Switch", WM8962_CLASS_D_CONTROL_1, 1, 1, 1,
  237. snd_soc_get_volsw, wm8962_put_spk_sw),
  238. SOC_SINGLE("Speaker ZC Switch", WM8962_SPKOUTL_VOLUME, 7, 1, 0),
  239. SOC_SINGLE("Speaker Mixer Switch", WM8962_SPEAKER_MIXER_3, 8, 1, 1),
  240. SOC_SINGLE_TLV("Speaker Mixer IN4L Volume", WM8962_SPEAKER_MIXER_3,
  241. 3, 7, 0, bypass_tlv),
  242. SOC_SINGLE_TLV("Speaker Mixer IN4R Volume", WM8962_SPEAKER_MIXER_3,
  243. 0, 7, 0, bypass_tlv),
  244. SOC_SINGLE_TLV("Speaker Mixer MIXINL Volume", WM8962_SPEAKER_MIXER_3,
  245. 7, 1, 1, inmix_tlv),
  246. SOC_SINGLE_TLV("Speaker Mixer MIXINR Volume", WM8962_SPEAKER_MIXER_3,
  247. 6, 1, 1, inmix_tlv),
  248. SOC_SINGLE_TLV("Speaker Mixer DACL Volume", WM8962_SPEAKER_MIXER_5,
  249. 7, 1, 0, inmix_tlv),
  250. SOC_SINGLE_TLV("Speaker Mixer DACR Volume", WM8962_SPEAKER_MIXER_5,
  251. 6, 1, 0, inmix_tlv),
  252. };
  253. static const struct snd_kcontrol_new wm8962_spk_stereo_controls[] = {
  254. SOC_DOUBLE_R_TLV("Speaker Volume", WM8962_SPKOUTL_VOLUME,
  255. WM8962_SPKOUTR_VOLUME, 0, 127, 0, out_tlv),
  256. SOC_DOUBLE_EXT("Speaker Switch", WM8962_CLASS_D_CONTROL_1, 1, 0, 1, 1,
  257. snd_soc_get_volsw, wm8962_put_spk_sw),
  258. SOC_DOUBLE_R("Speaker ZC Switch", WM8962_SPKOUTL_VOLUME, WM8962_SPKOUTR_VOLUME,
  259. 7, 1, 0),
  260. SOC_DOUBLE_R("Speaker Mixer Switch", WM8962_SPEAKER_MIXER_3,
  261. WM8962_SPEAKER_MIXER_4, 8, 1, 1),
  262. SOC_SINGLE_TLV("SPKOUTL Mixer IN4L Volume", WM8962_SPEAKER_MIXER_3,
  263. 3, 7, 0, bypass_tlv),
  264. SOC_SINGLE_TLV("SPKOUTL Mixer IN4R Volume", WM8962_SPEAKER_MIXER_3,
  265. 0, 7, 0, bypass_tlv),
  266. SOC_SINGLE_TLV("SPKOUTL Mixer MIXINL Volume", WM8962_SPEAKER_MIXER_3,
  267. 7, 1, 1, inmix_tlv),
  268. SOC_SINGLE_TLV("SPKOUTL Mixer MIXINR Volume", WM8962_SPEAKER_MIXER_3,
  269. 6, 1, 1, inmix_tlv),
  270. SOC_SINGLE_TLV("SPKOUTL Mixer DACL Volume", WM8962_SPEAKER_MIXER_5,
  271. 7, 1, 0, inmix_tlv),
  272. SOC_SINGLE_TLV("SPKOUTL Mixer DACR Volume", WM8962_SPEAKER_MIXER_5,
  273. 6, 1, 0, inmix_tlv),
  274. SOC_SINGLE_TLV("SPKOUTR Mixer IN4L Volume", WM8962_SPEAKER_MIXER_4,
  275. 3, 7, 0, bypass_tlv),
  276. SOC_SINGLE_TLV("SPKOUTR Mixer IN4R Volume", WM8962_SPEAKER_MIXER_4,
  277. 0, 7, 0, bypass_tlv),
  278. SOC_SINGLE_TLV("SPKOUTR Mixer MIXINL Volume", WM8962_SPEAKER_MIXER_4,
  279. 7, 1, 1, inmix_tlv),
  280. SOC_SINGLE_TLV("SPKOUTR Mixer MIXINR Volume", WM8962_SPEAKER_MIXER_4,
  281. 6, 1, 1, inmix_tlv),
  282. SOC_SINGLE_TLV("SPKOUTR Mixer DACL Volume", WM8962_SPEAKER_MIXER_5,
  283. 5, 1, 0, inmix_tlv),
  284. SOC_SINGLE_TLV("SPKOUTR Mixer DACR Volume", WM8962_SPEAKER_MIXER_5,
  285. 4, 1, 0, inmix_tlv),
  286. };
  287. static int sysclk_event(struct snd_soc_dapm_widget *w,
  288. struct snd_kcontrol *kcontrol, int event)
  289. {
  290. struct snd_soc_codec *codec = w->codec;
  291. int src;
  292. int fll;
  293. src = snd_soc_read(codec, WM8962_CLOCKING2) & WM8962_SYSCLK_SRC_MASK;
  294. switch (src) {
  295. case 0: /* MCLK */
  296. fll = 0;
  297. break;
  298. case 0x200: /* FLL */
  299. fll = 1;
  300. break;
  301. default:
  302. dev_err(codec->dev, "Unknown SYSCLK source %x\n", src);
  303. return -EINVAL;
  304. }
  305. switch (event) {
  306. case SND_SOC_DAPM_PRE_PMU:
  307. if (fll)
  308. snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1,
  309. WM8962_FLL_ENA, WM8962_FLL_ENA);
  310. break;
  311. case SND_SOC_DAPM_POST_PMD:
  312. if (fll)
  313. snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1,
  314. WM8962_FLL_ENA, 0);
  315. break;
  316. default:
  317. BUG();
  318. return -EINVAL;
  319. }
  320. return 0;
  321. }
  322. static int cp_event(struct snd_soc_dapm_widget *w,
  323. struct snd_kcontrol *kcontrol, int event)
  324. {
  325. switch (event) {
  326. case SND_SOC_DAPM_POST_PMU:
  327. msleep(5);
  328. break;
  329. default:
  330. BUG();
  331. return -EINVAL;
  332. }
  333. return 0;
  334. }
  335. static int hp_event(struct snd_soc_dapm_widget *w,
  336. struct snd_kcontrol *kcontrol, int event)
  337. {
  338. struct snd_soc_codec *codec = w->codec;
  339. int timeout;
  340. int reg;
  341. int expected = (WM8962_DCS_STARTUP_DONE_HP1L |
  342. WM8962_DCS_STARTUP_DONE_HP1R);
  343. switch (event) {
  344. case SND_SOC_DAPM_POST_PMU:
  345. snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
  346. WM8962_HP1L_ENA | WM8962_HP1R_ENA,
  347. WM8962_HP1L_ENA | WM8962_HP1R_ENA);
  348. udelay(20);
  349. snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
  350. WM8962_HP1L_ENA_DLY | WM8962_HP1R_ENA_DLY,
  351. WM8962_HP1L_ENA_DLY | WM8962_HP1R_ENA_DLY);
  352. /* Start the DC servo */
  353. snd_soc_update_bits(codec, WM8962_DC_SERVO_1,
  354. WM8962_HP1L_DCS_ENA | WM8962_HP1R_DCS_ENA |
  355. WM8962_HP1L_DCS_STARTUP |
  356. WM8962_HP1R_DCS_STARTUP,
  357. WM8962_HP1L_DCS_ENA | WM8962_HP1R_DCS_ENA |
  358. WM8962_HP1L_DCS_STARTUP |
  359. WM8962_HP1R_DCS_STARTUP);
  360. /* Wait for it to complete, should be well under 100ms */
  361. timeout = 0;
  362. do {
  363. msleep(1);
  364. reg = snd_soc_read(codec, WM8962_DC_SERVO_6);
  365. if (reg < 0) {
  366. dev_err(codec->dev,
  367. "Failed to read DCS status: %d\n",
  368. reg);
  369. continue;
  370. }
  371. dev_dbg(codec->dev, "DCS status: %x\n", reg);
  372. } while (++timeout < 200 && (reg & expected) != expected);
  373. if ((reg & expected) != expected)
  374. dev_err(codec->dev, "DC servo timed out\n");
  375. else
  376. dev_dbg(codec->dev, "DC servo complete after %dms\n",
  377. timeout);
  378. snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
  379. WM8962_HP1L_ENA_OUTP |
  380. WM8962_HP1R_ENA_OUTP,
  381. WM8962_HP1L_ENA_OUTP |
  382. WM8962_HP1R_ENA_OUTP);
  383. udelay(20);
  384. snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
  385. WM8962_HP1L_RMV_SHORT |
  386. WM8962_HP1R_RMV_SHORT,
  387. WM8962_HP1L_RMV_SHORT |
  388. WM8962_HP1R_RMV_SHORT);
  389. break;
  390. case SND_SOC_DAPM_PRE_PMD:
  391. snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
  392. WM8962_HP1L_RMV_SHORT |
  393. WM8962_HP1R_RMV_SHORT, 0);
  394. udelay(20);
  395. snd_soc_update_bits(codec, WM8962_DC_SERVO_1,
  396. WM8962_HP1L_DCS_ENA | WM8962_HP1R_DCS_ENA |
  397. WM8962_HP1L_DCS_STARTUP |
  398. WM8962_HP1R_DCS_STARTUP,
  399. 0);
  400. snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
  401. WM8962_HP1L_ENA | WM8962_HP1R_ENA |
  402. WM8962_HP1L_ENA_DLY | WM8962_HP1R_ENA_DLY |
  403. WM8962_HP1L_ENA_OUTP |
  404. WM8962_HP1R_ENA_OUTP, 0);
  405. break;
  406. default:
  407. BUG();
  408. return -EINVAL;
  409. }
  410. return 0;
  411. }
  412. /* VU bits for the output PGAs only take effect while the PGA is powered */
  413. static int out_pga_event(struct snd_soc_dapm_widget *w,
  414. struct snd_kcontrol *kcontrol, int event)
  415. {
  416. struct snd_soc_codec *codec = w->codec;
  417. struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
  418. u16 *reg_cache = wm8962->reg_cache;
  419. int reg;
  420. switch (w->shift) {
  421. case WM8962_HPOUTR_PGA_ENA_SHIFT:
  422. reg = WM8962_HPOUTR_VOLUME;
  423. break;
  424. case WM8962_HPOUTL_PGA_ENA_SHIFT:
  425. reg = WM8962_HPOUTL_VOLUME;
  426. break;
  427. case WM8962_SPKOUTR_PGA_ENA_SHIFT:
  428. reg = WM8962_SPKOUTR_VOLUME;
  429. break;
  430. case WM8962_SPKOUTL_PGA_ENA_SHIFT:
  431. reg = WM8962_SPKOUTL_VOLUME;
  432. break;
  433. default:
  434. BUG();
  435. return -EINVAL;
  436. }
  437. switch (event) {
  438. case SND_SOC_DAPM_POST_PMU:
  439. return snd_soc_write(codec, reg, reg_cache[reg]);
  440. default:
  441. BUG();
  442. return -EINVAL;
  443. }
  444. }
  445. static const char *st_text[] = { "None", "Right", "Left" };
  446. static const struct soc_enum str_enum =
  447. SOC_ENUM_SINGLE(WM8962_DAC_DSP_MIXING_1, 2, 3, st_text);
  448. static const struct snd_kcontrol_new str_mux =
  449. SOC_DAPM_ENUM("Right Sidetone", str_enum);
  450. static const struct soc_enum stl_enum =
  451. SOC_ENUM_SINGLE(WM8962_DAC_DSP_MIXING_2, 2, 3, st_text);
  452. static const struct snd_kcontrol_new stl_mux =
  453. SOC_DAPM_ENUM("Left Sidetone", stl_enum);
  454. static const char *outmux_text[] = { "DAC", "Mixer" };
  455. static const struct soc_enum spkoutr_enum =
  456. SOC_ENUM_SINGLE(WM8962_SPEAKER_MIXER_2, 7, 2, outmux_text);
  457. static const struct snd_kcontrol_new spkoutr_mux =
  458. SOC_DAPM_ENUM("SPKOUTR Mux", spkoutr_enum);
  459. static const struct soc_enum spkoutl_enum =
  460. SOC_ENUM_SINGLE(WM8962_SPEAKER_MIXER_1, 7, 2, outmux_text);
  461. static const struct snd_kcontrol_new spkoutl_mux =
  462. SOC_DAPM_ENUM("SPKOUTL Mux", spkoutl_enum);
  463. static const struct soc_enum hpoutr_enum =
  464. SOC_ENUM_SINGLE(WM8962_HEADPHONE_MIXER_2, 7, 2, outmux_text);
  465. static const struct snd_kcontrol_new hpoutr_mux =
  466. SOC_DAPM_ENUM("HPOUTR Mux", hpoutr_enum);
  467. static const struct soc_enum hpoutl_enum =
  468. SOC_ENUM_SINGLE(WM8962_HEADPHONE_MIXER_1, 7, 2, outmux_text);
  469. static const struct snd_kcontrol_new hpoutl_mux =
  470. SOC_DAPM_ENUM("HPOUTL Mux", hpoutl_enum);
  471. static const struct snd_kcontrol_new inpgal[] = {
  472. SOC_DAPM_SINGLE("IN1L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 3, 1, 0),
  473. SOC_DAPM_SINGLE("IN2L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 2, 1, 0),
  474. SOC_DAPM_SINGLE("IN3L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 1, 1, 0),
  475. SOC_DAPM_SINGLE("IN4L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 0, 1, 0),
  476. };
  477. static const struct snd_kcontrol_new inpgar[] = {
  478. SOC_DAPM_SINGLE("IN1R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 3, 1, 0),
  479. SOC_DAPM_SINGLE("IN2R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 2, 1, 0),
  480. SOC_DAPM_SINGLE("IN3R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 1, 1, 0),
  481. SOC_DAPM_SINGLE("IN4R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 0, 1, 0),
  482. };
  483. static const struct snd_kcontrol_new mixinl[] = {
  484. SOC_DAPM_SINGLE("IN2L Switch", WM8962_INPUT_MIXER_CONTROL_2, 5, 1, 0),
  485. SOC_DAPM_SINGLE("IN3L Switch", WM8962_INPUT_MIXER_CONTROL_2, 4, 1, 0),
  486. SOC_DAPM_SINGLE("PGA Switch", WM8962_INPUT_MIXER_CONTROL_2, 3, 1, 0),
  487. };
  488. static const struct snd_kcontrol_new mixinr[] = {
  489. SOC_DAPM_SINGLE("IN2R Switch", WM8962_INPUT_MIXER_CONTROL_2, 2, 1, 0),
  490. SOC_DAPM_SINGLE("IN3R Switch", WM8962_INPUT_MIXER_CONTROL_2, 1, 1, 0),
  491. SOC_DAPM_SINGLE("PGA Switch", WM8962_INPUT_MIXER_CONTROL_2, 0, 1, 0),
  492. };
  493. static const struct snd_kcontrol_new hpmixl[] = {
  494. SOC_DAPM_SINGLE("DACL Switch", WM8962_HEADPHONE_MIXER_1, 5, 1, 0),
  495. SOC_DAPM_SINGLE("DACR Switch", WM8962_HEADPHONE_MIXER_1, 4, 1, 0),
  496. SOC_DAPM_SINGLE("MIXINL Switch", WM8962_HEADPHONE_MIXER_1, 3, 1, 0),
  497. SOC_DAPM_SINGLE("MIXINR Switch", WM8962_HEADPHONE_MIXER_1, 2, 1, 0),
  498. SOC_DAPM_SINGLE("IN4L Switch", WM8962_HEADPHONE_MIXER_1, 1, 1, 0),
  499. SOC_DAPM_SINGLE("IN4R Switch", WM8962_HEADPHONE_MIXER_1, 0, 1, 0),
  500. };
  501. static const struct snd_kcontrol_new hpmixr[] = {
  502. SOC_DAPM_SINGLE("DACL Switch", WM8962_HEADPHONE_MIXER_2, 5, 1, 0),
  503. SOC_DAPM_SINGLE("DACR Switch", WM8962_HEADPHONE_MIXER_2, 4, 1, 0),
  504. SOC_DAPM_SINGLE("MIXINL Switch", WM8962_HEADPHONE_MIXER_2, 3, 1, 0),
  505. SOC_DAPM_SINGLE("MIXINR Switch", WM8962_HEADPHONE_MIXER_2, 2, 1, 0),
  506. SOC_DAPM_SINGLE("IN4L Switch", WM8962_HEADPHONE_MIXER_2, 1, 1, 0),
  507. SOC_DAPM_SINGLE("IN4R Switch", WM8962_HEADPHONE_MIXER_2, 0, 1, 0),
  508. };
  509. static const struct snd_kcontrol_new spkmixl[] = {
  510. SOC_DAPM_SINGLE("DACL Switch", WM8962_SPEAKER_MIXER_1, 5, 1, 0),
  511. SOC_DAPM_SINGLE("DACR Switch", WM8962_SPEAKER_MIXER_1, 4, 1, 0),
  512. SOC_DAPM_SINGLE("MIXINL Switch", WM8962_SPEAKER_MIXER_1, 3, 1, 0),
  513. SOC_DAPM_SINGLE("MIXINR Switch", WM8962_SPEAKER_MIXER_1, 2, 1, 0),
  514. SOC_DAPM_SINGLE("IN4L Switch", WM8962_SPEAKER_MIXER_1, 1, 1, 0),
  515. SOC_DAPM_SINGLE("IN4R Switch", WM8962_SPEAKER_MIXER_1, 0, 1, 0),
  516. };
  517. static const struct snd_kcontrol_new spkmixr[] = {
  518. SOC_DAPM_SINGLE("DACL Switch", WM8962_SPEAKER_MIXER_2, 5, 1, 0),
  519. SOC_DAPM_SINGLE("DACR Switch", WM8962_SPEAKER_MIXER_2, 4, 1, 0),
  520. SOC_DAPM_SINGLE("MIXINL Switch", WM8962_SPEAKER_MIXER_2, 3, 1, 0),
  521. SOC_DAPM_SINGLE("MIXINR Switch", WM8962_SPEAKER_MIXER_2, 2, 1, 0),
  522. SOC_DAPM_SINGLE("IN4L Switch", WM8962_SPEAKER_MIXER_2, 1, 1, 0),
  523. SOC_DAPM_SINGLE("IN4R Switch", WM8962_SPEAKER_MIXER_2, 0, 1, 0),
  524. };
  525. static const struct snd_soc_dapm_widget wm8962_dapm_widgets[] = {
  526. SND_SOC_DAPM_INPUT("IN1L"),
  527. SND_SOC_DAPM_INPUT("IN1R"),
  528. SND_SOC_DAPM_INPUT("IN2L"),
  529. SND_SOC_DAPM_INPUT("IN2R"),
  530. SND_SOC_DAPM_INPUT("IN3L"),
  531. SND_SOC_DAPM_INPUT("IN3R"),
  532. SND_SOC_DAPM_INPUT("IN4L"),
  533. SND_SOC_DAPM_INPUT("IN4R"),
  534. SND_SOC_DAPM_INPUT("Beep"),
  535. SND_SOC_DAPM_SUPPLY("Class G", WM8962_CHARGE_PUMP_B, 0, 1, NULL, 0),
  536. SND_SOC_DAPM_SUPPLY("SYSCLK", WM8962_CLOCKING2, 5, 0, sysclk_event,
  537. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  538. SND_SOC_DAPM_SUPPLY("Charge Pump", WM8962_CHARGE_PUMP_1, 0, 0, cp_event,
  539. SND_SOC_DAPM_POST_PMU),
  540. SND_SOC_DAPM_SUPPLY("TOCLK", WM8962_ADDITIONAL_CONTROL_1, 0, 0, NULL, 0),
  541. SND_SOC_DAPM_MIXER("INPGAL", WM8962_LEFT_INPUT_PGA_CONTROL, 4, 0,
  542. inpgal, ARRAY_SIZE(inpgal)),
  543. SND_SOC_DAPM_MIXER("INPGAR", WM8962_RIGHT_INPUT_PGA_CONTROL, 4, 0,
  544. inpgar, ARRAY_SIZE(inpgar)),
  545. SND_SOC_DAPM_MIXER("MIXINL", WM8962_PWR_MGMT_1, 5, 0,
  546. mixinl, ARRAY_SIZE(mixinl)),
  547. SND_SOC_DAPM_MIXER("MIXINR", WM8962_PWR_MGMT_1, 4, 0,
  548. mixinr, ARRAY_SIZE(mixinr)),
  549. SND_SOC_DAPM_ADC("ADCL", "Capture", WM8962_PWR_MGMT_1, 3, 0),
  550. SND_SOC_DAPM_ADC("ADCR", "Capture", WM8962_PWR_MGMT_1, 2, 0),
  551. SND_SOC_DAPM_MUX("STL", SND_SOC_NOPM, 0, 0, &stl_mux),
  552. SND_SOC_DAPM_MUX("STR", SND_SOC_NOPM, 0, 0, &str_mux),
  553. SND_SOC_DAPM_DAC("DACL", "Playback", WM8962_PWR_MGMT_2, 8, 0),
  554. SND_SOC_DAPM_DAC("DACR", "Playback", WM8962_PWR_MGMT_2, 7, 0),
  555. SND_SOC_DAPM_PGA("Left Bypass", SND_SOC_NOPM, 0, 0, NULL, 0),
  556. SND_SOC_DAPM_PGA("Right Bypass", SND_SOC_NOPM, 0, 0, NULL, 0),
  557. SND_SOC_DAPM_MIXER("HPMIXL", WM8962_MIXER_ENABLES, 3, 0,
  558. hpmixl, ARRAY_SIZE(hpmixl)),
  559. SND_SOC_DAPM_MIXER("HPMIXR", WM8962_MIXER_ENABLES, 2, 0,
  560. hpmixr, ARRAY_SIZE(hpmixr)),
  561. SND_SOC_DAPM_MUX_E("HPOUTL PGA", WM8962_PWR_MGMT_2, 6, 0, &hpoutl_mux,
  562. out_pga_event, SND_SOC_DAPM_POST_PMU),
  563. SND_SOC_DAPM_MUX_E("HPOUTR PGA", WM8962_PWR_MGMT_2, 5, 0, &hpoutr_mux,
  564. out_pga_event, SND_SOC_DAPM_POST_PMU),
  565. SND_SOC_DAPM_PGA_E("HPOUT", SND_SOC_NOPM, 0, 0, NULL, 0, hp_event,
  566. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
  567. SND_SOC_DAPM_OUTPUT("HPOUTL"),
  568. SND_SOC_DAPM_OUTPUT("HPOUTR"),
  569. };
  570. static const struct snd_soc_dapm_widget wm8962_dapm_spk_mono_widgets[] = {
  571. SND_SOC_DAPM_MIXER("Speaker Mixer", WM8962_MIXER_ENABLES, 1, 0,
  572. spkmixl, ARRAY_SIZE(spkmixl)),
  573. SND_SOC_DAPM_MUX_E("Speaker PGA", WM8962_PWR_MGMT_2, 4, 0, &spkoutl_mux,
  574. out_pga_event, SND_SOC_DAPM_POST_PMU),
  575. SND_SOC_DAPM_PGA("Speaker Output", WM8962_CLASS_D_CONTROL_1, 7, 0, NULL, 0),
  576. SND_SOC_DAPM_OUTPUT("SPKOUT"),
  577. };
  578. static const struct snd_soc_dapm_widget wm8962_dapm_spk_stereo_widgets[] = {
  579. SND_SOC_DAPM_MIXER("SPKOUTL Mixer", WM8962_MIXER_ENABLES, 1, 0,
  580. spkmixl, ARRAY_SIZE(spkmixl)),
  581. SND_SOC_DAPM_MIXER("SPKOUTR Mixer", WM8962_MIXER_ENABLES, 0, 0,
  582. spkmixr, ARRAY_SIZE(spkmixr)),
  583. SND_SOC_DAPM_MUX_E("SPKOUTL PGA", WM8962_PWR_MGMT_2, 4, 0, &spkoutl_mux,
  584. out_pga_event, SND_SOC_DAPM_POST_PMU),
  585. SND_SOC_DAPM_MUX_E("SPKOUTR PGA", WM8962_PWR_MGMT_2, 3, 0, &spkoutr_mux,
  586. out_pga_event, SND_SOC_DAPM_POST_PMU),
  587. SND_SOC_DAPM_PGA("SPKOUTR Output", WM8962_CLASS_D_CONTROL_1, 7, 0, NULL, 0),
  588. SND_SOC_DAPM_PGA("SPKOUTL Output", WM8962_CLASS_D_CONTROL_1, 6, 0, NULL, 0),
  589. SND_SOC_DAPM_OUTPUT("SPKOUTL"),
  590. SND_SOC_DAPM_OUTPUT("SPKOUTR"),
  591. };
  592. static const struct snd_soc_dapm_route wm8962_intercon[] = {
  593. { "INPGAL", "IN1L Switch", "IN1L" },
  594. { "INPGAL", "IN2L Switch", "IN2L" },
  595. { "INPGAL", "IN3L Switch", "IN3L" },
  596. { "INPGAL", "IN4L Switch", "IN4L" },
  597. { "INPGAR", "IN1R Switch", "IN1R" },
  598. { "INPGAR", "IN2R Switch", "IN2R" },
  599. { "INPGAR", "IN3R Switch", "IN3R" },
  600. { "INPGAR", "IN4R Switch", "IN4R" },
  601. { "MIXINL", "IN2L Switch", "IN2L" },
  602. { "MIXINL", "IN3L Switch", "IN3L" },
  603. { "MIXINL", "PGA Switch", "INPGAL" },
  604. { "MIXINR", "IN2R Switch", "IN2R" },
  605. { "MIXINR", "IN3R Switch", "IN3R" },
  606. { "MIXINR", "PGA Switch", "INPGAR" },
  607. { "ADCL", NULL, "SYSCLK" },
  608. { "ADCL", NULL, "TOCLK" },
  609. { "ADCL", NULL, "MIXINL" },
  610. { "ADCR", NULL, "SYSCLK" },
  611. { "ADCR", NULL, "TOCLK" },
  612. { "ADCR", NULL, "MIXINR" },
  613. { "STL", "Left", "ADCL" },
  614. { "STL", "Right", "ADCR" },
  615. { "STR", "Left", "ADCL" },
  616. { "STR", "Right", "ADCR" },
  617. { "DACL", NULL, "SYSCLK" },
  618. { "DACL", NULL, "TOCLK" },
  619. { "DACL", NULL, "Beep" },
  620. { "DACL", NULL, "STL" },
  621. { "DACR", NULL, "SYSCLK" },
  622. { "DACR", NULL, "TOCLK" },
  623. { "DACR", NULL, "Beep" },
  624. { "DACR", NULL, "STR" },
  625. { "HPMIXL", "IN4L Switch", "IN4L" },
  626. { "HPMIXL", "IN4R Switch", "IN4R" },
  627. { "HPMIXL", "DACL Switch", "DACL" },
  628. { "HPMIXL", "DACR Switch", "DACR" },
  629. { "HPMIXL", "MIXINL Switch", "MIXINL" },
  630. { "HPMIXL", "MIXINR Switch", "MIXINR" },
  631. { "HPMIXR", "IN4L Switch", "IN4L" },
  632. { "HPMIXR", "IN4R Switch", "IN4R" },
  633. { "HPMIXR", "DACL Switch", "DACL" },
  634. { "HPMIXR", "DACR Switch", "DACR" },
  635. { "HPMIXR", "MIXINL Switch", "MIXINL" },
  636. { "HPMIXR", "MIXINR Switch", "MIXINR" },
  637. { "Left Bypass", NULL, "HPMIXL" },
  638. { "Left Bypass", NULL, "Class G" },
  639. { "Right Bypass", NULL, "HPMIXR" },
  640. { "Right Bypass", NULL, "Class G" },
  641. { "HPOUTL PGA", "Mixer", "Left Bypass" },
  642. { "HPOUTL PGA", "DAC", "DACL" },
  643. { "HPOUTR PGA", "Mixer", "Right Bypass" },
  644. { "HPOUTR PGA", "DAC", "DACR" },
  645. { "HPOUT", NULL, "HPOUTL PGA" },
  646. { "HPOUT", NULL, "HPOUTR PGA" },
  647. { "HPOUT", NULL, "Charge Pump" },
  648. { "HPOUT", NULL, "SYSCLK" },
  649. { "HPOUT", NULL, "TOCLK" },
  650. { "HPOUTL", NULL, "HPOUT" },
  651. { "HPOUTR", NULL, "HPOUT" },
  652. };
  653. static const struct snd_soc_dapm_route wm8962_spk_mono_intercon[] = {
  654. { "Speaker Mixer", "IN4L Switch", "IN4L" },
  655. { "Speaker Mixer", "IN4R Switch", "IN4R" },
  656. { "Speaker Mixer", "DACL Switch", "DACL" },
  657. { "Speaker Mixer", "DACR Switch", "DACR" },
  658. { "Speaker Mixer", "MIXINL Switch", "MIXINL" },
  659. { "Speaker Mixer", "MIXINR Switch", "MIXINR" },
  660. { "Speaker PGA", "Mixer", "Speaker Mixer" },
  661. { "Speaker PGA", "DAC", "DACL" },
  662. { "Speaker Output", NULL, "Speaker PGA" },
  663. { "Speaker Output", NULL, "SYSCLK" },
  664. { "Speaker Output", NULL, "TOCLK" },
  665. { "SPKOUT", NULL, "Speaker Output" },
  666. };
  667. static const struct snd_soc_dapm_route wm8962_spk_stereo_intercon[] = {
  668. { "SPKOUTL Mixer", "IN4L Switch", "IN4L" },
  669. { "SPKOUTL Mixer", "IN4R Switch", "IN4R" },
  670. { "SPKOUTL Mixer", "DACL Switch", "DACL" },
  671. { "SPKOUTL Mixer", "DACR Switch", "DACR" },
  672. { "SPKOUTL Mixer", "MIXINL Switch", "MIXINL" },
  673. { "SPKOUTL Mixer", "MIXINR Switch", "MIXINR" },
  674. { "SPKOUTR Mixer", "IN4L Switch", "IN4L" },
  675. { "SPKOUTR Mixer", "IN4R Switch", "IN4R" },
  676. { "SPKOUTR Mixer", "DACL Switch", "DACL" },
  677. { "SPKOUTR Mixer", "DACR Switch", "DACR" },
  678. { "SPKOUTR Mixer", "MIXINL Switch", "MIXINL" },
  679. { "SPKOUTR Mixer", "MIXINR Switch", "MIXINR" },
  680. { "SPKOUTL PGA", "Mixer", "SPKOUTL Mixer" },
  681. { "SPKOUTL PGA", "DAC", "DACL" },
  682. { "SPKOUTR PGA", "Mixer", "SPKOUTR Mixer" },
  683. { "SPKOUTR PGA", "DAC", "DACR" },
  684. { "SPKOUTL Output", NULL, "SPKOUTL PGA" },
  685. { "SPKOUTL Output", NULL, "SYSCLK" },
  686. { "SPKOUTL Output", NULL, "TOCLK" },
  687. { "SPKOUTR Output", NULL, "SPKOUTR PGA" },
  688. { "SPKOUTR Output", NULL, "SYSCLK" },
  689. { "SPKOUTR Output", NULL, "TOCLK" },
  690. { "SPKOUTL", NULL, "SPKOUTL Output" },
  691. { "SPKOUTR", NULL, "SPKOUTR Output" },
  692. };
  693. static int wm8962_add_widgets(struct snd_soc_codec *codec)
  694. {
  695. struct wm8962_pdata *pdata = dev_get_platdata(codec->dev);
  696. snd_soc_add_controls(codec, wm8962_snd_controls,
  697. ARRAY_SIZE(wm8962_snd_controls));
  698. if (pdata && pdata->spk_mono)
  699. snd_soc_add_controls(codec, wm8962_spk_mono_controls,
  700. ARRAY_SIZE(wm8962_spk_mono_controls));
  701. else
  702. snd_soc_add_controls(codec, wm8962_spk_stereo_controls,
  703. ARRAY_SIZE(wm8962_spk_stereo_controls));
  704. snd_soc_dapm_new_controls(codec, wm8962_dapm_widgets,
  705. ARRAY_SIZE(wm8962_dapm_widgets));
  706. if (pdata && pdata->spk_mono)
  707. snd_soc_dapm_new_controls(codec, wm8962_dapm_spk_mono_widgets,
  708. ARRAY_SIZE(wm8962_dapm_spk_mono_widgets));
  709. else
  710. snd_soc_dapm_new_controls(codec, wm8962_dapm_spk_stereo_widgets,
  711. ARRAY_SIZE(wm8962_dapm_spk_stereo_widgets));
  712. snd_soc_dapm_add_routes(codec, wm8962_intercon,
  713. ARRAY_SIZE(wm8962_intercon));
  714. if (pdata && pdata->spk_mono)
  715. snd_soc_dapm_add_routes(codec, wm8962_spk_mono_intercon,
  716. ARRAY_SIZE(wm8962_spk_mono_intercon));
  717. else
  718. snd_soc_dapm_add_routes(codec, wm8962_spk_stereo_intercon,
  719. ARRAY_SIZE(wm8962_spk_stereo_intercon));
  720. snd_soc_dapm_disable_pin(codec, "Beep");
  721. return 0;
  722. }
  723. static void wm8962_sync_cache(struct snd_soc_codec *codec)
  724. {
  725. struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
  726. int i;
  727. if (!codec->cache_sync)
  728. return;
  729. dev_dbg(codec->dev, "Syncing cache\n");
  730. codec->cache_only = 0;
  731. /* Sync back cached values if they're different from the
  732. * hardware default.
  733. */
  734. for (i = 1; i < ARRAY_SIZE(wm8962->reg_cache); i++) {
  735. if (i == WM8962_SOFTWARE_RESET)
  736. continue;
  737. if (wm8962->reg_cache[i] == wm8962_reg[i])
  738. continue;
  739. snd_soc_write(codec, i, wm8962->reg_cache[i]);
  740. }
  741. codec->cache_sync = 0;
  742. }
  743. /* -1 for reserved values */
  744. static const int bclk_divs[] = {
  745. 1, -1, 2, 3, 4, -1, 6, 8, -1, 12, 16, 24, -1, 32, 32, 32
  746. };
  747. static void wm8962_configure_bclk(struct snd_soc_codec *codec)
  748. {
  749. struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
  750. int dspclk, i;
  751. int clocking2 = 0;
  752. int aif2 = 0;
  753. /* If the CODEC is powered on we can configure BCLK */
  754. if (codec->bias_level != SND_SOC_BIAS_OFF) {
  755. dev_dbg(codec->dev, "Bias is off, can't configure BCLK\n");
  756. return;
  757. }
  758. if (!wm8962->bclk) {
  759. dev_dbg(codec->dev, "No BCLK rate configured\n");
  760. return;
  761. }
  762. dspclk = snd_soc_read(codec, WM8962_CLOCKING1);
  763. if (dspclk < 0) {
  764. dev_err(codec->dev, "Failed to read DSPCLK: %d\n", dspclk);
  765. return;
  766. }
  767. dspclk = (dspclk & WM8962_DSPCLK_DIV_MASK) >> WM8962_DSPCLK_DIV_SHIFT;
  768. switch (dspclk) {
  769. case 0:
  770. dspclk = wm8962->sysclk_rate;
  771. break;
  772. case 1:
  773. dspclk = wm8962->sysclk_rate / 2;
  774. break;
  775. case 2:
  776. dspclk = wm8962->sysclk_rate / 4;
  777. break;
  778. default:
  779. dev_warn(codec->dev, "Unknown DSPCLK divisor read back\n");
  780. dspclk = wm8962->sysclk;
  781. }
  782. dev_dbg(codec->dev, "DSPCLK is %dHz, BCLK %d\n", dspclk, wm8962->bclk);
  783. /* We're expecting an exact match */
  784. for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
  785. if (bclk_divs[i] < 0)
  786. continue;
  787. if (dspclk / bclk_divs[i] == wm8962->bclk) {
  788. dev_dbg(codec->dev, "Selected BCLK_DIV %d for %dHz\n",
  789. bclk_divs[i], wm8962->bclk);
  790. clocking2 |= i;
  791. break;
  792. }
  793. }
  794. if (i == ARRAY_SIZE(bclk_divs)) {
  795. dev_err(codec->dev, "Unsupported BCLK ratio %d\n",
  796. dspclk / wm8962->bclk);
  797. return;
  798. }
  799. aif2 |= wm8962->bclk / wm8962->lrclk;
  800. dev_dbg(codec->dev, "Selected LRCLK divisor %d for %dHz\n",
  801. wm8962->bclk / wm8962->lrclk, wm8962->lrclk);
  802. snd_soc_update_bits(codec, WM8962_CLOCKING2,
  803. WM8962_BCLK_DIV_MASK, clocking2);
  804. snd_soc_update_bits(codec, WM8962_AUDIO_INTERFACE_2,
  805. WM8962_AIF_RATE_MASK, aif2);
  806. }
  807. static int wm8962_set_bias_level(struct snd_soc_codec *codec,
  808. enum snd_soc_bias_level level)
  809. {
  810. struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
  811. int ret;
  812. if (level == codec->bias_level)
  813. return 0;
  814. switch (level) {
  815. case SND_SOC_BIAS_ON:
  816. break;
  817. case SND_SOC_BIAS_PREPARE:
  818. /* VMID 2*50k */
  819. snd_soc_update_bits(codec, WM8962_PWR_MGMT_1,
  820. WM8962_VMID_SEL_MASK, 0x80);
  821. break;
  822. case SND_SOC_BIAS_STANDBY:
  823. if (codec->bias_level == SND_SOC_BIAS_OFF) {
  824. ret = regulator_bulk_enable(ARRAY_SIZE(wm8962->supplies),
  825. wm8962->supplies);
  826. if (ret != 0) {
  827. dev_err(codec->dev,
  828. "Failed to enable supplies: %d\n",
  829. ret);
  830. return ret;
  831. }
  832. wm8962_sync_cache(codec);
  833. snd_soc_update_bits(codec, WM8962_ANTI_POP,
  834. WM8962_STARTUP_BIAS_ENA |
  835. WM8962_VMID_BUF_ENA,
  836. WM8962_STARTUP_BIAS_ENA |
  837. WM8962_VMID_BUF_ENA);
  838. /* Bias enable at 2*50k for ramp */
  839. snd_soc_update_bits(codec, WM8962_PWR_MGMT_1,
  840. WM8962_VMID_SEL_MASK |
  841. WM8962_BIAS_ENA,
  842. WM8962_BIAS_ENA | 0x180);
  843. msleep(5);
  844. snd_soc_update_bits(codec, WM8962_CLOCKING2,
  845. WM8962_CLKREG_OVD,
  846. WM8962_CLKREG_OVD);
  847. wm8962_configure_bclk(codec);
  848. }
  849. /* VMID 2*250k */
  850. snd_soc_update_bits(codec, WM8962_PWR_MGMT_1,
  851. WM8962_VMID_SEL_MASK, 0x100);
  852. break;
  853. case SND_SOC_BIAS_OFF:
  854. snd_soc_update_bits(codec, WM8962_PWR_MGMT_1,
  855. WM8962_VMID_SEL_MASK | WM8962_BIAS_ENA, 0);
  856. snd_soc_update_bits(codec, WM8962_ANTI_POP,
  857. WM8962_STARTUP_BIAS_ENA |
  858. WM8962_VMID_BUF_ENA, 0);
  859. regulator_bulk_disable(ARRAY_SIZE(wm8962->supplies),
  860. wm8962->supplies);
  861. break;
  862. }
  863. codec->bias_level = level;
  864. return 0;
  865. }
  866. static const struct {
  867. int rate;
  868. int reg;
  869. } sr_vals[] = {
  870. { 48000, 0 },
  871. { 44100, 0 },
  872. { 32000, 1 },
  873. { 22050, 2 },
  874. { 24000, 2 },
  875. { 16000, 3 },
  876. { 11025, 4 },
  877. { 12000, 4 },
  878. { 8000, 5 },
  879. { 88200, 6 },
  880. { 96000, 6 },
  881. };
  882. static const int sysclk_rates[] = {
  883. 64, 128, 192, 256, 384, 512, 768, 1024, 1408, 1536,
  884. };
  885. static int wm8962_hw_params(struct snd_pcm_substream *substream,
  886. struct snd_pcm_hw_params *params,
  887. struct snd_soc_dai *dai)
  888. {
  889. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  890. struct snd_soc_codec *codec = rtd->codec;
  891. struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
  892. int rate = params_rate(params);
  893. int i;
  894. int aif0 = 0;
  895. int adctl3 = 0;
  896. int clocking4 = 0;
  897. wm8962->bclk = snd_soc_params_to_bclk(params);
  898. wm8962->lrclk = params_rate(params);
  899. for (i = 0; i < ARRAY_SIZE(sr_vals); i++) {
  900. if (sr_vals[i].rate == rate) {
  901. adctl3 |= sr_vals[i].reg;
  902. break;
  903. }
  904. }
  905. if (i == ARRAY_SIZE(sr_vals)) {
  906. dev_err(codec->dev, "Unsupported rate %dHz\n", rate);
  907. return -EINVAL;
  908. }
  909. if (rate % 8000 == 0)
  910. adctl3 |= WM8962_SAMPLE_RATE_INT_MODE;
  911. for (i = 0; i < ARRAY_SIZE(sysclk_rates); i++) {
  912. if (sysclk_rates[i] == wm8962->sysclk_rate / rate) {
  913. clocking4 |= i << WM8962_SYSCLK_RATE_SHIFT;
  914. break;
  915. }
  916. }
  917. if (i == ARRAY_SIZE(sysclk_rates)) {
  918. dev_err(codec->dev, "Unsupported sysclk ratio %d\n",
  919. wm8962->sysclk_rate / rate);
  920. return -EINVAL;
  921. }
  922. switch (params_format(params)) {
  923. case SNDRV_PCM_FORMAT_S16_LE:
  924. break;
  925. case SNDRV_PCM_FORMAT_S20_3LE:
  926. aif0 |= 0x40;
  927. break;
  928. case SNDRV_PCM_FORMAT_S24_LE:
  929. aif0 |= 0x80;
  930. break;
  931. case SNDRV_PCM_FORMAT_S32_LE:
  932. aif0 |= 0xc0;
  933. break;
  934. default:
  935. return -EINVAL;
  936. }
  937. snd_soc_update_bits(codec, WM8962_AUDIO_INTERFACE_0,
  938. WM8962_WL_MASK, aif0);
  939. snd_soc_update_bits(codec, WM8962_ADDITIONAL_CONTROL_3,
  940. WM8962_SAMPLE_RATE_INT_MODE |
  941. WM8962_SAMPLE_RATE_MASK, adctl3);
  942. snd_soc_update_bits(codec, WM8962_CLOCKING_4,
  943. WM8962_SYSCLK_RATE_MASK, clocking4);
  944. wm8962_configure_bclk(codec);
  945. return 0;
  946. }
  947. static int wm8962_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
  948. unsigned int freq, int dir)
  949. {
  950. struct snd_soc_codec *codec = dai->codec;
  951. struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
  952. int src;
  953. switch (clk_id) {
  954. case WM8962_SYSCLK_MCLK:
  955. wm8962->sysclk = WM8962_SYSCLK_MCLK;
  956. src = 0;
  957. break;
  958. case WM8962_SYSCLK_FLL:
  959. wm8962->sysclk = WM8962_SYSCLK_FLL;
  960. src = 1 << WM8962_SYSCLK_SRC_SHIFT;
  961. WARN_ON(freq != wm8962->fll_fout);
  962. break;
  963. default:
  964. return -EINVAL;
  965. }
  966. snd_soc_update_bits(codec, WM8962_CLOCKING2, WM8962_SYSCLK_SRC_MASK,
  967. src);
  968. wm8962->sysclk_rate = freq;
  969. return 0;
  970. }
  971. static int wm8962_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
  972. {
  973. struct snd_soc_codec *codec = dai->codec;
  974. int aif0 = 0;
  975. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  976. case SND_SOC_DAIFMT_DSP_A:
  977. aif0 |= WM8962_LRCLK_INV;
  978. case SND_SOC_DAIFMT_DSP_B:
  979. aif0 |= 3;
  980. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  981. case SND_SOC_DAIFMT_NB_NF:
  982. case SND_SOC_DAIFMT_IB_NF:
  983. break;
  984. default:
  985. return -EINVAL;
  986. }
  987. break;
  988. case SND_SOC_DAIFMT_RIGHT_J:
  989. break;
  990. case SND_SOC_DAIFMT_LEFT_J:
  991. aif0 |= 1;
  992. break;
  993. case SND_SOC_DAIFMT_I2S:
  994. aif0 |= 2;
  995. break;
  996. default:
  997. return -EINVAL;
  998. }
  999. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  1000. case SND_SOC_DAIFMT_NB_NF:
  1001. break;
  1002. case SND_SOC_DAIFMT_IB_NF:
  1003. aif0 |= WM8962_BCLK_INV;
  1004. break;
  1005. case SND_SOC_DAIFMT_NB_IF:
  1006. aif0 |= WM8962_LRCLK_INV;
  1007. break;
  1008. case SND_SOC_DAIFMT_IB_IF:
  1009. aif0 |= WM8962_BCLK_INV | WM8962_LRCLK_INV;
  1010. break;
  1011. default:
  1012. return -EINVAL;
  1013. }
  1014. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  1015. case SND_SOC_DAIFMT_CBM_CFM:
  1016. aif0 |= WM8962_MSTR;
  1017. break;
  1018. case SND_SOC_DAIFMT_CBS_CFS:
  1019. break;
  1020. default:
  1021. return -EINVAL;
  1022. }
  1023. snd_soc_update_bits(codec, WM8962_AUDIO_INTERFACE_0,
  1024. WM8962_FMT_MASK | WM8962_BCLK_INV | WM8962_MSTR |
  1025. WM8962_LRCLK_INV, aif0);
  1026. return 0;
  1027. }
  1028. struct _fll_div {
  1029. u16 fll_fratio;
  1030. u16 fll_outdiv;
  1031. u16 fll_refclk_div;
  1032. u16 n;
  1033. u16 theta;
  1034. u16 lambda;
  1035. };
  1036. /* The size in bits of the FLL divide multiplied by 10
  1037. * to allow rounding later */
  1038. #define FIXED_FLL_SIZE ((1 << 16) * 10)
  1039. static struct {
  1040. unsigned int min;
  1041. unsigned int max;
  1042. u16 fll_fratio;
  1043. int ratio;
  1044. } fll_fratios[] = {
  1045. { 0, 64000, 4, 16 },
  1046. { 64000, 128000, 3, 8 },
  1047. { 128000, 256000, 2, 4 },
  1048. { 256000, 1000000, 1, 2 },
  1049. { 1000000, 13500000, 0, 1 },
  1050. };
  1051. static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
  1052. unsigned int Fout)
  1053. {
  1054. unsigned int target;
  1055. unsigned int div;
  1056. unsigned int fratio, gcd_fll;
  1057. int i;
  1058. /* Fref must be <=13.5MHz */
  1059. div = 1;
  1060. fll_div->fll_refclk_div = 0;
  1061. while ((Fref / div) > 13500000) {
  1062. div *= 2;
  1063. fll_div->fll_refclk_div++;
  1064. if (div > 4) {
  1065. pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
  1066. Fref);
  1067. return -EINVAL;
  1068. }
  1069. }
  1070. pr_debug("FLL Fref=%u Fout=%u\n", Fref, Fout);
  1071. /* Apply the division for our remaining calculations */
  1072. Fref /= div;
  1073. /* Fvco should be 90-100MHz; don't check the upper bound */
  1074. div = 2;
  1075. while (Fout * div < 90000000) {
  1076. div++;
  1077. if (div > 64) {
  1078. pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
  1079. Fout);
  1080. return -EINVAL;
  1081. }
  1082. }
  1083. target = Fout * div;
  1084. fll_div->fll_outdiv = div - 1;
  1085. pr_debug("FLL Fvco=%dHz\n", target);
  1086. /* Find an appropraite FLL_FRATIO and factor it out of the target */
  1087. for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
  1088. if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
  1089. fll_div->fll_fratio = fll_fratios[i].fll_fratio;
  1090. fratio = fll_fratios[i].ratio;
  1091. break;
  1092. }
  1093. }
  1094. if (i == ARRAY_SIZE(fll_fratios)) {
  1095. pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
  1096. return -EINVAL;
  1097. }
  1098. fll_div->n = target / (fratio * Fref);
  1099. if (target % Fref == 0) {
  1100. fll_div->theta = 0;
  1101. fll_div->lambda = 0;
  1102. } else {
  1103. gcd_fll = gcd(target, fratio * Fref);
  1104. fll_div->theta = (target - (fll_div->n * fratio * Fref))
  1105. / gcd_fll;
  1106. fll_div->lambda = (fratio * Fref) / gcd_fll;
  1107. }
  1108. pr_debug("FLL N=%x THETA=%x LAMBDA=%x\n",
  1109. fll_div->n, fll_div->theta, fll_div->lambda);
  1110. pr_debug("FLL_FRATIO=%x FLL_OUTDIV=%x FLL_REFCLK_DIV=%x\n",
  1111. fll_div->fll_fratio, fll_div->fll_outdiv,
  1112. fll_div->fll_refclk_div);
  1113. return 0;
  1114. }
  1115. static int wm8962_set_fll(struct snd_soc_dai *dai, int fll_id, int source,
  1116. unsigned int Fref, unsigned int Fout)
  1117. {
  1118. struct snd_soc_codec *codec = dai->codec;
  1119. struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
  1120. struct _fll_div fll_div;
  1121. int ret;
  1122. int fll1 = snd_soc_read(codec, WM8962_FLL_CONTROL_1) & WM8962_FLL_ENA;
  1123. /* Any change? */
  1124. if (source == wm8962->fll_src && Fref == wm8962->fll_fref &&
  1125. Fout == wm8962->fll_fout)
  1126. return 0;
  1127. if (Fout == 0) {
  1128. dev_dbg(codec->dev, "FLL disabled\n");
  1129. wm8962->fll_fref = 0;
  1130. wm8962->fll_fout = 0;
  1131. snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1,
  1132. WM8962_FLL_ENA, 0);
  1133. return 0;
  1134. }
  1135. ret = fll_factors(&fll_div, Fref, Fout);
  1136. if (ret != 0)
  1137. return ret;
  1138. switch (fll_id) {
  1139. case WM8962_FLL_MCLK:
  1140. case WM8962_FLL_BCLK:
  1141. case WM8962_FLL_OSC:
  1142. fll1 |= (fll_id - 1) << WM8962_FLL_REFCLK_SRC_SHIFT;
  1143. break;
  1144. case WM8962_FLL_INT:
  1145. snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1,
  1146. WM8962_FLL_OSC_ENA, WM8962_FLL_OSC_ENA);
  1147. snd_soc_update_bits(codec, WM8962_FLL_CONTROL_5,
  1148. WM8962_FLL_FRC_NCO, WM8962_FLL_FRC_NCO);
  1149. break;
  1150. default:
  1151. dev_err(codec->dev, "Unknown FLL source %d\n", ret);
  1152. return -EINVAL;
  1153. }
  1154. if (fll_div.theta || fll_div.lambda)
  1155. fll1 |= WM8962_FLL_FRAC;
  1156. /* Stop the FLL while we reconfigure */
  1157. snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1, WM8962_FLL_ENA, 0);
  1158. snd_soc_update_bits(codec, WM8962_FLL_CONTROL_2,
  1159. WM8962_FLL_OUTDIV_MASK |
  1160. WM8962_FLL_REFCLK_DIV_MASK,
  1161. (fll_div.fll_outdiv << WM8962_FLL_OUTDIV_SHIFT) |
  1162. (fll_div.fll_refclk_div));
  1163. snd_soc_update_bits(codec, WM8962_FLL_CONTROL_3,
  1164. WM8962_FLL_FRATIO_MASK, fll_div.fll_fratio);
  1165. snd_soc_write(codec, WM8962_FLL_CONTROL_6, fll_div.theta);
  1166. snd_soc_write(codec, WM8962_FLL_CONTROL_7, fll_div.lambda);
  1167. snd_soc_write(codec, WM8962_FLL_CONTROL_8, fll_div.n);
  1168. snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1,
  1169. WM8962_FLL_FRAC | WM8962_FLL_REFCLK_SRC_MASK |
  1170. WM8962_FLL_ENA, fll1);
  1171. dev_dbg(codec->dev, "FLL configured for %dHz->%dHz\n", Fref, Fout);
  1172. wm8962->fll_fref = Fref;
  1173. wm8962->fll_fout = Fout;
  1174. wm8962->fll_src = source;
  1175. return 0;
  1176. }
  1177. static int wm8962_mute(struct snd_soc_dai *dai, int mute)
  1178. {
  1179. struct snd_soc_codec *codec = dai->codec;
  1180. int val;
  1181. if (mute)
  1182. val = WM8962_DAC_MUTE;
  1183. else
  1184. val = 0;
  1185. return snd_soc_update_bits(codec, WM8962_ADC_DAC_CONTROL_1,
  1186. WM8962_DAC_MUTE, val);
  1187. }
  1188. #define WM8962_RATES SNDRV_PCM_RATE_8000_96000
  1189. #define WM8962_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
  1190. SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
  1191. static struct snd_soc_dai_ops wm8962_dai_ops = {
  1192. .hw_params = wm8962_hw_params,
  1193. .set_sysclk = wm8962_set_dai_sysclk,
  1194. .set_fmt = wm8962_set_dai_fmt,
  1195. .set_pll = wm8962_set_fll,
  1196. .digital_mute = wm8962_mute,
  1197. };
  1198. static struct snd_soc_dai_driver wm8962_dai = {
  1199. .name = "wm8962",
  1200. .playback = {
  1201. .stream_name = "Playback",
  1202. .channels_min = 2,
  1203. .channels_max = 2,
  1204. .rates = WM8962_RATES,
  1205. .formats = WM8962_FORMATS,
  1206. },
  1207. .capture = {
  1208. .stream_name = "Capture",
  1209. .channels_min = 2,
  1210. .channels_max = 2,
  1211. .rates = WM8962_RATES,
  1212. .formats = WM8962_FORMATS,
  1213. },
  1214. .ops = &wm8962_dai_ops,
  1215. .symmetric_rates = 1,
  1216. };
  1217. #ifdef CONFIG_PM
  1218. static int wm8962_resume(struct snd_soc_codec *codec)
  1219. {
  1220. struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
  1221. u16 *reg_cache = codec->reg_cache;
  1222. int i;
  1223. /* Restore the registers */
  1224. for (i = 1; i < ARRAY_SIZE(wm8962->reg_cache); i++) {
  1225. switch (i) {
  1226. case WM8962_SOFTWARE_RESET:
  1227. continue;
  1228. default:
  1229. break;
  1230. }
  1231. if (reg_cache[i] != wm8962_reg[i])
  1232. snd_soc_write(codec, i, reg_cache[i]);
  1233. }
  1234. return 0;
  1235. }
  1236. #else
  1237. #define wm8962_resume NULL
  1238. #endif
  1239. #if defined(CONFIG_INPUT) || defined(CONFIG_INPUT_MODULE)
  1240. static int beep_rates[] = {
  1241. 500, 1000, 2000, 4000,
  1242. };
  1243. static void wm8962_beep_work(struct work_struct *work)
  1244. {
  1245. struct wm8962_priv *wm8962 =
  1246. container_of(work, struct wm8962_priv, beep_work);
  1247. struct snd_soc_codec *codec = wm8962->codec;
  1248. int i;
  1249. int reg = 0;
  1250. int best = 0;
  1251. if (wm8962->beep_rate) {
  1252. for (i = 0; i < ARRAY_SIZE(beep_rates); i++) {
  1253. if (abs(wm8962->beep_rate - beep_rates[i]) <
  1254. abs(wm8962->beep_rate - beep_rates[best]))
  1255. best = i;
  1256. }
  1257. dev_dbg(codec->dev, "Set beep rate %dHz for requested %dHz\n",
  1258. beep_rates[best], wm8962->beep_rate);
  1259. reg = WM8962_BEEP_ENA | (best << WM8962_BEEP_RATE_SHIFT);
  1260. snd_soc_dapm_enable_pin(codec, "Beep");
  1261. } else {
  1262. dev_dbg(codec->dev, "Disabling beep\n");
  1263. snd_soc_dapm_disable_pin(codec, "Beep");
  1264. }
  1265. snd_soc_update_bits(codec, WM8962_BEEP_GENERATOR_1,
  1266. WM8962_BEEP_ENA | WM8962_BEEP_RATE_MASK, reg);
  1267. snd_soc_dapm_sync(codec);
  1268. }
  1269. /* For usability define a way of injecting beep events for the device -
  1270. * many systems will not have a keyboard.
  1271. */
  1272. static int wm8962_beep_event(struct input_dev *dev, unsigned int type,
  1273. unsigned int code, int hz)
  1274. {
  1275. struct snd_soc_codec *codec = input_get_drvdata(dev);
  1276. struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
  1277. dev_dbg(codec->dev, "Beep event %x %x\n", code, hz);
  1278. switch (code) {
  1279. case SND_BELL:
  1280. if (hz)
  1281. hz = 1000;
  1282. case SND_TONE:
  1283. break;
  1284. default:
  1285. return -1;
  1286. }
  1287. /* Kick the beep from a workqueue */
  1288. wm8962->beep_rate = hz;
  1289. schedule_work(&wm8962->beep_work);
  1290. return 0;
  1291. }
  1292. static ssize_t wm8962_beep_set(struct device *dev,
  1293. struct device_attribute *attr,
  1294. const char *buf, size_t count)
  1295. {
  1296. struct wm8962_priv *wm8962 = dev_get_drvdata(dev);
  1297. long int time;
  1298. strict_strtol(buf, 10, &time);
  1299. input_event(wm8962->beep, EV_SND, SND_TONE, time);
  1300. return count;
  1301. }
  1302. static DEVICE_ATTR(beep, 0200, NULL, wm8962_beep_set);
  1303. static void wm8962_init_beep(struct snd_soc_codec *codec)
  1304. {
  1305. struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
  1306. int ret;
  1307. wm8962->beep = input_allocate_device();
  1308. if (!wm8962->beep) {
  1309. dev_err(codec->dev, "Failed to allocate beep device\n");
  1310. return;
  1311. }
  1312. INIT_WORK(&wm8962->beep_work, wm8962_beep_work);
  1313. wm8962->beep_rate = 0;
  1314. wm8962->beep->name = "WM8962 Beep Generator";
  1315. wm8962->beep->phys = dev_name(codec->dev);
  1316. wm8962->beep->id.bustype = BUS_I2C;
  1317. wm8962->beep->evbit[0] = BIT_MASK(EV_SND);
  1318. wm8962->beep->sndbit[0] = BIT_MASK(SND_BELL) | BIT_MASK(SND_TONE);
  1319. wm8962->beep->event = wm8962_beep_event;
  1320. wm8962->beep->dev.parent = codec->dev;
  1321. input_set_drvdata(wm8962->beep, codec);
  1322. ret = input_register_device(wm8962->beep);
  1323. if (ret != 0) {
  1324. input_free_device(wm8962->beep);
  1325. wm8962->beep = NULL;
  1326. dev_err(codec->dev, "Failed to register beep device\n");
  1327. }
  1328. ret = device_create_file(codec->dev, &dev_attr_beep);
  1329. if (ret != 0) {
  1330. dev_err(codec->dev, "Failed to create keyclick file: %d\n",
  1331. ret);
  1332. }
  1333. }
  1334. static void wm8962_free_beep(struct snd_soc_codec *codec)
  1335. {
  1336. struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
  1337. device_remove_file(codec->dev, &dev_attr_beep);
  1338. input_unregister_device(wm8962->beep);
  1339. cancel_work_sync(&wm8962->beep_work);
  1340. wm8962->beep = NULL;
  1341. snd_soc_update_bits(codec, WM8962_BEEP_GENERATOR_1, WM8962_BEEP_ENA,0);
  1342. }
  1343. #else
  1344. static void wm8962_init_beep(struct snd_soc_codec *codec)
  1345. {
  1346. }
  1347. static void wm8962_free_beep(struct snd_soc_codec *codec)
  1348. {
  1349. }
  1350. #endif
  1351. static int wm8962_probe(struct snd_soc_codec *codec)
  1352. {
  1353. int ret;
  1354. struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
  1355. struct wm8962_pdata *pdata = dev_get_platdata(codec->dev);
  1356. int i;
  1357. wm8962->codec = codec;
  1358. codec->cache_sync = 1;
  1359. codec->idle_bias_off = 1;
  1360. ret = snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_I2C);
  1361. if (ret != 0) {
  1362. dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
  1363. goto err;
  1364. }
  1365. for (i = 0; i < ARRAY_SIZE(wm8962->supplies); i++)
  1366. wm8962->supplies[i].supply = wm8962_supply_names[i];
  1367. ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8962->supplies),
  1368. wm8962->supplies);
  1369. if (ret != 0) {
  1370. dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
  1371. goto err;
  1372. }
  1373. wm8962->disable_nb[0].notifier_call = wm8962_regulator_event_0;
  1374. wm8962->disable_nb[1].notifier_call = wm8962_regulator_event_1;
  1375. wm8962->disable_nb[2].notifier_call = wm8962_regulator_event_2;
  1376. wm8962->disable_nb[3].notifier_call = wm8962_regulator_event_3;
  1377. wm8962->disable_nb[4].notifier_call = wm8962_regulator_event_4;
  1378. wm8962->disable_nb[5].notifier_call = wm8962_regulator_event_5;
  1379. wm8962->disable_nb[6].notifier_call = wm8962_regulator_event_6;
  1380. wm8962->disable_nb[7].notifier_call = wm8962_regulator_event_7;
  1381. /* This should really be moved into the regulator core */
  1382. for (i = 0; i < ARRAY_SIZE(wm8962->supplies); i++) {
  1383. ret = regulator_register_notifier(wm8962->supplies[i].consumer,
  1384. &wm8962->disable_nb[i]);
  1385. if (ret != 0) {
  1386. dev_err(codec->dev,
  1387. "Failed to register regulator notifier: %d\n",
  1388. ret);
  1389. }
  1390. }
  1391. ret = regulator_bulk_enable(ARRAY_SIZE(wm8962->supplies),
  1392. wm8962->supplies);
  1393. if (ret != 0) {
  1394. dev_err(codec->dev, "Failed to enable supplies: %d\n", ret);
  1395. goto err_get;
  1396. }
  1397. ret = snd_soc_read(codec, WM8962_SOFTWARE_RESET);
  1398. if (ret < 0) {
  1399. dev_err(codec->dev, "Failed to read ID register\n");
  1400. goto err_enable;
  1401. }
  1402. if (ret != wm8962_reg[WM8962_SOFTWARE_RESET]) {
  1403. dev_err(codec->dev, "Device is not a WM8962, ID %x != %x\n",
  1404. ret, wm8962_reg[WM8962_SOFTWARE_RESET]);
  1405. ret = -EINVAL;
  1406. goto err_enable;
  1407. }
  1408. ret = snd_soc_read(codec, WM8962_RIGHT_INPUT_VOLUME);
  1409. if (ret < 0) {
  1410. dev_err(codec->dev, "Failed to read device revision: %d\n",
  1411. ret);
  1412. goto err_enable;
  1413. }
  1414. dev_info(codec->dev, "customer id %x revision %c\n",
  1415. (ret & WM8962_CUST_ID_MASK) >> WM8962_CUST_ID_SHIFT,
  1416. ((ret & WM8962_CHIP_REV_MASK) >> WM8962_CHIP_REV_SHIFT)
  1417. + 'A');
  1418. ret = wm8962_reset(codec);
  1419. if (ret < 0) {
  1420. dev_err(codec->dev, "Failed to issue reset\n");
  1421. goto err_enable;
  1422. }
  1423. /* SYSCLK defaults to on; make sure it is off so we can safely
  1424. * write to registers if the device is declocked.
  1425. */
  1426. snd_soc_update_bits(codec, WM8962_CLOCKING2, WM8962_SYSCLK_ENA, 0);
  1427. regulator_bulk_disable(ARRAY_SIZE(wm8962->supplies), wm8962->supplies);
  1428. if (pdata) {
  1429. /* Apply static configuration for GPIOs */
  1430. for (i = 0; i < ARRAY_SIZE(pdata->gpio_init); i++)
  1431. if (pdata->gpio_init[i])
  1432. snd_soc_write(codec, 0x200 + i,
  1433. pdata->gpio_init[i] & 0xffff);
  1434. /* Put the speakers into mono mode? */
  1435. if (pdata->spk_mono)
  1436. wm8962->reg_cache[WM8962_CLASS_D_CONTROL_2]
  1437. |= WM8962_SPK_MONO;
  1438. }
  1439. /* Latch volume update bits */
  1440. wm8962->reg_cache[WM8962_LEFT_INPUT_VOLUME] |= WM8962_IN_VU;
  1441. wm8962->reg_cache[WM8962_RIGHT_INPUT_VOLUME] |= WM8962_IN_VU;
  1442. wm8962->reg_cache[WM8962_LEFT_ADC_VOLUME] |= WM8962_ADC_VU;
  1443. wm8962->reg_cache[WM8962_RIGHT_ADC_VOLUME] |= WM8962_ADC_VU;
  1444. wm8962->reg_cache[WM8962_LEFT_DAC_VOLUME] |= WM8962_DAC_VU;
  1445. wm8962->reg_cache[WM8962_RIGHT_DAC_VOLUME] |= WM8962_DAC_VU;
  1446. wm8962->reg_cache[WM8962_SPKOUTL_VOLUME] |= WM8962_SPKOUT_VU;
  1447. wm8962->reg_cache[WM8962_SPKOUTR_VOLUME] |= WM8962_SPKOUT_VU;
  1448. wm8962->reg_cache[WM8962_HPOUTL_VOLUME] |= WM8962_HPOUT_VU;
  1449. wm8962->reg_cache[WM8962_HPOUTR_VOLUME] |= WM8962_HPOUT_VU;
  1450. wm8962_add_widgets(codec);
  1451. wm8962_init_beep(codec);
  1452. return 0;
  1453. err_enable:
  1454. regulator_bulk_disable(ARRAY_SIZE(wm8962->supplies), wm8962->supplies);
  1455. err_get:
  1456. regulator_bulk_free(ARRAY_SIZE(wm8962->supplies), wm8962->supplies);
  1457. err:
  1458. kfree(wm8962);
  1459. return ret;
  1460. }
  1461. static int wm8962_remove(struct snd_soc_codec *codec)
  1462. {
  1463. struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
  1464. int i;
  1465. wm8962_free_beep(codec);
  1466. for (i = 0; i < ARRAY_SIZE(wm8962->supplies); i++)
  1467. regulator_unregister_notifier(wm8962->supplies[i].consumer,
  1468. &wm8962->disable_nb[i]);
  1469. regulator_bulk_free(ARRAY_SIZE(wm8962->supplies), wm8962->supplies);
  1470. return 0;
  1471. }
  1472. static struct snd_soc_codec_driver soc_codec_dev_wm8962 = {
  1473. .probe = wm8962_probe,
  1474. .remove = wm8962_remove,
  1475. .resume = wm8962_resume,
  1476. .set_bias_level = wm8962_set_bias_level,
  1477. .reg_cache_size = WM8962_MAX_REGISTER + 1,
  1478. .reg_word_size = sizeof(u16),
  1479. .reg_cache_default = wm8962_reg,
  1480. .volatile_register = wm8962_volatile_register,
  1481. .readable_register = wm8962_readable_register,
  1482. };
  1483. #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
  1484. static __devinit int wm8962_i2c_probe(struct i2c_client *i2c,
  1485. const struct i2c_device_id *id)
  1486. {
  1487. struct wm8962_priv *wm8962;
  1488. int ret;
  1489. wm8962 = kzalloc(sizeof(struct wm8962_priv), GFP_KERNEL);
  1490. if (wm8962 == NULL)
  1491. return -ENOMEM;
  1492. i2c_set_clientdata(i2c, wm8962);
  1493. ret = snd_soc_register_codec(&i2c->dev,
  1494. &soc_codec_dev_wm8962, &wm8962_dai, 1);
  1495. if (ret < 0)
  1496. kfree(wm8962);
  1497. return ret;
  1498. }
  1499. static __devexit int wm8962_i2c_remove(struct i2c_client *client)
  1500. {
  1501. snd_soc_unregister_codec(&client->dev);
  1502. kfree(i2c_get_clientdata(client));
  1503. return 0;
  1504. }
  1505. static const struct i2c_device_id wm8962_i2c_id[] = {
  1506. { "wm8962", 0 },
  1507. { }
  1508. };
  1509. MODULE_DEVICE_TABLE(i2c, wm8962_i2c_id);
  1510. static struct i2c_driver wm8962_i2c_driver = {
  1511. .driver = {
  1512. .name = "wm8962",
  1513. .owner = THIS_MODULE,
  1514. },
  1515. .probe = wm8962_i2c_probe,
  1516. .remove = __devexit_p(wm8962_i2c_remove),
  1517. .id_table = wm8962_i2c_id,
  1518. };
  1519. #endif
  1520. static int __init wm8962_modinit(void)
  1521. {
  1522. int ret;
  1523. #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
  1524. ret = i2c_add_driver(&wm8962_i2c_driver);
  1525. if (ret != 0) {
  1526. printk(KERN_ERR "Failed to register WM8962 I2C driver: %d\n",
  1527. ret);
  1528. }
  1529. #endif
  1530. return 0;
  1531. }
  1532. module_init(wm8962_modinit);
  1533. static void __exit wm8962_exit(void)
  1534. {
  1535. #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
  1536. i2c_del_driver(&wm8962_i2c_driver);
  1537. #endif
  1538. }
  1539. module_exit(wm8962_exit);
  1540. MODULE_DESCRIPTION("ASoC WM8962 driver");
  1541. MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
  1542. MODULE_LICENSE("GPL");