xhci-hub.c 21 KB

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  1. /*
  2. * xHCI host controller driver
  3. *
  4. * Copyright (C) 2008 Intel Corp.
  5. *
  6. * Author: Sarah Sharp
  7. * Some code borrowed from the Linux EHCI driver.
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License version 2 as
  11. * published by the Free Software Foundation.
  12. *
  13. * This program is distributed in the hope that it will be useful, but
  14. * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15. * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  16. * for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software Foundation,
  20. * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21. */
  22. #include <asm/unaligned.h>
  23. #include "xhci.h"
  24. #define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
  25. #define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \
  26. PORT_RC | PORT_PLC | PORT_PE)
  27. static void xhci_hub_descriptor(struct xhci_hcd *xhci,
  28. struct usb_hub_descriptor *desc)
  29. {
  30. int ports;
  31. u16 temp;
  32. ports = HCS_MAX_PORTS(xhci->hcs_params1);
  33. /* USB 3.0 hubs have a different descriptor, but we fake this for now */
  34. desc->bDescriptorType = 0x29;
  35. desc->bPwrOn2PwrGood = 10; /* xhci section 5.4.9 says 20ms max */
  36. desc->bHubContrCurrent = 0;
  37. desc->bNbrPorts = ports;
  38. temp = 1 + (ports / 8);
  39. desc->bDescLength = 7 + 2 * temp;
  40. /* Why does core/hcd.h define bitmap? It's just confusing. */
  41. memset(&desc->DeviceRemovable[0], 0, temp);
  42. memset(&desc->DeviceRemovable[temp], 0xff, temp);
  43. /* Ugh, these should be #defines, FIXME */
  44. /* Using table 11-13 in USB 2.0 spec. */
  45. temp = 0;
  46. /* Bits 1:0 - support port power switching, or power always on */
  47. if (HCC_PPC(xhci->hcc_params))
  48. temp |= 0x0001;
  49. else
  50. temp |= 0x0002;
  51. /* Bit 2 - root hubs are not part of a compound device */
  52. /* Bits 4:3 - individual port over current protection */
  53. temp |= 0x0008;
  54. /* Bits 6:5 - no TTs in root ports */
  55. /* Bit 7 - no port indicators */
  56. desc->wHubCharacteristics = (__force __u16) cpu_to_le16(temp);
  57. }
  58. static unsigned int xhci_port_speed(unsigned int port_status)
  59. {
  60. if (DEV_LOWSPEED(port_status))
  61. return USB_PORT_STAT_LOW_SPEED;
  62. if (DEV_HIGHSPEED(port_status))
  63. return USB_PORT_STAT_HIGH_SPEED;
  64. if (DEV_SUPERSPEED(port_status))
  65. return USB_PORT_STAT_SUPER_SPEED;
  66. /*
  67. * FIXME: Yes, we should check for full speed, but the core uses that as
  68. * a default in portspeed() in usb/core/hub.c (which is the only place
  69. * USB_PORT_STAT_*_SPEED is used).
  70. */
  71. return 0;
  72. }
  73. /*
  74. * These bits are Read Only (RO) and should be saved and written to the
  75. * registers: 0, 3, 10:13, 30
  76. * connect status, over-current status, port speed, and device removable.
  77. * connect status and port speed are also sticky - meaning they're in
  78. * the AUX well and they aren't changed by a hot, warm, or cold reset.
  79. */
  80. #define XHCI_PORT_RO ((1<<0) | (1<<3) | (0xf<<10) | (1<<30))
  81. /*
  82. * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit:
  83. * bits 5:8, 9, 14:15, 25:27
  84. * link state, port power, port indicator state, "wake on" enable state
  85. */
  86. #define XHCI_PORT_RWS ((0xf<<5) | (1<<9) | (0x3<<14) | (0x7<<25))
  87. /*
  88. * These bits are RW; writing a 1 sets the bit, writing a 0 has no effect:
  89. * bit 4 (port reset)
  90. */
  91. #define XHCI_PORT_RW1S ((1<<4))
  92. /*
  93. * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect:
  94. * bits 1, 17, 18, 19, 20, 21, 22, 23
  95. * port enable/disable, and
  96. * change bits: connect, PED, warm port reset changed (reserved zero for USB 2.0 ports),
  97. * over-current, reset, link state, and L1 change
  98. */
  99. #define XHCI_PORT_RW1CS ((1<<1) | (0x7f<<17))
  100. /*
  101. * Bit 16 is RW, and writing a '1' to it causes the link state control to be
  102. * latched in
  103. */
  104. #define XHCI_PORT_RW ((1<<16))
  105. /*
  106. * These bits are Reserved Zero (RsvdZ) and zero should be written to them:
  107. * bits 2, 24, 28:31
  108. */
  109. #define XHCI_PORT_RZ ((1<<2) | (1<<24) | (0xf<<28))
  110. /*
  111. * Given a port state, this function returns a value that would result in the
  112. * port being in the same state, if the value was written to the port status
  113. * control register.
  114. * Save Read Only (RO) bits and save read/write bits where
  115. * writing a 0 clears the bit and writing a 1 sets the bit (RWS).
  116. * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect.
  117. */
  118. u32 xhci_port_state_to_neutral(u32 state)
  119. {
  120. /* Save read-only status and port state */
  121. return (state & XHCI_PORT_RO) | (state & XHCI_PORT_RWS);
  122. }
  123. /*
  124. * find slot id based on port number.
  125. */
  126. int xhci_find_slot_id_by_port(struct xhci_hcd *xhci, u16 port)
  127. {
  128. int slot_id;
  129. int i;
  130. slot_id = 0;
  131. for (i = 0; i < MAX_HC_SLOTS; i++) {
  132. if (!xhci->devs[i])
  133. continue;
  134. if (xhci->devs[i]->port == port) {
  135. slot_id = i;
  136. break;
  137. }
  138. }
  139. return slot_id;
  140. }
  141. /*
  142. * Stop device
  143. * It issues stop endpoint command for EP 0 to 30. And wait the last command
  144. * to complete.
  145. * suspend will set to 1, if suspend bit need to set in command.
  146. */
  147. static int xhci_stop_device(struct xhci_hcd *xhci, int slot_id, int suspend)
  148. {
  149. struct xhci_virt_device *virt_dev;
  150. struct xhci_command *cmd;
  151. unsigned long flags;
  152. int timeleft;
  153. int ret;
  154. int i;
  155. ret = 0;
  156. virt_dev = xhci->devs[slot_id];
  157. cmd = xhci_alloc_command(xhci, false, true, GFP_NOIO);
  158. if (!cmd) {
  159. xhci_dbg(xhci, "Couldn't allocate command structure.\n");
  160. return -ENOMEM;
  161. }
  162. spin_lock_irqsave(&xhci->lock, flags);
  163. for (i = LAST_EP_INDEX; i > 0; i--) {
  164. if (virt_dev->eps[i].ring && virt_dev->eps[i].ring->dequeue)
  165. xhci_queue_stop_endpoint(xhci, slot_id, i, suspend);
  166. }
  167. cmd->command_trb = xhci->cmd_ring->enqueue;
  168. list_add_tail(&cmd->cmd_list, &virt_dev->cmd_list);
  169. xhci_queue_stop_endpoint(xhci, slot_id, 0, suspend);
  170. xhci_ring_cmd_db(xhci);
  171. spin_unlock_irqrestore(&xhci->lock, flags);
  172. /* Wait for last stop endpoint command to finish */
  173. timeleft = wait_for_completion_interruptible_timeout(
  174. cmd->completion,
  175. USB_CTRL_SET_TIMEOUT);
  176. if (timeleft <= 0) {
  177. xhci_warn(xhci, "%s while waiting for stop endpoint command\n",
  178. timeleft == 0 ? "Timeout" : "Signal");
  179. spin_lock_irqsave(&xhci->lock, flags);
  180. /* The timeout might have raced with the event ring handler, so
  181. * only delete from the list if the item isn't poisoned.
  182. */
  183. if (cmd->cmd_list.next != LIST_POISON1)
  184. list_del(&cmd->cmd_list);
  185. spin_unlock_irqrestore(&xhci->lock, flags);
  186. ret = -ETIME;
  187. goto command_cleanup;
  188. }
  189. command_cleanup:
  190. xhci_free_command(xhci, cmd);
  191. return ret;
  192. }
  193. /*
  194. * Ring device, it rings the all doorbells unconditionally.
  195. */
  196. void xhci_ring_device(struct xhci_hcd *xhci, int slot_id)
  197. {
  198. int i;
  199. for (i = 0; i < LAST_EP_INDEX + 1; i++)
  200. if (xhci->devs[slot_id]->eps[i].ring &&
  201. xhci->devs[slot_id]->eps[i].ring->dequeue)
  202. xhci_ring_ep_doorbell(xhci, slot_id, i, 0);
  203. return;
  204. }
  205. static void xhci_disable_port(struct xhci_hcd *xhci, u16 wIndex,
  206. u32 __iomem *addr, u32 port_status)
  207. {
  208. /* Write 1 to disable the port */
  209. xhci_writel(xhci, port_status | PORT_PE, addr);
  210. port_status = xhci_readl(xhci, addr);
  211. xhci_dbg(xhci, "disable port, actual port %d status = 0x%x\n",
  212. wIndex, port_status);
  213. }
  214. static void xhci_clear_port_change_bit(struct xhci_hcd *xhci, u16 wValue,
  215. u16 wIndex, u32 __iomem *addr, u32 port_status)
  216. {
  217. char *port_change_bit;
  218. u32 status;
  219. switch (wValue) {
  220. case USB_PORT_FEAT_C_RESET:
  221. status = PORT_RC;
  222. port_change_bit = "reset";
  223. break;
  224. case USB_PORT_FEAT_C_CONNECTION:
  225. status = PORT_CSC;
  226. port_change_bit = "connect";
  227. break;
  228. case USB_PORT_FEAT_C_OVER_CURRENT:
  229. status = PORT_OCC;
  230. port_change_bit = "over-current";
  231. break;
  232. case USB_PORT_FEAT_C_ENABLE:
  233. status = PORT_PEC;
  234. port_change_bit = "enable/disable";
  235. break;
  236. case USB_PORT_FEAT_C_SUSPEND:
  237. status = PORT_PLC;
  238. port_change_bit = "suspend/resume";
  239. break;
  240. default:
  241. /* Should never happen */
  242. return;
  243. }
  244. /* Change bits are all write 1 to clear */
  245. xhci_writel(xhci, port_status | status, addr);
  246. port_status = xhci_readl(xhci, addr);
  247. xhci_dbg(xhci, "clear port %s change, actual port %d status = 0x%x\n",
  248. port_change_bit, wIndex, port_status);
  249. }
  250. int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
  251. u16 wIndex, char *buf, u16 wLength)
  252. {
  253. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  254. int ports;
  255. unsigned long flags;
  256. u32 temp, temp1, status;
  257. int retval = 0;
  258. u32 __iomem *addr;
  259. int slot_id;
  260. ports = HCS_MAX_PORTS(xhci->hcs_params1);
  261. spin_lock_irqsave(&xhci->lock, flags);
  262. switch (typeReq) {
  263. case GetHubStatus:
  264. /* No power source, over-current reported per port */
  265. memset(buf, 0, 4);
  266. break;
  267. case GetHubDescriptor:
  268. xhci_hub_descriptor(xhci, (struct usb_hub_descriptor *) buf);
  269. break;
  270. case GetPortStatus:
  271. if (!wIndex || wIndex > ports)
  272. goto error;
  273. wIndex--;
  274. status = 0;
  275. addr = &xhci->op_regs->port_status_base + NUM_PORT_REGS*(wIndex & 0xff);
  276. temp = xhci_readl(xhci, addr);
  277. xhci_dbg(xhci, "get port status, actual port %d status = 0x%x\n", wIndex, temp);
  278. /* wPortChange bits */
  279. if (temp & PORT_CSC)
  280. status |= USB_PORT_STAT_C_CONNECTION << 16;
  281. if (temp & PORT_PEC)
  282. status |= USB_PORT_STAT_C_ENABLE << 16;
  283. if ((temp & PORT_OCC))
  284. status |= USB_PORT_STAT_C_OVERCURRENT << 16;
  285. /*
  286. * FIXME ignoring reset and USB 2.1/3.0 specific
  287. * changes
  288. */
  289. if ((temp & PORT_PLS_MASK) == XDEV_U3
  290. && (temp & PORT_POWER))
  291. status |= 1 << USB_PORT_FEAT_SUSPEND;
  292. if ((temp & PORT_PLS_MASK) == XDEV_RESUME) {
  293. if ((temp & PORT_RESET) || !(temp & PORT_PE))
  294. goto error;
  295. if (!DEV_SUPERSPEED(temp) && time_after_eq(jiffies,
  296. xhci->resume_done[wIndex])) {
  297. xhci_dbg(xhci, "Resume USB2 port %d\n",
  298. wIndex + 1);
  299. xhci->resume_done[wIndex] = 0;
  300. temp1 = xhci_port_state_to_neutral(temp);
  301. temp1 &= ~PORT_PLS_MASK;
  302. temp1 |= PORT_LINK_STROBE | XDEV_U0;
  303. xhci_writel(xhci, temp1, addr);
  304. xhci_dbg(xhci, "set port %d resume\n",
  305. wIndex + 1);
  306. slot_id = xhci_find_slot_id_by_port(xhci,
  307. wIndex + 1);
  308. if (!slot_id) {
  309. xhci_dbg(xhci, "slot_id is zero\n");
  310. goto error;
  311. }
  312. xhci_ring_device(xhci, slot_id);
  313. xhci->port_c_suspend[wIndex >> 5] |=
  314. 1 << (wIndex & 31);
  315. xhci->suspended_ports[wIndex >> 5] &=
  316. ~(1 << (wIndex & 31));
  317. }
  318. }
  319. if ((temp & PORT_PLS_MASK) == XDEV_U0
  320. && (temp & PORT_POWER)
  321. && (xhci->suspended_ports[wIndex >> 5] &
  322. (1 << (wIndex & 31)))) {
  323. xhci->suspended_ports[wIndex >> 5] &=
  324. ~(1 << (wIndex & 31));
  325. xhci->port_c_suspend[wIndex >> 5] |=
  326. 1 << (wIndex & 31);
  327. }
  328. if (temp & PORT_CONNECT) {
  329. status |= USB_PORT_STAT_CONNECTION;
  330. status |= xhci_port_speed(temp);
  331. }
  332. if (temp & PORT_PE)
  333. status |= USB_PORT_STAT_ENABLE;
  334. if (temp & PORT_OC)
  335. status |= USB_PORT_STAT_OVERCURRENT;
  336. if (temp & PORT_RESET)
  337. status |= USB_PORT_STAT_RESET;
  338. if (temp & PORT_POWER)
  339. status |= USB_PORT_STAT_POWER;
  340. if (xhci->port_c_suspend[wIndex >> 5] & (1 << (wIndex & 31)))
  341. status |= 1 << USB_PORT_FEAT_C_SUSPEND;
  342. xhci_dbg(xhci, "Get port status returned 0x%x\n", status);
  343. put_unaligned(cpu_to_le32(status), (__le32 *) buf);
  344. break;
  345. case SetPortFeature:
  346. wIndex &= 0xff;
  347. if (!wIndex || wIndex > ports)
  348. goto error;
  349. wIndex--;
  350. addr = &xhci->op_regs->port_status_base + NUM_PORT_REGS*(wIndex & 0xff);
  351. temp = xhci_readl(xhci, addr);
  352. temp = xhci_port_state_to_neutral(temp);
  353. switch (wValue) {
  354. case USB_PORT_FEAT_SUSPEND:
  355. temp = xhci_readl(xhci, addr);
  356. /* In spec software should not attempt to suspend
  357. * a port unless the port reports that it is in the
  358. * enabled (PED = ‘1’,PLS < ‘3’) state.
  359. */
  360. if ((temp & PORT_PE) == 0 || (temp & PORT_RESET)
  361. || (temp & PORT_PLS_MASK) >= XDEV_U3) {
  362. xhci_warn(xhci, "USB core suspending device "
  363. "not in U0/U1/U2.\n");
  364. goto error;
  365. }
  366. slot_id = xhci_find_slot_id_by_port(xhci, wIndex + 1);
  367. if (!slot_id) {
  368. xhci_warn(xhci, "slot_id is zero\n");
  369. goto error;
  370. }
  371. /* unlock to execute stop endpoint commands */
  372. spin_unlock_irqrestore(&xhci->lock, flags);
  373. xhci_stop_device(xhci, slot_id, 1);
  374. spin_lock_irqsave(&xhci->lock, flags);
  375. temp = xhci_port_state_to_neutral(temp);
  376. temp &= ~PORT_PLS_MASK;
  377. temp |= PORT_LINK_STROBE | XDEV_U3;
  378. xhci_writel(xhci, temp, addr);
  379. spin_unlock_irqrestore(&xhci->lock, flags);
  380. msleep(10); /* wait device to enter */
  381. spin_lock_irqsave(&xhci->lock, flags);
  382. temp = xhci_readl(xhci, addr);
  383. xhci->suspended_ports[wIndex >> 5] |=
  384. 1 << (wIndex & (31));
  385. break;
  386. case USB_PORT_FEAT_POWER:
  387. /*
  388. * Turn on ports, even if there isn't per-port switching.
  389. * HC will report connect events even before this is set.
  390. * However, khubd will ignore the roothub events until
  391. * the roothub is registered.
  392. */
  393. xhci_writel(xhci, temp | PORT_POWER, addr);
  394. temp = xhci_readl(xhci, addr);
  395. xhci_dbg(xhci, "set port power, actual port %d status = 0x%x\n", wIndex, temp);
  396. break;
  397. case USB_PORT_FEAT_RESET:
  398. temp = (temp | PORT_RESET);
  399. xhci_writel(xhci, temp, addr);
  400. temp = xhci_readl(xhci, addr);
  401. xhci_dbg(xhci, "set port reset, actual port %d status = 0x%x\n", wIndex, temp);
  402. break;
  403. default:
  404. goto error;
  405. }
  406. temp = xhci_readl(xhci, addr); /* unblock any posted writes */
  407. break;
  408. case ClearPortFeature:
  409. if (!wIndex || wIndex > ports)
  410. goto error;
  411. wIndex--;
  412. addr = &xhci->op_regs->port_status_base +
  413. NUM_PORT_REGS*(wIndex & 0xff);
  414. temp = xhci_readl(xhci, addr);
  415. temp = xhci_port_state_to_neutral(temp);
  416. switch (wValue) {
  417. case USB_PORT_FEAT_SUSPEND:
  418. temp = xhci_readl(xhci, addr);
  419. xhci_dbg(xhci, "clear USB_PORT_FEAT_SUSPEND\n");
  420. xhci_dbg(xhci, "PORTSC %04x\n", temp);
  421. if (temp & PORT_RESET)
  422. goto error;
  423. if (temp & XDEV_U3) {
  424. if ((temp & PORT_PE) == 0)
  425. goto error;
  426. if (DEV_SUPERSPEED(temp)) {
  427. temp = xhci_port_state_to_neutral(temp);
  428. temp &= ~PORT_PLS_MASK;
  429. temp |= PORT_LINK_STROBE | XDEV_U0;
  430. xhci_writel(xhci, temp, addr);
  431. xhci_readl(xhci, addr);
  432. } else {
  433. temp = xhci_port_state_to_neutral(temp);
  434. temp &= ~PORT_PLS_MASK;
  435. temp |= PORT_LINK_STROBE | XDEV_RESUME;
  436. xhci_writel(xhci, temp, addr);
  437. spin_unlock_irqrestore(&xhci->lock,
  438. flags);
  439. msleep(20);
  440. spin_lock_irqsave(&xhci->lock, flags);
  441. temp = xhci_readl(xhci, addr);
  442. temp = xhci_port_state_to_neutral(temp);
  443. temp &= ~PORT_PLS_MASK;
  444. temp |= PORT_LINK_STROBE | XDEV_U0;
  445. xhci_writel(xhci, temp, addr);
  446. }
  447. xhci->port_c_suspend[wIndex >> 5] |=
  448. 1 << (wIndex & 31);
  449. }
  450. slot_id = xhci_find_slot_id_by_port(xhci, wIndex + 1);
  451. if (!slot_id) {
  452. xhci_dbg(xhci, "slot_id is zero\n");
  453. goto error;
  454. }
  455. xhci_ring_device(xhci, slot_id);
  456. break;
  457. case USB_PORT_FEAT_C_SUSPEND:
  458. xhci->port_c_suspend[wIndex >> 5] &=
  459. ~(1 << (wIndex & 31));
  460. case USB_PORT_FEAT_C_RESET:
  461. case USB_PORT_FEAT_C_CONNECTION:
  462. case USB_PORT_FEAT_C_OVER_CURRENT:
  463. case USB_PORT_FEAT_C_ENABLE:
  464. xhci_clear_port_change_bit(xhci, wValue, wIndex,
  465. addr, temp);
  466. break;
  467. case USB_PORT_FEAT_ENABLE:
  468. xhci_disable_port(xhci, wIndex, addr, temp);
  469. break;
  470. default:
  471. goto error;
  472. }
  473. break;
  474. default:
  475. error:
  476. /* "stall" on error */
  477. retval = -EPIPE;
  478. }
  479. spin_unlock_irqrestore(&xhci->lock, flags);
  480. return retval;
  481. }
  482. /*
  483. * Returns 0 if the status hasn't changed, or the number of bytes in buf.
  484. * Ports are 0-indexed from the HCD point of view,
  485. * and 1-indexed from the USB core pointer of view.
  486. *
  487. * Note that the status change bits will be cleared as soon as a port status
  488. * change event is generated, so we use the saved status from that event.
  489. */
  490. int xhci_hub_status_data(struct usb_hcd *hcd, char *buf)
  491. {
  492. unsigned long flags;
  493. u32 temp, status;
  494. u32 mask;
  495. int i, retval;
  496. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  497. int ports;
  498. u32 __iomem *addr;
  499. ports = HCS_MAX_PORTS(xhci->hcs_params1);
  500. /* Initial status is no changes */
  501. retval = (ports + 8) / 8;
  502. memset(buf, 0, retval);
  503. status = 0;
  504. mask = PORT_CSC | PORT_PEC | PORT_OCC;
  505. spin_lock_irqsave(&xhci->lock, flags);
  506. /* For each port, did anything change? If so, set that bit in buf. */
  507. for (i = 0; i < ports; i++) {
  508. addr = &xhci->op_regs->port_status_base +
  509. NUM_PORT_REGS*i;
  510. temp = xhci_readl(xhci, addr);
  511. if ((temp & mask) != 0 ||
  512. (xhci->port_c_suspend[i >> 5] & 1 << (i & 31)) ||
  513. (xhci->resume_done[i] && time_after_eq(
  514. jiffies, xhci->resume_done[i]))) {
  515. buf[(i + 1) / 8] |= 1 << (i + 1) % 8;
  516. status = 1;
  517. }
  518. }
  519. spin_unlock_irqrestore(&xhci->lock, flags);
  520. return status ? retval : 0;
  521. }
  522. #ifdef CONFIG_PM
  523. int xhci_bus_suspend(struct usb_hcd *hcd)
  524. {
  525. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  526. int port;
  527. unsigned long flags;
  528. xhci_dbg(xhci, "suspend root hub\n");
  529. spin_lock_irqsave(&xhci->lock, flags);
  530. if (hcd->self.root_hub->do_remote_wakeup) {
  531. port = HCS_MAX_PORTS(xhci->hcs_params1);
  532. while (port--) {
  533. if (xhci->resume_done[port] != 0) {
  534. spin_unlock_irqrestore(&xhci->lock, flags);
  535. xhci_dbg(xhci, "suspend failed because "
  536. "port %d is resuming\n",
  537. port + 1);
  538. return -EBUSY;
  539. }
  540. }
  541. }
  542. port = HCS_MAX_PORTS(xhci->hcs_params1);
  543. xhci->bus_suspended = 0;
  544. while (port--) {
  545. /* suspend the port if the port is not suspended */
  546. u32 __iomem *addr;
  547. u32 t1, t2;
  548. int slot_id;
  549. addr = &xhci->op_regs->port_status_base +
  550. NUM_PORT_REGS * (port & 0xff);
  551. t1 = xhci_readl(xhci, addr);
  552. t2 = xhci_port_state_to_neutral(t1);
  553. if ((t1 & PORT_PE) && !(t1 & PORT_PLS_MASK)) {
  554. xhci_dbg(xhci, "port %d not suspended\n", port);
  555. slot_id = xhci_find_slot_id_by_port(xhci, port + 1);
  556. if (slot_id) {
  557. spin_unlock_irqrestore(&xhci->lock, flags);
  558. xhci_stop_device(xhci, slot_id, 1);
  559. spin_lock_irqsave(&xhci->lock, flags);
  560. }
  561. t2 &= ~PORT_PLS_MASK;
  562. t2 |= PORT_LINK_STROBE | XDEV_U3;
  563. set_bit(port, &xhci->bus_suspended);
  564. }
  565. if (hcd->self.root_hub->do_remote_wakeup) {
  566. if (t1 & PORT_CONNECT) {
  567. t2 |= PORT_WKOC_E | PORT_WKDISC_E;
  568. t2 &= ~PORT_WKCONN_E;
  569. } else {
  570. t2 |= PORT_WKOC_E | PORT_WKCONN_E;
  571. t2 &= ~PORT_WKDISC_E;
  572. }
  573. } else
  574. t2 &= ~PORT_WAKE_BITS;
  575. t1 = xhci_port_state_to_neutral(t1);
  576. if (t1 != t2)
  577. xhci_writel(xhci, t2, addr);
  578. if (DEV_HIGHSPEED(t1)) {
  579. /* enable remote wake up for USB 2.0 */
  580. u32 __iomem *addr;
  581. u32 tmp;
  582. addr = &xhci->op_regs->port_power_base +
  583. NUM_PORT_REGS * (port & 0xff);
  584. tmp = xhci_readl(xhci, addr);
  585. tmp |= PORT_RWE;
  586. xhci_writel(xhci, tmp, addr);
  587. }
  588. }
  589. hcd->state = HC_STATE_SUSPENDED;
  590. xhci->next_statechange = jiffies + msecs_to_jiffies(10);
  591. spin_unlock_irqrestore(&xhci->lock, flags);
  592. return 0;
  593. }
  594. int xhci_bus_resume(struct usb_hcd *hcd)
  595. {
  596. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  597. int port;
  598. u32 temp;
  599. unsigned long flags;
  600. xhci_dbg(xhci, "resume root hub\n");
  601. if (time_before(jiffies, xhci->next_statechange))
  602. msleep(5);
  603. spin_lock_irqsave(&xhci->lock, flags);
  604. if (!HCD_HW_ACCESSIBLE(hcd)) {
  605. spin_unlock_irqrestore(&xhci->lock, flags);
  606. return -ESHUTDOWN;
  607. }
  608. /* delay the irqs */
  609. temp = xhci_readl(xhci, &xhci->op_regs->command);
  610. temp &= ~CMD_EIE;
  611. xhci_writel(xhci, temp, &xhci->op_regs->command);
  612. port = HCS_MAX_PORTS(xhci->hcs_params1);
  613. while (port--) {
  614. /* Check whether need resume ports. If needed
  615. resume port and disable remote wakeup */
  616. u32 __iomem *addr;
  617. u32 temp;
  618. int slot_id;
  619. addr = &xhci->op_regs->port_status_base +
  620. NUM_PORT_REGS * (port & 0xff);
  621. temp = xhci_readl(xhci, addr);
  622. if (DEV_SUPERSPEED(temp))
  623. temp &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS);
  624. else
  625. temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS);
  626. if (test_bit(port, &xhci->bus_suspended) &&
  627. (temp & PORT_PLS_MASK)) {
  628. if (DEV_SUPERSPEED(temp)) {
  629. temp = xhci_port_state_to_neutral(temp);
  630. temp &= ~PORT_PLS_MASK;
  631. temp |= PORT_LINK_STROBE | XDEV_U0;
  632. xhci_writel(xhci, temp, addr);
  633. } else {
  634. temp = xhci_port_state_to_neutral(temp);
  635. temp &= ~PORT_PLS_MASK;
  636. temp |= PORT_LINK_STROBE | XDEV_RESUME;
  637. xhci_writel(xhci, temp, addr);
  638. spin_unlock_irqrestore(&xhci->lock, flags);
  639. msleep(20);
  640. spin_lock_irqsave(&xhci->lock, flags);
  641. temp = xhci_readl(xhci, addr);
  642. temp = xhci_port_state_to_neutral(temp);
  643. temp &= ~PORT_PLS_MASK;
  644. temp |= PORT_LINK_STROBE | XDEV_U0;
  645. xhci_writel(xhci, temp, addr);
  646. }
  647. slot_id = xhci_find_slot_id_by_port(xhci, port + 1);
  648. if (slot_id)
  649. xhci_ring_device(xhci, slot_id);
  650. } else
  651. xhci_writel(xhci, temp, addr);
  652. if (DEV_HIGHSPEED(temp)) {
  653. /* disable remote wake up for USB 2.0 */
  654. u32 __iomem *addr;
  655. u32 tmp;
  656. addr = &xhci->op_regs->port_power_base +
  657. NUM_PORT_REGS * (port & 0xff);
  658. tmp = xhci_readl(xhci, addr);
  659. tmp &= ~PORT_RWE;
  660. xhci_writel(xhci, tmp, addr);
  661. }
  662. }
  663. (void) xhci_readl(xhci, &xhci->op_regs->command);
  664. xhci->next_statechange = jiffies + msecs_to_jiffies(5);
  665. hcd->state = HC_STATE_RUNNING;
  666. /* re-enable irqs */
  667. temp = xhci_readl(xhci, &xhci->op_regs->command);
  668. temp |= CMD_EIE;
  669. xhci_writel(xhci, temp, &xhci->op_regs->command);
  670. temp = xhci_readl(xhci, &xhci->op_regs->command);
  671. spin_unlock_irqrestore(&xhci->lock, flags);
  672. return 0;
  673. }
  674. #endif /* CONFIG_PM */