uhci-q.c 46 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498149915001501150215031504150515061507150815091510151115121513151415151516151715181519152015211522152315241525152615271528152915301531153215331534153515361537153815391540154115421543154415451546154715481549155015511552155315541555155615571558155915601561156215631564156515661567156815691570157115721573157415751576157715781579158015811582158315841585158615871588158915901591159215931594159515961597159815991600160116021603160416051606160716081609161016111612161316141615161616171618161916201621162216231624162516261627162816291630163116321633163416351636163716381639164016411642164316441645164616471648164916501651165216531654165516561657165816591660166116621663166416651666166716681669167016711672167316741675167616771678167916801681168216831684168516861687168816891690169116921693169416951696169716981699170017011702170317041705170617071708170917101711171217131714171517161717171817191720172117221723172417251726172717281729173017311732173317341735173617371738173917401741174217431744174517461747174817491750175117521753175417551756175717581759176017611762176317641765176617671768176917701771177217731774177517761777177817791780178117821783178417851786
  1. /*
  2. * Universal Host Controller Interface driver for USB.
  3. *
  4. * Maintainer: Alan Stern <stern@rowland.harvard.edu>
  5. *
  6. * (C) Copyright 1999 Linus Torvalds
  7. * (C) Copyright 1999-2002 Johannes Erdfelt, johannes@erdfelt.com
  8. * (C) Copyright 1999 Randy Dunlap
  9. * (C) Copyright 1999 Georg Acher, acher@in.tum.de
  10. * (C) Copyright 1999 Deti Fliegl, deti@fliegl.de
  11. * (C) Copyright 1999 Thomas Sailer, sailer@ife.ee.ethz.ch
  12. * (C) Copyright 1999 Roman Weissgaerber, weissg@vienna.at
  13. * (C) Copyright 2000 Yggdrasil Computing, Inc. (port of new PCI interface
  14. * support from usb-ohci.c by Adam Richter, adam@yggdrasil.com).
  15. * (C) Copyright 1999 Gregory P. Smith (from usb-ohci.c)
  16. * (C) Copyright 2004-2007 Alan Stern, stern@rowland.harvard.edu
  17. */
  18. /*
  19. * Technically, updating td->status here is a race, but it's not really a
  20. * problem. The worst that can happen is that we set the IOC bit again
  21. * generating a spurious interrupt. We could fix this by creating another
  22. * QH and leaving the IOC bit always set, but then we would have to play
  23. * games with the FSBR code to make sure we get the correct order in all
  24. * the cases. I don't think it's worth the effort
  25. */
  26. static void uhci_set_next_interrupt(struct uhci_hcd *uhci)
  27. {
  28. if (uhci->is_stopped)
  29. mod_timer(&uhci_to_hcd(uhci)->rh_timer, jiffies);
  30. uhci->term_td->status |= cpu_to_le32(TD_CTRL_IOC);
  31. }
  32. static inline void uhci_clear_next_interrupt(struct uhci_hcd *uhci)
  33. {
  34. uhci->term_td->status &= ~cpu_to_le32(TD_CTRL_IOC);
  35. }
  36. /*
  37. * Full-Speed Bandwidth Reclamation (FSBR).
  38. * We turn on FSBR whenever a queue that wants it is advancing,
  39. * and leave it on for a short time thereafter.
  40. */
  41. static void uhci_fsbr_on(struct uhci_hcd *uhci)
  42. {
  43. struct uhci_qh *lqh;
  44. /* The terminating skeleton QH always points back to the first
  45. * FSBR QH. Make the last async QH point to the terminating
  46. * skeleton QH. */
  47. uhci->fsbr_is_on = 1;
  48. lqh = list_entry(uhci->skel_async_qh->node.prev,
  49. struct uhci_qh, node);
  50. lqh->link = LINK_TO_QH(uhci->skel_term_qh);
  51. }
  52. static void uhci_fsbr_off(struct uhci_hcd *uhci)
  53. {
  54. struct uhci_qh *lqh;
  55. /* Remove the link from the last async QH to the terminating
  56. * skeleton QH. */
  57. uhci->fsbr_is_on = 0;
  58. lqh = list_entry(uhci->skel_async_qh->node.prev,
  59. struct uhci_qh, node);
  60. lqh->link = UHCI_PTR_TERM;
  61. }
  62. static void uhci_add_fsbr(struct uhci_hcd *uhci, struct urb *urb)
  63. {
  64. struct urb_priv *urbp = urb->hcpriv;
  65. if (!(urb->transfer_flags & URB_NO_FSBR))
  66. urbp->fsbr = 1;
  67. }
  68. static void uhci_urbp_wants_fsbr(struct uhci_hcd *uhci, struct urb_priv *urbp)
  69. {
  70. if (urbp->fsbr) {
  71. uhci->fsbr_is_wanted = 1;
  72. if (!uhci->fsbr_is_on)
  73. uhci_fsbr_on(uhci);
  74. else if (uhci->fsbr_expiring) {
  75. uhci->fsbr_expiring = 0;
  76. del_timer(&uhci->fsbr_timer);
  77. }
  78. }
  79. }
  80. static void uhci_fsbr_timeout(unsigned long _uhci)
  81. {
  82. struct uhci_hcd *uhci = (struct uhci_hcd *) _uhci;
  83. unsigned long flags;
  84. spin_lock_irqsave(&uhci->lock, flags);
  85. if (uhci->fsbr_expiring) {
  86. uhci->fsbr_expiring = 0;
  87. uhci_fsbr_off(uhci);
  88. }
  89. spin_unlock_irqrestore(&uhci->lock, flags);
  90. }
  91. static struct uhci_td *uhci_alloc_td(struct uhci_hcd *uhci)
  92. {
  93. dma_addr_t dma_handle;
  94. struct uhci_td *td;
  95. td = dma_pool_alloc(uhci->td_pool, GFP_ATOMIC, &dma_handle);
  96. if (!td)
  97. return NULL;
  98. td->dma_handle = dma_handle;
  99. td->frame = -1;
  100. INIT_LIST_HEAD(&td->list);
  101. INIT_LIST_HEAD(&td->fl_list);
  102. return td;
  103. }
  104. static void uhci_free_td(struct uhci_hcd *uhci, struct uhci_td *td)
  105. {
  106. if (!list_empty(&td->list))
  107. dev_WARN(uhci_dev(uhci), "td %p still in list!\n", td);
  108. if (!list_empty(&td->fl_list))
  109. dev_WARN(uhci_dev(uhci), "td %p still in fl_list!\n", td);
  110. dma_pool_free(uhci->td_pool, td, td->dma_handle);
  111. }
  112. static inline void uhci_fill_td(struct uhci_td *td, u32 status,
  113. u32 token, u32 buffer)
  114. {
  115. td->status = cpu_to_le32(status);
  116. td->token = cpu_to_le32(token);
  117. td->buffer = cpu_to_le32(buffer);
  118. }
  119. static void uhci_add_td_to_urbp(struct uhci_td *td, struct urb_priv *urbp)
  120. {
  121. list_add_tail(&td->list, &urbp->td_list);
  122. }
  123. static void uhci_remove_td_from_urbp(struct uhci_td *td)
  124. {
  125. list_del_init(&td->list);
  126. }
  127. /*
  128. * We insert Isochronous URBs directly into the frame list at the beginning
  129. */
  130. static inline void uhci_insert_td_in_frame_list(struct uhci_hcd *uhci,
  131. struct uhci_td *td, unsigned framenum)
  132. {
  133. framenum &= (UHCI_NUMFRAMES - 1);
  134. td->frame = framenum;
  135. /* Is there a TD already mapped there? */
  136. if (uhci->frame_cpu[framenum]) {
  137. struct uhci_td *ftd, *ltd;
  138. ftd = uhci->frame_cpu[framenum];
  139. ltd = list_entry(ftd->fl_list.prev, struct uhci_td, fl_list);
  140. list_add_tail(&td->fl_list, &ftd->fl_list);
  141. td->link = ltd->link;
  142. wmb();
  143. ltd->link = LINK_TO_TD(td);
  144. } else {
  145. td->link = uhci->frame[framenum];
  146. wmb();
  147. uhci->frame[framenum] = LINK_TO_TD(td);
  148. uhci->frame_cpu[framenum] = td;
  149. }
  150. }
  151. static inline void uhci_remove_td_from_frame_list(struct uhci_hcd *uhci,
  152. struct uhci_td *td)
  153. {
  154. /* If it's not inserted, don't remove it */
  155. if (td->frame == -1) {
  156. WARN_ON(!list_empty(&td->fl_list));
  157. return;
  158. }
  159. if (uhci->frame_cpu[td->frame] == td) {
  160. if (list_empty(&td->fl_list)) {
  161. uhci->frame[td->frame] = td->link;
  162. uhci->frame_cpu[td->frame] = NULL;
  163. } else {
  164. struct uhci_td *ntd;
  165. ntd = list_entry(td->fl_list.next, struct uhci_td, fl_list);
  166. uhci->frame[td->frame] = LINK_TO_TD(ntd);
  167. uhci->frame_cpu[td->frame] = ntd;
  168. }
  169. } else {
  170. struct uhci_td *ptd;
  171. ptd = list_entry(td->fl_list.prev, struct uhci_td, fl_list);
  172. ptd->link = td->link;
  173. }
  174. list_del_init(&td->fl_list);
  175. td->frame = -1;
  176. }
  177. static inline void uhci_remove_tds_from_frame(struct uhci_hcd *uhci,
  178. unsigned int framenum)
  179. {
  180. struct uhci_td *ftd, *ltd;
  181. framenum &= (UHCI_NUMFRAMES - 1);
  182. ftd = uhci->frame_cpu[framenum];
  183. if (ftd) {
  184. ltd = list_entry(ftd->fl_list.prev, struct uhci_td, fl_list);
  185. uhci->frame[framenum] = ltd->link;
  186. uhci->frame_cpu[framenum] = NULL;
  187. while (!list_empty(&ftd->fl_list))
  188. list_del_init(ftd->fl_list.prev);
  189. }
  190. }
  191. /*
  192. * Remove all the TDs for an Isochronous URB from the frame list
  193. */
  194. static void uhci_unlink_isochronous_tds(struct uhci_hcd *uhci, struct urb *urb)
  195. {
  196. struct urb_priv *urbp = (struct urb_priv *) urb->hcpriv;
  197. struct uhci_td *td;
  198. list_for_each_entry(td, &urbp->td_list, list)
  199. uhci_remove_td_from_frame_list(uhci, td);
  200. }
  201. static struct uhci_qh *uhci_alloc_qh(struct uhci_hcd *uhci,
  202. struct usb_device *udev, struct usb_host_endpoint *hep)
  203. {
  204. dma_addr_t dma_handle;
  205. struct uhci_qh *qh;
  206. qh = dma_pool_alloc(uhci->qh_pool, GFP_ATOMIC, &dma_handle);
  207. if (!qh)
  208. return NULL;
  209. memset(qh, 0, sizeof(*qh));
  210. qh->dma_handle = dma_handle;
  211. qh->element = UHCI_PTR_TERM;
  212. qh->link = UHCI_PTR_TERM;
  213. INIT_LIST_HEAD(&qh->queue);
  214. INIT_LIST_HEAD(&qh->node);
  215. if (udev) { /* Normal QH */
  216. qh->type = usb_endpoint_type(&hep->desc);
  217. if (qh->type != USB_ENDPOINT_XFER_ISOC) {
  218. qh->dummy_td = uhci_alloc_td(uhci);
  219. if (!qh->dummy_td) {
  220. dma_pool_free(uhci->qh_pool, qh, dma_handle);
  221. return NULL;
  222. }
  223. }
  224. qh->state = QH_STATE_IDLE;
  225. qh->hep = hep;
  226. qh->udev = udev;
  227. hep->hcpriv = qh;
  228. if (qh->type == USB_ENDPOINT_XFER_INT ||
  229. qh->type == USB_ENDPOINT_XFER_ISOC)
  230. qh->load = usb_calc_bus_time(udev->speed,
  231. usb_endpoint_dir_in(&hep->desc),
  232. qh->type == USB_ENDPOINT_XFER_ISOC,
  233. le16_to_cpu(hep->desc.wMaxPacketSize))
  234. / 1000 + 1;
  235. } else { /* Skeleton QH */
  236. qh->state = QH_STATE_ACTIVE;
  237. qh->type = -1;
  238. }
  239. return qh;
  240. }
  241. static void uhci_free_qh(struct uhci_hcd *uhci, struct uhci_qh *qh)
  242. {
  243. WARN_ON(qh->state != QH_STATE_IDLE && qh->udev);
  244. if (!list_empty(&qh->queue))
  245. dev_WARN(uhci_dev(uhci), "qh %p list not empty!\n", qh);
  246. list_del(&qh->node);
  247. if (qh->udev) {
  248. qh->hep->hcpriv = NULL;
  249. if (qh->dummy_td)
  250. uhci_free_td(uhci, qh->dummy_td);
  251. }
  252. dma_pool_free(uhci->qh_pool, qh, qh->dma_handle);
  253. }
  254. /*
  255. * When a queue is stopped and a dequeued URB is given back, adjust
  256. * the previous TD link (if the URB isn't first on the queue) or
  257. * save its toggle value (if it is first and is currently executing).
  258. *
  259. * Returns 0 if the URB should not yet be given back, 1 otherwise.
  260. */
  261. static int uhci_cleanup_queue(struct uhci_hcd *uhci, struct uhci_qh *qh,
  262. struct urb *urb)
  263. {
  264. struct urb_priv *urbp = urb->hcpriv;
  265. struct uhci_td *td;
  266. int ret = 1;
  267. /* Isochronous pipes don't use toggles and their TD link pointers
  268. * get adjusted during uhci_urb_dequeue(). But since their queues
  269. * cannot truly be stopped, we have to watch out for dequeues
  270. * occurring after the nominal unlink frame. */
  271. if (qh->type == USB_ENDPOINT_XFER_ISOC) {
  272. ret = (uhci->frame_number + uhci->is_stopped !=
  273. qh->unlink_frame);
  274. goto done;
  275. }
  276. /* If the URB isn't first on its queue, adjust the link pointer
  277. * of the last TD in the previous URB. The toggle doesn't need
  278. * to be saved since this URB can't be executing yet. */
  279. if (qh->queue.next != &urbp->node) {
  280. struct urb_priv *purbp;
  281. struct uhci_td *ptd;
  282. purbp = list_entry(urbp->node.prev, struct urb_priv, node);
  283. WARN_ON(list_empty(&purbp->td_list));
  284. ptd = list_entry(purbp->td_list.prev, struct uhci_td,
  285. list);
  286. td = list_entry(urbp->td_list.prev, struct uhci_td,
  287. list);
  288. ptd->link = td->link;
  289. goto done;
  290. }
  291. /* If the QH element pointer is UHCI_PTR_TERM then then currently
  292. * executing URB has already been unlinked, so this one isn't it. */
  293. if (qh_element(qh) == UHCI_PTR_TERM)
  294. goto done;
  295. qh->element = UHCI_PTR_TERM;
  296. /* Control pipes don't have to worry about toggles */
  297. if (qh->type == USB_ENDPOINT_XFER_CONTROL)
  298. goto done;
  299. /* Save the next toggle value */
  300. WARN_ON(list_empty(&urbp->td_list));
  301. td = list_entry(urbp->td_list.next, struct uhci_td, list);
  302. qh->needs_fixup = 1;
  303. qh->initial_toggle = uhci_toggle(td_token(td));
  304. done:
  305. return ret;
  306. }
  307. /*
  308. * Fix up the data toggles for URBs in a queue, when one of them
  309. * terminates early (short transfer, error, or dequeued).
  310. */
  311. static void uhci_fixup_toggles(struct uhci_qh *qh, int skip_first)
  312. {
  313. struct urb_priv *urbp = NULL;
  314. struct uhci_td *td;
  315. unsigned int toggle = qh->initial_toggle;
  316. unsigned int pipe;
  317. /* Fixups for a short transfer start with the second URB in the
  318. * queue (the short URB is the first). */
  319. if (skip_first)
  320. urbp = list_entry(qh->queue.next, struct urb_priv, node);
  321. /* When starting with the first URB, if the QH element pointer is
  322. * still valid then we know the URB's toggles are okay. */
  323. else if (qh_element(qh) != UHCI_PTR_TERM)
  324. toggle = 2;
  325. /* Fix up the toggle for the URBs in the queue. Normally this
  326. * loop won't run more than once: When an error or short transfer
  327. * occurs, the queue usually gets emptied. */
  328. urbp = list_prepare_entry(urbp, &qh->queue, node);
  329. list_for_each_entry_continue(urbp, &qh->queue, node) {
  330. /* If the first TD has the right toggle value, we don't
  331. * need to change any toggles in this URB */
  332. td = list_entry(urbp->td_list.next, struct uhci_td, list);
  333. if (toggle > 1 || uhci_toggle(td_token(td)) == toggle) {
  334. td = list_entry(urbp->td_list.prev, struct uhci_td,
  335. list);
  336. toggle = uhci_toggle(td_token(td)) ^ 1;
  337. /* Otherwise all the toggles in the URB have to be switched */
  338. } else {
  339. list_for_each_entry(td, &urbp->td_list, list) {
  340. td->token ^= cpu_to_le32(
  341. TD_TOKEN_TOGGLE);
  342. toggle ^= 1;
  343. }
  344. }
  345. }
  346. wmb();
  347. pipe = list_entry(qh->queue.next, struct urb_priv, node)->urb->pipe;
  348. usb_settoggle(qh->udev, usb_pipeendpoint(pipe),
  349. usb_pipeout(pipe), toggle);
  350. qh->needs_fixup = 0;
  351. }
  352. /*
  353. * Link an Isochronous QH into its skeleton's list
  354. */
  355. static inline void link_iso(struct uhci_hcd *uhci, struct uhci_qh *qh)
  356. {
  357. list_add_tail(&qh->node, &uhci->skel_iso_qh->node);
  358. /* Isochronous QHs aren't linked by the hardware */
  359. }
  360. /*
  361. * Link a high-period interrupt QH into the schedule at the end of its
  362. * skeleton's list
  363. */
  364. static void link_interrupt(struct uhci_hcd *uhci, struct uhci_qh *qh)
  365. {
  366. struct uhci_qh *pqh;
  367. list_add_tail(&qh->node, &uhci->skelqh[qh->skel]->node);
  368. pqh = list_entry(qh->node.prev, struct uhci_qh, node);
  369. qh->link = pqh->link;
  370. wmb();
  371. pqh->link = LINK_TO_QH(qh);
  372. }
  373. /*
  374. * Link a period-1 interrupt or async QH into the schedule at the
  375. * correct spot in the async skeleton's list, and update the FSBR link
  376. */
  377. static void link_async(struct uhci_hcd *uhci, struct uhci_qh *qh)
  378. {
  379. struct uhci_qh *pqh;
  380. __le32 link_to_new_qh;
  381. /* Find the predecessor QH for our new one and insert it in the list.
  382. * The list of QHs is expected to be short, so linear search won't
  383. * take too long. */
  384. list_for_each_entry_reverse(pqh, &uhci->skel_async_qh->node, node) {
  385. if (pqh->skel <= qh->skel)
  386. break;
  387. }
  388. list_add(&qh->node, &pqh->node);
  389. /* Link it into the schedule */
  390. qh->link = pqh->link;
  391. wmb();
  392. link_to_new_qh = LINK_TO_QH(qh);
  393. pqh->link = link_to_new_qh;
  394. /* If this is now the first FSBR QH, link the terminating skeleton
  395. * QH to it. */
  396. if (pqh->skel < SKEL_FSBR && qh->skel >= SKEL_FSBR)
  397. uhci->skel_term_qh->link = link_to_new_qh;
  398. }
  399. /*
  400. * Put a QH on the schedule in both hardware and software
  401. */
  402. static void uhci_activate_qh(struct uhci_hcd *uhci, struct uhci_qh *qh)
  403. {
  404. WARN_ON(list_empty(&qh->queue));
  405. /* Set the element pointer if it isn't set already.
  406. * This isn't needed for Isochronous queues, but it doesn't hurt. */
  407. if (qh_element(qh) == UHCI_PTR_TERM) {
  408. struct urb_priv *urbp = list_entry(qh->queue.next,
  409. struct urb_priv, node);
  410. struct uhci_td *td = list_entry(urbp->td_list.next,
  411. struct uhci_td, list);
  412. qh->element = LINK_TO_TD(td);
  413. }
  414. /* Treat the queue as if it has just advanced */
  415. qh->wait_expired = 0;
  416. qh->advance_jiffies = jiffies;
  417. if (qh->state == QH_STATE_ACTIVE)
  418. return;
  419. qh->state = QH_STATE_ACTIVE;
  420. /* Move the QH from its old list to the correct spot in the appropriate
  421. * skeleton's list */
  422. if (qh == uhci->next_qh)
  423. uhci->next_qh = list_entry(qh->node.next, struct uhci_qh,
  424. node);
  425. list_del(&qh->node);
  426. if (qh->skel == SKEL_ISO)
  427. link_iso(uhci, qh);
  428. else if (qh->skel < SKEL_ASYNC)
  429. link_interrupt(uhci, qh);
  430. else
  431. link_async(uhci, qh);
  432. }
  433. /*
  434. * Unlink a high-period interrupt QH from the schedule
  435. */
  436. static void unlink_interrupt(struct uhci_hcd *uhci, struct uhci_qh *qh)
  437. {
  438. struct uhci_qh *pqh;
  439. pqh = list_entry(qh->node.prev, struct uhci_qh, node);
  440. pqh->link = qh->link;
  441. mb();
  442. }
  443. /*
  444. * Unlink a period-1 interrupt or async QH from the schedule
  445. */
  446. static void unlink_async(struct uhci_hcd *uhci, struct uhci_qh *qh)
  447. {
  448. struct uhci_qh *pqh;
  449. __le32 link_to_next_qh = qh->link;
  450. pqh = list_entry(qh->node.prev, struct uhci_qh, node);
  451. pqh->link = link_to_next_qh;
  452. /* If this was the old first FSBR QH, link the terminating skeleton
  453. * QH to the next (new first FSBR) QH. */
  454. if (pqh->skel < SKEL_FSBR && qh->skel >= SKEL_FSBR)
  455. uhci->skel_term_qh->link = link_to_next_qh;
  456. mb();
  457. }
  458. /*
  459. * Take a QH off the hardware schedule
  460. */
  461. static void uhci_unlink_qh(struct uhci_hcd *uhci, struct uhci_qh *qh)
  462. {
  463. if (qh->state == QH_STATE_UNLINKING)
  464. return;
  465. WARN_ON(qh->state != QH_STATE_ACTIVE || !qh->udev);
  466. qh->state = QH_STATE_UNLINKING;
  467. /* Unlink the QH from the schedule and record when we did it */
  468. if (qh->skel == SKEL_ISO)
  469. ;
  470. else if (qh->skel < SKEL_ASYNC)
  471. unlink_interrupt(uhci, qh);
  472. else
  473. unlink_async(uhci, qh);
  474. uhci_get_current_frame_number(uhci);
  475. qh->unlink_frame = uhci->frame_number;
  476. /* Force an interrupt so we know when the QH is fully unlinked */
  477. if (list_empty(&uhci->skel_unlink_qh->node) || uhci->is_stopped)
  478. uhci_set_next_interrupt(uhci);
  479. /* Move the QH from its old list to the end of the unlinking list */
  480. if (qh == uhci->next_qh)
  481. uhci->next_qh = list_entry(qh->node.next, struct uhci_qh,
  482. node);
  483. list_move_tail(&qh->node, &uhci->skel_unlink_qh->node);
  484. }
  485. /*
  486. * When we and the controller are through with a QH, it becomes IDLE.
  487. * This happens when a QH has been off the schedule (on the unlinking
  488. * list) for more than one frame, or when an error occurs while adding
  489. * the first URB onto a new QH.
  490. */
  491. static void uhci_make_qh_idle(struct uhci_hcd *uhci, struct uhci_qh *qh)
  492. {
  493. WARN_ON(qh->state == QH_STATE_ACTIVE);
  494. if (qh == uhci->next_qh)
  495. uhci->next_qh = list_entry(qh->node.next, struct uhci_qh,
  496. node);
  497. list_move(&qh->node, &uhci->idle_qh_list);
  498. qh->state = QH_STATE_IDLE;
  499. /* Now that the QH is idle, its post_td isn't being used */
  500. if (qh->post_td) {
  501. uhci_free_td(uhci, qh->post_td);
  502. qh->post_td = NULL;
  503. }
  504. /* If anyone is waiting for a QH to become idle, wake them up */
  505. if (uhci->num_waiting)
  506. wake_up_all(&uhci->waitqh);
  507. }
  508. /*
  509. * Find the highest existing bandwidth load for a given phase and period.
  510. */
  511. static int uhci_highest_load(struct uhci_hcd *uhci, int phase, int period)
  512. {
  513. int highest_load = uhci->load[phase];
  514. for (phase += period; phase < MAX_PHASE; phase += period)
  515. highest_load = max_t(int, highest_load, uhci->load[phase]);
  516. return highest_load;
  517. }
  518. /*
  519. * Set qh->phase to the optimal phase for a periodic transfer and
  520. * check whether the bandwidth requirement is acceptable.
  521. */
  522. static int uhci_check_bandwidth(struct uhci_hcd *uhci, struct uhci_qh *qh)
  523. {
  524. int minimax_load;
  525. /* Find the optimal phase (unless it is already set) and get
  526. * its load value. */
  527. if (qh->phase >= 0)
  528. minimax_load = uhci_highest_load(uhci, qh->phase, qh->period);
  529. else {
  530. int phase, load;
  531. int max_phase = min_t(int, MAX_PHASE, qh->period);
  532. qh->phase = 0;
  533. minimax_load = uhci_highest_load(uhci, qh->phase, qh->period);
  534. for (phase = 1; phase < max_phase; ++phase) {
  535. load = uhci_highest_load(uhci, phase, qh->period);
  536. if (load < minimax_load) {
  537. minimax_load = load;
  538. qh->phase = phase;
  539. }
  540. }
  541. }
  542. /* Maximum allowable periodic bandwidth is 90%, or 900 us per frame */
  543. if (minimax_load + qh->load > 900) {
  544. dev_dbg(uhci_dev(uhci), "bandwidth allocation failed: "
  545. "period %d, phase %d, %d + %d us\n",
  546. qh->period, qh->phase, minimax_load, qh->load);
  547. return -ENOSPC;
  548. }
  549. return 0;
  550. }
  551. /*
  552. * Reserve a periodic QH's bandwidth in the schedule
  553. */
  554. static void uhci_reserve_bandwidth(struct uhci_hcd *uhci, struct uhci_qh *qh)
  555. {
  556. int i;
  557. int load = qh->load;
  558. char *p = "??";
  559. for (i = qh->phase; i < MAX_PHASE; i += qh->period) {
  560. uhci->load[i] += load;
  561. uhci->total_load += load;
  562. }
  563. uhci_to_hcd(uhci)->self.bandwidth_allocated =
  564. uhci->total_load / MAX_PHASE;
  565. switch (qh->type) {
  566. case USB_ENDPOINT_XFER_INT:
  567. ++uhci_to_hcd(uhci)->self.bandwidth_int_reqs;
  568. p = "INT";
  569. break;
  570. case USB_ENDPOINT_XFER_ISOC:
  571. ++uhci_to_hcd(uhci)->self.bandwidth_isoc_reqs;
  572. p = "ISO";
  573. break;
  574. }
  575. qh->bandwidth_reserved = 1;
  576. dev_dbg(uhci_dev(uhci),
  577. "%s dev %d ep%02x-%s, period %d, phase %d, %d us\n",
  578. "reserve", qh->udev->devnum,
  579. qh->hep->desc.bEndpointAddress, p,
  580. qh->period, qh->phase, load);
  581. }
  582. /*
  583. * Release a periodic QH's bandwidth reservation
  584. */
  585. static void uhci_release_bandwidth(struct uhci_hcd *uhci, struct uhci_qh *qh)
  586. {
  587. int i;
  588. int load = qh->load;
  589. char *p = "??";
  590. for (i = qh->phase; i < MAX_PHASE; i += qh->period) {
  591. uhci->load[i] -= load;
  592. uhci->total_load -= load;
  593. }
  594. uhci_to_hcd(uhci)->self.bandwidth_allocated =
  595. uhci->total_load / MAX_PHASE;
  596. switch (qh->type) {
  597. case USB_ENDPOINT_XFER_INT:
  598. --uhci_to_hcd(uhci)->self.bandwidth_int_reqs;
  599. p = "INT";
  600. break;
  601. case USB_ENDPOINT_XFER_ISOC:
  602. --uhci_to_hcd(uhci)->self.bandwidth_isoc_reqs;
  603. p = "ISO";
  604. break;
  605. }
  606. qh->bandwidth_reserved = 0;
  607. dev_dbg(uhci_dev(uhci),
  608. "%s dev %d ep%02x-%s, period %d, phase %d, %d us\n",
  609. "release", qh->udev->devnum,
  610. qh->hep->desc.bEndpointAddress, p,
  611. qh->period, qh->phase, load);
  612. }
  613. static inline struct urb_priv *uhci_alloc_urb_priv(struct uhci_hcd *uhci,
  614. struct urb *urb)
  615. {
  616. struct urb_priv *urbp;
  617. urbp = kmem_cache_zalloc(uhci_up_cachep, GFP_ATOMIC);
  618. if (!urbp)
  619. return NULL;
  620. urbp->urb = urb;
  621. urb->hcpriv = urbp;
  622. INIT_LIST_HEAD(&urbp->node);
  623. INIT_LIST_HEAD(&urbp->td_list);
  624. return urbp;
  625. }
  626. static void uhci_free_urb_priv(struct uhci_hcd *uhci,
  627. struct urb_priv *urbp)
  628. {
  629. struct uhci_td *td, *tmp;
  630. if (!list_empty(&urbp->node))
  631. dev_WARN(uhci_dev(uhci), "urb %p still on QH's list!\n",
  632. urbp->urb);
  633. list_for_each_entry_safe(td, tmp, &urbp->td_list, list) {
  634. uhci_remove_td_from_urbp(td);
  635. uhci_free_td(uhci, td);
  636. }
  637. kmem_cache_free(uhci_up_cachep, urbp);
  638. }
  639. /*
  640. * Map status to standard result codes
  641. *
  642. * <status> is (td_status(td) & 0xF60000), a.k.a.
  643. * uhci_status_bits(td_status(td)).
  644. * Note: <status> does not include the TD_CTRL_NAK bit.
  645. * <dir_out> is True for output TDs and False for input TDs.
  646. */
  647. static int uhci_map_status(int status, int dir_out)
  648. {
  649. if (!status)
  650. return 0;
  651. if (status & TD_CTRL_BITSTUFF) /* Bitstuff error */
  652. return -EPROTO;
  653. if (status & TD_CTRL_CRCTIMEO) { /* CRC/Timeout */
  654. if (dir_out)
  655. return -EPROTO;
  656. else
  657. return -EILSEQ;
  658. }
  659. if (status & TD_CTRL_BABBLE) /* Babble */
  660. return -EOVERFLOW;
  661. if (status & TD_CTRL_DBUFERR) /* Buffer error */
  662. return -ENOSR;
  663. if (status & TD_CTRL_STALLED) /* Stalled */
  664. return -EPIPE;
  665. return 0;
  666. }
  667. /*
  668. * Control transfers
  669. */
  670. static int uhci_submit_control(struct uhci_hcd *uhci, struct urb *urb,
  671. struct uhci_qh *qh)
  672. {
  673. struct uhci_td *td;
  674. unsigned long destination, status;
  675. int maxsze = le16_to_cpu(qh->hep->desc.wMaxPacketSize);
  676. int len = urb->transfer_buffer_length;
  677. dma_addr_t data = urb->transfer_dma;
  678. __le32 *plink;
  679. struct urb_priv *urbp = urb->hcpriv;
  680. int skel;
  681. /* The "pipe" thing contains the destination in bits 8--18 */
  682. destination = (urb->pipe & PIPE_DEVEP_MASK) | USB_PID_SETUP;
  683. /* 3 errors, dummy TD remains inactive */
  684. status = uhci_maxerr(3);
  685. if (urb->dev->speed == USB_SPEED_LOW)
  686. status |= TD_CTRL_LS;
  687. /*
  688. * Build the TD for the control request setup packet
  689. */
  690. td = qh->dummy_td;
  691. uhci_add_td_to_urbp(td, urbp);
  692. uhci_fill_td(td, status, destination | uhci_explen(8),
  693. urb->setup_dma);
  694. plink = &td->link;
  695. status |= TD_CTRL_ACTIVE;
  696. /*
  697. * If direction is "send", change the packet ID from SETUP (0x2D)
  698. * to OUT (0xE1). Else change it from SETUP to IN (0x69) and
  699. * set Short Packet Detect (SPD) for all data packets.
  700. *
  701. * 0-length transfers always get treated as "send".
  702. */
  703. if (usb_pipeout(urb->pipe) || len == 0)
  704. destination ^= (USB_PID_SETUP ^ USB_PID_OUT);
  705. else {
  706. destination ^= (USB_PID_SETUP ^ USB_PID_IN);
  707. status |= TD_CTRL_SPD;
  708. }
  709. /*
  710. * Build the DATA TDs
  711. */
  712. while (len > 0) {
  713. int pktsze = maxsze;
  714. if (len <= pktsze) { /* The last data packet */
  715. pktsze = len;
  716. status &= ~TD_CTRL_SPD;
  717. }
  718. td = uhci_alloc_td(uhci);
  719. if (!td)
  720. goto nomem;
  721. *plink = LINK_TO_TD(td);
  722. /* Alternate Data0/1 (start with Data1) */
  723. destination ^= TD_TOKEN_TOGGLE;
  724. uhci_add_td_to_urbp(td, urbp);
  725. uhci_fill_td(td, status, destination | uhci_explen(pktsze),
  726. data);
  727. plink = &td->link;
  728. data += pktsze;
  729. len -= pktsze;
  730. }
  731. /*
  732. * Build the final TD for control status
  733. */
  734. td = uhci_alloc_td(uhci);
  735. if (!td)
  736. goto nomem;
  737. *plink = LINK_TO_TD(td);
  738. /* Change direction for the status transaction */
  739. destination ^= (USB_PID_IN ^ USB_PID_OUT);
  740. destination |= TD_TOKEN_TOGGLE; /* End in Data1 */
  741. uhci_add_td_to_urbp(td, urbp);
  742. uhci_fill_td(td, status | TD_CTRL_IOC,
  743. destination | uhci_explen(0), 0);
  744. plink = &td->link;
  745. /*
  746. * Build the new dummy TD and activate the old one
  747. */
  748. td = uhci_alloc_td(uhci);
  749. if (!td)
  750. goto nomem;
  751. *plink = LINK_TO_TD(td);
  752. uhci_fill_td(td, 0, USB_PID_OUT | uhci_explen(0), 0);
  753. wmb();
  754. qh->dummy_td->status |= cpu_to_le32(TD_CTRL_ACTIVE);
  755. qh->dummy_td = td;
  756. /* Low-speed transfers get a different queue, and won't hog the bus.
  757. * Also, some devices enumerate better without FSBR; the easiest way
  758. * to do that is to put URBs on the low-speed queue while the device
  759. * isn't in the CONFIGURED state. */
  760. if (urb->dev->speed == USB_SPEED_LOW ||
  761. urb->dev->state != USB_STATE_CONFIGURED)
  762. skel = SKEL_LS_CONTROL;
  763. else {
  764. skel = SKEL_FS_CONTROL;
  765. uhci_add_fsbr(uhci, urb);
  766. }
  767. if (qh->state != QH_STATE_ACTIVE)
  768. qh->skel = skel;
  769. return 0;
  770. nomem:
  771. /* Remove the dummy TD from the td_list so it doesn't get freed */
  772. uhci_remove_td_from_urbp(qh->dummy_td);
  773. return -ENOMEM;
  774. }
  775. /*
  776. * Common submit for bulk and interrupt
  777. */
  778. static int uhci_submit_common(struct uhci_hcd *uhci, struct urb *urb,
  779. struct uhci_qh *qh)
  780. {
  781. struct uhci_td *td;
  782. unsigned long destination, status;
  783. int maxsze = le16_to_cpu(qh->hep->desc.wMaxPacketSize);
  784. int len = urb->transfer_buffer_length;
  785. int this_sg_len;
  786. dma_addr_t data;
  787. __le32 *plink;
  788. struct urb_priv *urbp = urb->hcpriv;
  789. unsigned int toggle;
  790. struct scatterlist *sg;
  791. int i;
  792. if (len < 0)
  793. return -EINVAL;
  794. /* The "pipe" thing contains the destination in bits 8--18 */
  795. destination = (urb->pipe & PIPE_DEVEP_MASK) | usb_packetid(urb->pipe);
  796. toggle = usb_gettoggle(urb->dev, usb_pipeendpoint(urb->pipe),
  797. usb_pipeout(urb->pipe));
  798. /* 3 errors, dummy TD remains inactive */
  799. status = uhci_maxerr(3);
  800. if (urb->dev->speed == USB_SPEED_LOW)
  801. status |= TD_CTRL_LS;
  802. if (usb_pipein(urb->pipe))
  803. status |= TD_CTRL_SPD;
  804. i = urb->num_sgs;
  805. if (len > 0 && i > 0) {
  806. sg = urb->sg;
  807. data = sg_dma_address(sg);
  808. /* urb->transfer_buffer_length may be smaller than the
  809. * size of the scatterlist (or vice versa)
  810. */
  811. this_sg_len = min_t(int, sg_dma_len(sg), len);
  812. } else {
  813. sg = NULL;
  814. data = urb->transfer_dma;
  815. this_sg_len = len;
  816. }
  817. /*
  818. * Build the DATA TDs
  819. */
  820. plink = NULL;
  821. td = qh->dummy_td;
  822. for (;;) { /* Allow zero length packets */
  823. int pktsze = maxsze;
  824. if (len <= pktsze) { /* The last packet */
  825. pktsze = len;
  826. if (!(urb->transfer_flags & URB_SHORT_NOT_OK))
  827. status &= ~TD_CTRL_SPD;
  828. }
  829. if (plink) {
  830. td = uhci_alloc_td(uhci);
  831. if (!td)
  832. goto nomem;
  833. *plink = LINK_TO_TD(td);
  834. }
  835. uhci_add_td_to_urbp(td, urbp);
  836. uhci_fill_td(td, status,
  837. destination | uhci_explen(pktsze) |
  838. (toggle << TD_TOKEN_TOGGLE_SHIFT),
  839. data);
  840. plink = &td->link;
  841. status |= TD_CTRL_ACTIVE;
  842. toggle ^= 1;
  843. data += pktsze;
  844. this_sg_len -= pktsze;
  845. len -= maxsze;
  846. if (this_sg_len <= 0) {
  847. if (--i <= 0 || len <= 0)
  848. break;
  849. sg = sg_next(sg);
  850. data = sg_dma_address(sg);
  851. this_sg_len = min_t(int, sg_dma_len(sg), len);
  852. }
  853. }
  854. /*
  855. * URB_ZERO_PACKET means adding a 0-length packet, if direction
  856. * is OUT and the transfer_length was an exact multiple of maxsze,
  857. * hence (len = transfer_length - N * maxsze) == 0
  858. * however, if transfer_length == 0, the zero packet was already
  859. * prepared above.
  860. */
  861. if ((urb->transfer_flags & URB_ZERO_PACKET) &&
  862. usb_pipeout(urb->pipe) && len == 0 &&
  863. urb->transfer_buffer_length > 0) {
  864. td = uhci_alloc_td(uhci);
  865. if (!td)
  866. goto nomem;
  867. *plink = LINK_TO_TD(td);
  868. uhci_add_td_to_urbp(td, urbp);
  869. uhci_fill_td(td, status,
  870. destination | uhci_explen(0) |
  871. (toggle << TD_TOKEN_TOGGLE_SHIFT),
  872. data);
  873. plink = &td->link;
  874. toggle ^= 1;
  875. }
  876. /* Set the interrupt-on-completion flag on the last packet.
  877. * A more-or-less typical 4 KB URB (= size of one memory page)
  878. * will require about 3 ms to transfer; that's a little on the
  879. * fast side but not enough to justify delaying an interrupt
  880. * more than 2 or 3 URBs, so we will ignore the URB_NO_INTERRUPT
  881. * flag setting. */
  882. td->status |= cpu_to_le32(TD_CTRL_IOC);
  883. /*
  884. * Build the new dummy TD and activate the old one
  885. */
  886. td = uhci_alloc_td(uhci);
  887. if (!td)
  888. goto nomem;
  889. *plink = LINK_TO_TD(td);
  890. uhci_fill_td(td, 0, USB_PID_OUT | uhci_explen(0), 0);
  891. wmb();
  892. qh->dummy_td->status |= cpu_to_le32(TD_CTRL_ACTIVE);
  893. qh->dummy_td = td;
  894. usb_settoggle(urb->dev, usb_pipeendpoint(urb->pipe),
  895. usb_pipeout(urb->pipe), toggle);
  896. return 0;
  897. nomem:
  898. /* Remove the dummy TD from the td_list so it doesn't get freed */
  899. uhci_remove_td_from_urbp(qh->dummy_td);
  900. return -ENOMEM;
  901. }
  902. static int uhci_submit_bulk(struct uhci_hcd *uhci, struct urb *urb,
  903. struct uhci_qh *qh)
  904. {
  905. int ret;
  906. /* Can't have low-speed bulk transfers */
  907. if (urb->dev->speed == USB_SPEED_LOW)
  908. return -EINVAL;
  909. if (qh->state != QH_STATE_ACTIVE)
  910. qh->skel = SKEL_BULK;
  911. ret = uhci_submit_common(uhci, urb, qh);
  912. if (ret == 0)
  913. uhci_add_fsbr(uhci, urb);
  914. return ret;
  915. }
  916. static int uhci_submit_interrupt(struct uhci_hcd *uhci, struct urb *urb,
  917. struct uhci_qh *qh)
  918. {
  919. int ret;
  920. /* USB 1.1 interrupt transfers only involve one packet per interval.
  921. * Drivers can submit URBs of any length, but longer ones will need
  922. * multiple intervals to complete.
  923. */
  924. if (!qh->bandwidth_reserved) {
  925. int exponent;
  926. /* Figure out which power-of-two queue to use */
  927. for (exponent = 7; exponent >= 0; --exponent) {
  928. if ((1 << exponent) <= urb->interval)
  929. break;
  930. }
  931. if (exponent < 0)
  932. return -EINVAL;
  933. /* If the slot is full, try a lower period */
  934. do {
  935. qh->period = 1 << exponent;
  936. qh->skel = SKEL_INDEX(exponent);
  937. /* For now, interrupt phase is fixed by the layout
  938. * of the QH lists.
  939. */
  940. qh->phase = (qh->period / 2) & (MAX_PHASE - 1);
  941. ret = uhci_check_bandwidth(uhci, qh);
  942. } while (ret != 0 && --exponent >= 0);
  943. if (ret)
  944. return ret;
  945. } else if (qh->period > urb->interval)
  946. return -EINVAL; /* Can't decrease the period */
  947. ret = uhci_submit_common(uhci, urb, qh);
  948. if (ret == 0) {
  949. urb->interval = qh->period;
  950. if (!qh->bandwidth_reserved)
  951. uhci_reserve_bandwidth(uhci, qh);
  952. }
  953. return ret;
  954. }
  955. /*
  956. * Fix up the data structures following a short transfer
  957. */
  958. static int uhci_fixup_short_transfer(struct uhci_hcd *uhci,
  959. struct uhci_qh *qh, struct urb_priv *urbp)
  960. {
  961. struct uhci_td *td;
  962. struct list_head *tmp;
  963. int ret;
  964. td = list_entry(urbp->td_list.prev, struct uhci_td, list);
  965. if (qh->type == USB_ENDPOINT_XFER_CONTROL) {
  966. /* When a control transfer is short, we have to restart
  967. * the queue at the status stage transaction, which is
  968. * the last TD. */
  969. WARN_ON(list_empty(&urbp->td_list));
  970. qh->element = LINK_TO_TD(td);
  971. tmp = td->list.prev;
  972. ret = -EINPROGRESS;
  973. } else {
  974. /* When a bulk/interrupt transfer is short, we have to
  975. * fix up the toggles of the following URBs on the queue
  976. * before restarting the queue at the next URB. */
  977. qh->initial_toggle = uhci_toggle(td_token(qh->post_td)) ^ 1;
  978. uhci_fixup_toggles(qh, 1);
  979. if (list_empty(&urbp->td_list))
  980. td = qh->post_td;
  981. qh->element = td->link;
  982. tmp = urbp->td_list.prev;
  983. ret = 0;
  984. }
  985. /* Remove all the TDs we skipped over, from tmp back to the start */
  986. while (tmp != &urbp->td_list) {
  987. td = list_entry(tmp, struct uhci_td, list);
  988. tmp = tmp->prev;
  989. uhci_remove_td_from_urbp(td);
  990. uhci_free_td(uhci, td);
  991. }
  992. return ret;
  993. }
  994. /*
  995. * Common result for control, bulk, and interrupt
  996. */
  997. static int uhci_result_common(struct uhci_hcd *uhci, struct urb *urb)
  998. {
  999. struct urb_priv *urbp = urb->hcpriv;
  1000. struct uhci_qh *qh = urbp->qh;
  1001. struct uhci_td *td, *tmp;
  1002. unsigned status;
  1003. int ret = 0;
  1004. list_for_each_entry_safe(td, tmp, &urbp->td_list, list) {
  1005. unsigned int ctrlstat;
  1006. int len;
  1007. ctrlstat = td_status(td);
  1008. status = uhci_status_bits(ctrlstat);
  1009. if (status & TD_CTRL_ACTIVE)
  1010. return -EINPROGRESS;
  1011. len = uhci_actual_length(ctrlstat);
  1012. urb->actual_length += len;
  1013. if (status) {
  1014. ret = uhci_map_status(status,
  1015. uhci_packetout(td_token(td)));
  1016. if ((debug == 1 && ret != -EPIPE) || debug > 1) {
  1017. /* Some debugging code */
  1018. dev_dbg(&urb->dev->dev,
  1019. "%s: failed with status %x\n",
  1020. __func__, status);
  1021. if (debug > 1 && errbuf) {
  1022. /* Print the chain for debugging */
  1023. uhci_show_qh(uhci, urbp->qh, errbuf,
  1024. ERRBUF_LEN, 0);
  1025. lprintk(errbuf);
  1026. }
  1027. }
  1028. /* Did we receive a short packet? */
  1029. } else if (len < uhci_expected_length(td_token(td))) {
  1030. /* For control transfers, go to the status TD if
  1031. * this isn't already the last data TD */
  1032. if (qh->type == USB_ENDPOINT_XFER_CONTROL) {
  1033. if (td->list.next != urbp->td_list.prev)
  1034. ret = 1;
  1035. }
  1036. /* For bulk and interrupt, this may be an error */
  1037. else if (urb->transfer_flags & URB_SHORT_NOT_OK)
  1038. ret = -EREMOTEIO;
  1039. /* Fixup needed only if this isn't the URB's last TD */
  1040. else if (&td->list != urbp->td_list.prev)
  1041. ret = 1;
  1042. }
  1043. uhci_remove_td_from_urbp(td);
  1044. if (qh->post_td)
  1045. uhci_free_td(uhci, qh->post_td);
  1046. qh->post_td = td;
  1047. if (ret != 0)
  1048. goto err;
  1049. }
  1050. return ret;
  1051. err:
  1052. if (ret < 0) {
  1053. /* Note that the queue has stopped and save
  1054. * the next toggle value */
  1055. qh->element = UHCI_PTR_TERM;
  1056. qh->is_stopped = 1;
  1057. qh->needs_fixup = (qh->type != USB_ENDPOINT_XFER_CONTROL);
  1058. qh->initial_toggle = uhci_toggle(td_token(td)) ^
  1059. (ret == -EREMOTEIO);
  1060. } else /* Short packet received */
  1061. ret = uhci_fixup_short_transfer(uhci, qh, urbp);
  1062. return ret;
  1063. }
  1064. /*
  1065. * Isochronous transfers
  1066. */
  1067. static int uhci_submit_isochronous(struct uhci_hcd *uhci, struct urb *urb,
  1068. struct uhci_qh *qh)
  1069. {
  1070. struct uhci_td *td = NULL; /* Since urb->number_of_packets > 0 */
  1071. int i, frame;
  1072. unsigned long destination, status;
  1073. struct urb_priv *urbp = (struct urb_priv *) urb->hcpriv;
  1074. /* Values must not be too big (could overflow below) */
  1075. if (urb->interval >= UHCI_NUMFRAMES ||
  1076. urb->number_of_packets >= UHCI_NUMFRAMES)
  1077. return -EFBIG;
  1078. /* Check the period and figure out the starting frame number */
  1079. if (!qh->bandwidth_reserved) {
  1080. qh->period = urb->interval;
  1081. if (urb->transfer_flags & URB_ISO_ASAP) {
  1082. qh->phase = -1; /* Find the best phase */
  1083. i = uhci_check_bandwidth(uhci, qh);
  1084. if (i)
  1085. return i;
  1086. /* Allow a little time to allocate the TDs */
  1087. uhci_get_current_frame_number(uhci);
  1088. frame = uhci->frame_number + 10;
  1089. /* Move forward to the first frame having the
  1090. * correct phase */
  1091. urb->start_frame = frame + ((qh->phase - frame) &
  1092. (qh->period - 1));
  1093. } else {
  1094. i = urb->start_frame - uhci->last_iso_frame;
  1095. if (i <= 0 || i >= UHCI_NUMFRAMES)
  1096. return -EINVAL;
  1097. qh->phase = urb->start_frame & (qh->period - 1);
  1098. i = uhci_check_bandwidth(uhci, qh);
  1099. if (i)
  1100. return i;
  1101. }
  1102. } else if (qh->period != urb->interval) {
  1103. return -EINVAL; /* Can't change the period */
  1104. } else {
  1105. /* Find the next unused frame */
  1106. if (list_empty(&qh->queue)) {
  1107. frame = qh->iso_frame;
  1108. } else {
  1109. struct urb *lurb;
  1110. lurb = list_entry(qh->queue.prev,
  1111. struct urb_priv, node)->urb;
  1112. frame = lurb->start_frame +
  1113. lurb->number_of_packets *
  1114. lurb->interval;
  1115. }
  1116. if (urb->transfer_flags & URB_ISO_ASAP) {
  1117. /* Skip some frames if necessary to insure
  1118. * the start frame is in the future.
  1119. */
  1120. uhci_get_current_frame_number(uhci);
  1121. if (uhci_frame_before_eq(frame, uhci->frame_number)) {
  1122. frame = uhci->frame_number + 1;
  1123. frame += ((qh->phase - frame) &
  1124. (qh->period - 1));
  1125. }
  1126. } /* Otherwise pick up where the last URB leaves off */
  1127. urb->start_frame = frame;
  1128. }
  1129. /* Make sure we won't have to go too far into the future */
  1130. if (uhci_frame_before_eq(uhci->last_iso_frame + UHCI_NUMFRAMES,
  1131. urb->start_frame + urb->number_of_packets *
  1132. urb->interval))
  1133. return -EFBIG;
  1134. status = TD_CTRL_ACTIVE | TD_CTRL_IOS;
  1135. destination = (urb->pipe & PIPE_DEVEP_MASK) | usb_packetid(urb->pipe);
  1136. for (i = 0; i < urb->number_of_packets; i++) {
  1137. td = uhci_alloc_td(uhci);
  1138. if (!td)
  1139. return -ENOMEM;
  1140. uhci_add_td_to_urbp(td, urbp);
  1141. uhci_fill_td(td, status, destination |
  1142. uhci_explen(urb->iso_frame_desc[i].length),
  1143. urb->transfer_dma +
  1144. urb->iso_frame_desc[i].offset);
  1145. }
  1146. /* Set the interrupt-on-completion flag on the last packet. */
  1147. td->status |= cpu_to_le32(TD_CTRL_IOC);
  1148. /* Add the TDs to the frame list */
  1149. frame = urb->start_frame;
  1150. list_for_each_entry(td, &urbp->td_list, list) {
  1151. uhci_insert_td_in_frame_list(uhci, td, frame);
  1152. frame += qh->period;
  1153. }
  1154. if (list_empty(&qh->queue)) {
  1155. qh->iso_packet_desc = &urb->iso_frame_desc[0];
  1156. qh->iso_frame = urb->start_frame;
  1157. }
  1158. qh->skel = SKEL_ISO;
  1159. if (!qh->bandwidth_reserved)
  1160. uhci_reserve_bandwidth(uhci, qh);
  1161. return 0;
  1162. }
  1163. static int uhci_result_isochronous(struct uhci_hcd *uhci, struct urb *urb)
  1164. {
  1165. struct uhci_td *td, *tmp;
  1166. struct urb_priv *urbp = urb->hcpriv;
  1167. struct uhci_qh *qh = urbp->qh;
  1168. list_for_each_entry_safe(td, tmp, &urbp->td_list, list) {
  1169. unsigned int ctrlstat;
  1170. int status;
  1171. int actlength;
  1172. if (uhci_frame_before_eq(uhci->cur_iso_frame, qh->iso_frame))
  1173. return -EINPROGRESS;
  1174. uhci_remove_tds_from_frame(uhci, qh->iso_frame);
  1175. ctrlstat = td_status(td);
  1176. if (ctrlstat & TD_CTRL_ACTIVE) {
  1177. status = -EXDEV; /* TD was added too late? */
  1178. } else {
  1179. status = uhci_map_status(uhci_status_bits(ctrlstat),
  1180. usb_pipeout(urb->pipe));
  1181. actlength = uhci_actual_length(ctrlstat);
  1182. urb->actual_length += actlength;
  1183. qh->iso_packet_desc->actual_length = actlength;
  1184. qh->iso_packet_desc->status = status;
  1185. }
  1186. if (status)
  1187. urb->error_count++;
  1188. uhci_remove_td_from_urbp(td);
  1189. uhci_free_td(uhci, td);
  1190. qh->iso_frame += qh->period;
  1191. ++qh->iso_packet_desc;
  1192. }
  1193. return 0;
  1194. }
  1195. static int uhci_urb_enqueue(struct usb_hcd *hcd,
  1196. struct urb *urb, gfp_t mem_flags)
  1197. {
  1198. int ret;
  1199. struct uhci_hcd *uhci = hcd_to_uhci(hcd);
  1200. unsigned long flags;
  1201. struct urb_priv *urbp;
  1202. struct uhci_qh *qh;
  1203. spin_lock_irqsave(&uhci->lock, flags);
  1204. ret = usb_hcd_link_urb_to_ep(hcd, urb);
  1205. if (ret)
  1206. goto done_not_linked;
  1207. ret = -ENOMEM;
  1208. urbp = uhci_alloc_urb_priv(uhci, urb);
  1209. if (!urbp)
  1210. goto done;
  1211. if (urb->ep->hcpriv)
  1212. qh = urb->ep->hcpriv;
  1213. else {
  1214. qh = uhci_alloc_qh(uhci, urb->dev, urb->ep);
  1215. if (!qh)
  1216. goto err_no_qh;
  1217. }
  1218. urbp->qh = qh;
  1219. switch (qh->type) {
  1220. case USB_ENDPOINT_XFER_CONTROL:
  1221. ret = uhci_submit_control(uhci, urb, qh);
  1222. break;
  1223. case USB_ENDPOINT_XFER_BULK:
  1224. ret = uhci_submit_bulk(uhci, urb, qh);
  1225. break;
  1226. case USB_ENDPOINT_XFER_INT:
  1227. ret = uhci_submit_interrupt(uhci, urb, qh);
  1228. break;
  1229. case USB_ENDPOINT_XFER_ISOC:
  1230. urb->error_count = 0;
  1231. ret = uhci_submit_isochronous(uhci, urb, qh);
  1232. break;
  1233. }
  1234. if (ret != 0)
  1235. goto err_submit_failed;
  1236. /* Add this URB to the QH */
  1237. list_add_tail(&urbp->node, &qh->queue);
  1238. /* If the new URB is the first and only one on this QH then either
  1239. * the QH is new and idle or else it's unlinked and waiting to
  1240. * become idle, so we can activate it right away. But only if the
  1241. * queue isn't stopped. */
  1242. if (qh->queue.next == &urbp->node && !qh->is_stopped) {
  1243. uhci_activate_qh(uhci, qh);
  1244. uhci_urbp_wants_fsbr(uhci, urbp);
  1245. }
  1246. goto done;
  1247. err_submit_failed:
  1248. if (qh->state == QH_STATE_IDLE)
  1249. uhci_make_qh_idle(uhci, qh); /* Reclaim unused QH */
  1250. err_no_qh:
  1251. uhci_free_urb_priv(uhci, urbp);
  1252. done:
  1253. if (ret)
  1254. usb_hcd_unlink_urb_from_ep(hcd, urb);
  1255. done_not_linked:
  1256. spin_unlock_irqrestore(&uhci->lock, flags);
  1257. return ret;
  1258. }
  1259. static int uhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
  1260. {
  1261. struct uhci_hcd *uhci = hcd_to_uhci(hcd);
  1262. unsigned long flags;
  1263. struct uhci_qh *qh;
  1264. int rc;
  1265. spin_lock_irqsave(&uhci->lock, flags);
  1266. rc = usb_hcd_check_unlink_urb(hcd, urb, status);
  1267. if (rc)
  1268. goto done;
  1269. qh = ((struct urb_priv *) urb->hcpriv)->qh;
  1270. /* Remove Isochronous TDs from the frame list ASAP */
  1271. if (qh->type == USB_ENDPOINT_XFER_ISOC) {
  1272. uhci_unlink_isochronous_tds(uhci, urb);
  1273. mb();
  1274. /* If the URB has already started, update the QH unlink time */
  1275. uhci_get_current_frame_number(uhci);
  1276. if (uhci_frame_before_eq(urb->start_frame, uhci->frame_number))
  1277. qh->unlink_frame = uhci->frame_number;
  1278. }
  1279. uhci_unlink_qh(uhci, qh);
  1280. done:
  1281. spin_unlock_irqrestore(&uhci->lock, flags);
  1282. return rc;
  1283. }
  1284. /*
  1285. * Finish unlinking an URB and give it back
  1286. */
  1287. static void uhci_giveback_urb(struct uhci_hcd *uhci, struct uhci_qh *qh,
  1288. struct urb *urb, int status)
  1289. __releases(uhci->lock)
  1290. __acquires(uhci->lock)
  1291. {
  1292. struct urb_priv *urbp = (struct urb_priv *) urb->hcpriv;
  1293. if (qh->type == USB_ENDPOINT_XFER_CONTROL) {
  1294. /* Subtract off the length of the SETUP packet from
  1295. * urb->actual_length.
  1296. */
  1297. urb->actual_length -= min_t(u32, 8, urb->actual_length);
  1298. }
  1299. /* When giving back the first URB in an Isochronous queue,
  1300. * reinitialize the QH's iso-related members for the next URB. */
  1301. else if (qh->type == USB_ENDPOINT_XFER_ISOC &&
  1302. urbp->node.prev == &qh->queue &&
  1303. urbp->node.next != &qh->queue) {
  1304. struct urb *nurb = list_entry(urbp->node.next,
  1305. struct urb_priv, node)->urb;
  1306. qh->iso_packet_desc = &nurb->iso_frame_desc[0];
  1307. qh->iso_frame = nurb->start_frame;
  1308. }
  1309. /* Take the URB off the QH's queue. If the queue is now empty,
  1310. * this is a perfect time for a toggle fixup. */
  1311. list_del_init(&urbp->node);
  1312. if (list_empty(&qh->queue) && qh->needs_fixup) {
  1313. usb_settoggle(urb->dev, usb_pipeendpoint(urb->pipe),
  1314. usb_pipeout(urb->pipe), qh->initial_toggle);
  1315. qh->needs_fixup = 0;
  1316. }
  1317. uhci_free_urb_priv(uhci, urbp);
  1318. usb_hcd_unlink_urb_from_ep(uhci_to_hcd(uhci), urb);
  1319. spin_unlock(&uhci->lock);
  1320. usb_hcd_giveback_urb(uhci_to_hcd(uhci), urb, status);
  1321. spin_lock(&uhci->lock);
  1322. /* If the queue is now empty, we can unlink the QH and give up its
  1323. * reserved bandwidth. */
  1324. if (list_empty(&qh->queue)) {
  1325. uhci_unlink_qh(uhci, qh);
  1326. if (qh->bandwidth_reserved)
  1327. uhci_release_bandwidth(uhci, qh);
  1328. }
  1329. }
  1330. /*
  1331. * Scan the URBs in a QH's queue
  1332. */
  1333. #define QH_FINISHED_UNLINKING(qh) \
  1334. (qh->state == QH_STATE_UNLINKING && \
  1335. uhci->frame_number + uhci->is_stopped != qh->unlink_frame)
  1336. static void uhci_scan_qh(struct uhci_hcd *uhci, struct uhci_qh *qh)
  1337. {
  1338. struct urb_priv *urbp;
  1339. struct urb *urb;
  1340. int status;
  1341. while (!list_empty(&qh->queue)) {
  1342. urbp = list_entry(qh->queue.next, struct urb_priv, node);
  1343. urb = urbp->urb;
  1344. if (qh->type == USB_ENDPOINT_XFER_ISOC)
  1345. status = uhci_result_isochronous(uhci, urb);
  1346. else
  1347. status = uhci_result_common(uhci, urb);
  1348. if (status == -EINPROGRESS)
  1349. break;
  1350. /* Dequeued but completed URBs can't be given back unless
  1351. * the QH is stopped or has finished unlinking. */
  1352. if (urb->unlinked) {
  1353. if (QH_FINISHED_UNLINKING(qh))
  1354. qh->is_stopped = 1;
  1355. else if (!qh->is_stopped)
  1356. return;
  1357. }
  1358. uhci_giveback_urb(uhci, qh, urb, status);
  1359. if (status < 0)
  1360. break;
  1361. }
  1362. /* If the QH is neither stopped nor finished unlinking (normal case),
  1363. * our work here is done. */
  1364. if (QH_FINISHED_UNLINKING(qh))
  1365. qh->is_stopped = 1;
  1366. else if (!qh->is_stopped)
  1367. return;
  1368. /* Otherwise give back each of the dequeued URBs */
  1369. restart:
  1370. list_for_each_entry(urbp, &qh->queue, node) {
  1371. urb = urbp->urb;
  1372. if (urb->unlinked) {
  1373. /* Fix up the TD links and save the toggles for
  1374. * non-Isochronous queues. For Isochronous queues,
  1375. * test for too-recent dequeues. */
  1376. if (!uhci_cleanup_queue(uhci, qh, urb)) {
  1377. qh->is_stopped = 0;
  1378. return;
  1379. }
  1380. uhci_giveback_urb(uhci, qh, urb, 0);
  1381. goto restart;
  1382. }
  1383. }
  1384. qh->is_stopped = 0;
  1385. /* There are no more dequeued URBs. If there are still URBs on the
  1386. * queue, the QH can now be re-activated. */
  1387. if (!list_empty(&qh->queue)) {
  1388. if (qh->needs_fixup)
  1389. uhci_fixup_toggles(qh, 0);
  1390. /* If the first URB on the queue wants FSBR but its time
  1391. * limit has expired, set the next TD to interrupt on
  1392. * completion before reactivating the QH. */
  1393. urbp = list_entry(qh->queue.next, struct urb_priv, node);
  1394. if (urbp->fsbr && qh->wait_expired) {
  1395. struct uhci_td *td = list_entry(urbp->td_list.next,
  1396. struct uhci_td, list);
  1397. td->status |= __cpu_to_le32(TD_CTRL_IOC);
  1398. }
  1399. uhci_activate_qh(uhci, qh);
  1400. }
  1401. /* The queue is empty. The QH can become idle if it is fully
  1402. * unlinked. */
  1403. else if (QH_FINISHED_UNLINKING(qh))
  1404. uhci_make_qh_idle(uhci, qh);
  1405. }
  1406. /*
  1407. * Check for queues that have made some forward progress.
  1408. * Returns 0 if the queue is not Isochronous, is ACTIVE, and
  1409. * has not advanced since last examined; 1 otherwise.
  1410. *
  1411. * Early Intel controllers have a bug which causes qh->element sometimes
  1412. * not to advance when a TD completes successfully. The queue remains
  1413. * stuck on the inactive completed TD. We detect such cases and advance
  1414. * the element pointer by hand.
  1415. */
  1416. static int uhci_advance_check(struct uhci_hcd *uhci, struct uhci_qh *qh)
  1417. {
  1418. struct urb_priv *urbp = NULL;
  1419. struct uhci_td *td;
  1420. int ret = 1;
  1421. unsigned status;
  1422. if (qh->type == USB_ENDPOINT_XFER_ISOC)
  1423. goto done;
  1424. /* Treat an UNLINKING queue as though it hasn't advanced.
  1425. * This is okay because reactivation will treat it as though
  1426. * it has advanced, and if it is going to become IDLE then
  1427. * this doesn't matter anyway. Furthermore it's possible
  1428. * for an UNLINKING queue not to have any URBs at all, or
  1429. * for its first URB not to have any TDs (if it was dequeued
  1430. * just as it completed). So it's not easy in any case to
  1431. * test whether such queues have advanced. */
  1432. if (qh->state != QH_STATE_ACTIVE) {
  1433. urbp = NULL;
  1434. status = 0;
  1435. } else {
  1436. urbp = list_entry(qh->queue.next, struct urb_priv, node);
  1437. td = list_entry(urbp->td_list.next, struct uhci_td, list);
  1438. status = td_status(td);
  1439. if (!(status & TD_CTRL_ACTIVE)) {
  1440. /* We're okay, the queue has advanced */
  1441. qh->wait_expired = 0;
  1442. qh->advance_jiffies = jiffies;
  1443. goto done;
  1444. }
  1445. ret = uhci->is_stopped;
  1446. }
  1447. /* The queue hasn't advanced; check for timeout */
  1448. if (qh->wait_expired)
  1449. goto done;
  1450. if (time_after(jiffies, qh->advance_jiffies + QH_WAIT_TIMEOUT)) {
  1451. /* Detect the Intel bug and work around it */
  1452. if (qh->post_td && qh_element(qh) == LINK_TO_TD(qh->post_td)) {
  1453. qh->element = qh->post_td->link;
  1454. qh->advance_jiffies = jiffies;
  1455. ret = 1;
  1456. goto done;
  1457. }
  1458. qh->wait_expired = 1;
  1459. /* If the current URB wants FSBR, unlink it temporarily
  1460. * so that we can safely set the next TD to interrupt on
  1461. * completion. That way we'll know as soon as the queue
  1462. * starts moving again. */
  1463. if (urbp && urbp->fsbr && !(status & TD_CTRL_IOC))
  1464. uhci_unlink_qh(uhci, qh);
  1465. } else {
  1466. /* Unmoving but not-yet-expired queues keep FSBR alive */
  1467. if (urbp)
  1468. uhci_urbp_wants_fsbr(uhci, urbp);
  1469. }
  1470. done:
  1471. return ret;
  1472. }
  1473. /*
  1474. * Process events in the schedule, but only in one thread at a time
  1475. */
  1476. static void uhci_scan_schedule(struct uhci_hcd *uhci)
  1477. {
  1478. int i;
  1479. struct uhci_qh *qh;
  1480. /* Don't allow re-entrant calls */
  1481. if (uhci->scan_in_progress) {
  1482. uhci->need_rescan = 1;
  1483. return;
  1484. }
  1485. uhci->scan_in_progress = 1;
  1486. rescan:
  1487. uhci->need_rescan = 0;
  1488. uhci->fsbr_is_wanted = 0;
  1489. uhci_clear_next_interrupt(uhci);
  1490. uhci_get_current_frame_number(uhci);
  1491. uhci->cur_iso_frame = uhci->frame_number;
  1492. /* Go through all the QH queues and process the URBs in each one */
  1493. for (i = 0; i < UHCI_NUM_SKELQH - 1; ++i) {
  1494. uhci->next_qh = list_entry(uhci->skelqh[i]->node.next,
  1495. struct uhci_qh, node);
  1496. while ((qh = uhci->next_qh) != uhci->skelqh[i]) {
  1497. uhci->next_qh = list_entry(qh->node.next,
  1498. struct uhci_qh, node);
  1499. if (uhci_advance_check(uhci, qh)) {
  1500. uhci_scan_qh(uhci, qh);
  1501. if (qh->state == QH_STATE_ACTIVE) {
  1502. uhci_urbp_wants_fsbr(uhci,
  1503. list_entry(qh->queue.next, struct urb_priv, node));
  1504. }
  1505. }
  1506. }
  1507. }
  1508. uhci->last_iso_frame = uhci->cur_iso_frame;
  1509. if (uhci->need_rescan)
  1510. goto rescan;
  1511. uhci->scan_in_progress = 0;
  1512. if (uhci->fsbr_is_on && !uhci->fsbr_is_wanted &&
  1513. !uhci->fsbr_expiring) {
  1514. uhci->fsbr_expiring = 1;
  1515. mod_timer(&uhci->fsbr_timer, jiffies + FSBR_OFF_DELAY);
  1516. }
  1517. if (list_empty(&uhci->skel_unlink_qh->node))
  1518. uhci_clear_next_interrupt(uhci);
  1519. else
  1520. uhci_set_next_interrupt(uhci);
  1521. }