cx23885-dvb.c 30 KB

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  1. /*
  2. * Driver for the Conexant CX23885 PCIe bridge
  3. *
  4. * Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. *
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20. */
  21. #include <linux/module.h>
  22. #include <linux/init.h>
  23. #include <linux/device.h>
  24. #include <linux/fs.h>
  25. #include <linux/kthread.h>
  26. #include <linux/file.h>
  27. #include <linux/suspend.h>
  28. #include "cx23885.h"
  29. #include <media/v4l2-common.h>
  30. #include "dvb_ca_en50221.h"
  31. #include "s5h1409.h"
  32. #include "s5h1411.h"
  33. #include "mt2131.h"
  34. #include "tda8290.h"
  35. #include "tda18271.h"
  36. #include "lgdt330x.h"
  37. #include "xc5000.h"
  38. #include "max2165.h"
  39. #include "tda10048.h"
  40. #include "tuner-xc2028.h"
  41. #include "tuner-simple.h"
  42. #include "dib7000p.h"
  43. #include "dibx000_common.h"
  44. #include "zl10353.h"
  45. #include "stv0900.h"
  46. #include "stv0900_reg.h"
  47. #include "stv6110.h"
  48. #include "lnbh24.h"
  49. #include "cx24116.h"
  50. #include "cimax2.h"
  51. #include "lgs8gxx.h"
  52. #include "netup-eeprom.h"
  53. #include "netup-init.h"
  54. #include "lgdt3305.h"
  55. #include "atbm8830.h"
  56. static unsigned int debug;
  57. #define dprintk(level, fmt, arg...)\
  58. do { if (debug >= level)\
  59. printk(KERN_DEBUG "%s/0: " fmt, dev->name, ## arg);\
  60. } while (0)
  61. /* ------------------------------------------------------------------ */
  62. static unsigned int alt_tuner;
  63. module_param(alt_tuner, int, 0644);
  64. MODULE_PARM_DESC(alt_tuner, "Enable alternate tuner configuration");
  65. DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
  66. /* ------------------------------------------------------------------ */
  67. static int dvb_buf_setup(struct videobuf_queue *q,
  68. unsigned int *count, unsigned int *size)
  69. {
  70. struct cx23885_tsport *port = q->priv_data;
  71. port->ts_packet_size = 188 * 4;
  72. port->ts_packet_count = 32;
  73. *size = port->ts_packet_size * port->ts_packet_count;
  74. *count = 32;
  75. return 0;
  76. }
  77. static int dvb_buf_prepare(struct videobuf_queue *q,
  78. struct videobuf_buffer *vb, enum v4l2_field field)
  79. {
  80. struct cx23885_tsport *port = q->priv_data;
  81. return cx23885_buf_prepare(q, port, (struct cx23885_buffer *)vb, field);
  82. }
  83. static void dvb_buf_queue(struct videobuf_queue *q, struct videobuf_buffer *vb)
  84. {
  85. struct cx23885_tsport *port = q->priv_data;
  86. cx23885_buf_queue(port, (struct cx23885_buffer *)vb);
  87. }
  88. static void dvb_buf_release(struct videobuf_queue *q,
  89. struct videobuf_buffer *vb)
  90. {
  91. cx23885_free_buffer(q, (struct cx23885_buffer *)vb);
  92. }
  93. static struct videobuf_queue_ops dvb_qops = {
  94. .buf_setup = dvb_buf_setup,
  95. .buf_prepare = dvb_buf_prepare,
  96. .buf_queue = dvb_buf_queue,
  97. .buf_release = dvb_buf_release,
  98. };
  99. static struct s5h1409_config hauppauge_generic_config = {
  100. .demod_address = 0x32 >> 1,
  101. .output_mode = S5H1409_SERIAL_OUTPUT,
  102. .gpio = S5H1409_GPIO_ON,
  103. .qam_if = 44000,
  104. .inversion = S5H1409_INVERSION_OFF,
  105. .status_mode = S5H1409_DEMODLOCKING,
  106. .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  107. };
  108. static struct tda10048_config hauppauge_hvr1200_config = {
  109. .demod_address = 0x10 >> 1,
  110. .output_mode = TDA10048_SERIAL_OUTPUT,
  111. .fwbulkwritelen = TDA10048_BULKWRITE_200,
  112. .inversion = TDA10048_INVERSION_ON,
  113. .dtv6_if_freq_khz = TDA10048_IF_3300,
  114. .dtv7_if_freq_khz = TDA10048_IF_3800,
  115. .dtv8_if_freq_khz = TDA10048_IF_4300,
  116. .clk_freq_khz = TDA10048_CLK_16000,
  117. };
  118. static struct tda10048_config hauppauge_hvr1210_config = {
  119. .demod_address = 0x10 >> 1,
  120. .output_mode = TDA10048_SERIAL_OUTPUT,
  121. .fwbulkwritelen = TDA10048_BULKWRITE_200,
  122. .inversion = TDA10048_INVERSION_ON,
  123. .dtv6_if_freq_khz = TDA10048_IF_3300,
  124. .dtv7_if_freq_khz = TDA10048_IF_3500,
  125. .dtv8_if_freq_khz = TDA10048_IF_4000,
  126. .clk_freq_khz = TDA10048_CLK_16000,
  127. };
  128. static struct s5h1409_config hauppauge_ezqam_config = {
  129. .demod_address = 0x32 >> 1,
  130. .output_mode = S5H1409_SERIAL_OUTPUT,
  131. .gpio = S5H1409_GPIO_OFF,
  132. .qam_if = 4000,
  133. .inversion = S5H1409_INVERSION_ON,
  134. .status_mode = S5H1409_DEMODLOCKING,
  135. .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  136. };
  137. static struct s5h1409_config hauppauge_hvr1800lp_config = {
  138. .demod_address = 0x32 >> 1,
  139. .output_mode = S5H1409_SERIAL_OUTPUT,
  140. .gpio = S5H1409_GPIO_OFF,
  141. .qam_if = 44000,
  142. .inversion = S5H1409_INVERSION_OFF,
  143. .status_mode = S5H1409_DEMODLOCKING,
  144. .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  145. };
  146. static struct s5h1409_config hauppauge_hvr1500_config = {
  147. .demod_address = 0x32 >> 1,
  148. .output_mode = S5H1409_SERIAL_OUTPUT,
  149. .gpio = S5H1409_GPIO_OFF,
  150. .inversion = S5H1409_INVERSION_OFF,
  151. .status_mode = S5H1409_DEMODLOCKING,
  152. .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  153. };
  154. static struct mt2131_config hauppauge_generic_tunerconfig = {
  155. 0x61
  156. };
  157. static struct lgdt330x_config fusionhdtv_5_express = {
  158. .demod_address = 0x0e,
  159. .demod_chip = LGDT3303,
  160. .serial_mpeg = 0x40,
  161. };
  162. static struct s5h1409_config hauppauge_hvr1500q_config = {
  163. .demod_address = 0x32 >> 1,
  164. .output_mode = S5H1409_SERIAL_OUTPUT,
  165. .gpio = S5H1409_GPIO_ON,
  166. .qam_if = 44000,
  167. .inversion = S5H1409_INVERSION_OFF,
  168. .status_mode = S5H1409_DEMODLOCKING,
  169. .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  170. };
  171. static struct s5h1409_config dvico_s5h1409_config = {
  172. .demod_address = 0x32 >> 1,
  173. .output_mode = S5H1409_SERIAL_OUTPUT,
  174. .gpio = S5H1409_GPIO_ON,
  175. .qam_if = 44000,
  176. .inversion = S5H1409_INVERSION_OFF,
  177. .status_mode = S5H1409_DEMODLOCKING,
  178. .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  179. };
  180. static struct s5h1411_config dvico_s5h1411_config = {
  181. .output_mode = S5H1411_SERIAL_OUTPUT,
  182. .gpio = S5H1411_GPIO_ON,
  183. .qam_if = S5H1411_IF_44000,
  184. .vsb_if = S5H1411_IF_44000,
  185. .inversion = S5H1411_INVERSION_OFF,
  186. .status_mode = S5H1411_DEMODLOCKING,
  187. .mpeg_timing = S5H1411_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  188. };
  189. static struct s5h1411_config hcw_s5h1411_config = {
  190. .output_mode = S5H1411_SERIAL_OUTPUT,
  191. .gpio = S5H1411_GPIO_OFF,
  192. .vsb_if = S5H1411_IF_44000,
  193. .qam_if = S5H1411_IF_4000,
  194. .inversion = S5H1411_INVERSION_ON,
  195. .status_mode = S5H1411_DEMODLOCKING,
  196. .mpeg_timing = S5H1411_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  197. };
  198. static struct xc5000_config hauppauge_hvr1500q_tunerconfig = {
  199. .i2c_address = 0x61,
  200. .if_khz = 5380,
  201. };
  202. static struct xc5000_config dvico_xc5000_tunerconfig = {
  203. .i2c_address = 0x64,
  204. .if_khz = 5380,
  205. };
  206. static struct tda829x_config tda829x_no_probe = {
  207. .probe_tuner = TDA829X_DONT_PROBE,
  208. };
  209. static struct tda18271_std_map hauppauge_tda18271_std_map = {
  210. .atsc_6 = { .if_freq = 5380, .agc_mode = 3, .std = 3,
  211. .if_lvl = 6, .rfagc_top = 0x37 },
  212. .qam_6 = { .if_freq = 4000, .agc_mode = 3, .std = 0,
  213. .if_lvl = 6, .rfagc_top = 0x37 },
  214. };
  215. static struct tda18271_std_map hauppauge_hvr1200_tda18271_std_map = {
  216. .dvbt_6 = { .if_freq = 3300, .agc_mode = 3, .std = 4,
  217. .if_lvl = 1, .rfagc_top = 0x37, },
  218. .dvbt_7 = { .if_freq = 3800, .agc_mode = 3, .std = 5,
  219. .if_lvl = 1, .rfagc_top = 0x37, },
  220. .dvbt_8 = { .if_freq = 4300, .agc_mode = 3, .std = 6,
  221. .if_lvl = 1, .rfagc_top = 0x37, },
  222. };
  223. static struct tda18271_config hauppauge_tda18271_config = {
  224. .std_map = &hauppauge_tda18271_std_map,
  225. .gate = TDA18271_GATE_ANALOG,
  226. .output_opt = TDA18271_OUTPUT_LT_OFF,
  227. };
  228. static struct tda18271_config hauppauge_hvr1200_tuner_config = {
  229. .std_map = &hauppauge_hvr1200_tda18271_std_map,
  230. .gate = TDA18271_GATE_ANALOG,
  231. .output_opt = TDA18271_OUTPUT_LT_OFF,
  232. };
  233. static struct tda18271_config hauppauge_hvr1210_tuner_config = {
  234. .gate = TDA18271_GATE_DIGITAL,
  235. .output_opt = TDA18271_OUTPUT_LT_OFF,
  236. };
  237. static struct tda18271_std_map hauppauge_hvr127x_std_map = {
  238. .atsc_6 = { .if_freq = 3250, .agc_mode = 3, .std = 4,
  239. .if_lvl = 1, .rfagc_top = 0x58 },
  240. .qam_6 = { .if_freq = 4000, .agc_mode = 3, .std = 5,
  241. .if_lvl = 1, .rfagc_top = 0x58 },
  242. };
  243. static struct tda18271_config hauppauge_hvr127x_config = {
  244. .std_map = &hauppauge_hvr127x_std_map,
  245. .output_opt = TDA18271_OUTPUT_LT_OFF,
  246. };
  247. static struct lgdt3305_config hauppauge_lgdt3305_config = {
  248. .i2c_addr = 0x0e,
  249. .mpeg_mode = LGDT3305_MPEG_SERIAL,
  250. .tpclk_edge = LGDT3305_TPCLK_FALLING_EDGE,
  251. .tpvalid_polarity = LGDT3305_TP_VALID_HIGH,
  252. .deny_i2c_rptr = 1,
  253. .spectral_inversion = 1,
  254. .qam_if_khz = 4000,
  255. .vsb_if_khz = 3250,
  256. };
  257. static struct dibx000_agc_config xc3028_agc_config = {
  258. BAND_VHF | BAND_UHF, /* band_caps */
  259. /* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=0,
  260. * P_agc_inv_pwm1=0, P_agc_inv_pwm2=0,
  261. * P_agc_inh_dc_rv_est=0, P_agc_time_est=3, P_agc_freeze=0,
  262. * P_agc_nb_est=2, P_agc_write=0
  263. */
  264. (0 << 15) | (0 << 14) | (0 << 11) | (0 << 10) | (0 << 9) | (0 << 8) |
  265. (3 << 5) | (0 << 4) | (2 << 1) | (0 << 0), /* setup */
  266. 712, /* inv_gain */
  267. 21, /* time_stabiliz */
  268. 0, /* alpha_level */
  269. 118, /* thlock */
  270. 0, /* wbd_inv */
  271. 2867, /* wbd_ref */
  272. 0, /* wbd_sel */
  273. 2, /* wbd_alpha */
  274. 0, /* agc1_max */
  275. 0, /* agc1_min */
  276. 39718, /* agc2_max */
  277. 9930, /* agc2_min */
  278. 0, /* agc1_pt1 */
  279. 0, /* agc1_pt2 */
  280. 0, /* agc1_pt3 */
  281. 0, /* agc1_slope1 */
  282. 0, /* agc1_slope2 */
  283. 0, /* agc2_pt1 */
  284. 128, /* agc2_pt2 */
  285. 29, /* agc2_slope1 */
  286. 29, /* agc2_slope2 */
  287. 17, /* alpha_mant */
  288. 27, /* alpha_exp */
  289. 23, /* beta_mant */
  290. 51, /* beta_exp */
  291. 1, /* perform_agc_softsplit */
  292. };
  293. /* PLL Configuration for COFDM BW_MHz = 8.000000
  294. * With external clock = 30.000000 */
  295. static struct dibx000_bandwidth_config xc3028_bw_config = {
  296. 60000, /* internal */
  297. 30000, /* sampling */
  298. 1, /* pll_cfg: prediv */
  299. 8, /* pll_cfg: ratio */
  300. 3, /* pll_cfg: range */
  301. 1, /* pll_cfg: reset */
  302. 0, /* pll_cfg: bypass */
  303. 0, /* misc: refdiv */
  304. 0, /* misc: bypclk_div */
  305. 1, /* misc: IO_CLK_en_core */
  306. 1, /* misc: ADClkSrc */
  307. 0, /* misc: modulo */
  308. (3 << 14) | (1 << 12) | (524 << 0), /* sad_cfg: refsel, sel, freq_15k */
  309. (1 << 25) | 5816102, /* ifreq = 5.200000 MHz */
  310. 20452225, /* timf */
  311. 30000000 /* xtal_hz */
  312. };
  313. static struct dib7000p_config hauppauge_hvr1400_dib7000_config = {
  314. .output_mpeg2_in_188_bytes = 1,
  315. .hostbus_diversity = 1,
  316. .tuner_is_baseband = 0,
  317. .update_lna = NULL,
  318. .agc_config_count = 1,
  319. .agc = &xc3028_agc_config,
  320. .bw = &xc3028_bw_config,
  321. .gpio_dir = DIB7000P_GPIO_DEFAULT_DIRECTIONS,
  322. .gpio_val = DIB7000P_GPIO_DEFAULT_VALUES,
  323. .gpio_pwm_pos = DIB7000P_GPIO_DEFAULT_PWM_POS,
  324. .pwm_freq_div = 0,
  325. .agc_control = NULL,
  326. .spur_protect = 0,
  327. .output_mode = OUTMODE_MPEG2_SERIAL,
  328. };
  329. static struct zl10353_config dvico_fusionhdtv_xc3028 = {
  330. .demod_address = 0x0f,
  331. .if2 = 45600,
  332. .no_tuner = 1,
  333. .disable_i2c_gate_ctrl = 1,
  334. };
  335. static struct stv0900_reg stv0900_ts_regs[] = {
  336. { R0900_TSGENERAL, 0x00 },
  337. { R0900_P1_TSSPEED, 0x40 },
  338. { R0900_P2_TSSPEED, 0x40 },
  339. { R0900_P1_TSCFGM, 0xc0 },
  340. { R0900_P2_TSCFGM, 0xc0 },
  341. { R0900_P1_TSCFGH, 0xe0 },
  342. { R0900_P2_TSCFGH, 0xe0 },
  343. { R0900_P1_TSCFGL, 0x20 },
  344. { R0900_P2_TSCFGL, 0x20 },
  345. { 0xffff, 0xff }, /* terminate */
  346. };
  347. static struct stv0900_config netup_stv0900_config = {
  348. .demod_address = 0x68,
  349. .demod_mode = 1, /* dual */
  350. .xtal = 8000000,
  351. .clkmode = 3,/* 0-CLKI, 2-XTALI, else AUTO */
  352. .diseqc_mode = 2,/* 2/3 PWM */
  353. .ts_config_regs = stv0900_ts_regs,
  354. .tun1_maddress = 0,/* 0x60 */
  355. .tun2_maddress = 3,/* 0x63 */
  356. .tun1_adc = 1,/* 1 Vpp */
  357. .tun2_adc = 1,/* 1 Vpp */
  358. };
  359. static struct stv6110_config netup_stv6110_tunerconfig_a = {
  360. .i2c_address = 0x60,
  361. .mclk = 16000000,
  362. .clk_div = 1,
  363. .gain = 8, /* +16 dB - maximum gain */
  364. };
  365. static struct stv6110_config netup_stv6110_tunerconfig_b = {
  366. .i2c_address = 0x63,
  367. .mclk = 16000000,
  368. .clk_div = 1,
  369. .gain = 8, /* +16 dB - maximum gain */
  370. };
  371. static int tbs_set_voltage(struct dvb_frontend *fe, fe_sec_voltage_t voltage)
  372. {
  373. struct cx23885_tsport *port = fe->dvb->priv;
  374. struct cx23885_dev *dev = port->dev;
  375. if (voltage == SEC_VOLTAGE_18)
  376. cx_write(MC417_RWD, 0x00001e00);/* GPIO-13 high */
  377. else if (voltage == SEC_VOLTAGE_13)
  378. cx_write(MC417_RWD, 0x00001a00);/* GPIO-13 low */
  379. else
  380. cx_write(MC417_RWD, 0x00001800);/* GPIO-12 low */
  381. return 0;
  382. }
  383. static struct cx24116_config tbs_cx24116_config = {
  384. .demod_address = 0x05,
  385. };
  386. static struct cx24116_config tevii_cx24116_config = {
  387. .demod_address = 0x55,
  388. };
  389. static struct cx24116_config dvbworld_cx24116_config = {
  390. .demod_address = 0x05,
  391. };
  392. static struct lgs8gxx_config mygica_x8506_lgs8gl5_config = {
  393. .prod = LGS8GXX_PROD_LGS8GL5,
  394. .demod_address = 0x19,
  395. .serial_ts = 0,
  396. .ts_clk_pol = 1,
  397. .ts_clk_gated = 1,
  398. .if_clk_freq = 30400, /* 30.4 MHz */
  399. .if_freq = 5380, /* 5.38 MHz */
  400. .if_neg_center = 1,
  401. .ext_adc = 0,
  402. .adc_signed = 0,
  403. .if_neg_edge = 0,
  404. };
  405. static struct xc5000_config mygica_x8506_xc5000_config = {
  406. .i2c_address = 0x61,
  407. .if_khz = 5380,
  408. };
  409. static int cx23885_dvb_set_frontend(struct dvb_frontend *fe,
  410. struct dvb_frontend_parameters *param)
  411. {
  412. struct cx23885_tsport *port = fe->dvb->priv;
  413. struct cx23885_dev *dev = port->dev;
  414. switch (dev->board) {
  415. case CX23885_BOARD_HAUPPAUGE_HVR1275:
  416. switch (param->u.vsb.modulation) {
  417. case VSB_8:
  418. cx23885_gpio_clear(dev, GPIO_5);
  419. break;
  420. case QAM_64:
  421. case QAM_256:
  422. default:
  423. cx23885_gpio_set(dev, GPIO_5);
  424. break;
  425. }
  426. break;
  427. case CX23885_BOARD_MYGICA_X8506:
  428. case CX23885_BOARD_MAGICPRO_PROHDTVE2:
  429. /* Select Digital TV */
  430. cx23885_gpio_set(dev, GPIO_0);
  431. break;
  432. }
  433. return 0;
  434. }
  435. static int cx23885_dvb_fe_ioctl_override(struct dvb_frontend *fe,
  436. unsigned int cmd, void *parg,
  437. unsigned int stage)
  438. {
  439. int err = 0;
  440. switch (stage) {
  441. case DVB_FE_IOCTL_PRE:
  442. switch (cmd) {
  443. case FE_SET_FRONTEND:
  444. err = cx23885_dvb_set_frontend(fe,
  445. (struct dvb_frontend_parameters *) parg);
  446. break;
  447. }
  448. break;
  449. case DVB_FE_IOCTL_POST:
  450. /* no post-ioctl handling required */
  451. break;
  452. }
  453. return err;
  454. };
  455. static struct lgs8gxx_config magicpro_prohdtve2_lgs8g75_config = {
  456. .prod = LGS8GXX_PROD_LGS8G75,
  457. .demod_address = 0x19,
  458. .serial_ts = 0,
  459. .ts_clk_pol = 1,
  460. .ts_clk_gated = 1,
  461. .if_clk_freq = 30400, /* 30.4 MHz */
  462. .if_freq = 6500, /* 6.50 MHz */
  463. .if_neg_center = 1,
  464. .ext_adc = 0,
  465. .adc_signed = 1,
  466. .adc_vpp = 2, /* 1.6 Vpp */
  467. .if_neg_edge = 1,
  468. };
  469. static struct xc5000_config magicpro_prohdtve2_xc5000_config = {
  470. .i2c_address = 0x61,
  471. .if_khz = 6500,
  472. };
  473. static struct atbm8830_config mygica_x8558pro_atbm8830_cfg1 = {
  474. .prod = ATBM8830_PROD_8830,
  475. .demod_address = 0x44,
  476. .serial_ts = 0,
  477. .ts_sampling_edge = 1,
  478. .ts_clk_gated = 0,
  479. .osc_clk_freq = 30400, /* in kHz */
  480. .if_freq = 0, /* zero IF */
  481. .zif_swap_iq = 1,
  482. };
  483. static struct max2165_config mygic_x8558pro_max2165_cfg1 = {
  484. .i2c_address = 0x60,
  485. .osc_clk = 20
  486. };
  487. static struct atbm8830_config mygica_x8558pro_atbm8830_cfg2 = {
  488. .prod = ATBM8830_PROD_8830,
  489. .demod_address = 0x44,
  490. .serial_ts = 1,
  491. .ts_sampling_edge = 1,
  492. .ts_clk_gated = 0,
  493. .osc_clk_freq = 30400, /* in kHz */
  494. .if_freq = 0, /* zero IF */
  495. .zif_swap_iq = 1,
  496. };
  497. static struct max2165_config mygic_x8558pro_max2165_cfg2 = {
  498. .i2c_address = 0x60,
  499. .osc_clk = 20
  500. };
  501. static int dvb_register(struct cx23885_tsport *port)
  502. {
  503. struct cx23885_dev *dev = port->dev;
  504. struct cx23885_i2c *i2c_bus = NULL, *i2c_bus2 = NULL;
  505. struct videobuf_dvb_frontend *fe0;
  506. int ret;
  507. /* Get the first frontend */
  508. fe0 = videobuf_dvb_get_frontend(&port->frontends, 1);
  509. if (!fe0)
  510. return -EINVAL;
  511. /* init struct videobuf_dvb */
  512. fe0->dvb.name = dev->name;
  513. /* init frontend */
  514. switch (dev->board) {
  515. case CX23885_BOARD_HAUPPAUGE_HVR1250:
  516. i2c_bus = &dev->i2c_bus[0];
  517. fe0->dvb.frontend = dvb_attach(s5h1409_attach,
  518. &hauppauge_generic_config,
  519. &i2c_bus->i2c_adap);
  520. if (fe0->dvb.frontend != NULL) {
  521. dvb_attach(mt2131_attach, fe0->dvb.frontend,
  522. &i2c_bus->i2c_adap,
  523. &hauppauge_generic_tunerconfig, 0);
  524. }
  525. break;
  526. case CX23885_BOARD_HAUPPAUGE_HVR1270:
  527. case CX23885_BOARD_HAUPPAUGE_HVR1275:
  528. i2c_bus = &dev->i2c_bus[0];
  529. fe0->dvb.frontend = dvb_attach(lgdt3305_attach,
  530. &hauppauge_lgdt3305_config,
  531. &i2c_bus->i2c_adap);
  532. if (fe0->dvb.frontend != NULL) {
  533. dvb_attach(tda18271_attach, fe0->dvb.frontend,
  534. 0x60, &dev->i2c_bus[1].i2c_adap,
  535. &hauppauge_hvr127x_config);
  536. }
  537. break;
  538. case CX23885_BOARD_HAUPPAUGE_HVR1255:
  539. i2c_bus = &dev->i2c_bus[0];
  540. fe0->dvb.frontend = dvb_attach(s5h1411_attach,
  541. &hcw_s5h1411_config,
  542. &i2c_bus->i2c_adap);
  543. if (fe0->dvb.frontend != NULL) {
  544. dvb_attach(tda18271_attach, fe0->dvb.frontend,
  545. 0x60, &dev->i2c_bus[1].i2c_adap,
  546. &hauppauge_tda18271_config);
  547. }
  548. break;
  549. case CX23885_BOARD_HAUPPAUGE_HVR1800:
  550. i2c_bus = &dev->i2c_bus[0];
  551. switch (alt_tuner) {
  552. case 1:
  553. fe0->dvb.frontend =
  554. dvb_attach(s5h1409_attach,
  555. &hauppauge_ezqam_config,
  556. &i2c_bus->i2c_adap);
  557. if (fe0->dvb.frontend != NULL) {
  558. dvb_attach(tda829x_attach, fe0->dvb.frontend,
  559. &dev->i2c_bus[1].i2c_adap, 0x42,
  560. &tda829x_no_probe);
  561. dvb_attach(tda18271_attach, fe0->dvb.frontend,
  562. 0x60, &dev->i2c_bus[1].i2c_adap,
  563. &hauppauge_tda18271_config);
  564. }
  565. break;
  566. case 0:
  567. default:
  568. fe0->dvb.frontend =
  569. dvb_attach(s5h1409_attach,
  570. &hauppauge_generic_config,
  571. &i2c_bus->i2c_adap);
  572. if (fe0->dvb.frontend != NULL)
  573. dvb_attach(mt2131_attach, fe0->dvb.frontend,
  574. &i2c_bus->i2c_adap,
  575. &hauppauge_generic_tunerconfig, 0);
  576. break;
  577. }
  578. break;
  579. case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
  580. i2c_bus = &dev->i2c_bus[0];
  581. fe0->dvb.frontend = dvb_attach(s5h1409_attach,
  582. &hauppauge_hvr1800lp_config,
  583. &i2c_bus->i2c_adap);
  584. if (fe0->dvb.frontend != NULL) {
  585. dvb_attach(mt2131_attach, fe0->dvb.frontend,
  586. &i2c_bus->i2c_adap,
  587. &hauppauge_generic_tunerconfig, 0);
  588. }
  589. break;
  590. case CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP:
  591. i2c_bus = &dev->i2c_bus[0];
  592. fe0->dvb.frontend = dvb_attach(lgdt330x_attach,
  593. &fusionhdtv_5_express,
  594. &i2c_bus->i2c_adap);
  595. if (fe0->dvb.frontend != NULL) {
  596. dvb_attach(simple_tuner_attach, fe0->dvb.frontend,
  597. &i2c_bus->i2c_adap, 0x61,
  598. TUNER_LG_TDVS_H06XF);
  599. }
  600. break;
  601. case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
  602. i2c_bus = &dev->i2c_bus[1];
  603. fe0->dvb.frontend = dvb_attach(s5h1409_attach,
  604. &hauppauge_hvr1500q_config,
  605. &dev->i2c_bus[0].i2c_adap);
  606. if (fe0->dvb.frontend != NULL)
  607. dvb_attach(xc5000_attach, fe0->dvb.frontend,
  608. &i2c_bus->i2c_adap,
  609. &hauppauge_hvr1500q_tunerconfig);
  610. break;
  611. case CX23885_BOARD_HAUPPAUGE_HVR1500:
  612. i2c_bus = &dev->i2c_bus[1];
  613. fe0->dvb.frontend = dvb_attach(s5h1409_attach,
  614. &hauppauge_hvr1500_config,
  615. &dev->i2c_bus[0].i2c_adap);
  616. if (fe0->dvb.frontend != NULL) {
  617. struct dvb_frontend *fe;
  618. struct xc2028_config cfg = {
  619. .i2c_adap = &i2c_bus->i2c_adap,
  620. .i2c_addr = 0x61,
  621. };
  622. static struct xc2028_ctrl ctl = {
  623. .fname = XC2028_DEFAULT_FIRMWARE,
  624. .max_len = 64,
  625. .demod = XC3028_FE_OREN538,
  626. };
  627. fe = dvb_attach(xc2028_attach,
  628. fe0->dvb.frontend, &cfg);
  629. if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
  630. fe->ops.tuner_ops.set_config(fe, &ctl);
  631. }
  632. break;
  633. case CX23885_BOARD_HAUPPAUGE_HVR1200:
  634. case CX23885_BOARD_HAUPPAUGE_HVR1700:
  635. i2c_bus = &dev->i2c_bus[0];
  636. fe0->dvb.frontend = dvb_attach(tda10048_attach,
  637. &hauppauge_hvr1200_config,
  638. &i2c_bus->i2c_adap);
  639. if (fe0->dvb.frontend != NULL) {
  640. dvb_attach(tda829x_attach, fe0->dvb.frontend,
  641. &dev->i2c_bus[1].i2c_adap, 0x42,
  642. &tda829x_no_probe);
  643. dvb_attach(tda18271_attach, fe0->dvb.frontend,
  644. 0x60, &dev->i2c_bus[1].i2c_adap,
  645. &hauppauge_hvr1200_tuner_config);
  646. }
  647. break;
  648. case CX23885_BOARD_HAUPPAUGE_HVR1210:
  649. i2c_bus = &dev->i2c_bus[0];
  650. fe0->dvb.frontend = dvb_attach(tda10048_attach,
  651. &hauppauge_hvr1210_config,
  652. &i2c_bus->i2c_adap);
  653. if (fe0->dvb.frontend != NULL) {
  654. dvb_attach(tda18271_attach, fe0->dvb.frontend,
  655. 0x60, &dev->i2c_bus[1].i2c_adap,
  656. &hauppauge_hvr1210_tuner_config);
  657. }
  658. break;
  659. case CX23885_BOARD_HAUPPAUGE_HVR1400:
  660. i2c_bus = &dev->i2c_bus[0];
  661. fe0->dvb.frontend = dvb_attach(dib7000p_attach,
  662. &i2c_bus->i2c_adap,
  663. 0x12, &hauppauge_hvr1400_dib7000_config);
  664. if (fe0->dvb.frontend != NULL) {
  665. struct dvb_frontend *fe;
  666. struct xc2028_config cfg = {
  667. .i2c_adap = &dev->i2c_bus[1].i2c_adap,
  668. .i2c_addr = 0x64,
  669. };
  670. static struct xc2028_ctrl ctl = {
  671. .fname = XC3028L_DEFAULT_FIRMWARE,
  672. .max_len = 64,
  673. .demod = 5000,
  674. /* This is true for all demods with
  675. v36 firmware? */
  676. .type = XC2028_D2633,
  677. };
  678. fe = dvb_attach(xc2028_attach,
  679. fe0->dvb.frontend, &cfg);
  680. if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
  681. fe->ops.tuner_ops.set_config(fe, &ctl);
  682. }
  683. break;
  684. case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
  685. i2c_bus = &dev->i2c_bus[port->nr - 1];
  686. fe0->dvb.frontend = dvb_attach(s5h1409_attach,
  687. &dvico_s5h1409_config,
  688. &i2c_bus->i2c_adap);
  689. if (fe0->dvb.frontend == NULL)
  690. fe0->dvb.frontend = dvb_attach(s5h1411_attach,
  691. &dvico_s5h1411_config,
  692. &i2c_bus->i2c_adap);
  693. if (fe0->dvb.frontend != NULL)
  694. dvb_attach(xc5000_attach, fe0->dvb.frontend,
  695. &i2c_bus->i2c_adap,
  696. &dvico_xc5000_tunerconfig);
  697. break;
  698. case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP: {
  699. i2c_bus = &dev->i2c_bus[port->nr - 1];
  700. fe0->dvb.frontend = dvb_attach(zl10353_attach,
  701. &dvico_fusionhdtv_xc3028,
  702. &i2c_bus->i2c_adap);
  703. if (fe0->dvb.frontend != NULL) {
  704. struct dvb_frontend *fe;
  705. struct xc2028_config cfg = {
  706. .i2c_adap = &i2c_bus->i2c_adap,
  707. .i2c_addr = 0x61,
  708. };
  709. static struct xc2028_ctrl ctl = {
  710. .fname = XC2028_DEFAULT_FIRMWARE,
  711. .max_len = 64,
  712. .demod = XC3028_FE_ZARLINK456,
  713. };
  714. fe = dvb_attach(xc2028_attach, fe0->dvb.frontend,
  715. &cfg);
  716. if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
  717. fe->ops.tuner_ops.set_config(fe, &ctl);
  718. }
  719. break;
  720. }
  721. case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
  722. case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
  723. case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
  724. i2c_bus = &dev->i2c_bus[0];
  725. fe0->dvb.frontend = dvb_attach(zl10353_attach,
  726. &dvico_fusionhdtv_xc3028,
  727. &i2c_bus->i2c_adap);
  728. if (fe0->dvb.frontend != NULL) {
  729. struct dvb_frontend *fe;
  730. struct xc2028_config cfg = {
  731. .i2c_adap = &dev->i2c_bus[1].i2c_adap,
  732. .i2c_addr = 0x61,
  733. };
  734. static struct xc2028_ctrl ctl = {
  735. .fname = XC2028_DEFAULT_FIRMWARE,
  736. .max_len = 64,
  737. .demod = XC3028_FE_ZARLINK456,
  738. };
  739. fe = dvb_attach(xc2028_attach, fe0->dvb.frontend,
  740. &cfg);
  741. if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
  742. fe->ops.tuner_ops.set_config(fe, &ctl);
  743. }
  744. break;
  745. case CX23885_BOARD_TBS_6920:
  746. i2c_bus = &dev->i2c_bus[0];
  747. fe0->dvb.frontend = dvb_attach(cx24116_attach,
  748. &tbs_cx24116_config,
  749. &i2c_bus->i2c_adap);
  750. if (fe0->dvb.frontend != NULL)
  751. fe0->dvb.frontend->ops.set_voltage = tbs_set_voltage;
  752. break;
  753. case CX23885_BOARD_TEVII_S470:
  754. i2c_bus = &dev->i2c_bus[1];
  755. fe0->dvb.frontend = dvb_attach(cx24116_attach,
  756. &tevii_cx24116_config,
  757. &i2c_bus->i2c_adap);
  758. if (fe0->dvb.frontend != NULL)
  759. fe0->dvb.frontend->ops.set_voltage = tbs_set_voltage;
  760. break;
  761. case CX23885_BOARD_DVBWORLD_2005:
  762. i2c_bus = &dev->i2c_bus[1];
  763. fe0->dvb.frontend = dvb_attach(cx24116_attach,
  764. &dvbworld_cx24116_config,
  765. &i2c_bus->i2c_adap);
  766. break;
  767. case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
  768. i2c_bus = &dev->i2c_bus[0];
  769. switch (port->nr) {
  770. /* port B */
  771. case 1:
  772. fe0->dvb.frontend = dvb_attach(stv0900_attach,
  773. &netup_stv0900_config,
  774. &i2c_bus->i2c_adap, 0);
  775. if (fe0->dvb.frontend != NULL) {
  776. if (dvb_attach(stv6110_attach,
  777. fe0->dvb.frontend,
  778. &netup_stv6110_tunerconfig_a,
  779. &i2c_bus->i2c_adap)) {
  780. if (!dvb_attach(lnbh24_attach,
  781. fe0->dvb.frontend,
  782. &i2c_bus->i2c_adap,
  783. LNBH24_PCL | LNBH24_TTX,
  784. LNBH24_TEN, 0x09))
  785. printk(KERN_ERR
  786. "No LNBH24 found!\n");
  787. }
  788. }
  789. break;
  790. /* port C */
  791. case 2:
  792. fe0->dvb.frontend = dvb_attach(stv0900_attach,
  793. &netup_stv0900_config,
  794. &i2c_bus->i2c_adap, 1);
  795. if (fe0->dvb.frontend != NULL) {
  796. if (dvb_attach(stv6110_attach,
  797. fe0->dvb.frontend,
  798. &netup_stv6110_tunerconfig_b,
  799. &i2c_bus->i2c_adap)) {
  800. if (!dvb_attach(lnbh24_attach,
  801. fe0->dvb.frontend,
  802. &i2c_bus->i2c_adap,
  803. LNBH24_PCL | LNBH24_TTX,
  804. LNBH24_TEN, 0x0a))
  805. printk(KERN_ERR
  806. "No LNBH24 found!\n");
  807. }
  808. }
  809. break;
  810. }
  811. break;
  812. case CX23885_BOARD_MYGICA_X8506:
  813. i2c_bus = &dev->i2c_bus[0];
  814. i2c_bus2 = &dev->i2c_bus[1];
  815. fe0->dvb.frontend = dvb_attach(lgs8gxx_attach,
  816. &mygica_x8506_lgs8gl5_config,
  817. &i2c_bus->i2c_adap);
  818. if (fe0->dvb.frontend != NULL) {
  819. dvb_attach(xc5000_attach,
  820. fe0->dvb.frontend,
  821. &i2c_bus2->i2c_adap,
  822. &mygica_x8506_xc5000_config);
  823. }
  824. break;
  825. case CX23885_BOARD_MAGICPRO_PROHDTVE2:
  826. i2c_bus = &dev->i2c_bus[0];
  827. i2c_bus2 = &dev->i2c_bus[1];
  828. fe0->dvb.frontend = dvb_attach(lgs8gxx_attach,
  829. &magicpro_prohdtve2_lgs8g75_config,
  830. &i2c_bus->i2c_adap);
  831. if (fe0->dvb.frontend != NULL) {
  832. dvb_attach(xc5000_attach,
  833. fe0->dvb.frontend,
  834. &i2c_bus2->i2c_adap,
  835. &magicpro_prohdtve2_xc5000_config);
  836. }
  837. break;
  838. case CX23885_BOARD_HAUPPAUGE_HVR1850:
  839. case CX23885_BOARD_HAUPPAUGE_HVR1290:
  840. i2c_bus = &dev->i2c_bus[0];
  841. fe0->dvb.frontend = dvb_attach(s5h1411_attach,
  842. &hcw_s5h1411_config,
  843. &i2c_bus->i2c_adap);
  844. if (fe0->dvb.frontend != NULL)
  845. dvb_attach(tda18271_attach, fe0->dvb.frontend,
  846. 0x60, &dev->i2c_bus[0].i2c_adap,
  847. &hauppauge_tda18271_config);
  848. break;
  849. case CX23885_BOARD_MYGICA_X8558PRO:
  850. switch (port->nr) {
  851. /* port B */
  852. case 1:
  853. i2c_bus = &dev->i2c_bus[0];
  854. fe0->dvb.frontend = dvb_attach(atbm8830_attach,
  855. &mygica_x8558pro_atbm8830_cfg1,
  856. &i2c_bus->i2c_adap);
  857. if (fe0->dvb.frontend != NULL) {
  858. dvb_attach(max2165_attach,
  859. fe0->dvb.frontend,
  860. &i2c_bus->i2c_adap,
  861. &mygic_x8558pro_max2165_cfg1);
  862. }
  863. break;
  864. /* port C */
  865. case 2:
  866. i2c_bus = &dev->i2c_bus[1];
  867. fe0->dvb.frontend = dvb_attach(atbm8830_attach,
  868. &mygica_x8558pro_atbm8830_cfg2,
  869. &i2c_bus->i2c_adap);
  870. if (fe0->dvb.frontend != NULL) {
  871. dvb_attach(max2165_attach,
  872. fe0->dvb.frontend,
  873. &i2c_bus->i2c_adap,
  874. &mygic_x8558pro_max2165_cfg2);
  875. }
  876. break;
  877. }
  878. break;
  879. default:
  880. printk(KERN_INFO "%s: The frontend of your DVB/ATSC card "
  881. " isn't supported yet\n",
  882. dev->name);
  883. break;
  884. }
  885. if (NULL == fe0->dvb.frontend) {
  886. printk(KERN_ERR "%s: frontend initialization failed\n",
  887. dev->name);
  888. return -1;
  889. }
  890. /* define general-purpose callback pointer */
  891. fe0->dvb.frontend->callback = cx23885_tuner_callback;
  892. /* Put the analog decoder in standby to keep it quiet */
  893. call_all(dev, core, s_power, 0);
  894. if (fe0->dvb.frontend->ops.analog_ops.standby)
  895. fe0->dvb.frontend->ops.analog_ops.standby(fe0->dvb.frontend);
  896. /* register everything */
  897. ret = videobuf_dvb_register_bus(&port->frontends, THIS_MODULE, port,
  898. &dev->pci->dev, adapter_nr, 0,
  899. cx23885_dvb_fe_ioctl_override);
  900. /* init CI & MAC */
  901. switch (dev->board) {
  902. case CX23885_BOARD_NETUP_DUAL_DVBS2_CI: {
  903. static struct netup_card_info cinfo;
  904. netup_get_card_info(&dev->i2c_bus[0].i2c_adap, &cinfo);
  905. memcpy(port->frontends.adapter.proposed_mac,
  906. cinfo.port[port->nr - 1].mac, 6);
  907. printk(KERN_INFO "NetUP Dual DVB-S2 CI card port%d MAC="
  908. "%02X:%02X:%02X:%02X:%02X:%02X\n",
  909. port->nr,
  910. port->frontends.adapter.proposed_mac[0],
  911. port->frontends.adapter.proposed_mac[1],
  912. port->frontends.adapter.proposed_mac[2],
  913. port->frontends.adapter.proposed_mac[3],
  914. port->frontends.adapter.proposed_mac[4],
  915. port->frontends.adapter.proposed_mac[5]);
  916. netup_ci_init(port);
  917. break;
  918. }
  919. }
  920. return ret;
  921. }
  922. int cx23885_dvb_register(struct cx23885_tsport *port)
  923. {
  924. struct videobuf_dvb_frontend *fe0;
  925. struct cx23885_dev *dev = port->dev;
  926. int err, i;
  927. /* Here we need to allocate the correct number of frontends,
  928. * as reflected in the cards struct. The reality is that currrently
  929. * no cx23885 boards support this - yet. But, if we don't modify this
  930. * code then the second frontend would never be allocated (later)
  931. * and fail with error before the attach in dvb_register().
  932. * Without these changes we risk an OOPS later. The changes here
  933. * are for safety, and should provide a good foundation for the
  934. * future addition of any multi-frontend cx23885 based boards.
  935. */
  936. printk(KERN_INFO "%s() allocating %d frontend(s)\n", __func__,
  937. port->num_frontends);
  938. for (i = 1; i <= port->num_frontends; i++) {
  939. if (videobuf_dvb_alloc_frontend(
  940. &port->frontends, i) == NULL) {
  941. printk(KERN_ERR "%s() failed to alloc\n", __func__);
  942. return -ENOMEM;
  943. }
  944. fe0 = videobuf_dvb_get_frontend(&port->frontends, i);
  945. if (!fe0)
  946. err = -EINVAL;
  947. dprintk(1, "%s\n", __func__);
  948. dprintk(1, " ->probed by Card=%d Name=%s, PCI %02x:%02x\n",
  949. dev->board,
  950. dev->name,
  951. dev->pci_bus,
  952. dev->pci_slot);
  953. err = -ENODEV;
  954. /* dvb stuff */
  955. /* We have to init the queue for each frontend on a port. */
  956. printk(KERN_INFO "%s: cx23885 based dvb card\n", dev->name);
  957. videobuf_queue_sg_init(&fe0->dvb.dvbq, &dvb_qops,
  958. &dev->pci->dev, &port->slock,
  959. V4L2_BUF_TYPE_VIDEO_CAPTURE, V4L2_FIELD_TOP,
  960. sizeof(struct cx23885_buffer), port);
  961. }
  962. err = dvb_register(port);
  963. if (err != 0)
  964. printk(KERN_ERR "%s() dvb_register failed err = %d\n",
  965. __func__, err);
  966. return err;
  967. }
  968. int cx23885_dvb_unregister(struct cx23885_tsport *port)
  969. {
  970. struct videobuf_dvb_frontend *fe0;
  971. /* FIXME: in an error condition where the we have
  972. * an expected number of frontends (attach problem)
  973. * then this might not clean up correctly, if 1
  974. * is invalid.
  975. * This comment only applies to future boards IF they
  976. * implement MFE support.
  977. */
  978. fe0 = videobuf_dvb_get_frontend(&port->frontends, 1);
  979. if (fe0->dvb.frontend)
  980. videobuf_dvb_unregister_bus(&port->frontends);
  981. switch (port->dev->board) {
  982. case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
  983. netup_ci_exit(port);
  984. break;
  985. }
  986. return 0;
  987. }