iwl-ucode.c 21 KB

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  1. /******************************************************************************
  2. *
  3. * GPL LICENSE SUMMARY
  4. *
  5. * Copyright(c) 2008 - 2012 Intel Corporation. All rights reserved.
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of version 2 of the GNU General Public License as
  9. * published by the Free Software Foundation.
  10. *
  11. * This program is distributed in the hope that it will be useful, but
  12. * WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  14. * General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
  19. * USA
  20. *
  21. * The full GNU General Public License is included in this distribution
  22. * in the file called LICENSE.GPL.
  23. *
  24. * Contact Information:
  25. * Intel Linux Wireless <ilw@linux.intel.com>
  26. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27. *
  28. *****************************************************************************/
  29. #include <linux/kernel.h>
  30. #include <linux/module.h>
  31. #include <linux/init.h>
  32. #include <linux/sched.h>
  33. #include <linux/dma-mapping.h>
  34. #include "iwl-wifi.h"
  35. #include "iwl-dev.h"
  36. #include "iwl-core.h"
  37. #include "iwl-io.h"
  38. #include "iwl-agn-hw.h"
  39. #include "iwl-agn.h"
  40. #include "iwl-agn-calib.h"
  41. #include "iwl-trans.h"
  42. #include "iwl-fh.h"
  43. static struct iwl_wimax_coex_event_entry cu_priorities[COEX_NUM_OF_EVENTS] = {
  44. {COEX_CU_UNASSOC_IDLE_RP, COEX_CU_UNASSOC_IDLE_WP,
  45. 0, COEX_UNASSOC_IDLE_FLAGS},
  46. {COEX_CU_UNASSOC_MANUAL_SCAN_RP, COEX_CU_UNASSOC_MANUAL_SCAN_WP,
  47. 0, COEX_UNASSOC_MANUAL_SCAN_FLAGS},
  48. {COEX_CU_UNASSOC_AUTO_SCAN_RP, COEX_CU_UNASSOC_AUTO_SCAN_WP,
  49. 0, COEX_UNASSOC_AUTO_SCAN_FLAGS},
  50. {COEX_CU_CALIBRATION_RP, COEX_CU_CALIBRATION_WP,
  51. 0, COEX_CALIBRATION_FLAGS},
  52. {COEX_CU_PERIODIC_CALIBRATION_RP, COEX_CU_PERIODIC_CALIBRATION_WP,
  53. 0, COEX_PERIODIC_CALIBRATION_FLAGS},
  54. {COEX_CU_CONNECTION_ESTAB_RP, COEX_CU_CONNECTION_ESTAB_WP,
  55. 0, COEX_CONNECTION_ESTAB_FLAGS},
  56. {COEX_CU_ASSOCIATED_IDLE_RP, COEX_CU_ASSOCIATED_IDLE_WP,
  57. 0, COEX_ASSOCIATED_IDLE_FLAGS},
  58. {COEX_CU_ASSOC_MANUAL_SCAN_RP, COEX_CU_ASSOC_MANUAL_SCAN_WP,
  59. 0, COEX_ASSOC_MANUAL_SCAN_FLAGS},
  60. {COEX_CU_ASSOC_AUTO_SCAN_RP, COEX_CU_ASSOC_AUTO_SCAN_WP,
  61. 0, COEX_ASSOC_AUTO_SCAN_FLAGS},
  62. {COEX_CU_ASSOC_ACTIVE_LEVEL_RP, COEX_CU_ASSOC_ACTIVE_LEVEL_WP,
  63. 0, COEX_ASSOC_ACTIVE_LEVEL_FLAGS},
  64. {COEX_CU_RF_ON_RP, COEX_CU_RF_ON_WP, 0, COEX_CU_RF_ON_FLAGS},
  65. {COEX_CU_RF_OFF_RP, COEX_CU_RF_OFF_WP, 0, COEX_RF_OFF_FLAGS},
  66. {COEX_CU_STAND_ALONE_DEBUG_RP, COEX_CU_STAND_ALONE_DEBUG_WP,
  67. 0, COEX_STAND_ALONE_DEBUG_FLAGS},
  68. {COEX_CU_IPAN_ASSOC_LEVEL_RP, COEX_CU_IPAN_ASSOC_LEVEL_WP,
  69. 0, COEX_IPAN_ASSOC_LEVEL_FLAGS},
  70. {COEX_CU_RSRVD1_RP, COEX_CU_RSRVD1_WP, 0, COEX_RSRVD1_FLAGS},
  71. {COEX_CU_RSRVD2_RP, COEX_CU_RSRVD2_WP, 0, COEX_RSRVD2_FLAGS}
  72. };
  73. /******************************************************************************
  74. *
  75. * uCode download functions
  76. *
  77. ******************************************************************************/
  78. static void iwl_free_fw_desc(struct iwl_bus *bus, struct fw_desc *desc)
  79. {
  80. if (desc->v_addr)
  81. dma_free_coherent(trans(bus)->dev, desc->len,
  82. desc->v_addr, desc->p_addr);
  83. desc->v_addr = NULL;
  84. desc->len = 0;
  85. }
  86. static void iwl_free_fw_img(struct iwl_bus *bus, struct fw_img *img)
  87. {
  88. iwl_free_fw_desc(bus, &img->code);
  89. iwl_free_fw_desc(bus, &img->data);
  90. }
  91. void iwl_dealloc_ucode(struct iwl_trans *trans)
  92. {
  93. iwl_free_fw_img(bus(trans), &trans->ucode_rt);
  94. iwl_free_fw_img(bus(trans), &trans->ucode_init);
  95. iwl_free_fw_img(bus(trans), &trans->ucode_wowlan);
  96. }
  97. int iwl_alloc_fw_desc(struct iwl_bus *bus, struct fw_desc *desc,
  98. const void *data, size_t len)
  99. {
  100. if (!len) {
  101. desc->v_addr = NULL;
  102. return -EINVAL;
  103. }
  104. desc->v_addr = dma_alloc_coherent(trans(bus)->dev, len,
  105. &desc->p_addr, GFP_KERNEL);
  106. if (!desc->v_addr)
  107. return -ENOMEM;
  108. desc->len = len;
  109. memcpy(desc->v_addr, data, len);
  110. return 0;
  111. }
  112. /*
  113. * ucode
  114. */
  115. static int iwl_load_section(struct iwl_trans *trans, const char *name,
  116. struct fw_desc *image, u32 dst_addr)
  117. {
  118. dma_addr_t phy_addr = image->p_addr;
  119. u32 byte_cnt = image->len;
  120. int ret;
  121. trans->ucode_write_complete = 0;
  122. iwl_write_direct32(trans,
  123. FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
  124. FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
  125. iwl_write_direct32(trans,
  126. FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr);
  127. iwl_write_direct32(trans,
  128. FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
  129. phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
  130. iwl_write_direct32(trans,
  131. FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
  132. (iwl_get_dma_hi_addr(phy_addr)
  133. << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
  134. iwl_write_direct32(trans,
  135. FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
  136. 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
  137. 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
  138. FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
  139. iwl_write_direct32(trans,
  140. FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
  141. FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
  142. FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
  143. FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
  144. IWL_DEBUG_FW(trans, "%s uCode section being loaded...\n", name);
  145. ret = wait_event_timeout(trans->shrd->wait_command_queue,
  146. trans->ucode_write_complete, 5 * HZ);
  147. if (!ret) {
  148. IWL_ERR(trans, "Could not load the %s uCode section\n",
  149. name);
  150. return -ETIMEDOUT;
  151. }
  152. return 0;
  153. }
  154. static inline struct fw_img *iwl_get_ucode_image(struct iwl_trans *trans,
  155. enum iwl_ucode_type ucode_type)
  156. {
  157. switch (ucode_type) {
  158. case IWL_UCODE_INIT:
  159. return &trans->ucode_init;
  160. case IWL_UCODE_WOWLAN:
  161. return &trans->ucode_wowlan;
  162. case IWL_UCODE_REGULAR:
  163. return &trans->ucode_rt;
  164. case IWL_UCODE_NONE:
  165. break;
  166. }
  167. return NULL;
  168. }
  169. static int iwl_load_given_ucode(struct iwl_trans *trans,
  170. enum iwl_ucode_type ucode_type)
  171. {
  172. int ret = 0;
  173. struct fw_img *image = iwl_get_ucode_image(trans, ucode_type);
  174. if (!image) {
  175. IWL_ERR(trans, "Invalid ucode requested (%d)\n",
  176. ucode_type);
  177. return -EINVAL;
  178. }
  179. ret = iwl_load_section(trans, "INST", &image->code,
  180. IWLAGN_RTC_INST_LOWER_BOUND);
  181. if (ret)
  182. return ret;
  183. return iwl_load_section(trans, "DATA", &image->data,
  184. IWLAGN_RTC_DATA_LOWER_BOUND);
  185. }
  186. /*
  187. * Calibration
  188. */
  189. static int iwl_set_Xtal_calib(struct iwl_trans *trans)
  190. {
  191. struct iwl_calib_xtal_freq_cmd cmd;
  192. __le16 *xtal_calib =
  193. (__le16 *)iwl_eeprom_query_addr(trans->shrd, EEPROM_XTAL);
  194. iwl_set_calib_hdr(&cmd.hdr, IWL_PHY_CALIBRATE_CRYSTAL_FRQ_CMD);
  195. cmd.cap_pin1 = le16_to_cpu(xtal_calib[0]);
  196. cmd.cap_pin2 = le16_to_cpu(xtal_calib[1]);
  197. return iwl_calib_set(trans, (void *)&cmd, sizeof(cmd));
  198. }
  199. static int iwl_set_temperature_offset_calib(struct iwl_trans *trans)
  200. {
  201. struct iwl_calib_temperature_offset_cmd cmd;
  202. __le16 *offset_calib =
  203. (__le16 *)iwl_eeprom_query_addr(trans->shrd,
  204. EEPROM_RAW_TEMPERATURE);
  205. memset(&cmd, 0, sizeof(cmd));
  206. iwl_set_calib_hdr(&cmd.hdr, IWL_PHY_CALIBRATE_TEMP_OFFSET_CMD);
  207. memcpy(&cmd.radio_sensor_offset, offset_calib, sizeof(*offset_calib));
  208. if (!(cmd.radio_sensor_offset))
  209. cmd.radio_sensor_offset = DEFAULT_RADIO_SENSOR_OFFSET;
  210. IWL_DEBUG_CALIB(trans, "Radio sensor offset: %d\n",
  211. le16_to_cpu(cmd.radio_sensor_offset));
  212. return iwl_calib_set(trans, (void *)&cmd, sizeof(cmd));
  213. }
  214. static int iwl_set_temperature_offset_calib_v2(struct iwl_trans *trans)
  215. {
  216. struct iwl_calib_temperature_offset_v2_cmd cmd;
  217. __le16 *offset_calib_high = (__le16 *)iwl_eeprom_query_addr(trans->shrd,
  218. EEPROM_KELVIN_TEMPERATURE);
  219. __le16 *offset_calib_low =
  220. (__le16 *)iwl_eeprom_query_addr(trans->shrd,
  221. EEPROM_RAW_TEMPERATURE);
  222. struct iwl_eeprom_calib_hdr *hdr;
  223. memset(&cmd, 0, sizeof(cmd));
  224. iwl_set_calib_hdr(&cmd.hdr, IWL_PHY_CALIBRATE_TEMP_OFFSET_CMD);
  225. hdr = (struct iwl_eeprom_calib_hdr *)iwl_eeprom_query_addr(trans->shrd,
  226. EEPROM_CALIB_ALL);
  227. memcpy(&cmd.radio_sensor_offset_high, offset_calib_high,
  228. sizeof(*offset_calib_high));
  229. memcpy(&cmd.radio_sensor_offset_low, offset_calib_low,
  230. sizeof(*offset_calib_low));
  231. if (!(cmd.radio_sensor_offset_low)) {
  232. IWL_DEBUG_CALIB(trans, "no info in EEPROM, use default\n");
  233. cmd.radio_sensor_offset_low = DEFAULT_RADIO_SENSOR_OFFSET;
  234. cmd.radio_sensor_offset_high = DEFAULT_RADIO_SENSOR_OFFSET;
  235. }
  236. memcpy(&cmd.burntVoltageRef, &hdr->voltage,
  237. sizeof(hdr->voltage));
  238. IWL_DEBUG_CALIB(trans, "Radio sensor offset high: %d\n",
  239. le16_to_cpu(cmd.radio_sensor_offset_high));
  240. IWL_DEBUG_CALIB(trans, "Radio sensor offset low: %d\n",
  241. le16_to_cpu(cmd.radio_sensor_offset_low));
  242. IWL_DEBUG_CALIB(trans, "Voltage Ref: %d\n",
  243. le16_to_cpu(cmd.burntVoltageRef));
  244. return iwl_calib_set(trans, (void *)&cmd, sizeof(cmd));
  245. }
  246. static int iwl_send_calib_cfg(struct iwl_trans *trans)
  247. {
  248. struct iwl_calib_cfg_cmd calib_cfg_cmd;
  249. struct iwl_host_cmd cmd = {
  250. .id = CALIBRATION_CFG_CMD,
  251. .len = { sizeof(struct iwl_calib_cfg_cmd), },
  252. .data = { &calib_cfg_cmd, },
  253. };
  254. memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd));
  255. calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL;
  256. calib_cfg_cmd.ucd_calib_cfg.once.start = IWL_CALIB_INIT_CFG_ALL;
  257. calib_cfg_cmd.ucd_calib_cfg.once.send_res = IWL_CALIB_INIT_CFG_ALL;
  258. calib_cfg_cmd.ucd_calib_cfg.flags =
  259. IWL_CALIB_CFG_FLAG_SEND_COMPLETE_NTFY_MSK;
  260. return iwl_trans_send_cmd(trans, &cmd);
  261. }
  262. int iwlagn_rx_calib_result(struct iwl_priv *priv,
  263. struct iwl_rx_mem_buffer *rxb,
  264. struct iwl_device_cmd *cmd)
  265. {
  266. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  267. struct iwl_calib_hdr *hdr = (struct iwl_calib_hdr *)pkt->u.raw;
  268. int len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
  269. /* reduce the size of the length field itself */
  270. len -= 4;
  271. if (iwl_calib_set(trans(priv), hdr, len))
  272. IWL_ERR(priv, "Failed to record calibration data %d\n",
  273. hdr->op_code);
  274. return 0;
  275. }
  276. int iwl_init_alive_start(struct iwl_trans *trans)
  277. {
  278. int ret;
  279. if (cfg(trans)->bt_params &&
  280. cfg(trans)->bt_params->advanced_bt_coexist) {
  281. /*
  282. * Tell uCode we are ready to perform calibration
  283. * need to perform this before any calibration
  284. * no need to close the envlope since we are going
  285. * to load the runtime uCode later.
  286. */
  287. ret = iwl_send_bt_env(trans, IWL_BT_COEX_ENV_OPEN,
  288. BT_COEX_PRIO_TBL_EVT_INIT_CALIB2);
  289. if (ret)
  290. return ret;
  291. }
  292. ret = iwl_send_calib_cfg(trans);
  293. if (ret)
  294. return ret;
  295. /**
  296. * temperature offset calibration is only needed for runtime ucode,
  297. * so prepare the value now.
  298. */
  299. if (cfg(trans)->need_temp_offset_calib) {
  300. if (cfg(trans)->temp_offset_v2)
  301. return iwl_set_temperature_offset_calib_v2(trans);
  302. else
  303. return iwl_set_temperature_offset_calib(trans);
  304. }
  305. return 0;
  306. }
  307. static int iwl_send_wimax_coex(struct iwl_trans *trans)
  308. {
  309. struct iwl_wimax_coex_cmd coex_cmd;
  310. if (cfg(trans)->base_params->support_wimax_coexist) {
  311. /* UnMask wake up src at associated sleep */
  312. coex_cmd.flags = COEX_FLAGS_ASSOC_WA_UNMASK_MSK;
  313. /* UnMask wake up src at unassociated sleep */
  314. coex_cmd.flags |= COEX_FLAGS_UNASSOC_WA_UNMASK_MSK;
  315. memcpy(coex_cmd.sta_prio, cu_priorities,
  316. sizeof(struct iwl_wimax_coex_event_entry) *
  317. COEX_NUM_OF_EVENTS);
  318. /* enabling the coexistence feature */
  319. coex_cmd.flags |= COEX_FLAGS_COEX_ENABLE_MSK;
  320. /* enabling the priorities tables */
  321. coex_cmd.flags |= COEX_FLAGS_STA_TABLE_VALID_MSK;
  322. } else {
  323. /* coexistence is disabled */
  324. memset(&coex_cmd, 0, sizeof(coex_cmd));
  325. }
  326. return iwl_trans_send_cmd_pdu(trans,
  327. COEX_PRIORITY_TABLE_CMD, CMD_SYNC,
  328. sizeof(coex_cmd), &coex_cmd);
  329. }
  330. static const u8 iwl_bt_prio_tbl[BT_COEX_PRIO_TBL_EVT_MAX] = {
  331. ((BT_COEX_PRIO_TBL_PRIO_BYPASS << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
  332. (0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
  333. ((BT_COEX_PRIO_TBL_PRIO_BYPASS << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
  334. (1 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
  335. ((BT_COEX_PRIO_TBL_PRIO_LOW << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
  336. (0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
  337. ((BT_COEX_PRIO_TBL_PRIO_LOW << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
  338. (1 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
  339. ((BT_COEX_PRIO_TBL_PRIO_HIGH << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
  340. (0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
  341. ((BT_COEX_PRIO_TBL_PRIO_HIGH << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
  342. (1 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
  343. ((BT_COEX_PRIO_TBL_PRIO_BYPASS << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
  344. (0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
  345. ((BT_COEX_PRIO_TBL_PRIO_COEX_OFF << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
  346. (0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
  347. ((BT_COEX_PRIO_TBL_PRIO_COEX_ON << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
  348. (0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
  349. 0, 0, 0, 0, 0, 0, 0
  350. };
  351. void iwl_send_prio_tbl(struct iwl_trans *trans)
  352. {
  353. struct iwl_bt_coex_prio_table_cmd prio_tbl_cmd;
  354. memcpy(prio_tbl_cmd.prio_tbl, iwl_bt_prio_tbl,
  355. sizeof(iwl_bt_prio_tbl));
  356. if (iwl_trans_send_cmd_pdu(trans,
  357. REPLY_BT_COEX_PRIO_TABLE, CMD_SYNC,
  358. sizeof(prio_tbl_cmd), &prio_tbl_cmd))
  359. IWL_ERR(trans, "failed to send BT prio tbl command\n");
  360. }
  361. int iwl_send_bt_env(struct iwl_trans *trans, u8 action, u8 type)
  362. {
  363. struct iwl_bt_coex_prot_env_cmd env_cmd;
  364. int ret;
  365. env_cmd.action = action;
  366. env_cmd.type = type;
  367. ret = iwl_trans_send_cmd_pdu(trans,
  368. REPLY_BT_COEX_PROT_ENV, CMD_SYNC,
  369. sizeof(env_cmd), &env_cmd);
  370. if (ret)
  371. IWL_ERR(trans, "failed to send BT env command\n");
  372. return ret;
  373. }
  374. static int iwl_alive_notify(struct iwl_trans *trans)
  375. {
  376. struct iwl_priv *priv = priv(trans);
  377. struct iwl_rxon_context *ctx;
  378. int ret;
  379. if (!priv->tx_cmd_pool)
  380. priv->tx_cmd_pool =
  381. kmem_cache_create("iwl_dev_cmd",
  382. sizeof(struct iwl_device_cmd),
  383. sizeof(void *), 0, NULL);
  384. if (!priv->tx_cmd_pool)
  385. return -ENOMEM;
  386. iwl_trans_fw_alive(trans);
  387. for_each_context(priv, ctx)
  388. ctx->last_tx_rejected = false;
  389. ret = iwl_send_wimax_coex(trans);
  390. if (ret)
  391. return ret;
  392. if (!cfg(priv)->no_xtal_calib) {
  393. ret = iwl_set_Xtal_calib(trans);
  394. if (ret)
  395. return ret;
  396. }
  397. return iwl_send_calib_results(trans);
  398. }
  399. /**
  400. * iwl_verify_inst_sparse - verify runtime uCode image in card vs. host,
  401. * using sample data 100 bytes apart. If these sample points are good,
  402. * it's a pretty good bet that everything between them is good, too.
  403. */
  404. static int iwl_verify_inst_sparse(struct iwl_trans *trans,
  405. struct fw_desc *fw_desc)
  406. {
  407. __le32 *image = (__le32 *)fw_desc->v_addr;
  408. u32 len = fw_desc->len;
  409. u32 val;
  410. u32 i;
  411. IWL_DEBUG_FW(trans, "ucode inst image size is %u\n", len);
  412. for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
  413. /* read data comes through single port, auto-incr addr */
  414. /* NOTE: Use the debugless read so we don't flood kernel log
  415. * if IWL_DL_IO is set */
  416. iwl_write_direct32(trans, HBUS_TARG_MEM_RADDR,
  417. i + IWLAGN_RTC_INST_LOWER_BOUND);
  418. val = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
  419. if (val != le32_to_cpu(*image))
  420. return -EIO;
  421. }
  422. return 0;
  423. }
  424. static void iwl_print_mismatch_inst(struct iwl_trans *trans,
  425. struct fw_desc *fw_desc)
  426. {
  427. __le32 *image = (__le32 *)fw_desc->v_addr;
  428. u32 len = fw_desc->len;
  429. u32 val;
  430. u32 offs;
  431. int errors = 0;
  432. IWL_DEBUG_FW(trans, "ucode inst image size is %u\n", len);
  433. iwl_write_direct32(trans, HBUS_TARG_MEM_RADDR,
  434. IWLAGN_RTC_INST_LOWER_BOUND);
  435. for (offs = 0;
  436. offs < len && errors < 20;
  437. offs += sizeof(u32), image++) {
  438. /* read data comes through single port, auto-incr addr */
  439. val = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
  440. if (val != le32_to_cpu(*image)) {
  441. IWL_ERR(trans, "uCode INST section at "
  442. "offset 0x%x, is 0x%x, s/b 0x%x\n",
  443. offs, val, le32_to_cpu(*image));
  444. errors++;
  445. }
  446. }
  447. }
  448. /**
  449. * iwl_verify_ucode - determine which instruction image is in SRAM,
  450. * and verify its contents
  451. */
  452. static int iwl_verify_ucode(struct iwl_trans *trans,
  453. enum iwl_ucode_type ucode_type)
  454. {
  455. struct fw_img *img = iwl_get_ucode_image(trans, ucode_type);
  456. if (!img) {
  457. IWL_ERR(trans, "Invalid ucode requested (%d)\n", ucode_type);
  458. return -EINVAL;
  459. }
  460. if (!iwl_verify_inst_sparse(trans, &img->code)) {
  461. IWL_DEBUG_FW(trans, "uCode is good in inst SRAM\n");
  462. return 0;
  463. }
  464. IWL_ERR(trans, "UCODE IMAGE IN INSTRUCTION SRAM NOT VALID!!\n");
  465. iwl_print_mismatch_inst(trans, &img->code);
  466. return -EIO;
  467. }
  468. struct iwl_alive_data {
  469. bool valid;
  470. u8 subtype;
  471. };
  472. static void iwl_alive_fn(struct iwl_trans *trans,
  473. struct iwl_rx_packet *pkt,
  474. void *data)
  475. {
  476. struct iwl_alive_data *alive_data = data;
  477. struct iwl_alive_resp *palive;
  478. palive = &pkt->u.alive_frame;
  479. IWL_DEBUG_FW(trans, "Alive ucode status 0x%08X revision "
  480. "0x%01X 0x%01X\n",
  481. palive->is_valid, palive->ver_type,
  482. palive->ver_subtype);
  483. trans->shrd->device_pointers.error_event_table =
  484. le32_to_cpu(palive->error_event_table_ptr);
  485. trans->shrd->device_pointers.log_event_table =
  486. le32_to_cpu(palive->log_event_table_ptr);
  487. alive_data->subtype = palive->ver_subtype;
  488. alive_data->valid = palive->is_valid == UCODE_VALID_OK;
  489. }
  490. /* notification wait support */
  491. void iwl_init_notification_wait(struct iwl_shared *shrd,
  492. struct iwl_notification_wait *wait_entry,
  493. u8 cmd,
  494. void (*fn)(struct iwl_trans *trans,
  495. struct iwl_rx_packet *pkt,
  496. void *data),
  497. void *fn_data)
  498. {
  499. wait_entry->fn = fn;
  500. wait_entry->fn_data = fn_data;
  501. wait_entry->cmd = cmd;
  502. wait_entry->triggered = false;
  503. wait_entry->aborted = false;
  504. spin_lock_bh(&shrd->notif_wait_lock);
  505. list_add(&wait_entry->list, &shrd->notif_waits);
  506. spin_unlock_bh(&shrd->notif_wait_lock);
  507. }
  508. int iwl_wait_notification(struct iwl_shared *shrd,
  509. struct iwl_notification_wait *wait_entry,
  510. unsigned long timeout)
  511. {
  512. int ret;
  513. ret = wait_event_timeout(shrd->notif_waitq,
  514. wait_entry->triggered || wait_entry->aborted,
  515. timeout);
  516. spin_lock_bh(&shrd->notif_wait_lock);
  517. list_del(&wait_entry->list);
  518. spin_unlock_bh(&shrd->notif_wait_lock);
  519. if (wait_entry->aborted)
  520. return -EIO;
  521. /* return value is always >= 0 */
  522. if (ret <= 0)
  523. return -ETIMEDOUT;
  524. return 0;
  525. }
  526. void iwl_remove_notification(struct iwl_shared *shrd,
  527. struct iwl_notification_wait *wait_entry)
  528. {
  529. spin_lock_bh(&shrd->notif_wait_lock);
  530. list_del(&wait_entry->list);
  531. spin_unlock_bh(&shrd->notif_wait_lock);
  532. }
  533. void iwl_abort_notification_waits(struct iwl_shared *shrd)
  534. {
  535. unsigned long flags;
  536. struct iwl_notification_wait *wait_entry;
  537. spin_lock_irqsave(&shrd->notif_wait_lock, flags);
  538. list_for_each_entry(wait_entry, &shrd->notif_waits, list)
  539. wait_entry->aborted = true;
  540. spin_unlock_irqrestore(&shrd->notif_wait_lock, flags);
  541. wake_up_all(&shrd->notif_waitq);
  542. }
  543. #define UCODE_ALIVE_TIMEOUT HZ
  544. #define UCODE_CALIB_TIMEOUT (2*HZ)
  545. int iwl_load_ucode_wait_alive(struct iwl_trans *trans,
  546. enum iwl_ucode_type ucode_type)
  547. {
  548. struct iwl_notification_wait alive_wait;
  549. struct iwl_alive_data alive_data;
  550. int ret;
  551. enum iwl_ucode_type old_type;
  552. ret = iwl_trans_start_device(trans);
  553. if (ret)
  554. return ret;
  555. iwl_init_notification_wait(trans->shrd, &alive_wait, REPLY_ALIVE,
  556. iwl_alive_fn, &alive_data);
  557. old_type = trans->shrd->ucode_type;
  558. trans->shrd->ucode_type = ucode_type;
  559. ret = iwl_load_given_ucode(trans, ucode_type);
  560. if (ret) {
  561. trans->shrd->ucode_type = old_type;
  562. iwl_remove_notification(trans->shrd, &alive_wait);
  563. return ret;
  564. }
  565. iwl_trans_kick_nic(trans);
  566. /*
  567. * Some things may run in the background now, but we
  568. * just wait for the ALIVE notification here.
  569. */
  570. ret = iwl_wait_notification(trans->shrd, &alive_wait,
  571. UCODE_ALIVE_TIMEOUT);
  572. if (ret) {
  573. trans->shrd->ucode_type = old_type;
  574. return ret;
  575. }
  576. if (!alive_data.valid) {
  577. IWL_ERR(trans, "Loaded ucode is not valid!\n");
  578. trans->shrd->ucode_type = old_type;
  579. return -EIO;
  580. }
  581. /*
  582. * This step takes a long time (60-80ms!!) and
  583. * WoWLAN image should be loaded quickly, so
  584. * skip it for WoWLAN.
  585. */
  586. if (ucode_type != IWL_UCODE_WOWLAN) {
  587. ret = iwl_verify_ucode(trans, ucode_type);
  588. if (ret) {
  589. trans->shrd->ucode_type = old_type;
  590. return ret;
  591. }
  592. /* delay a bit to give rfkill time to run */
  593. msleep(5);
  594. }
  595. ret = iwl_alive_notify(trans);
  596. if (ret) {
  597. IWL_WARN(trans,
  598. "Could not complete ALIVE transition: %d\n", ret);
  599. trans->shrd->ucode_type = old_type;
  600. return ret;
  601. }
  602. return 0;
  603. }
  604. int iwl_run_init_ucode(struct iwl_trans *trans)
  605. {
  606. struct iwl_notification_wait calib_wait;
  607. int ret;
  608. lockdep_assert_held(&trans->shrd->mutex);
  609. /* No init ucode required? Curious, but maybe ok */
  610. if (!trans->ucode_init.code.len)
  611. return 0;
  612. if (trans->shrd->ucode_type != IWL_UCODE_NONE)
  613. return 0;
  614. iwl_init_notification_wait(trans->shrd, &calib_wait,
  615. CALIBRATION_COMPLETE_NOTIFICATION,
  616. NULL, NULL);
  617. /* Will also start the device */
  618. ret = iwl_load_ucode_wait_alive(trans, IWL_UCODE_INIT);
  619. if (ret)
  620. goto error;
  621. ret = iwl_init_alive_start(trans);
  622. if (ret)
  623. goto error;
  624. /*
  625. * Some things may run in the background now, but we
  626. * just wait for the calibration complete notification.
  627. */
  628. ret = iwl_wait_notification(trans->shrd, &calib_wait,
  629. UCODE_CALIB_TIMEOUT);
  630. goto out;
  631. error:
  632. iwl_remove_notification(trans->shrd, &calib_wait);
  633. out:
  634. /* Whatever happened, stop the device */
  635. iwl_trans_stop_device(trans);
  636. return ret;
  637. }