au1550_ac97.c 51 KB

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  1. /*
  2. * au1550_ac97.c -- Sound driver for Alchemy Au1550 MIPS Internet Edge
  3. * Processor.
  4. *
  5. * Copyright 2004 Embedded Edge, LLC
  6. * dan@embeddededge.com
  7. *
  8. * Mostly copied from the au1000.c driver and some from the
  9. * PowerMac dbdma driver.
  10. * We assume the processor can do memory coherent DMA.
  11. *
  12. * Ported to 2.6 by Matt Porter <mporter@kernel.crashing.org>
  13. *
  14. * This program is free software; you can redistribute it and/or modify it
  15. * under the terms of the GNU General Public License as published by the
  16. * Free Software Foundation; either version 2 of the License, or (at your
  17. * option) any later version.
  18. *
  19. * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  20. * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  21. * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  22. * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  23. * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  24. * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  25. * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  26. * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  27. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  28. * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  29. *
  30. * You should have received a copy of the GNU General Public License along
  31. * with this program; if not, write to the Free Software Foundation, Inc.,
  32. * 675 Mass Ave, Cambridge, MA 02139, USA.
  33. *
  34. */
  35. #undef DEBUG
  36. #include <linux/module.h>
  37. #include <linux/string.h>
  38. #include <linux/ioport.h>
  39. #include <linux/sched.h>
  40. #include <linux/delay.h>
  41. #include <linux/sound.h>
  42. #include <linux/slab.h>
  43. #include <linux/soundcard.h>
  44. #include <linux/init.h>
  45. #include <linux/interrupt.h>
  46. #include <linux/kernel.h>
  47. #include <linux/poll.h>
  48. #include <linux/bitops.h>
  49. #include <linux/spinlock.h>
  50. #include <linux/smp_lock.h>
  51. #include <linux/ac97_codec.h>
  52. #include <linux/mutex.h>
  53. #include <asm/io.h>
  54. #include <asm/uaccess.h>
  55. #include <asm/hardirq.h>
  56. #include <asm/mach-au1x00/au1xxx_psc.h>
  57. #include <asm/mach-au1x00/au1xxx_dbdma.h>
  58. #include <asm/mach-au1x00/au1xxx.h>
  59. #undef OSS_DOCUMENTED_MIXER_SEMANTICS
  60. /* misc stuff */
  61. #define POLL_COUNT 0x50000
  62. #define AC97_EXT_DACS (AC97_EXTID_SDAC | AC97_EXTID_CDAC | AC97_EXTID_LDAC)
  63. /* The number of DBDMA ring descriptors to allocate. No sense making
  64. * this too large....if you can't keep up with a few you aren't likely
  65. * to be able to with lots of them, either.
  66. */
  67. #define NUM_DBDMA_DESCRIPTORS 4
  68. #define err(format, arg...) printk(KERN_ERR format "\n" , ## arg)
  69. /* Boot options
  70. * 0 = no VRA, 1 = use VRA if codec supports it
  71. */
  72. static int vra = 1;
  73. module_param(vra, bool, 0);
  74. MODULE_PARM_DESC(vra, "if 1 use VRA if codec supports it");
  75. static struct au1550_state {
  76. /* soundcore stuff */
  77. int dev_audio;
  78. struct ac97_codec *codec;
  79. unsigned codec_base_caps; /* AC'97 reg 00h, "Reset Register" */
  80. unsigned codec_ext_caps; /* AC'97 reg 28h, "Extended Audio ID" */
  81. int no_vra; /* do not use VRA */
  82. spinlock_t lock;
  83. struct mutex open_mutex;
  84. struct mutex sem;
  85. fmode_t open_mode;
  86. wait_queue_head_t open_wait;
  87. struct dmabuf {
  88. u32 dmanr;
  89. unsigned sample_rate;
  90. unsigned src_factor;
  91. unsigned sample_size;
  92. int num_channels;
  93. int dma_bytes_per_sample;
  94. int user_bytes_per_sample;
  95. int cnt_factor;
  96. void *rawbuf;
  97. unsigned buforder;
  98. unsigned numfrag;
  99. unsigned fragshift;
  100. void *nextIn;
  101. void *nextOut;
  102. int count;
  103. unsigned total_bytes;
  104. unsigned error;
  105. wait_queue_head_t wait;
  106. /* redundant, but makes calculations easier */
  107. unsigned fragsize;
  108. unsigned dma_fragsize;
  109. unsigned dmasize;
  110. unsigned dma_qcount;
  111. /* OSS stuff */
  112. unsigned mapped:1;
  113. unsigned ready:1;
  114. unsigned stopped:1;
  115. unsigned ossfragshift;
  116. int ossmaxfrags;
  117. unsigned subdivision;
  118. } dma_dac, dma_adc;
  119. } au1550_state;
  120. static unsigned
  121. ld2(unsigned int x)
  122. {
  123. unsigned r = 0;
  124. if (x >= 0x10000) {
  125. x >>= 16;
  126. r += 16;
  127. }
  128. if (x >= 0x100) {
  129. x >>= 8;
  130. r += 8;
  131. }
  132. if (x >= 0x10) {
  133. x >>= 4;
  134. r += 4;
  135. }
  136. if (x >= 4) {
  137. x >>= 2;
  138. r += 2;
  139. }
  140. if (x >= 2)
  141. r++;
  142. return r;
  143. }
  144. static void
  145. au1550_delay(int msec)
  146. {
  147. unsigned long tmo;
  148. signed long tmo2;
  149. if (in_interrupt())
  150. return;
  151. tmo = jiffies + (msec * HZ) / 1000;
  152. for (;;) {
  153. tmo2 = tmo - jiffies;
  154. if (tmo2 <= 0)
  155. break;
  156. schedule_timeout(tmo2);
  157. }
  158. }
  159. static u16
  160. rdcodec(struct ac97_codec *codec, u8 addr)
  161. {
  162. struct au1550_state *s = (struct au1550_state *)codec->private_data;
  163. unsigned long flags;
  164. u32 cmd, val;
  165. u16 data;
  166. int i;
  167. spin_lock_irqsave(&s->lock, flags);
  168. for (i = 0; i < POLL_COUNT; i++) {
  169. val = au_readl(PSC_AC97STAT);
  170. au_sync();
  171. if (!(val & PSC_AC97STAT_CP))
  172. break;
  173. }
  174. if (i == POLL_COUNT)
  175. err("rdcodec: codec cmd pending expired!");
  176. cmd = (u32)PSC_AC97CDC_INDX(addr);
  177. cmd |= PSC_AC97CDC_RD; /* read command */
  178. au_writel(cmd, PSC_AC97CDC);
  179. au_sync();
  180. /* now wait for the data
  181. */
  182. for (i = 0; i < POLL_COUNT; i++) {
  183. val = au_readl(PSC_AC97STAT);
  184. au_sync();
  185. if (!(val & PSC_AC97STAT_CP))
  186. break;
  187. }
  188. if (i == POLL_COUNT) {
  189. err("rdcodec: read poll expired!");
  190. data = 0;
  191. goto out;
  192. }
  193. /* wait for command done?
  194. */
  195. for (i = 0; i < POLL_COUNT; i++) {
  196. val = au_readl(PSC_AC97EVNT);
  197. au_sync();
  198. if (val & PSC_AC97EVNT_CD)
  199. break;
  200. }
  201. if (i == POLL_COUNT) {
  202. err("rdcodec: read cmdwait expired!");
  203. data = 0;
  204. goto out;
  205. }
  206. data = au_readl(PSC_AC97CDC) & 0xffff;
  207. au_sync();
  208. /* Clear command done event.
  209. */
  210. au_writel(PSC_AC97EVNT_CD, PSC_AC97EVNT);
  211. au_sync();
  212. out:
  213. spin_unlock_irqrestore(&s->lock, flags);
  214. return data;
  215. }
  216. static void
  217. wrcodec(struct ac97_codec *codec, u8 addr, u16 data)
  218. {
  219. struct au1550_state *s = (struct au1550_state *)codec->private_data;
  220. unsigned long flags;
  221. u32 cmd, val;
  222. int i;
  223. spin_lock_irqsave(&s->lock, flags);
  224. for (i = 0; i < POLL_COUNT; i++) {
  225. val = au_readl(PSC_AC97STAT);
  226. au_sync();
  227. if (!(val & PSC_AC97STAT_CP))
  228. break;
  229. }
  230. if (i == POLL_COUNT)
  231. err("wrcodec: codec cmd pending expired!");
  232. cmd = (u32)PSC_AC97CDC_INDX(addr);
  233. cmd |= (u32)data;
  234. au_writel(cmd, PSC_AC97CDC);
  235. au_sync();
  236. for (i = 0; i < POLL_COUNT; i++) {
  237. val = au_readl(PSC_AC97STAT);
  238. au_sync();
  239. if (!(val & PSC_AC97STAT_CP))
  240. break;
  241. }
  242. if (i == POLL_COUNT)
  243. err("wrcodec: codec cmd pending expired!");
  244. for (i = 0; i < POLL_COUNT; i++) {
  245. val = au_readl(PSC_AC97EVNT);
  246. au_sync();
  247. if (val & PSC_AC97EVNT_CD)
  248. break;
  249. }
  250. if (i == POLL_COUNT)
  251. err("wrcodec: read cmdwait expired!");
  252. /* Clear command done event.
  253. */
  254. au_writel(PSC_AC97EVNT_CD, PSC_AC97EVNT);
  255. au_sync();
  256. spin_unlock_irqrestore(&s->lock, flags);
  257. }
  258. static void
  259. waitcodec(struct ac97_codec *codec)
  260. {
  261. u16 temp;
  262. u32 val;
  263. int i;
  264. /* codec_wait is used to wait for a ready state after
  265. * an AC97C_RESET.
  266. */
  267. au1550_delay(10);
  268. /* first poll the CODEC_READY tag bit
  269. */
  270. for (i = 0; i < POLL_COUNT; i++) {
  271. val = au_readl(PSC_AC97STAT);
  272. au_sync();
  273. if (val & PSC_AC97STAT_CR)
  274. break;
  275. }
  276. if (i == POLL_COUNT) {
  277. err("waitcodec: CODEC_READY poll expired!");
  278. return;
  279. }
  280. /* get AC'97 powerdown control/status register
  281. */
  282. temp = rdcodec(codec, AC97_POWER_CONTROL);
  283. /* If anything is powered down, power'em up
  284. */
  285. if (temp & 0x7f00) {
  286. /* Power on
  287. */
  288. wrcodec(codec, AC97_POWER_CONTROL, 0);
  289. au1550_delay(100);
  290. /* Reread
  291. */
  292. temp = rdcodec(codec, AC97_POWER_CONTROL);
  293. }
  294. /* Check if Codec REF,ANL,DAC,ADC ready
  295. */
  296. if ((temp & 0x7f0f) != 0x000f)
  297. err("codec reg 26 status (0x%x) not ready!!", temp);
  298. }
  299. /* stop the ADC before calling */
  300. static void
  301. set_adc_rate(struct au1550_state *s, unsigned rate)
  302. {
  303. struct dmabuf *adc = &s->dma_adc;
  304. struct dmabuf *dac = &s->dma_dac;
  305. unsigned adc_rate, dac_rate;
  306. u16 ac97_extstat;
  307. if (s->no_vra) {
  308. /* calc SRC factor
  309. */
  310. adc->src_factor = ((96000 / rate) + 1) >> 1;
  311. adc->sample_rate = 48000 / adc->src_factor;
  312. return;
  313. }
  314. adc->src_factor = 1;
  315. ac97_extstat = rdcodec(s->codec, AC97_EXTENDED_STATUS);
  316. rate = rate > 48000 ? 48000 : rate;
  317. /* enable VRA
  318. */
  319. wrcodec(s->codec, AC97_EXTENDED_STATUS,
  320. ac97_extstat | AC97_EXTSTAT_VRA);
  321. /* now write the sample rate
  322. */
  323. wrcodec(s->codec, AC97_PCM_LR_ADC_RATE, (u16) rate);
  324. /* read it back for actual supported rate
  325. */
  326. adc_rate = rdcodec(s->codec, AC97_PCM_LR_ADC_RATE);
  327. pr_debug("set_adc_rate: set to %d Hz\n", adc_rate);
  328. /* some codec's don't allow unequal DAC and ADC rates, in which case
  329. * writing one rate reg actually changes both.
  330. */
  331. dac_rate = rdcodec(s->codec, AC97_PCM_FRONT_DAC_RATE);
  332. if (dac->num_channels > 2)
  333. wrcodec(s->codec, AC97_PCM_SURR_DAC_RATE, dac_rate);
  334. if (dac->num_channels > 4)
  335. wrcodec(s->codec, AC97_PCM_LFE_DAC_RATE, dac_rate);
  336. adc->sample_rate = adc_rate;
  337. dac->sample_rate = dac_rate;
  338. }
  339. /* stop the DAC before calling */
  340. static void
  341. set_dac_rate(struct au1550_state *s, unsigned rate)
  342. {
  343. struct dmabuf *dac = &s->dma_dac;
  344. struct dmabuf *adc = &s->dma_adc;
  345. unsigned adc_rate, dac_rate;
  346. u16 ac97_extstat;
  347. if (s->no_vra) {
  348. /* calc SRC factor
  349. */
  350. dac->src_factor = ((96000 / rate) + 1) >> 1;
  351. dac->sample_rate = 48000 / dac->src_factor;
  352. return;
  353. }
  354. dac->src_factor = 1;
  355. ac97_extstat = rdcodec(s->codec, AC97_EXTENDED_STATUS);
  356. rate = rate > 48000 ? 48000 : rate;
  357. /* enable VRA
  358. */
  359. wrcodec(s->codec, AC97_EXTENDED_STATUS,
  360. ac97_extstat | AC97_EXTSTAT_VRA);
  361. /* now write the sample rate
  362. */
  363. wrcodec(s->codec, AC97_PCM_FRONT_DAC_RATE, (u16) rate);
  364. /* I don't support different sample rates for multichannel,
  365. * so make these channels the same.
  366. */
  367. if (dac->num_channels > 2)
  368. wrcodec(s->codec, AC97_PCM_SURR_DAC_RATE, (u16) rate);
  369. if (dac->num_channels > 4)
  370. wrcodec(s->codec, AC97_PCM_LFE_DAC_RATE, (u16) rate);
  371. /* read it back for actual supported rate
  372. */
  373. dac_rate = rdcodec(s->codec, AC97_PCM_FRONT_DAC_RATE);
  374. pr_debug("set_dac_rate: set to %d Hz\n", dac_rate);
  375. /* some codec's don't allow unequal DAC and ADC rates, in which case
  376. * writing one rate reg actually changes both.
  377. */
  378. adc_rate = rdcodec(s->codec, AC97_PCM_LR_ADC_RATE);
  379. dac->sample_rate = dac_rate;
  380. adc->sample_rate = adc_rate;
  381. }
  382. static void
  383. stop_dac(struct au1550_state *s)
  384. {
  385. struct dmabuf *db = &s->dma_dac;
  386. u32 stat;
  387. unsigned long flags;
  388. if (db->stopped)
  389. return;
  390. spin_lock_irqsave(&s->lock, flags);
  391. au_writel(PSC_AC97PCR_TP, PSC_AC97PCR);
  392. au_sync();
  393. /* Wait for Transmit Busy to show disabled.
  394. */
  395. do {
  396. stat = au_readl(PSC_AC97STAT);
  397. au_sync();
  398. } while ((stat & PSC_AC97STAT_TB) != 0);
  399. au1xxx_dbdma_reset(db->dmanr);
  400. db->stopped = 1;
  401. spin_unlock_irqrestore(&s->lock, flags);
  402. }
  403. static void
  404. stop_adc(struct au1550_state *s)
  405. {
  406. struct dmabuf *db = &s->dma_adc;
  407. unsigned long flags;
  408. u32 stat;
  409. if (db->stopped)
  410. return;
  411. spin_lock_irqsave(&s->lock, flags);
  412. au_writel(PSC_AC97PCR_RP, PSC_AC97PCR);
  413. au_sync();
  414. /* Wait for Receive Busy to show disabled.
  415. */
  416. do {
  417. stat = au_readl(PSC_AC97STAT);
  418. au_sync();
  419. } while ((stat & PSC_AC97STAT_RB) != 0);
  420. au1xxx_dbdma_reset(db->dmanr);
  421. db->stopped = 1;
  422. spin_unlock_irqrestore(&s->lock, flags);
  423. }
  424. static void
  425. set_xmit_slots(int num_channels)
  426. {
  427. u32 ac97_config, stat;
  428. ac97_config = au_readl(PSC_AC97CFG);
  429. au_sync();
  430. ac97_config &= ~(PSC_AC97CFG_TXSLOT_MASK | PSC_AC97CFG_DE_ENABLE);
  431. au_writel(ac97_config, PSC_AC97CFG);
  432. au_sync();
  433. switch (num_channels) {
  434. case 6: /* stereo with surround and center/LFE,
  435. * slots 3,4,6,7,8,9
  436. */
  437. ac97_config |= PSC_AC97CFG_TXSLOT_ENA(6);
  438. ac97_config |= PSC_AC97CFG_TXSLOT_ENA(9);
  439. case 4: /* stereo with surround, slots 3,4,7,8 */
  440. ac97_config |= PSC_AC97CFG_TXSLOT_ENA(7);
  441. ac97_config |= PSC_AC97CFG_TXSLOT_ENA(8);
  442. case 2: /* stereo, slots 3,4 */
  443. case 1: /* mono */
  444. ac97_config |= PSC_AC97CFG_TXSLOT_ENA(3);
  445. ac97_config |= PSC_AC97CFG_TXSLOT_ENA(4);
  446. }
  447. au_writel(ac97_config, PSC_AC97CFG);
  448. au_sync();
  449. ac97_config |= PSC_AC97CFG_DE_ENABLE;
  450. au_writel(ac97_config, PSC_AC97CFG);
  451. au_sync();
  452. /* Wait for Device ready.
  453. */
  454. do {
  455. stat = au_readl(PSC_AC97STAT);
  456. au_sync();
  457. } while ((stat & PSC_AC97STAT_DR) == 0);
  458. }
  459. static void
  460. set_recv_slots(int num_channels)
  461. {
  462. u32 ac97_config, stat;
  463. ac97_config = au_readl(PSC_AC97CFG);
  464. au_sync();
  465. ac97_config &= ~(PSC_AC97CFG_RXSLOT_MASK | PSC_AC97CFG_DE_ENABLE);
  466. au_writel(ac97_config, PSC_AC97CFG);
  467. au_sync();
  468. /* Always enable slots 3 and 4 (stereo). Slot 6 is
  469. * optional Mic ADC, which we don't support yet.
  470. */
  471. ac97_config |= PSC_AC97CFG_RXSLOT_ENA(3);
  472. ac97_config |= PSC_AC97CFG_RXSLOT_ENA(4);
  473. au_writel(ac97_config, PSC_AC97CFG);
  474. au_sync();
  475. ac97_config |= PSC_AC97CFG_DE_ENABLE;
  476. au_writel(ac97_config, PSC_AC97CFG);
  477. au_sync();
  478. /* Wait for Device ready.
  479. */
  480. do {
  481. stat = au_readl(PSC_AC97STAT);
  482. au_sync();
  483. } while ((stat & PSC_AC97STAT_DR) == 0);
  484. }
  485. /* Hold spinlock for both start_dac() and start_adc() calls */
  486. static void
  487. start_dac(struct au1550_state *s)
  488. {
  489. struct dmabuf *db = &s->dma_dac;
  490. if (!db->stopped)
  491. return;
  492. set_xmit_slots(db->num_channels);
  493. au_writel(PSC_AC97PCR_TC, PSC_AC97PCR);
  494. au_sync();
  495. au_writel(PSC_AC97PCR_TS, PSC_AC97PCR);
  496. au_sync();
  497. au1xxx_dbdma_start(db->dmanr);
  498. db->stopped = 0;
  499. }
  500. static void
  501. start_adc(struct au1550_state *s)
  502. {
  503. struct dmabuf *db = &s->dma_adc;
  504. int i;
  505. if (!db->stopped)
  506. return;
  507. /* Put two buffers on the ring to get things started.
  508. */
  509. for (i=0; i<2; i++) {
  510. au1xxx_dbdma_put_dest(db->dmanr, db->nextIn,
  511. db->dma_fragsize, DDMA_FLAGS_IE);
  512. db->nextIn += db->dma_fragsize;
  513. if (db->nextIn >= db->rawbuf + db->dmasize)
  514. db->nextIn -= db->dmasize;
  515. }
  516. set_recv_slots(db->num_channels);
  517. au1xxx_dbdma_start(db->dmanr);
  518. au_writel(PSC_AC97PCR_RC, PSC_AC97PCR);
  519. au_sync();
  520. au_writel(PSC_AC97PCR_RS, PSC_AC97PCR);
  521. au_sync();
  522. db->stopped = 0;
  523. }
  524. static int
  525. prog_dmabuf(struct au1550_state *s, struct dmabuf *db)
  526. {
  527. unsigned user_bytes_per_sec;
  528. unsigned bufs;
  529. unsigned rate = db->sample_rate;
  530. if (!db->rawbuf) {
  531. db->ready = db->mapped = 0;
  532. db->buforder = 5; /* 32 * PAGE_SIZE */
  533. db->rawbuf = kmalloc((PAGE_SIZE << db->buforder), GFP_KERNEL);
  534. if (!db->rawbuf)
  535. return -ENOMEM;
  536. }
  537. db->cnt_factor = 1;
  538. if (db->sample_size == 8)
  539. db->cnt_factor *= 2;
  540. if (db->num_channels == 1)
  541. db->cnt_factor *= 2;
  542. db->cnt_factor *= db->src_factor;
  543. db->count = 0;
  544. db->dma_qcount = 0;
  545. db->nextIn = db->nextOut = db->rawbuf;
  546. db->user_bytes_per_sample = (db->sample_size>>3) * db->num_channels;
  547. db->dma_bytes_per_sample = 2 * ((db->num_channels == 1) ?
  548. 2 : db->num_channels);
  549. user_bytes_per_sec = rate * db->user_bytes_per_sample;
  550. bufs = PAGE_SIZE << db->buforder;
  551. if (db->ossfragshift) {
  552. if ((1000 << db->ossfragshift) < user_bytes_per_sec)
  553. db->fragshift = ld2(user_bytes_per_sec/1000);
  554. else
  555. db->fragshift = db->ossfragshift;
  556. } else {
  557. db->fragshift = ld2(user_bytes_per_sec / 100 /
  558. (db->subdivision ? db->subdivision : 1));
  559. if (db->fragshift < 3)
  560. db->fragshift = 3;
  561. }
  562. db->fragsize = 1 << db->fragshift;
  563. db->dma_fragsize = db->fragsize * db->cnt_factor;
  564. db->numfrag = bufs / db->dma_fragsize;
  565. while (db->numfrag < 4 && db->fragshift > 3) {
  566. db->fragshift--;
  567. db->fragsize = 1 << db->fragshift;
  568. db->dma_fragsize = db->fragsize * db->cnt_factor;
  569. db->numfrag = bufs / db->dma_fragsize;
  570. }
  571. if (db->ossmaxfrags >= 4 && db->ossmaxfrags < db->numfrag)
  572. db->numfrag = db->ossmaxfrags;
  573. db->dmasize = db->dma_fragsize * db->numfrag;
  574. memset(db->rawbuf, 0, bufs);
  575. pr_debug("prog_dmabuf: rate=%d, samplesize=%d, channels=%d\n",
  576. rate, db->sample_size, db->num_channels);
  577. pr_debug("prog_dmabuf: fragsize=%d, cnt_factor=%d, dma_fragsize=%d\n",
  578. db->fragsize, db->cnt_factor, db->dma_fragsize);
  579. pr_debug("prog_dmabuf: numfrag=%d, dmasize=%d\n", db->numfrag, db->dmasize);
  580. db->ready = 1;
  581. return 0;
  582. }
  583. static int
  584. prog_dmabuf_adc(struct au1550_state *s)
  585. {
  586. stop_adc(s);
  587. return prog_dmabuf(s, &s->dma_adc);
  588. }
  589. static int
  590. prog_dmabuf_dac(struct au1550_state *s)
  591. {
  592. stop_dac(s);
  593. return prog_dmabuf(s, &s->dma_dac);
  594. }
  595. static void dac_dma_interrupt(int irq, void *dev_id)
  596. {
  597. struct au1550_state *s = (struct au1550_state *) dev_id;
  598. struct dmabuf *db = &s->dma_dac;
  599. u32 ac97c_stat;
  600. spin_lock(&s->lock);
  601. ac97c_stat = au_readl(PSC_AC97STAT);
  602. if (ac97c_stat & (AC97C_XU | AC97C_XO | AC97C_TE))
  603. pr_debug("AC97C status = 0x%08x\n", ac97c_stat);
  604. db->dma_qcount--;
  605. if (db->count >= db->fragsize) {
  606. if (au1xxx_dbdma_put_source(db->dmanr, db->nextOut,
  607. db->fragsize, DDMA_FLAGS_IE) == 0) {
  608. err("qcount < 2 and no ring room!");
  609. }
  610. db->nextOut += db->fragsize;
  611. if (db->nextOut >= db->rawbuf + db->dmasize)
  612. db->nextOut -= db->dmasize;
  613. db->count -= db->fragsize;
  614. db->total_bytes += db->dma_fragsize;
  615. db->dma_qcount++;
  616. }
  617. /* wake up anybody listening */
  618. if (waitqueue_active(&db->wait))
  619. wake_up(&db->wait);
  620. spin_unlock(&s->lock);
  621. }
  622. static void adc_dma_interrupt(int irq, void *dev_id)
  623. {
  624. struct au1550_state *s = (struct au1550_state *)dev_id;
  625. struct dmabuf *dp = &s->dma_adc;
  626. u32 obytes;
  627. char *obuf;
  628. spin_lock(&s->lock);
  629. /* Pull the buffer from the dma queue.
  630. */
  631. au1xxx_dbdma_get_dest(dp->dmanr, (void *)(&obuf), &obytes);
  632. if ((dp->count + obytes) > dp->dmasize) {
  633. /* Overrun. Stop ADC and log the error
  634. */
  635. spin_unlock(&s->lock);
  636. stop_adc(s);
  637. dp->error++;
  638. err("adc overrun");
  639. return;
  640. }
  641. /* Put a new empty buffer on the destination DMA.
  642. */
  643. au1xxx_dbdma_put_dest(dp->dmanr, dp->nextIn,
  644. dp->dma_fragsize, DDMA_FLAGS_IE);
  645. dp->nextIn += dp->dma_fragsize;
  646. if (dp->nextIn >= dp->rawbuf + dp->dmasize)
  647. dp->nextIn -= dp->dmasize;
  648. dp->count += obytes;
  649. dp->total_bytes += obytes;
  650. /* wake up anybody listening
  651. */
  652. if (waitqueue_active(&dp->wait))
  653. wake_up(&dp->wait);
  654. spin_unlock(&s->lock);
  655. }
  656. static loff_t
  657. au1550_llseek(struct file *file, loff_t offset, int origin)
  658. {
  659. return -ESPIPE;
  660. }
  661. static int
  662. au1550_open_mixdev(struct inode *inode, struct file *file)
  663. {
  664. file->private_data = &au1550_state;
  665. return 0;
  666. }
  667. static int
  668. au1550_release_mixdev(struct inode *inode, struct file *file)
  669. {
  670. return 0;
  671. }
  672. static int
  673. mixdev_ioctl(struct ac97_codec *codec, unsigned int cmd,
  674. unsigned long arg)
  675. {
  676. return codec->mixer_ioctl(codec, cmd, arg);
  677. }
  678. static int
  679. au1550_ioctl_mixdev(struct inode *inode, struct file *file,
  680. unsigned int cmd, unsigned long arg)
  681. {
  682. struct au1550_state *s = (struct au1550_state *)file->private_data;
  683. struct ac97_codec *codec = s->codec;
  684. return mixdev_ioctl(codec, cmd, arg);
  685. }
  686. static /*const */ struct file_operations au1550_mixer_fops = {
  687. owner:THIS_MODULE,
  688. llseek:au1550_llseek,
  689. ioctl:au1550_ioctl_mixdev,
  690. open:au1550_open_mixdev,
  691. release:au1550_release_mixdev,
  692. };
  693. static int
  694. drain_dac(struct au1550_state *s, int nonblock)
  695. {
  696. unsigned long flags;
  697. int count, tmo;
  698. if (s->dma_dac.mapped || !s->dma_dac.ready || s->dma_dac.stopped)
  699. return 0;
  700. for (;;) {
  701. spin_lock_irqsave(&s->lock, flags);
  702. count = s->dma_dac.count;
  703. spin_unlock_irqrestore(&s->lock, flags);
  704. if (count <= s->dma_dac.fragsize)
  705. break;
  706. if (signal_pending(current))
  707. break;
  708. if (nonblock)
  709. return -EBUSY;
  710. tmo = 1000 * count / (s->no_vra ?
  711. 48000 : s->dma_dac.sample_rate);
  712. tmo /= s->dma_dac.dma_bytes_per_sample;
  713. au1550_delay(tmo);
  714. }
  715. if (signal_pending(current))
  716. return -ERESTARTSYS;
  717. return 0;
  718. }
  719. static inline u8 S16_TO_U8(s16 ch)
  720. {
  721. return (u8) (ch >> 8) + 0x80;
  722. }
  723. static inline s16 U8_TO_S16(u8 ch)
  724. {
  725. return (s16) (ch - 0x80) << 8;
  726. }
  727. /*
  728. * Translates user samples to dma buffer suitable for AC'97 DAC data:
  729. * If mono, copy left channel to right channel in dma buffer.
  730. * If 8 bit samples, cvt to 16-bit before writing to dma buffer.
  731. * If interpolating (no VRA), duplicate every audio frame src_factor times.
  732. */
  733. static int
  734. translate_from_user(struct dmabuf *db, char* dmabuf, char* userbuf,
  735. int dmacount)
  736. {
  737. int sample, i;
  738. int interp_bytes_per_sample;
  739. int num_samples;
  740. int mono = (db->num_channels == 1);
  741. char usersample[12];
  742. s16 ch, dmasample[6];
  743. if (db->sample_size == 16 && !mono && db->src_factor == 1) {
  744. /* no translation necessary, just copy
  745. */
  746. if (copy_from_user(dmabuf, userbuf, dmacount))
  747. return -EFAULT;
  748. return dmacount;
  749. }
  750. interp_bytes_per_sample = db->dma_bytes_per_sample * db->src_factor;
  751. num_samples = dmacount / interp_bytes_per_sample;
  752. for (sample = 0; sample < num_samples; sample++) {
  753. if (copy_from_user(usersample, userbuf,
  754. db->user_bytes_per_sample)) {
  755. return -EFAULT;
  756. }
  757. for (i = 0; i < db->num_channels; i++) {
  758. if (db->sample_size == 8)
  759. ch = U8_TO_S16(usersample[i]);
  760. else
  761. ch = *((s16 *) (&usersample[i * 2]));
  762. dmasample[i] = ch;
  763. if (mono)
  764. dmasample[i + 1] = ch; /* right channel */
  765. }
  766. /* duplicate every audio frame src_factor times
  767. */
  768. for (i = 0; i < db->src_factor; i++)
  769. memcpy(dmabuf, dmasample, db->dma_bytes_per_sample);
  770. userbuf += db->user_bytes_per_sample;
  771. dmabuf += interp_bytes_per_sample;
  772. }
  773. return num_samples * interp_bytes_per_sample;
  774. }
  775. /*
  776. * Translates AC'97 ADC samples to user buffer:
  777. * If mono, send only left channel to user buffer.
  778. * If 8 bit samples, cvt from 16 to 8 bit before writing to user buffer.
  779. * If decimating (no VRA), skip over src_factor audio frames.
  780. */
  781. static int
  782. translate_to_user(struct dmabuf *db, char* userbuf, char* dmabuf,
  783. int dmacount)
  784. {
  785. int sample, i;
  786. int interp_bytes_per_sample;
  787. int num_samples;
  788. int mono = (db->num_channels == 1);
  789. char usersample[12];
  790. if (db->sample_size == 16 && !mono && db->src_factor == 1) {
  791. /* no translation necessary, just copy
  792. */
  793. if (copy_to_user(userbuf, dmabuf, dmacount))
  794. return -EFAULT;
  795. return dmacount;
  796. }
  797. interp_bytes_per_sample = db->dma_bytes_per_sample * db->src_factor;
  798. num_samples = dmacount / interp_bytes_per_sample;
  799. for (sample = 0; sample < num_samples; sample++) {
  800. for (i = 0; i < db->num_channels; i++) {
  801. if (db->sample_size == 8)
  802. usersample[i] =
  803. S16_TO_U8(*((s16 *) (&dmabuf[i * 2])));
  804. else
  805. *((s16 *) (&usersample[i * 2])) =
  806. *((s16 *) (&dmabuf[i * 2]));
  807. }
  808. if (copy_to_user(userbuf, usersample,
  809. db->user_bytes_per_sample)) {
  810. return -EFAULT;
  811. }
  812. userbuf += db->user_bytes_per_sample;
  813. dmabuf += interp_bytes_per_sample;
  814. }
  815. return num_samples * interp_bytes_per_sample;
  816. }
  817. /*
  818. * Copy audio data to/from user buffer from/to dma buffer, taking care
  819. * that we wrap when reading/writing the dma buffer. Returns actual byte
  820. * count written to or read from the dma buffer.
  821. */
  822. static int
  823. copy_dmabuf_user(struct dmabuf *db, char* userbuf, int count, int to_user)
  824. {
  825. char *bufptr = to_user ? db->nextOut : db->nextIn;
  826. char *bufend = db->rawbuf + db->dmasize;
  827. int cnt, ret;
  828. if (bufptr + count > bufend) {
  829. int partial = (int) (bufend - bufptr);
  830. if (to_user) {
  831. if ((cnt = translate_to_user(db, userbuf,
  832. bufptr, partial)) < 0)
  833. return cnt;
  834. ret = cnt;
  835. if ((cnt = translate_to_user(db, userbuf + partial,
  836. db->rawbuf,
  837. count - partial)) < 0)
  838. return cnt;
  839. ret += cnt;
  840. } else {
  841. if ((cnt = translate_from_user(db, bufptr, userbuf,
  842. partial)) < 0)
  843. return cnt;
  844. ret = cnt;
  845. if ((cnt = translate_from_user(db, db->rawbuf,
  846. userbuf + partial,
  847. count - partial)) < 0)
  848. return cnt;
  849. ret += cnt;
  850. }
  851. } else {
  852. if (to_user)
  853. ret = translate_to_user(db, userbuf, bufptr, count);
  854. else
  855. ret = translate_from_user(db, bufptr, userbuf, count);
  856. }
  857. return ret;
  858. }
  859. static ssize_t
  860. au1550_read(struct file *file, char *buffer, size_t count, loff_t *ppos)
  861. {
  862. struct au1550_state *s = (struct au1550_state *)file->private_data;
  863. struct dmabuf *db = &s->dma_adc;
  864. DECLARE_WAITQUEUE(wait, current);
  865. ssize_t ret;
  866. unsigned long flags;
  867. int cnt, usercnt, avail;
  868. if (db->mapped)
  869. return -ENXIO;
  870. if (!access_ok(VERIFY_WRITE, buffer, count))
  871. return -EFAULT;
  872. ret = 0;
  873. count *= db->cnt_factor;
  874. mutex_lock(&s->sem);
  875. add_wait_queue(&db->wait, &wait);
  876. while (count > 0) {
  877. /* wait for samples in ADC dma buffer
  878. */
  879. do {
  880. spin_lock_irqsave(&s->lock, flags);
  881. if (db->stopped)
  882. start_adc(s);
  883. avail = db->count;
  884. if (avail <= 0)
  885. __set_current_state(TASK_INTERRUPTIBLE);
  886. spin_unlock_irqrestore(&s->lock, flags);
  887. if (avail <= 0) {
  888. if (file->f_flags & O_NONBLOCK) {
  889. if (!ret)
  890. ret = -EAGAIN;
  891. goto out;
  892. }
  893. mutex_unlock(&s->sem);
  894. schedule();
  895. if (signal_pending(current)) {
  896. if (!ret)
  897. ret = -ERESTARTSYS;
  898. goto out2;
  899. }
  900. mutex_lock(&s->sem);
  901. }
  902. } while (avail <= 0);
  903. /* copy from nextOut to user
  904. */
  905. if ((cnt = copy_dmabuf_user(db, buffer,
  906. count > avail ?
  907. avail : count, 1)) < 0) {
  908. if (!ret)
  909. ret = -EFAULT;
  910. goto out;
  911. }
  912. spin_lock_irqsave(&s->lock, flags);
  913. db->count -= cnt;
  914. db->nextOut += cnt;
  915. if (db->nextOut >= db->rawbuf + db->dmasize)
  916. db->nextOut -= db->dmasize;
  917. spin_unlock_irqrestore(&s->lock, flags);
  918. count -= cnt;
  919. usercnt = cnt / db->cnt_factor;
  920. buffer += usercnt;
  921. ret += usercnt;
  922. } /* while (count > 0) */
  923. out:
  924. mutex_unlock(&s->sem);
  925. out2:
  926. remove_wait_queue(&db->wait, &wait);
  927. set_current_state(TASK_RUNNING);
  928. return ret;
  929. }
  930. static ssize_t
  931. au1550_write(struct file *file, const char *buffer, size_t count, loff_t * ppos)
  932. {
  933. struct au1550_state *s = (struct au1550_state *)file->private_data;
  934. struct dmabuf *db = &s->dma_dac;
  935. DECLARE_WAITQUEUE(wait, current);
  936. ssize_t ret = 0;
  937. unsigned long flags;
  938. int cnt, usercnt, avail;
  939. pr_debug("write: count=%d\n", count);
  940. if (db->mapped)
  941. return -ENXIO;
  942. if (!access_ok(VERIFY_READ, buffer, count))
  943. return -EFAULT;
  944. count *= db->cnt_factor;
  945. mutex_lock(&s->sem);
  946. add_wait_queue(&db->wait, &wait);
  947. while (count > 0) {
  948. /* wait for space in playback buffer
  949. */
  950. do {
  951. spin_lock_irqsave(&s->lock, flags);
  952. avail = (int) db->dmasize - db->count;
  953. if (avail <= 0)
  954. __set_current_state(TASK_INTERRUPTIBLE);
  955. spin_unlock_irqrestore(&s->lock, flags);
  956. if (avail <= 0) {
  957. if (file->f_flags & O_NONBLOCK) {
  958. if (!ret)
  959. ret = -EAGAIN;
  960. goto out;
  961. }
  962. mutex_unlock(&s->sem);
  963. schedule();
  964. if (signal_pending(current)) {
  965. if (!ret)
  966. ret = -ERESTARTSYS;
  967. goto out2;
  968. }
  969. mutex_lock(&s->sem);
  970. }
  971. } while (avail <= 0);
  972. /* copy from user to nextIn
  973. */
  974. if ((cnt = copy_dmabuf_user(db, (char *) buffer,
  975. count > avail ?
  976. avail : count, 0)) < 0) {
  977. if (!ret)
  978. ret = -EFAULT;
  979. goto out;
  980. }
  981. spin_lock_irqsave(&s->lock, flags);
  982. db->count += cnt;
  983. db->nextIn += cnt;
  984. if (db->nextIn >= db->rawbuf + db->dmasize)
  985. db->nextIn -= db->dmasize;
  986. /* If the data is available, we want to keep two buffers
  987. * on the dma queue. If the queue count reaches zero,
  988. * we know the dma has stopped.
  989. */
  990. while ((db->dma_qcount < 2) && (db->count >= db->fragsize)) {
  991. if (au1xxx_dbdma_put_source(db->dmanr,
  992. db->nextOut, db->fragsize, DDMA_FLAGS_IE) == 0) {
  993. err("qcount < 2 and no ring room!");
  994. }
  995. db->nextOut += db->fragsize;
  996. if (db->nextOut >= db->rawbuf + db->dmasize)
  997. db->nextOut -= db->dmasize;
  998. db->total_bytes += db->dma_fragsize;
  999. if (db->dma_qcount == 0)
  1000. start_dac(s);
  1001. db->dma_qcount++;
  1002. }
  1003. spin_unlock_irqrestore(&s->lock, flags);
  1004. count -= cnt;
  1005. usercnt = cnt / db->cnt_factor;
  1006. buffer += usercnt;
  1007. ret += usercnt;
  1008. } /* while (count > 0) */
  1009. out:
  1010. mutex_unlock(&s->sem);
  1011. out2:
  1012. remove_wait_queue(&db->wait, &wait);
  1013. set_current_state(TASK_RUNNING);
  1014. return ret;
  1015. }
  1016. /* No kernel lock - we have our own spinlock */
  1017. static unsigned int
  1018. au1550_poll(struct file *file, struct poll_table_struct *wait)
  1019. {
  1020. struct au1550_state *s = (struct au1550_state *)file->private_data;
  1021. unsigned long flags;
  1022. unsigned int mask = 0;
  1023. if (file->f_mode & FMODE_WRITE) {
  1024. if (!s->dma_dac.ready)
  1025. return 0;
  1026. poll_wait(file, &s->dma_dac.wait, wait);
  1027. }
  1028. if (file->f_mode & FMODE_READ) {
  1029. if (!s->dma_adc.ready)
  1030. return 0;
  1031. poll_wait(file, &s->dma_adc.wait, wait);
  1032. }
  1033. spin_lock_irqsave(&s->lock, flags);
  1034. if (file->f_mode & FMODE_READ) {
  1035. if (s->dma_adc.count >= (signed)s->dma_adc.dma_fragsize)
  1036. mask |= POLLIN | POLLRDNORM;
  1037. }
  1038. if (file->f_mode & FMODE_WRITE) {
  1039. if (s->dma_dac.mapped) {
  1040. if (s->dma_dac.count >=
  1041. (signed)s->dma_dac.dma_fragsize)
  1042. mask |= POLLOUT | POLLWRNORM;
  1043. } else {
  1044. if ((signed) s->dma_dac.dmasize >=
  1045. s->dma_dac.count + (signed)s->dma_dac.dma_fragsize)
  1046. mask |= POLLOUT | POLLWRNORM;
  1047. }
  1048. }
  1049. spin_unlock_irqrestore(&s->lock, flags);
  1050. return mask;
  1051. }
  1052. static int
  1053. au1550_mmap(struct file *file, struct vm_area_struct *vma)
  1054. {
  1055. struct au1550_state *s = (struct au1550_state *)file->private_data;
  1056. struct dmabuf *db;
  1057. unsigned long size;
  1058. int ret = 0;
  1059. lock_kernel();
  1060. mutex_lock(&s->sem);
  1061. if (vma->vm_flags & VM_WRITE)
  1062. db = &s->dma_dac;
  1063. else if (vma->vm_flags & VM_READ)
  1064. db = &s->dma_adc;
  1065. else {
  1066. ret = -EINVAL;
  1067. goto out;
  1068. }
  1069. if (vma->vm_pgoff != 0) {
  1070. ret = -EINVAL;
  1071. goto out;
  1072. }
  1073. size = vma->vm_end - vma->vm_start;
  1074. if (size > (PAGE_SIZE << db->buforder)) {
  1075. ret = -EINVAL;
  1076. goto out;
  1077. }
  1078. if (remap_pfn_range(vma, vma->vm_start, page_to_pfn(virt_to_page(db->rawbuf)),
  1079. size, vma->vm_page_prot)) {
  1080. ret = -EAGAIN;
  1081. goto out;
  1082. }
  1083. vma->vm_flags &= ~VM_IO;
  1084. db->mapped = 1;
  1085. out:
  1086. mutex_unlock(&s->sem);
  1087. unlock_kernel();
  1088. return ret;
  1089. }
  1090. #ifdef DEBUG
  1091. static struct ioctl_str_t {
  1092. unsigned int cmd;
  1093. const char *str;
  1094. } ioctl_str[] = {
  1095. {SNDCTL_DSP_RESET, "SNDCTL_DSP_RESET"},
  1096. {SNDCTL_DSP_SYNC, "SNDCTL_DSP_SYNC"},
  1097. {SNDCTL_DSP_SPEED, "SNDCTL_DSP_SPEED"},
  1098. {SNDCTL_DSP_STEREO, "SNDCTL_DSP_STEREO"},
  1099. {SNDCTL_DSP_GETBLKSIZE, "SNDCTL_DSP_GETBLKSIZE"},
  1100. {SNDCTL_DSP_SAMPLESIZE, "SNDCTL_DSP_SAMPLESIZE"},
  1101. {SNDCTL_DSP_CHANNELS, "SNDCTL_DSP_CHANNELS"},
  1102. {SOUND_PCM_WRITE_CHANNELS, "SOUND_PCM_WRITE_CHANNELS"},
  1103. {SOUND_PCM_WRITE_FILTER, "SOUND_PCM_WRITE_FILTER"},
  1104. {SNDCTL_DSP_POST, "SNDCTL_DSP_POST"},
  1105. {SNDCTL_DSP_SUBDIVIDE, "SNDCTL_DSP_SUBDIVIDE"},
  1106. {SNDCTL_DSP_SETFRAGMENT, "SNDCTL_DSP_SETFRAGMENT"},
  1107. {SNDCTL_DSP_GETFMTS, "SNDCTL_DSP_GETFMTS"},
  1108. {SNDCTL_DSP_SETFMT, "SNDCTL_DSP_SETFMT"},
  1109. {SNDCTL_DSP_GETOSPACE, "SNDCTL_DSP_GETOSPACE"},
  1110. {SNDCTL_DSP_GETISPACE, "SNDCTL_DSP_GETISPACE"},
  1111. {SNDCTL_DSP_NONBLOCK, "SNDCTL_DSP_NONBLOCK"},
  1112. {SNDCTL_DSP_GETCAPS, "SNDCTL_DSP_GETCAPS"},
  1113. {SNDCTL_DSP_GETTRIGGER, "SNDCTL_DSP_GETTRIGGER"},
  1114. {SNDCTL_DSP_SETTRIGGER, "SNDCTL_DSP_SETTRIGGER"},
  1115. {SNDCTL_DSP_GETIPTR, "SNDCTL_DSP_GETIPTR"},
  1116. {SNDCTL_DSP_GETOPTR, "SNDCTL_DSP_GETOPTR"},
  1117. {SNDCTL_DSP_MAPINBUF, "SNDCTL_DSP_MAPINBUF"},
  1118. {SNDCTL_DSP_MAPOUTBUF, "SNDCTL_DSP_MAPOUTBUF"},
  1119. {SNDCTL_DSP_SETSYNCRO, "SNDCTL_DSP_SETSYNCRO"},
  1120. {SNDCTL_DSP_SETDUPLEX, "SNDCTL_DSP_SETDUPLEX"},
  1121. {SNDCTL_DSP_GETODELAY, "SNDCTL_DSP_GETODELAY"},
  1122. {SNDCTL_DSP_GETCHANNELMASK, "SNDCTL_DSP_GETCHANNELMASK"},
  1123. {SNDCTL_DSP_BIND_CHANNEL, "SNDCTL_DSP_BIND_CHANNEL"},
  1124. {OSS_GETVERSION, "OSS_GETVERSION"},
  1125. {SOUND_PCM_READ_RATE, "SOUND_PCM_READ_RATE"},
  1126. {SOUND_PCM_READ_CHANNELS, "SOUND_PCM_READ_CHANNELS"},
  1127. {SOUND_PCM_READ_BITS, "SOUND_PCM_READ_BITS"},
  1128. {SOUND_PCM_READ_FILTER, "SOUND_PCM_READ_FILTER"}
  1129. };
  1130. #endif
  1131. static int
  1132. dma_count_done(struct dmabuf *db)
  1133. {
  1134. if (db->stopped)
  1135. return 0;
  1136. return db->dma_fragsize - au1xxx_get_dma_residue(db->dmanr);
  1137. }
  1138. static int
  1139. au1550_ioctl(struct inode *inode, struct file *file, unsigned int cmd,
  1140. unsigned long arg)
  1141. {
  1142. struct au1550_state *s = (struct au1550_state *)file->private_data;
  1143. unsigned long flags;
  1144. audio_buf_info abinfo;
  1145. count_info cinfo;
  1146. int count;
  1147. int val, mapped, ret, diff;
  1148. mapped = ((file->f_mode & FMODE_WRITE) && s->dma_dac.mapped) ||
  1149. ((file->f_mode & FMODE_READ) && s->dma_adc.mapped);
  1150. #ifdef DEBUG
  1151. for (count = 0; count < ARRAY_SIZE(ioctl_str); count++) {
  1152. if (ioctl_str[count].cmd == cmd)
  1153. break;
  1154. }
  1155. if (count < ARRAY_SIZE(ioctl_str))
  1156. pr_debug("ioctl %s, arg=0x%lxn", ioctl_str[count].str, arg);
  1157. else
  1158. pr_debug("ioctl 0x%x unknown, arg=0x%lx\n", cmd, arg);
  1159. #endif
  1160. switch (cmd) {
  1161. case OSS_GETVERSION:
  1162. return put_user(SOUND_VERSION, (int *) arg);
  1163. case SNDCTL_DSP_SYNC:
  1164. if (file->f_mode & FMODE_WRITE)
  1165. return drain_dac(s, file->f_flags & O_NONBLOCK);
  1166. return 0;
  1167. case SNDCTL_DSP_SETDUPLEX:
  1168. return 0;
  1169. case SNDCTL_DSP_GETCAPS:
  1170. return put_user(DSP_CAP_DUPLEX | DSP_CAP_REALTIME |
  1171. DSP_CAP_TRIGGER | DSP_CAP_MMAP, (int *)arg);
  1172. case SNDCTL_DSP_RESET:
  1173. if (file->f_mode & FMODE_WRITE) {
  1174. stop_dac(s);
  1175. synchronize_irq();
  1176. s->dma_dac.count = s->dma_dac.total_bytes = 0;
  1177. s->dma_dac.nextIn = s->dma_dac.nextOut =
  1178. s->dma_dac.rawbuf;
  1179. }
  1180. if (file->f_mode & FMODE_READ) {
  1181. stop_adc(s);
  1182. synchronize_irq();
  1183. s->dma_adc.count = s->dma_adc.total_bytes = 0;
  1184. s->dma_adc.nextIn = s->dma_adc.nextOut =
  1185. s->dma_adc.rawbuf;
  1186. }
  1187. return 0;
  1188. case SNDCTL_DSP_SPEED:
  1189. if (get_user(val, (int *) arg))
  1190. return -EFAULT;
  1191. if (val >= 0) {
  1192. if (file->f_mode & FMODE_READ) {
  1193. stop_adc(s);
  1194. set_adc_rate(s, val);
  1195. }
  1196. if (file->f_mode & FMODE_WRITE) {
  1197. stop_dac(s);
  1198. set_dac_rate(s, val);
  1199. }
  1200. if (s->open_mode & FMODE_READ)
  1201. if ((ret = prog_dmabuf_adc(s)))
  1202. return ret;
  1203. if (s->open_mode & FMODE_WRITE)
  1204. if ((ret = prog_dmabuf_dac(s)))
  1205. return ret;
  1206. }
  1207. return put_user((file->f_mode & FMODE_READ) ?
  1208. s->dma_adc.sample_rate :
  1209. s->dma_dac.sample_rate,
  1210. (int *)arg);
  1211. case SNDCTL_DSP_STEREO:
  1212. if (get_user(val, (int *) arg))
  1213. return -EFAULT;
  1214. if (file->f_mode & FMODE_READ) {
  1215. stop_adc(s);
  1216. s->dma_adc.num_channels = val ? 2 : 1;
  1217. if ((ret = prog_dmabuf_adc(s)))
  1218. return ret;
  1219. }
  1220. if (file->f_mode & FMODE_WRITE) {
  1221. stop_dac(s);
  1222. s->dma_dac.num_channels = val ? 2 : 1;
  1223. if (s->codec_ext_caps & AC97_EXT_DACS) {
  1224. /* disable surround and center/lfe in AC'97
  1225. */
  1226. u16 ext_stat = rdcodec(s->codec,
  1227. AC97_EXTENDED_STATUS);
  1228. wrcodec(s->codec, AC97_EXTENDED_STATUS,
  1229. ext_stat | (AC97_EXTSTAT_PRI |
  1230. AC97_EXTSTAT_PRJ |
  1231. AC97_EXTSTAT_PRK));
  1232. }
  1233. if ((ret = prog_dmabuf_dac(s)))
  1234. return ret;
  1235. }
  1236. return 0;
  1237. case SNDCTL_DSP_CHANNELS:
  1238. if (get_user(val, (int *) arg))
  1239. return -EFAULT;
  1240. if (val != 0) {
  1241. if (file->f_mode & FMODE_READ) {
  1242. if (val < 0 || val > 2)
  1243. return -EINVAL;
  1244. stop_adc(s);
  1245. s->dma_adc.num_channels = val;
  1246. if ((ret = prog_dmabuf_adc(s)))
  1247. return ret;
  1248. }
  1249. if (file->f_mode & FMODE_WRITE) {
  1250. switch (val) {
  1251. case 1:
  1252. case 2:
  1253. break;
  1254. case 3:
  1255. case 5:
  1256. return -EINVAL;
  1257. case 4:
  1258. if (!(s->codec_ext_caps &
  1259. AC97_EXTID_SDAC))
  1260. return -EINVAL;
  1261. break;
  1262. case 6:
  1263. if ((s->codec_ext_caps &
  1264. AC97_EXT_DACS) != AC97_EXT_DACS)
  1265. return -EINVAL;
  1266. break;
  1267. default:
  1268. return -EINVAL;
  1269. }
  1270. stop_dac(s);
  1271. if (val <= 2 &&
  1272. (s->codec_ext_caps & AC97_EXT_DACS)) {
  1273. /* disable surround and center/lfe
  1274. * channels in AC'97
  1275. */
  1276. u16 ext_stat =
  1277. rdcodec(s->codec,
  1278. AC97_EXTENDED_STATUS);
  1279. wrcodec(s->codec,
  1280. AC97_EXTENDED_STATUS,
  1281. ext_stat | (AC97_EXTSTAT_PRI |
  1282. AC97_EXTSTAT_PRJ |
  1283. AC97_EXTSTAT_PRK));
  1284. } else if (val >= 4) {
  1285. /* enable surround, center/lfe
  1286. * channels in AC'97
  1287. */
  1288. u16 ext_stat =
  1289. rdcodec(s->codec,
  1290. AC97_EXTENDED_STATUS);
  1291. ext_stat &= ~AC97_EXTSTAT_PRJ;
  1292. if (val == 6)
  1293. ext_stat &=
  1294. ~(AC97_EXTSTAT_PRI |
  1295. AC97_EXTSTAT_PRK);
  1296. wrcodec(s->codec,
  1297. AC97_EXTENDED_STATUS,
  1298. ext_stat);
  1299. }
  1300. s->dma_dac.num_channels = val;
  1301. if ((ret = prog_dmabuf_dac(s)))
  1302. return ret;
  1303. }
  1304. }
  1305. return put_user(val, (int *) arg);
  1306. case SNDCTL_DSP_GETFMTS: /* Returns a mask */
  1307. return put_user(AFMT_S16_LE | AFMT_U8, (int *) arg);
  1308. case SNDCTL_DSP_SETFMT: /* Selects ONE fmt */
  1309. if (get_user(val, (int *) arg))
  1310. return -EFAULT;
  1311. if (val != AFMT_QUERY) {
  1312. if (file->f_mode & FMODE_READ) {
  1313. stop_adc(s);
  1314. if (val == AFMT_S16_LE)
  1315. s->dma_adc.sample_size = 16;
  1316. else {
  1317. val = AFMT_U8;
  1318. s->dma_adc.sample_size = 8;
  1319. }
  1320. if ((ret = prog_dmabuf_adc(s)))
  1321. return ret;
  1322. }
  1323. if (file->f_mode & FMODE_WRITE) {
  1324. stop_dac(s);
  1325. if (val == AFMT_S16_LE)
  1326. s->dma_dac.sample_size = 16;
  1327. else {
  1328. val = AFMT_U8;
  1329. s->dma_dac.sample_size = 8;
  1330. }
  1331. if ((ret = prog_dmabuf_dac(s)))
  1332. return ret;
  1333. }
  1334. } else {
  1335. if (file->f_mode & FMODE_READ)
  1336. val = (s->dma_adc.sample_size == 16) ?
  1337. AFMT_S16_LE : AFMT_U8;
  1338. else
  1339. val = (s->dma_dac.sample_size == 16) ?
  1340. AFMT_S16_LE : AFMT_U8;
  1341. }
  1342. return put_user(val, (int *) arg);
  1343. case SNDCTL_DSP_POST:
  1344. return 0;
  1345. case SNDCTL_DSP_GETTRIGGER:
  1346. val = 0;
  1347. spin_lock_irqsave(&s->lock, flags);
  1348. if (file->f_mode & FMODE_READ && !s->dma_adc.stopped)
  1349. val |= PCM_ENABLE_INPUT;
  1350. if (file->f_mode & FMODE_WRITE && !s->dma_dac.stopped)
  1351. val |= PCM_ENABLE_OUTPUT;
  1352. spin_unlock_irqrestore(&s->lock, flags);
  1353. return put_user(val, (int *) arg);
  1354. case SNDCTL_DSP_SETTRIGGER:
  1355. if (get_user(val, (int *) arg))
  1356. return -EFAULT;
  1357. if (file->f_mode & FMODE_READ) {
  1358. if (val & PCM_ENABLE_INPUT) {
  1359. spin_lock_irqsave(&s->lock, flags);
  1360. start_adc(s);
  1361. spin_unlock_irqrestore(&s->lock, flags);
  1362. } else
  1363. stop_adc(s);
  1364. }
  1365. if (file->f_mode & FMODE_WRITE) {
  1366. if (val & PCM_ENABLE_OUTPUT) {
  1367. spin_lock_irqsave(&s->lock, flags);
  1368. start_dac(s);
  1369. spin_unlock_irqrestore(&s->lock, flags);
  1370. } else
  1371. stop_dac(s);
  1372. }
  1373. return 0;
  1374. case SNDCTL_DSP_GETOSPACE:
  1375. if (!(file->f_mode & FMODE_WRITE))
  1376. return -EINVAL;
  1377. abinfo.fragsize = s->dma_dac.fragsize;
  1378. spin_lock_irqsave(&s->lock, flags);
  1379. count = s->dma_dac.count;
  1380. count -= dma_count_done(&s->dma_dac);
  1381. spin_unlock_irqrestore(&s->lock, flags);
  1382. if (count < 0)
  1383. count = 0;
  1384. abinfo.bytes = (s->dma_dac.dmasize - count) /
  1385. s->dma_dac.cnt_factor;
  1386. abinfo.fragstotal = s->dma_dac.numfrag;
  1387. abinfo.fragments = abinfo.bytes >> s->dma_dac.fragshift;
  1388. pr_debug("ioctl SNDCTL_DSP_GETOSPACE: bytes=%d, fragments=%d\n", abinfo.bytes, abinfo.fragments);
  1389. return copy_to_user((void *) arg, &abinfo,
  1390. sizeof(abinfo)) ? -EFAULT : 0;
  1391. case SNDCTL_DSP_GETISPACE:
  1392. if (!(file->f_mode & FMODE_READ))
  1393. return -EINVAL;
  1394. abinfo.fragsize = s->dma_adc.fragsize;
  1395. spin_lock_irqsave(&s->lock, flags);
  1396. count = s->dma_adc.count;
  1397. count += dma_count_done(&s->dma_adc);
  1398. spin_unlock_irqrestore(&s->lock, flags);
  1399. if (count < 0)
  1400. count = 0;
  1401. abinfo.bytes = count / s->dma_adc.cnt_factor;
  1402. abinfo.fragstotal = s->dma_adc.numfrag;
  1403. abinfo.fragments = abinfo.bytes >> s->dma_adc.fragshift;
  1404. return copy_to_user((void *) arg, &abinfo,
  1405. sizeof(abinfo)) ? -EFAULT : 0;
  1406. case SNDCTL_DSP_NONBLOCK:
  1407. spin_lock(&file->f_lock);
  1408. file->f_flags |= O_NONBLOCK;
  1409. spin_unlock(&file->f_lock);
  1410. return 0;
  1411. case SNDCTL_DSP_GETODELAY:
  1412. if (!(file->f_mode & FMODE_WRITE))
  1413. return -EINVAL;
  1414. spin_lock_irqsave(&s->lock, flags);
  1415. count = s->dma_dac.count;
  1416. count -= dma_count_done(&s->dma_dac);
  1417. spin_unlock_irqrestore(&s->lock, flags);
  1418. if (count < 0)
  1419. count = 0;
  1420. count /= s->dma_dac.cnt_factor;
  1421. return put_user(count, (int *) arg);
  1422. case SNDCTL_DSP_GETIPTR:
  1423. if (!(file->f_mode & FMODE_READ))
  1424. return -EINVAL;
  1425. spin_lock_irqsave(&s->lock, flags);
  1426. cinfo.bytes = s->dma_adc.total_bytes;
  1427. count = s->dma_adc.count;
  1428. if (!s->dma_adc.stopped) {
  1429. diff = dma_count_done(&s->dma_adc);
  1430. count += diff;
  1431. cinfo.bytes += diff;
  1432. cinfo.ptr = virt_to_phys(s->dma_adc.nextIn) + diff -
  1433. virt_to_phys(s->dma_adc.rawbuf);
  1434. } else
  1435. cinfo.ptr = virt_to_phys(s->dma_adc.nextIn) -
  1436. virt_to_phys(s->dma_adc.rawbuf);
  1437. if (s->dma_adc.mapped)
  1438. s->dma_adc.count &= (s->dma_adc.dma_fragsize-1);
  1439. spin_unlock_irqrestore(&s->lock, flags);
  1440. if (count < 0)
  1441. count = 0;
  1442. cinfo.blocks = count >> s->dma_adc.fragshift;
  1443. return copy_to_user((void *) arg, &cinfo, sizeof(cinfo));
  1444. case SNDCTL_DSP_GETOPTR:
  1445. if (!(file->f_mode & FMODE_READ))
  1446. return -EINVAL;
  1447. spin_lock_irqsave(&s->lock, flags);
  1448. cinfo.bytes = s->dma_dac.total_bytes;
  1449. count = s->dma_dac.count;
  1450. if (!s->dma_dac.stopped) {
  1451. diff = dma_count_done(&s->dma_dac);
  1452. count -= diff;
  1453. cinfo.bytes += diff;
  1454. cinfo.ptr = virt_to_phys(s->dma_dac.nextOut) + diff -
  1455. virt_to_phys(s->dma_dac.rawbuf);
  1456. } else
  1457. cinfo.ptr = virt_to_phys(s->dma_dac.nextOut) -
  1458. virt_to_phys(s->dma_dac.rawbuf);
  1459. if (s->dma_dac.mapped)
  1460. s->dma_dac.count &= (s->dma_dac.dma_fragsize-1);
  1461. spin_unlock_irqrestore(&s->lock, flags);
  1462. if (count < 0)
  1463. count = 0;
  1464. cinfo.blocks = count >> s->dma_dac.fragshift;
  1465. return copy_to_user((void *) arg, &cinfo, sizeof(cinfo));
  1466. case SNDCTL_DSP_GETBLKSIZE:
  1467. if (file->f_mode & FMODE_WRITE)
  1468. return put_user(s->dma_dac.fragsize, (int *) arg);
  1469. else
  1470. return put_user(s->dma_adc.fragsize, (int *) arg);
  1471. case SNDCTL_DSP_SETFRAGMENT:
  1472. if (get_user(val, (int *) arg))
  1473. return -EFAULT;
  1474. if (file->f_mode & FMODE_READ) {
  1475. stop_adc(s);
  1476. s->dma_adc.ossfragshift = val & 0xffff;
  1477. s->dma_adc.ossmaxfrags = (val >> 16) & 0xffff;
  1478. if (s->dma_adc.ossfragshift < 4)
  1479. s->dma_adc.ossfragshift = 4;
  1480. if (s->dma_adc.ossfragshift > 15)
  1481. s->dma_adc.ossfragshift = 15;
  1482. if (s->dma_adc.ossmaxfrags < 4)
  1483. s->dma_adc.ossmaxfrags = 4;
  1484. if ((ret = prog_dmabuf_adc(s)))
  1485. return ret;
  1486. }
  1487. if (file->f_mode & FMODE_WRITE) {
  1488. stop_dac(s);
  1489. s->dma_dac.ossfragshift = val & 0xffff;
  1490. s->dma_dac.ossmaxfrags = (val >> 16) & 0xffff;
  1491. if (s->dma_dac.ossfragshift < 4)
  1492. s->dma_dac.ossfragshift = 4;
  1493. if (s->dma_dac.ossfragshift > 15)
  1494. s->dma_dac.ossfragshift = 15;
  1495. if (s->dma_dac.ossmaxfrags < 4)
  1496. s->dma_dac.ossmaxfrags = 4;
  1497. if ((ret = prog_dmabuf_dac(s)))
  1498. return ret;
  1499. }
  1500. return 0;
  1501. case SNDCTL_DSP_SUBDIVIDE:
  1502. if ((file->f_mode & FMODE_READ && s->dma_adc.subdivision) ||
  1503. (file->f_mode & FMODE_WRITE && s->dma_dac.subdivision))
  1504. return -EINVAL;
  1505. if (get_user(val, (int *) arg))
  1506. return -EFAULT;
  1507. if (val != 1 && val != 2 && val != 4)
  1508. return -EINVAL;
  1509. if (file->f_mode & FMODE_READ) {
  1510. stop_adc(s);
  1511. s->dma_adc.subdivision = val;
  1512. if ((ret = prog_dmabuf_adc(s)))
  1513. return ret;
  1514. }
  1515. if (file->f_mode & FMODE_WRITE) {
  1516. stop_dac(s);
  1517. s->dma_dac.subdivision = val;
  1518. if ((ret = prog_dmabuf_dac(s)))
  1519. return ret;
  1520. }
  1521. return 0;
  1522. case SOUND_PCM_READ_RATE:
  1523. return put_user((file->f_mode & FMODE_READ) ?
  1524. s->dma_adc.sample_rate :
  1525. s->dma_dac.sample_rate,
  1526. (int *)arg);
  1527. case SOUND_PCM_READ_CHANNELS:
  1528. if (file->f_mode & FMODE_READ)
  1529. return put_user(s->dma_adc.num_channels, (int *)arg);
  1530. else
  1531. return put_user(s->dma_dac.num_channels, (int *)arg);
  1532. case SOUND_PCM_READ_BITS:
  1533. if (file->f_mode & FMODE_READ)
  1534. return put_user(s->dma_adc.sample_size, (int *)arg);
  1535. else
  1536. return put_user(s->dma_dac.sample_size, (int *)arg);
  1537. case SOUND_PCM_WRITE_FILTER:
  1538. case SNDCTL_DSP_SETSYNCRO:
  1539. case SOUND_PCM_READ_FILTER:
  1540. return -EINVAL;
  1541. }
  1542. return mixdev_ioctl(s->codec, cmd, arg);
  1543. }
  1544. static int
  1545. au1550_open(struct inode *inode, struct file *file)
  1546. {
  1547. int minor = MINOR(inode->i_rdev);
  1548. DECLARE_WAITQUEUE(wait, current);
  1549. struct au1550_state *s = &au1550_state;
  1550. int ret;
  1551. #ifdef DEBUG
  1552. if (file->f_flags & O_NONBLOCK)
  1553. pr_debug("open: non-blocking\n");
  1554. else
  1555. pr_debug("open: blocking\n");
  1556. #endif
  1557. file->private_data = s;
  1558. /* wait for device to become free */
  1559. mutex_lock(&s->open_mutex);
  1560. while (s->open_mode & file->f_mode) {
  1561. if (file->f_flags & O_NONBLOCK) {
  1562. mutex_unlock(&s->open_mutex);
  1563. return -EBUSY;
  1564. }
  1565. add_wait_queue(&s->open_wait, &wait);
  1566. __set_current_state(TASK_INTERRUPTIBLE);
  1567. mutex_unlock(&s->open_mutex);
  1568. schedule();
  1569. remove_wait_queue(&s->open_wait, &wait);
  1570. set_current_state(TASK_RUNNING);
  1571. if (signal_pending(current))
  1572. return -ERESTARTSYS;
  1573. mutex_lock(&s->open_mutex);
  1574. }
  1575. stop_dac(s);
  1576. stop_adc(s);
  1577. if (file->f_mode & FMODE_READ) {
  1578. s->dma_adc.ossfragshift = s->dma_adc.ossmaxfrags =
  1579. s->dma_adc.subdivision = s->dma_adc.total_bytes = 0;
  1580. s->dma_adc.num_channels = 1;
  1581. s->dma_adc.sample_size = 8;
  1582. set_adc_rate(s, 8000);
  1583. if ((minor & 0xf) == SND_DEV_DSP16)
  1584. s->dma_adc.sample_size = 16;
  1585. }
  1586. if (file->f_mode & FMODE_WRITE) {
  1587. s->dma_dac.ossfragshift = s->dma_dac.ossmaxfrags =
  1588. s->dma_dac.subdivision = s->dma_dac.total_bytes = 0;
  1589. s->dma_dac.num_channels = 1;
  1590. s->dma_dac.sample_size = 8;
  1591. set_dac_rate(s, 8000);
  1592. if ((minor & 0xf) == SND_DEV_DSP16)
  1593. s->dma_dac.sample_size = 16;
  1594. }
  1595. if (file->f_mode & FMODE_READ) {
  1596. if ((ret = prog_dmabuf_adc(s)))
  1597. return ret;
  1598. }
  1599. if (file->f_mode & FMODE_WRITE) {
  1600. if ((ret = prog_dmabuf_dac(s)))
  1601. return ret;
  1602. }
  1603. s->open_mode |= file->f_mode & (FMODE_READ | FMODE_WRITE);
  1604. mutex_unlock(&s->open_mutex);
  1605. mutex_init(&s->sem);
  1606. return 0;
  1607. }
  1608. static int
  1609. au1550_release(struct inode *inode, struct file *file)
  1610. {
  1611. struct au1550_state *s = (struct au1550_state *)file->private_data;
  1612. lock_kernel();
  1613. if (file->f_mode & FMODE_WRITE) {
  1614. unlock_kernel();
  1615. drain_dac(s, file->f_flags & O_NONBLOCK);
  1616. lock_kernel();
  1617. }
  1618. mutex_lock(&s->open_mutex);
  1619. if (file->f_mode & FMODE_WRITE) {
  1620. stop_dac(s);
  1621. kfree(s->dma_dac.rawbuf);
  1622. s->dma_dac.rawbuf = NULL;
  1623. }
  1624. if (file->f_mode & FMODE_READ) {
  1625. stop_adc(s);
  1626. kfree(s->dma_adc.rawbuf);
  1627. s->dma_adc.rawbuf = NULL;
  1628. }
  1629. s->open_mode &= ((~file->f_mode) & (FMODE_READ|FMODE_WRITE));
  1630. mutex_unlock(&s->open_mutex);
  1631. wake_up(&s->open_wait);
  1632. unlock_kernel();
  1633. return 0;
  1634. }
  1635. static /*const */ struct file_operations au1550_audio_fops = {
  1636. owner: THIS_MODULE,
  1637. llseek: au1550_llseek,
  1638. read: au1550_read,
  1639. write: au1550_write,
  1640. poll: au1550_poll,
  1641. ioctl: au1550_ioctl,
  1642. mmap: au1550_mmap,
  1643. open: au1550_open,
  1644. release: au1550_release,
  1645. };
  1646. MODULE_AUTHOR("Advanced Micro Devices (AMD), dan@embeddededge.com");
  1647. MODULE_DESCRIPTION("Au1550 AC97 Audio Driver");
  1648. MODULE_LICENSE("GPL");
  1649. static int __devinit
  1650. au1550_probe(void)
  1651. {
  1652. struct au1550_state *s = &au1550_state;
  1653. int val;
  1654. memset(s, 0, sizeof(struct au1550_state));
  1655. init_waitqueue_head(&s->dma_adc.wait);
  1656. init_waitqueue_head(&s->dma_dac.wait);
  1657. init_waitqueue_head(&s->open_wait);
  1658. mutex_init(&s->open_mutex);
  1659. spin_lock_init(&s->lock);
  1660. s->codec = ac97_alloc_codec();
  1661. if(s->codec == NULL) {
  1662. err("Out of memory");
  1663. return -1;
  1664. }
  1665. s->codec->private_data = s;
  1666. s->codec->id = 0;
  1667. s->codec->codec_read = rdcodec;
  1668. s->codec->codec_write = wrcodec;
  1669. s->codec->codec_wait = waitcodec;
  1670. if (!request_mem_region(CPHYSADDR(AC97_PSC_SEL),
  1671. 0x30, "Au1550 AC97")) {
  1672. err("AC'97 ports in use");
  1673. }
  1674. /* Allocate the DMA Channels
  1675. */
  1676. if ((s->dma_dac.dmanr = au1xxx_dbdma_chan_alloc(DBDMA_MEM_CHAN,
  1677. DBDMA_AC97_TX_CHAN, dac_dma_interrupt, (void *)s)) == 0) {
  1678. err("Can't get DAC DMA");
  1679. goto err_dma1;
  1680. }
  1681. au1xxx_dbdma_set_devwidth(s->dma_dac.dmanr, 16);
  1682. if (au1xxx_dbdma_ring_alloc(s->dma_dac.dmanr,
  1683. NUM_DBDMA_DESCRIPTORS) == 0) {
  1684. err("Can't get DAC DMA descriptors");
  1685. goto err_dma1;
  1686. }
  1687. if ((s->dma_adc.dmanr = au1xxx_dbdma_chan_alloc(DBDMA_AC97_RX_CHAN,
  1688. DBDMA_MEM_CHAN, adc_dma_interrupt, (void *)s)) == 0) {
  1689. err("Can't get ADC DMA");
  1690. goto err_dma2;
  1691. }
  1692. au1xxx_dbdma_set_devwidth(s->dma_adc.dmanr, 16);
  1693. if (au1xxx_dbdma_ring_alloc(s->dma_adc.dmanr,
  1694. NUM_DBDMA_DESCRIPTORS) == 0) {
  1695. err("Can't get ADC DMA descriptors");
  1696. goto err_dma2;
  1697. }
  1698. pr_info("DAC: DMA%d, ADC: DMA%d", DBDMA_AC97_TX_CHAN, DBDMA_AC97_RX_CHAN);
  1699. /* register devices */
  1700. if ((s->dev_audio = register_sound_dsp(&au1550_audio_fops, -1)) < 0)
  1701. goto err_dev1;
  1702. if ((s->codec->dev_mixer =
  1703. register_sound_mixer(&au1550_mixer_fops, -1)) < 0)
  1704. goto err_dev2;
  1705. /* The GPIO for the appropriate PSC was configured by the
  1706. * board specific start up.
  1707. *
  1708. * configure PSC for AC'97
  1709. */
  1710. au_writel(0, AC97_PSC_CTRL); /* Disable PSC */
  1711. au_sync();
  1712. au_writel((PSC_SEL_CLK_SERCLK | PSC_SEL_PS_AC97MODE), AC97_PSC_SEL);
  1713. au_sync();
  1714. /* cold reset the AC'97
  1715. */
  1716. au_writel(PSC_AC97RST_RST, PSC_AC97RST);
  1717. au_sync();
  1718. au1550_delay(10);
  1719. au_writel(0, PSC_AC97RST);
  1720. au_sync();
  1721. /* need to delay around 500msec(bleech) to give
  1722. some CODECs enough time to wakeup */
  1723. au1550_delay(500);
  1724. /* warm reset the AC'97 to start the bitclk
  1725. */
  1726. au_writel(PSC_AC97RST_SNC, PSC_AC97RST);
  1727. au_sync();
  1728. udelay(100);
  1729. au_writel(0, PSC_AC97RST);
  1730. au_sync();
  1731. /* Enable PSC
  1732. */
  1733. au_writel(PSC_CTRL_ENABLE, AC97_PSC_CTRL);
  1734. au_sync();
  1735. /* Wait for PSC ready.
  1736. */
  1737. do {
  1738. val = au_readl(PSC_AC97STAT);
  1739. au_sync();
  1740. } while ((val & PSC_AC97STAT_SR) == 0);
  1741. /* Configure AC97 controller.
  1742. * Deep FIFO, 16-bit sample, DMA, make sure DMA matches fifo size.
  1743. */
  1744. val = PSC_AC97CFG_SET_LEN(16);
  1745. val |= PSC_AC97CFG_RT_FIFO8 | PSC_AC97CFG_TT_FIFO8;
  1746. /* Enable device so we can at least
  1747. * talk over the AC-link.
  1748. */
  1749. au_writel(val, PSC_AC97CFG);
  1750. au_writel(PSC_AC97MSK_ALLMASK, PSC_AC97MSK);
  1751. au_sync();
  1752. val |= PSC_AC97CFG_DE_ENABLE;
  1753. au_writel(val, PSC_AC97CFG);
  1754. au_sync();
  1755. /* Wait for Device ready.
  1756. */
  1757. do {
  1758. val = au_readl(PSC_AC97STAT);
  1759. au_sync();
  1760. } while ((val & PSC_AC97STAT_DR) == 0);
  1761. /* codec init */
  1762. if (!ac97_probe_codec(s->codec))
  1763. goto err_dev3;
  1764. s->codec_base_caps = rdcodec(s->codec, AC97_RESET);
  1765. s->codec_ext_caps = rdcodec(s->codec, AC97_EXTENDED_ID);
  1766. pr_info("AC'97 Base/Extended ID = %04x/%04x",
  1767. s->codec_base_caps, s->codec_ext_caps);
  1768. if (!(s->codec_ext_caps & AC97_EXTID_VRA)) {
  1769. /* codec does not support VRA
  1770. */
  1771. s->no_vra = 1;
  1772. } else if (!vra) {
  1773. /* Boot option says disable VRA
  1774. */
  1775. u16 ac97_extstat = rdcodec(s->codec, AC97_EXTENDED_STATUS);
  1776. wrcodec(s->codec, AC97_EXTENDED_STATUS,
  1777. ac97_extstat & ~AC97_EXTSTAT_VRA);
  1778. s->no_vra = 1;
  1779. }
  1780. if (s->no_vra)
  1781. pr_info("no VRA, interpolating and decimating");
  1782. /* set mic to be the recording source */
  1783. val = SOUND_MASK_MIC;
  1784. mixdev_ioctl(s->codec, SOUND_MIXER_WRITE_RECSRC,
  1785. (unsigned long) &val);
  1786. return 0;
  1787. err_dev3:
  1788. unregister_sound_mixer(s->codec->dev_mixer);
  1789. err_dev2:
  1790. unregister_sound_dsp(s->dev_audio);
  1791. err_dev1:
  1792. au1xxx_dbdma_chan_free(s->dma_adc.dmanr);
  1793. err_dma2:
  1794. au1xxx_dbdma_chan_free(s->dma_dac.dmanr);
  1795. err_dma1:
  1796. release_mem_region(CPHYSADDR(AC97_PSC_SEL), 0x30);
  1797. ac97_release_codec(s->codec);
  1798. return -1;
  1799. }
  1800. static void __devinit
  1801. au1550_remove(void)
  1802. {
  1803. struct au1550_state *s = &au1550_state;
  1804. if (!s)
  1805. return;
  1806. synchronize_irq();
  1807. au1xxx_dbdma_chan_free(s->dma_adc.dmanr);
  1808. au1xxx_dbdma_chan_free(s->dma_dac.dmanr);
  1809. release_mem_region(CPHYSADDR(AC97_PSC_SEL), 0x30);
  1810. unregister_sound_dsp(s->dev_audio);
  1811. unregister_sound_mixer(s->codec->dev_mixer);
  1812. ac97_release_codec(s->codec);
  1813. }
  1814. static int __init
  1815. init_au1550(void)
  1816. {
  1817. return au1550_probe();
  1818. }
  1819. static void __exit
  1820. cleanup_au1550(void)
  1821. {
  1822. au1550_remove();
  1823. }
  1824. module_init(init_au1550);
  1825. module_exit(cleanup_au1550);
  1826. #ifndef MODULE
  1827. static int __init
  1828. au1550_setup(char *options)
  1829. {
  1830. char *this_opt;
  1831. if (!options || !*options)
  1832. return 0;
  1833. while ((this_opt = strsep(&options, ","))) {
  1834. if (!*this_opt)
  1835. continue;
  1836. if (!strncmp(this_opt, "vra", 3)) {
  1837. vra = 1;
  1838. }
  1839. }
  1840. return 1;
  1841. }
  1842. __setup("au1550_audio=", au1550_setup);
  1843. #endif /* MODULE */