fw.c 24 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2009-2012 Realtek Corporation.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of version 2 of the GNU General Public License as
  7. * published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program; if not, write to the Free Software Foundation, Inc.,
  16. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17. *
  18. * The full GNU General Public License is included in this distribution in the
  19. * file called LICENSE.
  20. *
  21. * Contact Information:
  22. * wlanfae <wlanfae@realtek.com>
  23. * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  24. * Hsinchu 300, Taiwan.
  25. *
  26. * Larry Finger <Larry.Finger@lwfinger.net>
  27. *
  28. ****************************************************************************
  29. */
  30. #include "../wifi.h"
  31. #include "../pci.h"
  32. #include "../base.h"
  33. #include "reg.h"
  34. #include "def.h"
  35. #include "fw.h"
  36. static void _rtl8723ae_enable_fw_download(struct ieee80211_hw *hw, bool enable)
  37. {
  38. struct rtl_priv *rtlpriv = rtl_priv(hw);
  39. u8 tmp;
  40. if (enable) {
  41. tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
  42. rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmp | 0x04);
  43. tmp = rtl_read_byte(rtlpriv, REG_MCUFWDL);
  44. rtl_write_byte(rtlpriv, REG_MCUFWDL, tmp | 0x01);
  45. tmp = rtl_read_byte(rtlpriv, REG_MCUFWDL + 2);
  46. rtl_write_byte(rtlpriv, REG_MCUFWDL + 2, tmp & 0xf7);
  47. } else {
  48. tmp = rtl_read_byte(rtlpriv, REG_MCUFWDL);
  49. rtl_write_byte(rtlpriv, REG_MCUFWDL, tmp & 0xfe);
  50. rtl_write_byte(rtlpriv, REG_MCUFWDL + 1, 0x00);
  51. }
  52. }
  53. static void _rtl8723ae_fw_block_write(struct ieee80211_hw *hw,
  54. const u8 *buffer, u32 size)
  55. {
  56. struct rtl_priv *rtlpriv = rtl_priv(hw);
  57. u32 blockSize = sizeof(u32);
  58. u8 *bufferPtr = (u8 *) buffer;
  59. u32 *pu4BytePtr = (u32 *) buffer;
  60. u32 i, offset, blockCount, remainSize;
  61. blockCount = size / blockSize;
  62. remainSize = size % blockSize;
  63. for (i = 0; i < blockCount; i++) {
  64. offset = i * blockSize;
  65. rtl_write_dword(rtlpriv, (FW_8192C_START_ADDRESS + offset),
  66. *(pu4BytePtr + i));
  67. }
  68. if (remainSize) {
  69. offset = blockCount * blockSize;
  70. bufferPtr += offset;
  71. for (i = 0; i < remainSize; i++) {
  72. rtl_write_byte(rtlpriv, (FW_8192C_START_ADDRESS +
  73. offset + i), *(bufferPtr + i));
  74. }
  75. }
  76. }
  77. static void _rtl8723ae_fw_page_write(struct ieee80211_hw *hw,
  78. u32 page, const u8 *buffer, u32 size)
  79. {
  80. struct rtl_priv *rtlpriv = rtl_priv(hw);
  81. u8 value8;
  82. u8 u8page = (u8) (page & 0x07);
  83. value8 = (rtl_read_byte(rtlpriv, REG_MCUFWDL + 2) & 0xF8) | u8page;
  84. rtl_write_byte(rtlpriv, (REG_MCUFWDL + 2), value8);
  85. _rtl8723ae_fw_block_write(hw, buffer, size);
  86. }
  87. static void _rtl8723ae_write_fw(struct ieee80211_hw *hw,
  88. enum version_8723e version, u8 *buffer,
  89. u32 size)
  90. {
  91. struct rtl_priv *rtlpriv = rtl_priv(hw);
  92. u8 *bufferPtr = (u8 *) buffer;
  93. u32 page_nums, remain_size;
  94. u32 page, offset;
  95. RT_TRACE(rtlpriv, COMP_FW, DBG_TRACE, "FW size is %d bytes,\n", size);
  96. page_nums = size / FW_8192C_PAGE_SIZE;
  97. remain_size = size % FW_8192C_PAGE_SIZE;
  98. if (page_nums > 6) {
  99. RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
  100. "Page numbers should not be greater then 6\n");
  101. }
  102. for (page = 0; page < page_nums; page++) {
  103. offset = page * FW_8192C_PAGE_SIZE;
  104. _rtl8723ae_fw_page_write(hw, page, (bufferPtr + offset),
  105. FW_8192C_PAGE_SIZE);
  106. }
  107. if (remain_size) {
  108. offset = page_nums * FW_8192C_PAGE_SIZE;
  109. page = page_nums;
  110. _rtl8723ae_fw_page_write(hw, page, (bufferPtr + offset),
  111. remain_size);
  112. }
  113. RT_TRACE(rtlpriv, COMP_FW, DBG_TRACE, "FW write done.\n");
  114. }
  115. static int _rtl8723ae_fw_free_to_go(struct ieee80211_hw *hw)
  116. {
  117. struct rtl_priv *rtlpriv = rtl_priv(hw);
  118. int err = -EIO;
  119. u32 counter = 0;
  120. u32 value32;
  121. do {
  122. value32 = rtl_read_dword(rtlpriv, REG_MCUFWDL);
  123. } while ((counter++ < FW_8192C_POLLING_TIMEOUT_COUNT) &&
  124. (!(value32 & FWDL_ChkSum_rpt)));
  125. if (counter >= FW_8192C_POLLING_TIMEOUT_COUNT) {
  126. RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
  127. "chksum report faill ! REG_MCUFWDL:0x%08x .\n",
  128. value32);
  129. goto exit;
  130. }
  131. RT_TRACE(rtlpriv, COMP_FW, DBG_TRACE,
  132. "Checksum report OK ! REG_MCUFWDL:0x%08x .\n", value32);
  133. value32 = rtl_read_dword(rtlpriv, REG_MCUFWDL);
  134. value32 |= MCUFWDL_RDY;
  135. value32 &= ~WINTINI_RDY;
  136. rtl_write_dword(rtlpriv, REG_MCUFWDL, value32);
  137. counter = 0;
  138. do {
  139. value32 = rtl_read_dword(rtlpriv, REG_MCUFWDL);
  140. if (value32 & WINTINI_RDY) {
  141. RT_TRACE(rtlpriv, COMP_FW, DBG_TRACE,
  142. "Polling FW ready success!! REG_MCUFWDL:0x%08x .\n",
  143. value32);
  144. err = 0;
  145. goto exit;
  146. }
  147. mdelay(FW_8192C_POLLING_DELAY);
  148. } while (counter++ < FW_8192C_POLLING_TIMEOUT_COUNT);
  149. RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
  150. "Polling FW ready fail!! REG_MCUFWDL:0x%08x .\n", value32);
  151. exit:
  152. return err;
  153. }
  154. int rtl8723ae_download_fw(struct ieee80211_hw *hw)
  155. {
  156. struct rtl_priv *rtlpriv = rtl_priv(hw);
  157. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  158. struct rtl8723ae_firmware_header *pfwheader;
  159. u8 *pfwdata;
  160. u32 fwsize;
  161. int err;
  162. enum version_8723e version = rtlhal->version;
  163. if (!rtlhal->pfirmware)
  164. return 1;
  165. pfwheader = (struct rtl8723ae_firmware_header *)rtlhal->pfirmware;
  166. pfwdata = (u8 *) rtlhal->pfirmware;
  167. fwsize = rtlhal->fwsize;
  168. if (IS_FW_HEADER_EXIST(pfwheader)) {
  169. RT_TRACE(rtlpriv, COMP_FW, DBG_DMESG,
  170. "Firmware Version(%d), Signature(%#x),Size(%d)\n",
  171. pfwheader->version, pfwheader->signature,
  172. (int)sizeof(struct rtl8723ae_firmware_header));
  173. pfwdata = pfwdata + sizeof(struct rtl8723ae_firmware_header);
  174. fwsize = fwsize - sizeof(struct rtl8723ae_firmware_header);
  175. }
  176. if (rtl_read_byte(rtlpriv, REG_MCUFWDL)&BIT(7)) {
  177. rtl8723ae_firmware_selfreset(hw);
  178. rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00);
  179. }
  180. _rtl8723ae_enable_fw_download(hw, true);
  181. _rtl8723ae_write_fw(hw, version, pfwdata, fwsize);
  182. _rtl8723ae_enable_fw_download(hw, false);
  183. err = _rtl8723ae_fw_free_to_go(hw);
  184. if (err) {
  185. RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
  186. "Firmware is not ready to run!\n");
  187. } else {
  188. RT_TRACE(rtlpriv, COMP_FW, DBG_TRACE,
  189. "Firmware is ready to run!\n");
  190. }
  191. return 0;
  192. }
  193. static bool rtl8723ae_check_fw_read_last_h2c(struct ieee80211_hw *hw, u8 boxnum)
  194. {
  195. struct rtl_priv *rtlpriv = rtl_priv(hw);
  196. u8 val_hmetfr, val_mcutst_1;
  197. bool result = false;
  198. val_hmetfr = rtl_read_byte(rtlpriv, REG_HMETFR);
  199. val_mcutst_1 = rtl_read_byte(rtlpriv, (REG_MCUTST_1 + boxnum));
  200. if (((val_hmetfr >> boxnum) & BIT(0)) == 0 && val_mcutst_1 == 0)
  201. result = true;
  202. return result;
  203. }
  204. static void _rtl8723ae_fill_h2c_command(struct ieee80211_hw *hw,
  205. u8 element_id, u32 cmd_len,
  206. u8 *p_cmdbuffer)
  207. {
  208. struct rtl_priv *rtlpriv = rtl_priv(hw);
  209. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  210. u8 boxnum;
  211. u16 box_reg = 0, box_extreg = 0;
  212. u8 u1tmp;
  213. bool isfw_rd = false;
  214. bool bwrite_success = false;
  215. u8 wait_h2c_limmit = 100;
  216. u8 wait_writeh2c_limmit = 100;
  217. u8 boxcontent[4], boxextcontent[2];
  218. u32 h2c_waitcounter = 0;
  219. unsigned long flag;
  220. u8 idx;
  221. RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "come in\n");
  222. while (true) {
  223. spin_lock_irqsave(&rtlpriv->locks.h2c_lock, flag);
  224. if (rtlhal->h2c_setinprogress) {
  225. RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
  226. "H2C set in progress! Wait to set..element_id(%d).\n",
  227. element_id);
  228. while (rtlhal->h2c_setinprogress) {
  229. spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock,
  230. flag);
  231. h2c_waitcounter++;
  232. RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
  233. "Wait 100 us (%d times)...\n",
  234. h2c_waitcounter);
  235. udelay(100);
  236. if (h2c_waitcounter > 1000)
  237. return;
  238. spin_lock_irqsave(&rtlpriv->locks.h2c_lock,
  239. flag);
  240. }
  241. spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock, flag);
  242. } else {
  243. rtlhal->h2c_setinprogress = true;
  244. spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock, flag);
  245. break;
  246. }
  247. }
  248. while (!bwrite_success) {
  249. wait_writeh2c_limmit--;
  250. if (wait_writeh2c_limmit == 0) {
  251. RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
  252. "Write H2C fail because no trigger "
  253. "for FW INT!\n");
  254. break;
  255. }
  256. boxnum = rtlhal->last_hmeboxnum;
  257. switch (boxnum) {
  258. case 0:
  259. box_reg = REG_HMEBOX_0;
  260. box_extreg = REG_HMEBOX_EXT_0;
  261. break;
  262. case 1:
  263. box_reg = REG_HMEBOX_1;
  264. box_extreg = REG_HMEBOX_EXT_1;
  265. break;
  266. case 2:
  267. box_reg = REG_HMEBOX_2;
  268. box_extreg = REG_HMEBOX_EXT_2;
  269. break;
  270. case 3:
  271. box_reg = REG_HMEBOX_3;
  272. box_extreg = REG_HMEBOX_EXT_3;
  273. break;
  274. default:
  275. RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
  276. "switch case not processed\n");
  277. break;
  278. }
  279. isfw_rd = rtl8723ae_check_fw_read_last_h2c(hw, boxnum);
  280. while (!isfw_rd) {
  281. wait_h2c_limmit--;
  282. if (wait_h2c_limmit == 0) {
  283. RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
  284. "Waiting too long for FW read clear HMEBox(%d)!\n",
  285. boxnum);
  286. break;
  287. }
  288. udelay(10);
  289. isfw_rd = rtl8723ae_check_fw_read_last_h2c(hw, boxnum);
  290. u1tmp = rtl_read_byte(rtlpriv, 0x1BF);
  291. RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
  292. "Waiting for FW read clear HMEBox(%d)!!! "
  293. "0x1BF = %2x\n", boxnum, u1tmp);
  294. }
  295. if (!isfw_rd) {
  296. RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
  297. "Write H2C register BOX[%d] fail!!!!! "
  298. "Fw do not read.\n", boxnum);
  299. break;
  300. }
  301. memset(boxcontent, 0, sizeof(boxcontent));
  302. memset(boxextcontent, 0, sizeof(boxextcontent));
  303. boxcontent[0] = element_id;
  304. RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
  305. "Write element_id box_reg(%4x) = %2x\n",
  306. box_reg, element_id);
  307. switch (cmd_len) {
  308. case 1:
  309. boxcontent[0] &= ~(BIT(7));
  310. memcpy((u8 *) (boxcontent) + 1,
  311. p_cmdbuffer, 1);
  312. for (idx = 0; idx < 4; idx++) {
  313. rtl_write_byte(rtlpriv, box_reg + idx,
  314. boxcontent[idx]);
  315. }
  316. break;
  317. case 2:
  318. boxcontent[0] &= ~(BIT(7));
  319. memcpy((u8 *) (boxcontent) + 1,
  320. p_cmdbuffer, 2);
  321. for (idx = 0; idx < 4; idx++) {
  322. rtl_write_byte(rtlpriv, box_reg + idx,
  323. boxcontent[idx]);
  324. }
  325. break;
  326. case 3:
  327. boxcontent[0] &= ~(BIT(7));
  328. memcpy((u8 *) (boxcontent) + 1,
  329. p_cmdbuffer, 3);
  330. for (idx = 0; idx < 4; idx++) {
  331. rtl_write_byte(rtlpriv, box_reg + idx,
  332. boxcontent[idx]);
  333. }
  334. break;
  335. case 4:
  336. boxcontent[0] |= (BIT(7));
  337. memcpy((u8 *) (boxextcontent),
  338. p_cmdbuffer, 2);
  339. memcpy((u8 *) (boxcontent) + 1,
  340. p_cmdbuffer + 2, 2);
  341. for (idx = 0; idx < 2; idx++) {
  342. rtl_write_byte(rtlpriv, box_extreg + idx,
  343. boxextcontent[idx]);
  344. }
  345. for (idx = 0; idx < 4; idx++) {
  346. rtl_write_byte(rtlpriv, box_reg + idx,
  347. boxcontent[idx]);
  348. }
  349. break;
  350. case 5:
  351. boxcontent[0] |= (BIT(7));
  352. memcpy((u8 *) (boxextcontent),
  353. p_cmdbuffer, 2);
  354. memcpy((u8 *) (boxcontent) + 1,
  355. p_cmdbuffer + 2, 3);
  356. for (idx = 0; idx < 2; idx++) {
  357. rtl_write_byte(rtlpriv, box_extreg + idx,
  358. boxextcontent[idx]);
  359. }
  360. for (idx = 0; idx < 4; idx++) {
  361. rtl_write_byte(rtlpriv, box_reg + idx,
  362. boxcontent[idx]);
  363. }
  364. break;
  365. default:
  366. RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
  367. "switch case not process\n");
  368. break;
  369. }
  370. bwrite_success = true;
  371. rtlhal->last_hmeboxnum = boxnum + 1;
  372. if (rtlhal->last_hmeboxnum == 4)
  373. rtlhal->last_hmeboxnum = 0;
  374. RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
  375. "pHalData->last_hmeboxnum = %d\n",
  376. rtlhal->last_hmeboxnum);
  377. }
  378. spin_lock_irqsave(&rtlpriv->locks.h2c_lock, flag);
  379. rtlhal->h2c_setinprogress = false;
  380. spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock, flag);
  381. RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "go out\n");
  382. }
  383. void rtl8723ae_fill_h2c_cmd(struct ieee80211_hw *hw,
  384. u8 element_id, u32 cmd_len, u8 *p_cmdbuffer)
  385. {
  386. struct rtl_priv *rtlpriv = rtl_priv(hw);
  387. struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
  388. if (rtlhal->fw_ready == false) {
  389. RT_ASSERT(false,
  390. "return H2C cmd because of Fw download fail!!!\n");
  391. return;
  392. }
  393. _rtl8723ae_fill_h2c_command(hw, element_id, cmd_len, p_cmdbuffer);
  394. return;
  395. }
  396. void rtl8723ae_firmware_selfreset(struct ieee80211_hw *hw)
  397. {
  398. u8 u1tmp;
  399. u8 delay = 100;
  400. struct rtl_priv *rtlpriv = rtl_priv(hw);
  401. rtl_write_byte(rtlpriv, REG_HMETFR + 3, 0x20);
  402. u1tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
  403. while (u1tmp & BIT(2)) {
  404. delay--;
  405. if (delay == 0)
  406. break;
  407. udelay(50);
  408. u1tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
  409. }
  410. if (delay == 0) {
  411. u1tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
  412. rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, u1tmp&(~BIT(2)));
  413. }
  414. }
  415. void rtl8723ae_set_fw_pwrmode_cmd(struct ieee80211_hw *hw, u8 mode)
  416. {
  417. struct rtl_priv *rtlpriv = rtl_priv(hw);
  418. u8 u1_h2c_set_pwrmode[3] = { 0 };
  419. struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
  420. RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, "FW LPS mode = %d\n", mode);
  421. SET_H2CCMD_PWRMODE_PARM_MODE(u1_h2c_set_pwrmode, mode);
  422. SET_H2CCMD_PWRMODE_PARM_SMART_PS(u1_h2c_set_pwrmode,
  423. (rtlpriv->mac80211.p2p) ?
  424. ppsc->smart_ps : 1);
  425. SET_H2CCMD_PWRMODE_PARM_BCN_PASS_TIME(u1_h2c_set_pwrmode,
  426. ppsc->reg_max_lps_awakeintvl);
  427. RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_DMESG,
  428. "rtl8723ae_set_fw_rsvdpagepkt(): u1_h2c_set_pwrmode\n",
  429. u1_h2c_set_pwrmode, 3);
  430. rtl8723ae_fill_h2c_cmd(hw, H2C_SETPWRMODE, 3, u1_h2c_set_pwrmode);
  431. }
  432. static bool _rtl8723ae_cmd_send_packet(struct ieee80211_hw *hw,
  433. struct sk_buff *skb)
  434. {
  435. struct rtl_priv *rtlpriv = rtl_priv(hw);
  436. struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  437. struct rtl8192_tx_ring *ring;
  438. struct rtl_tx_desc *pdesc;
  439. unsigned long flags;
  440. struct sk_buff *pskb = NULL;
  441. ring = &rtlpci->tx_ring[BEACON_QUEUE];
  442. pskb = __skb_dequeue(&ring->queue);
  443. if (pskb)
  444. kfree_skb(pskb);
  445. spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
  446. pdesc = &ring->desc[0];
  447. rtlpriv->cfg->ops->fill_tx_cmddesc(hw, (u8 *) pdesc, 1, 1, skb);
  448. __skb_queue_tail(&ring->queue, skb);
  449. spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
  450. rtlpriv->cfg->ops->tx_polling(hw, BEACON_QUEUE);
  451. return true;
  452. }
  453. static u8 reserved_page_packet[TOTAL_RESERVED_PKT_LEN] = {
  454. /* page 0 beacon */
  455. 0x80, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF,
  456. 0xFF, 0xFF, 0x00, 0xE0, 0x4C, 0x76, 0x00, 0x42,
  457. 0x00, 0x40, 0x10, 0x10, 0x00, 0x03, 0x50, 0x08,
  458. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  459. 0x64, 0x00, 0x00, 0x04, 0x00, 0x0C, 0x6C, 0x69,
  460. 0x6E, 0x6B, 0x73, 0x79, 0x73, 0x5F, 0x77, 0x6C,
  461. 0x61, 0x6E, 0x01, 0x04, 0x82, 0x84, 0x8B, 0x96,
  462. 0x03, 0x01, 0x01, 0x06, 0x02, 0x00, 0x00, 0x2A,
  463. 0x01, 0x00, 0x32, 0x08, 0x24, 0x30, 0x48, 0x6C,
  464. 0x0C, 0x12, 0x18, 0x60, 0x2D, 0x1A, 0x6C, 0x18,
  465. 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  466. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  467. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  468. 0x3D, 0x00, 0xDD, 0x06, 0x00, 0xE0, 0x4C, 0x02,
  469. 0x01, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  470. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  471. /* page 1 beacon */
  472. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  473. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  474. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  475. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  476. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  477. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  478. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  479. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  480. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  481. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  482. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  483. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  484. 0x10, 0x00, 0x20, 0x8C, 0x00, 0x12, 0x10, 0x00,
  485. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  486. 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  487. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  488. /* page 2 ps-poll */
  489. 0xA4, 0x10, 0x01, 0xC0, 0x00, 0x40, 0x10, 0x10,
  490. 0x00, 0x03, 0x00, 0xE0, 0x4C, 0x76, 0x00, 0x42,
  491. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  492. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  493. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  494. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  495. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  496. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  497. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  498. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  499. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  500. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  501. 0x18, 0x00, 0x20, 0x8C, 0x00, 0x12, 0x00, 0x00,
  502. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80,
  503. 0x80, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  504. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  505. /* page 3 null */
  506. 0x48, 0x01, 0x00, 0x00, 0x00, 0x40, 0x10, 0x10,
  507. 0x00, 0x03, 0x00, 0xE0, 0x4C, 0x76, 0x00, 0x42,
  508. 0x00, 0x40, 0x10, 0x10, 0x00, 0x03, 0x00, 0x00,
  509. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  510. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  511. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  512. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  513. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  514. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  515. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  516. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  517. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  518. 0x72, 0x00, 0x20, 0x8C, 0x00, 0x12, 0x00, 0x00,
  519. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80,
  520. 0x80, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  521. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  522. /* page 4 probe_resp */
  523. 0x50, 0x00, 0x00, 0x00, 0x00, 0x40, 0x10, 0x10,
  524. 0x00, 0x03, 0x00, 0xE0, 0x4C, 0x76, 0x00, 0x42,
  525. 0x00, 0x40, 0x10, 0x10, 0x00, 0x03, 0x00, 0x00,
  526. 0x9E, 0x46, 0x15, 0x32, 0x27, 0xF2, 0x2D, 0x00,
  527. 0x64, 0x00, 0x00, 0x04, 0x00, 0x0C, 0x6C, 0x69,
  528. 0x6E, 0x6B, 0x73, 0x79, 0x73, 0x5F, 0x77, 0x6C,
  529. 0x61, 0x6E, 0x01, 0x04, 0x82, 0x84, 0x8B, 0x96,
  530. 0x03, 0x01, 0x01, 0x06, 0x02, 0x00, 0x00, 0x2A,
  531. 0x01, 0x00, 0x32, 0x08, 0x24, 0x30, 0x48, 0x6C,
  532. 0x0C, 0x12, 0x18, 0x60, 0x2D, 0x1A, 0x6C, 0x18,
  533. 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  534. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  535. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  536. 0x3D, 0x00, 0xDD, 0x06, 0x00, 0xE0, 0x4C, 0x02,
  537. 0x01, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  538. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  539. /* page 5 probe_resp */
  540. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  541. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  542. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  543. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  544. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  545. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  546. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  547. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  548. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  549. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  550. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  551. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  552. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  553. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  554. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  555. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  556. };
  557. void rtl8723ae_set_fw_rsvdpagepkt(struct ieee80211_hw *hw, bool dl_finished)
  558. {
  559. struct rtl_priv *rtlpriv = rtl_priv(hw);
  560. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  561. struct sk_buff *skb = NULL;
  562. u32 totalpacketlen;
  563. bool rtstatus;
  564. u8 u1RsvdPageLoc[3] = { 0 };
  565. bool dlok = false;
  566. u8 *beacon;
  567. u8 *p_pspoll;
  568. u8 *nullfunc;
  569. u8 *p_probersp;
  570. /*---------------------------------------------------------
  571. (1) beacon
  572. ---------------------------------------------------------
  573. */
  574. beacon = &reserved_page_packet[BEACON_PG * 128];
  575. SET_80211_HDR_ADDRESS2(beacon, mac->mac_addr);
  576. SET_80211_HDR_ADDRESS3(beacon, mac->bssid);
  577. /*-------------------------------------------------------
  578. (2) ps-poll
  579. --------------------------------------------------------
  580. */
  581. p_pspoll = &reserved_page_packet[PSPOLL_PG * 128];
  582. SET_80211_PS_POLL_AID(p_pspoll, (mac->assoc_id | 0xc000));
  583. SET_80211_PS_POLL_BSSID(p_pspoll, mac->bssid);
  584. SET_80211_PS_POLL_TA(p_pspoll, mac->mac_addr);
  585. SET_H2CCMD_RSVDPAGE_LOC_PSPOLL(u1RsvdPageLoc, PSPOLL_PG);
  586. /*--------------------------------------------------------
  587. (3) null data
  588. ---------------------------------------------------------i
  589. */
  590. nullfunc = &reserved_page_packet[NULL_PG * 128];
  591. SET_80211_HDR_ADDRESS1(nullfunc, mac->bssid);
  592. SET_80211_HDR_ADDRESS2(nullfunc, mac->mac_addr);
  593. SET_80211_HDR_ADDRESS3(nullfunc, mac->bssid);
  594. SET_H2CCMD_RSVDPAGE_LOC_NULL_DATA(u1RsvdPageLoc, NULL_PG);
  595. /*---------------------------------------------------------
  596. (4) probe response
  597. ----------------------------------------------------------
  598. */
  599. p_probersp = &reserved_page_packet[PROBERSP_PG * 128];
  600. SET_80211_HDR_ADDRESS1(p_probersp, mac->bssid);
  601. SET_80211_HDR_ADDRESS2(p_probersp, mac->mac_addr);
  602. SET_80211_HDR_ADDRESS3(p_probersp, mac->bssid);
  603. SET_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(u1RsvdPageLoc, PROBERSP_PG);
  604. totalpacketlen = TOTAL_RESERVED_PKT_LEN;
  605. RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_LOUD,
  606. "rtl8723ae_set_fw_rsvdpagepkt(): HW_VAR_SET_TX_CMD: ALL\n",
  607. &reserved_page_packet[0], totalpacketlen);
  608. RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_DMESG,
  609. "rtl8723ae_set_fw_rsvdpagepkt(): HW_VAR_SET_TX_CMD: ALL\n",
  610. u1RsvdPageLoc, 3);
  611. skb = dev_alloc_skb(totalpacketlen);
  612. memcpy((u8 *) skb_put(skb, totalpacketlen),
  613. &reserved_page_packet, totalpacketlen);
  614. rtstatus = _rtl8723ae_cmd_send_packet(hw, skb);
  615. if (rtstatus)
  616. dlok = true;
  617. if (dlok) {
  618. RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
  619. "Set RSVD page location to Fw.\n");
  620. RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_DMESG,
  621. "H2C_RSVDPAGE:\n",
  622. u1RsvdPageLoc, 3);
  623. rtl8723ae_fill_h2c_cmd(hw, H2C_RSVDPAGE,
  624. sizeof(u1RsvdPageLoc), u1RsvdPageLoc);
  625. } else
  626. RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
  627. "Set RSVD page location to Fw FAIL!!!!!!.\n");
  628. }
  629. void rtl8723ae_set_fw_joinbss_report_cmd(struct ieee80211_hw *hw, u8 mstatus)
  630. {
  631. u8 u1_joinbssrpt_parm[1] = { 0 };
  632. SET_H2CCMD_JOINBSSRPT_PARM_OPMODE(u1_joinbssrpt_parm, mstatus);
  633. rtl8723ae_fill_h2c_cmd(hw, H2C_JOINBSSRPT, 1, u1_joinbssrpt_parm);
  634. }
  635. static void rtl8723e_set_p2p_ctw_period_cmd(struct ieee80211_hw *hw,
  636. u8 ctwindow)
  637. {
  638. u8 u1_ctwindow_period[1] = {ctwindow};
  639. rtl8723ae_fill_h2c_cmd(hw, H2C_P2P_PS_CTW_CMD, 1, u1_ctwindow_period);
  640. }
  641. void rtl8723ae_set_p2p_ps_offload_cmd(struct ieee80211_hw *hw, u8 p2p_ps_state)
  642. {
  643. struct rtl_priv *rtlpriv = rtl_priv(hw);
  644. struct rtl_ps_ctl *rtlps = rtl_psc(rtl_priv(hw));
  645. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  646. struct rtl_p2p_ps_info *p2pinfo = &(rtlps->p2p_ps_info);
  647. struct p2p_ps_offload_t *p2p_ps_offload = &rtlhal->p2p_ps_offload;
  648. u8 i;
  649. u16 ctwindow;
  650. u32 start_time, tsf_low;
  651. switch (p2p_ps_state) {
  652. case P2P_PS_DISABLE:
  653. RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD, "P2P_PS_DISABLE\n");
  654. memset(p2p_ps_offload, 0, sizeof(struct p2p_ps_offload_t));
  655. break;
  656. case P2P_PS_ENABLE:
  657. RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD, "P2P_PS_ENABLE\n");
  658. /* update CTWindow value. */
  659. if (p2pinfo->ctwindow > 0) {
  660. p2p_ps_offload->ctwindow_en = 1;
  661. ctwindow = p2pinfo->ctwindow;
  662. rtl8723e_set_p2p_ctw_period_cmd(hw, ctwindow);
  663. }
  664. /* hw only support 2 set of NoA */
  665. for (i = 0; i < p2pinfo->noa_num; i++) {
  666. /* To control the register setting for which NOA*/
  667. rtl_write_byte(rtlpriv, 0x5cf, (i << 4));
  668. if (i == 0)
  669. p2p_ps_offload->noa0_en = 1;
  670. else
  671. p2p_ps_offload->noa1_en = 1;
  672. /* config P2P NoA Descriptor Register */
  673. rtl_write_dword(rtlpriv, 0x5E0,
  674. p2pinfo->noa_duration[i]);
  675. rtl_write_dword(rtlpriv, 0x5E4,
  676. p2pinfo->noa_interval[i]);
  677. /*Get Current TSF value */
  678. tsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
  679. start_time = p2pinfo->noa_start_time[i];
  680. if (p2pinfo->noa_count_type[i] != 1) {
  681. while (start_time <= (tsf_low+(50*1024))) {
  682. start_time += p2pinfo->noa_interval[i];
  683. if (p2pinfo->noa_count_type[i] != 255)
  684. p2pinfo->noa_count_type[i]--;
  685. }
  686. }
  687. rtl_write_dword(rtlpriv, 0x5E8, start_time);
  688. rtl_write_dword(rtlpriv, 0x5EC,
  689. p2pinfo->noa_count_type[i]);
  690. }
  691. if ((p2pinfo->opp_ps == 1) || (p2pinfo->noa_num > 0)) {
  692. /* rst p2p circuit */
  693. rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, BIT(4));
  694. p2p_ps_offload->offload_en = 1;
  695. if (P2P_ROLE_GO == rtlpriv->mac80211.p2p) {
  696. p2p_ps_offload->role = 1;
  697. p2p_ps_offload->allstasleep = 0;
  698. } else {
  699. p2p_ps_offload->role = 0;
  700. }
  701. p2p_ps_offload->discovery = 0;
  702. }
  703. break;
  704. case P2P_PS_SCAN:
  705. RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD, "P2P_PS_SCAN\n");
  706. p2p_ps_offload->discovery = 1;
  707. break;
  708. case P2P_PS_SCAN_DONE:
  709. RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD, "P2P_PS_SCAN_DONE\n");
  710. p2p_ps_offload->discovery = 0;
  711. p2pinfo->p2p_ps_state = P2P_PS_ENABLE;
  712. break;
  713. default:
  714. break;
  715. }
  716. rtl8723ae_fill_h2c_cmd(hw, H2C_P2P_PS_OFFLOAD, 1, (u8 *)p2p_ps_offload);
  717. }