sw.c 13 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2009-2013 Realtek Corporation.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of version 2 of the GNU General Public License as
  7. * published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program; if not, write to the Free Software Foundation, Inc.,
  16. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17. *
  18. * The full GNU General Public License is included in this distribution in the
  19. * file called LICENSE.
  20. *
  21. * Contact Information:
  22. * wlanfae <wlanfae@realtek.com>
  23. * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  24. * Hsinchu 300, Taiwan.
  25. *
  26. * Larry Finger <Larry.Finger@lwfinger.net>
  27. *
  28. *****************************************************************************/
  29. #include "../wifi.h"
  30. #include "../core.h"
  31. #include "../pci.h"
  32. #include "reg.h"
  33. #include "def.h"
  34. #include "phy.h"
  35. #include "dm.h"
  36. #include "hw.h"
  37. #include "sw.h"
  38. #include "trx.h"
  39. #include "led.h"
  40. #include "table.h"
  41. #include <linux/vmalloc.h>
  42. #include <linux/module.h>
  43. static void rtl88e_init_aspm_vars(struct ieee80211_hw *hw)
  44. {
  45. struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  46. /*close ASPM for AMD defaultly */
  47. rtlpci->const_amdpci_aspm = 0;
  48. /* ASPM PS mode.
  49. * 0 - Disable ASPM,
  50. * 1 - Enable ASPM without Clock Req,
  51. * 2 - Enable ASPM with Clock Req,
  52. * 3 - Alwyas Enable ASPM with Clock Req,
  53. * 4 - Always Enable ASPM without Clock Req.
  54. * set defult to RTL8192CE:3 RTL8192E:2
  55. */
  56. rtlpci->const_pci_aspm = 3;
  57. /*Setting for PCI-E device */
  58. rtlpci->const_devicepci_aspm_setting = 0x03;
  59. /*Setting for PCI-E bridge */
  60. rtlpci->const_hostpci_aspm_setting = 0x02;
  61. /* In Hw/Sw Radio Off situation.
  62. * 0 - Default,
  63. * 1 - From ASPM setting without low Mac Pwr,
  64. * 2 - From ASPM setting with low Mac Pwr,
  65. * 3 - Bus D3
  66. * set default to RTL8192CE:0 RTL8192SE:2
  67. */
  68. rtlpci->const_hwsw_rfoff_d3 = 0;
  69. /* This setting works for those device with
  70. * backdoor ASPM setting such as EPHY setting.
  71. * 0 - Not support ASPM,
  72. * 1 - Support ASPM,
  73. * 2 - According to chipset.
  74. */
  75. rtlpci->const_support_pciaspm = 1;
  76. }
  77. int rtl88e_init_sw_vars(struct ieee80211_hw *hw)
  78. {
  79. int err = 0;
  80. struct rtl_priv *rtlpriv = rtl_priv(hw);
  81. struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  82. u8 tid;
  83. rtl8188ee_bt_reg_init(hw);
  84. rtlpriv->dm.dm_initialgain_enable = 1;
  85. rtlpriv->dm.dm_flag = 0;
  86. rtlpriv->dm.disable_framebursting = 0;
  87. rtlpriv->dm.thermalvalue = 0;
  88. rtlpci->transmit_config = CFENDFORM | BIT(15);
  89. /* compatible 5G band 88ce just 2.4G band & smsp */
  90. rtlpriv->rtlhal.current_bandtype = BAND_ON_2_4G;
  91. rtlpriv->rtlhal.bandset = BAND_ON_2_4G;
  92. rtlpriv->rtlhal.macphymode = SINGLEMAC_SINGLEPHY;
  93. rtlpci->receive_config = (RCR_APPFCS |
  94. RCR_APP_MIC |
  95. RCR_APP_ICV |
  96. RCR_APP_PHYST_RXFF |
  97. RCR_HTC_LOC_CTRL |
  98. RCR_AMF |
  99. RCR_ACF |
  100. RCR_ADF |
  101. RCR_AICV |
  102. RCR_ACRC32 |
  103. RCR_AB |
  104. RCR_AM |
  105. RCR_APM |
  106. 0);
  107. rtlpci->irq_mask[0] =
  108. (u32) (IMR_PSTIMEOUT |
  109. IMR_HSISR_IND_ON_INT |
  110. IMR_C2HCMD |
  111. IMR_HIGHDOK |
  112. IMR_MGNTDOK |
  113. IMR_BKDOK |
  114. IMR_BEDOK |
  115. IMR_VIDOK |
  116. IMR_VODOK |
  117. IMR_RDU |
  118. IMR_ROK |
  119. 0);
  120. rtlpci->irq_mask[1] = (u32) (IMR_RXFOVW | 0);
  121. rtlpci->sys_irq_mask = (u32) (HSIMR_PDN_INT_EN | HSIMR_RON_INT_EN);
  122. /* for debug level */
  123. rtlpriv->dbg.global_debuglevel = rtlpriv->cfg->mod_params->debug;
  124. /* for LPS & IPS */
  125. rtlpriv->psc.inactiveps = rtlpriv->cfg->mod_params->inactiveps;
  126. rtlpriv->psc.swctrl_lps = rtlpriv->cfg->mod_params->swctrl_lps;
  127. rtlpriv->psc.fwctrl_lps = rtlpriv->cfg->mod_params->fwctrl_lps;
  128. if (!rtlpriv->psc.inactiveps)
  129. pr_info("rtl8188ee: Power Save off (module option)\n");
  130. if (!rtlpriv->psc.fwctrl_lps)
  131. pr_info("rtl8188ee: FW Power Save off (module option)\n");
  132. rtlpriv->psc.reg_fwctrl_lps = 3;
  133. rtlpriv->psc.reg_max_lps_awakeintvl = 5;
  134. /* for ASPM, you can close aspm through
  135. * set const_support_pciaspm = 0
  136. */
  137. rtl88e_init_aspm_vars(hw);
  138. if (rtlpriv->psc.reg_fwctrl_lps == 1)
  139. rtlpriv->psc.fwctrl_psmode = FW_PS_MIN_MODE;
  140. else if (rtlpriv->psc.reg_fwctrl_lps == 2)
  141. rtlpriv->psc.fwctrl_psmode = FW_PS_MAX_MODE;
  142. else if (rtlpriv->psc.reg_fwctrl_lps == 3)
  143. rtlpriv->psc.fwctrl_psmode = FW_PS_DTIM_MODE;
  144. /* for firmware buf */
  145. rtlpriv->rtlhal.pfirmware = vmalloc(0x8000);
  146. if (!rtlpriv->rtlhal.pfirmware) {
  147. RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
  148. "Can't alloc buffer for fw.\n");
  149. return 1;
  150. }
  151. rtlpriv->cfg->fw_name = "rtlwifi/rtl8188efw.bin";
  152. rtlpriv->max_fw_size = 0x8000;
  153. pr_info("Using firmware %s\n", rtlpriv->cfg->fw_name);
  154. err = request_firmware_nowait(THIS_MODULE, 1, rtlpriv->cfg->fw_name,
  155. rtlpriv->io.dev, GFP_KERNEL, hw,
  156. rtl_fw_cb);
  157. if (err) {
  158. RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
  159. "Failed to request firmware!\n");
  160. return 1;
  161. }
  162. /* for early mode */
  163. rtlpriv->rtlhal.earlymode_enable = false;
  164. rtlpriv->rtlhal.max_earlymode_num = 10;
  165. for (tid = 0; tid < 8; tid++)
  166. skb_queue_head_init(&rtlpriv->mac80211.skb_waitq[tid]);
  167. /*low power */
  168. rtlpriv->psc.low_power_enable = false;
  169. if (rtlpriv->psc.low_power_enable) {
  170. init_timer(&rtlpriv->works.fw_clockoff_timer);
  171. setup_timer(&rtlpriv->works.fw_clockoff_timer,
  172. rtl88ee_fw_clk_off_timer_callback,
  173. (unsigned long)hw);
  174. }
  175. init_timer(&rtlpriv->works.fast_antenna_training_timer);
  176. setup_timer(&rtlpriv->works.fast_antenna_training_timer,
  177. rtl88e_dm_fast_antenna_training_callback,
  178. (unsigned long)hw);
  179. return err;
  180. }
  181. void rtl88e_deinit_sw_vars(struct ieee80211_hw *hw)
  182. {
  183. struct rtl_priv *rtlpriv = rtl_priv(hw);
  184. if (rtlpriv->rtlhal.pfirmware) {
  185. vfree(rtlpriv->rtlhal.pfirmware);
  186. rtlpriv->rtlhal.pfirmware = NULL;
  187. }
  188. if (rtlpriv->psc.low_power_enable)
  189. del_timer_sync(&rtlpriv->works.fw_clockoff_timer);
  190. del_timer_sync(&rtlpriv->works.fast_antenna_training_timer);
  191. }
  192. static struct rtl_hal_ops rtl8188ee_hal_ops = {
  193. .init_sw_vars = rtl88e_init_sw_vars,
  194. .deinit_sw_vars = rtl88e_deinit_sw_vars,
  195. .read_eeprom_info = rtl88ee_read_eeprom_info,
  196. .interrupt_recognized = rtl88ee_interrupt_recognized,/*need check*/
  197. .hw_init = rtl88ee_hw_init,
  198. .hw_disable = rtl88ee_card_disable,
  199. .hw_suspend = rtl88ee_suspend,
  200. .hw_resume = rtl88ee_resume,
  201. .enable_interrupt = rtl88ee_enable_interrupt,
  202. .disable_interrupt = rtl88ee_disable_interrupt,
  203. .set_network_type = rtl88ee_set_network_type,
  204. .set_chk_bssid = rtl88ee_set_check_bssid,
  205. .set_qos = rtl88ee_set_qos,
  206. .set_bcn_reg = rtl88ee_set_beacon_related_registers,
  207. .set_bcn_intv = rtl88ee_set_beacon_interval,
  208. .update_interrupt_mask = rtl88ee_update_interrupt_mask,
  209. .get_hw_reg = rtl88ee_get_hw_reg,
  210. .set_hw_reg = rtl88ee_set_hw_reg,
  211. .update_rate_tbl = rtl88ee_update_hal_rate_tbl,
  212. .fill_tx_desc = rtl88ee_tx_fill_desc,
  213. .fill_tx_cmddesc = rtl88ee_tx_fill_cmddesc,
  214. .query_rx_desc = rtl88ee_rx_query_desc,
  215. .set_channel_access = rtl88ee_update_channel_access_setting,
  216. .radio_onoff_checking = rtl88ee_gpio_radio_on_off_checking,
  217. .set_bw_mode = rtl88e_phy_set_bw_mode,
  218. .switch_channel = rtl88e_phy_sw_chnl,
  219. .dm_watchdog = rtl88e_dm_watchdog,
  220. .scan_operation_backup = rtl88e_phy_scan_operation_backup,
  221. .set_rf_power_state = rtl88e_phy_set_rf_power_state,
  222. .led_control = rtl88ee_led_control,
  223. .set_desc = rtl88ee_set_desc,
  224. .get_desc = rtl88ee_get_desc,
  225. .tx_polling = rtl88ee_tx_polling,
  226. .enable_hw_sec = rtl88ee_enable_hw_security_config,
  227. .set_key = rtl88ee_set_key,
  228. .init_sw_leds = rtl88ee_init_sw_leds,
  229. .allow_all_destaddr = rtl88ee_allow_all_destaddr,
  230. .get_bbreg = rtl88e_phy_query_bb_reg,
  231. .set_bbreg = rtl88e_phy_set_bb_reg,
  232. .get_rfreg = rtl88e_phy_query_rf_reg,
  233. .set_rfreg = rtl88e_phy_set_rf_reg,
  234. };
  235. static struct rtl_mod_params rtl88ee_mod_params = {
  236. .sw_crypto = false,
  237. .inactiveps = true,
  238. .swctrl_lps = false,
  239. .fwctrl_lps = true,
  240. .debug = DBG_EMERG,
  241. };
  242. static struct rtl_hal_cfg rtl88ee_hal_cfg = {
  243. .bar_id = 2,
  244. .write_readback = true,
  245. .name = "rtl88e_pci",
  246. .ops = &rtl8188ee_hal_ops,
  247. .mod_params = &rtl88ee_mod_params,
  248. .maps[SYS_ISO_CTRL] = REG_SYS_ISO_CTRL,
  249. .maps[SYS_FUNC_EN] = REG_SYS_FUNC_EN,
  250. .maps[SYS_CLK] = REG_SYS_CLKR,
  251. .maps[MAC_RCR_AM] = AM,
  252. .maps[MAC_RCR_AB] = AB,
  253. .maps[MAC_RCR_ACRC32] = ACRC32,
  254. .maps[MAC_RCR_ACF] = ACF,
  255. .maps[MAC_RCR_AAP] = AAP,
  256. .maps[EFUSE_ACCESS] = REG_EFUSE_ACCESS,
  257. .maps[EFUSE_TEST] = REG_EFUSE_TEST,
  258. .maps[EFUSE_CTRL] = REG_EFUSE_CTRL,
  259. .maps[EFUSE_CLK] = 0,
  260. .maps[EFUSE_CLK_CTRL] = REG_EFUSE_CTRL,
  261. .maps[EFUSE_PWC_EV12V] = PWC_EV12V,
  262. .maps[EFUSE_FEN_ELDR] = FEN_ELDR,
  263. .maps[EFUSE_LOADER_CLK_EN] = LOADER_CLK_EN,
  264. .maps[EFUSE_ANA8M] = ANA8M,
  265. .maps[EFUSE_HWSET_MAX_SIZE] = HWSET_MAX_SIZE,
  266. .maps[EFUSE_MAX_SECTION_MAP] = EFUSE_MAX_SECTION,
  267. .maps[EFUSE_REAL_CONTENT_SIZE] = EFUSE_REAL_CONTENT_LEN,
  268. .maps[EFUSE_OOB_PROTECT_BYTES_LEN] = EFUSE_OOB_PROTECT_BYTES,
  269. .maps[RWCAM] = REG_CAMCMD,
  270. .maps[WCAMI] = REG_CAMWRITE,
  271. .maps[RCAMO] = REG_CAMREAD,
  272. .maps[CAMDBG] = REG_CAMDBG,
  273. .maps[SECR] = REG_SECCFG,
  274. .maps[SEC_CAM_NONE] = CAM_NONE,
  275. .maps[SEC_CAM_WEP40] = CAM_WEP40,
  276. .maps[SEC_CAM_TKIP] = CAM_TKIP,
  277. .maps[SEC_CAM_AES] = CAM_AES,
  278. .maps[SEC_CAM_WEP104] = CAM_WEP104,
  279. .maps[RTL_IMR_BCNDMAINT6] = IMR_BCNDMAINT6,
  280. .maps[RTL_IMR_BCNDMAINT5] = IMR_BCNDMAINT5,
  281. .maps[RTL_IMR_BCNDMAINT4] = IMR_BCNDMAINT4,
  282. .maps[RTL_IMR_BCNDMAINT3] = IMR_BCNDMAINT3,
  283. .maps[RTL_IMR_BCNDMAINT2] = IMR_BCNDMAINT2,
  284. .maps[RTL_IMR_BCNDMAINT1] = IMR_BCNDMAINT1,
  285. /* .maps[RTL_IMR_BCNDOK8] = IMR_BCNDOK8, */ /*need check*/
  286. .maps[RTL_IMR_BCNDOK7] = IMR_BCNDOK7,
  287. .maps[RTL_IMR_BCNDOK6] = IMR_BCNDOK6,
  288. .maps[RTL_IMR_BCNDOK5] = IMR_BCNDOK5,
  289. .maps[RTL_IMR_BCNDOK4] = IMR_BCNDOK4,
  290. .maps[RTL_IMR_BCNDOK3] = IMR_BCNDOK3,
  291. .maps[RTL_IMR_BCNDOK2] = IMR_BCNDOK2,
  292. .maps[RTL_IMR_BCNDOK1] = IMR_BCNDOK1,
  293. /* .maps[RTL_IMR_TIMEOUT2] = IMR_TIMEOUT2,*/
  294. /* .maps[RTL_IMR_TIMEOUT1] = IMR_TIMEOUT1,*/
  295. .maps[RTL_IMR_TXFOVW] = IMR_TXFOVW,
  296. .maps[RTL_IMR_PSTIMEOUT] = IMR_PSTIMEOUT,
  297. .maps[RTL_IMR_BCNINT] = IMR_BCNDMAINT0,
  298. .maps[RTL_IMR_RXFOVW] = IMR_RXFOVW,
  299. .maps[RTL_IMR_RDU] = IMR_RDU,
  300. .maps[RTL_IMR_ATIMEND] = IMR_ATIMEND,
  301. .maps[RTL_IMR_BDOK] = IMR_BCNDOK0,
  302. .maps[RTL_IMR_MGNTDOK] = IMR_MGNTDOK,
  303. .maps[RTL_IMR_TBDER] = IMR_TBDER,
  304. .maps[RTL_IMR_HIGHDOK] = IMR_HIGHDOK,
  305. .maps[RTL_IMR_TBDOK] = IMR_TBDOK,
  306. .maps[RTL_IMR_BKDOK] = IMR_BKDOK,
  307. .maps[RTL_IMR_BEDOK] = IMR_BEDOK,
  308. .maps[RTL_IMR_VIDOK] = IMR_VIDOK,
  309. .maps[RTL_IMR_VODOK] = IMR_VODOK,
  310. .maps[RTL_IMR_ROK] = IMR_ROK,
  311. .maps[RTL_IBSS_INT_MASKS] = (IMR_BCNDMAINT0 | IMR_TBDOK | IMR_TBDER),
  312. .maps[RTL_RC_CCK_RATE1M] = DESC92C_RATE1M,
  313. .maps[RTL_RC_CCK_RATE2M] = DESC92C_RATE2M,
  314. .maps[RTL_RC_CCK_RATE5_5M] = DESC92C_RATE5_5M,
  315. .maps[RTL_RC_CCK_RATE11M] = DESC92C_RATE11M,
  316. .maps[RTL_RC_OFDM_RATE6M] = DESC92C_RATE6M,
  317. .maps[RTL_RC_OFDM_RATE9M] = DESC92C_RATE9M,
  318. .maps[RTL_RC_OFDM_RATE12M] = DESC92C_RATE12M,
  319. .maps[RTL_RC_OFDM_RATE18M] = DESC92C_RATE18M,
  320. .maps[RTL_RC_OFDM_RATE24M] = DESC92C_RATE24M,
  321. .maps[RTL_RC_OFDM_RATE36M] = DESC92C_RATE36M,
  322. .maps[RTL_RC_OFDM_RATE48M] = DESC92C_RATE48M,
  323. .maps[RTL_RC_OFDM_RATE54M] = DESC92C_RATE54M,
  324. .maps[RTL_RC_HT_RATEMCS7] = DESC92C_RATEMCS7,
  325. .maps[RTL_RC_HT_RATEMCS15] = DESC92C_RATEMCS15,
  326. };
  327. static DEFINE_PCI_DEVICE_TABLE(rtl88ee_pci_ids) = {
  328. {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8179, rtl88ee_hal_cfg)},
  329. {},
  330. };
  331. MODULE_DEVICE_TABLE(pci, rtl88ee_pci_ids);
  332. MODULE_AUTHOR("zhiyuan_yang <zhiyuan_yang@realsil.com.cn>");
  333. MODULE_AUTHOR("Realtek WlanFAE <wlanfae@realtek.com>");
  334. MODULE_AUTHOR("Larry Finger <Larry.Finger@lwfinger.net>");
  335. MODULE_LICENSE("GPL");
  336. MODULE_DESCRIPTION("Realtek 8188E 802.11n PCI wireless");
  337. MODULE_FIRMWARE("rtlwifi/rtl8188efw.bin");
  338. module_param_named(swenc, rtl88ee_mod_params.sw_crypto, bool, 0444);
  339. module_param_named(debug, rtl88ee_mod_params.debug, int, 0444);
  340. module_param_named(ips, rtl88ee_mod_params.inactiveps, bool, 0444);
  341. module_param_named(swlps, rtl88ee_mod_params.swctrl_lps, bool, 0444);
  342. module_param_named(fwlps, rtl88ee_mod_params.fwctrl_lps, bool, 0444);
  343. MODULE_PARM_DESC(swenc, "Set to 1 for software crypto (default 0)\n");
  344. MODULE_PARM_DESC(ips, "Set to 0 to not use link power save (default 1)\n");
  345. MODULE_PARM_DESC(swlps, "Set to 1 to use SW control power save (default 0)\n");
  346. MODULE_PARM_DESC(fwlps, "Set to 1 to use FW control power save (default 1)\n");
  347. MODULE_PARM_DESC(debug, "Set debug level (0-5) (default 0)");
  348. static SIMPLE_DEV_PM_OPS(rtlwifi_pm_ops, rtl_pci_suspend, rtl_pci_resume);
  349. static struct pci_driver rtl88ee_driver = {
  350. .name = KBUILD_MODNAME,
  351. .id_table = rtl88ee_pci_ids,
  352. .probe = rtl_pci_probe,
  353. .remove = rtl_pci_disconnect,
  354. .driver.pm = &rtlwifi_pm_ops,
  355. };
  356. module_pci_driver(rtl88ee_driver);