htc_drv_init.c 26 KB

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  1. /*
  2. * Copyright (c) 2010-2011 Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  17. #include "htc.h"
  18. MODULE_AUTHOR("Atheros Communications");
  19. MODULE_LICENSE("Dual BSD/GPL");
  20. MODULE_DESCRIPTION("Atheros driver 802.11n HTC based wireless devices");
  21. static unsigned int ath9k_debug = ATH_DBG_DEFAULT;
  22. module_param_named(debug, ath9k_debug, uint, 0);
  23. MODULE_PARM_DESC(debug, "Debugging mask");
  24. int htc_modparam_nohwcrypt;
  25. module_param_named(nohwcrypt, htc_modparam_nohwcrypt, int, 0444);
  26. MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
  27. static int ath9k_htc_btcoex_enable;
  28. module_param_named(btcoex_enable, ath9k_htc_btcoex_enable, int, 0444);
  29. MODULE_PARM_DESC(btcoex_enable, "Enable wifi-BT coexistence");
  30. #define CHAN2G(_freq, _idx) { \
  31. .center_freq = (_freq), \
  32. .hw_value = (_idx), \
  33. .max_power = 20, \
  34. }
  35. #define CHAN5G(_freq, _idx) { \
  36. .band = IEEE80211_BAND_5GHZ, \
  37. .center_freq = (_freq), \
  38. .hw_value = (_idx), \
  39. .max_power = 20, \
  40. }
  41. static struct ieee80211_channel ath9k_2ghz_channels[] = {
  42. CHAN2G(2412, 0), /* Channel 1 */
  43. CHAN2G(2417, 1), /* Channel 2 */
  44. CHAN2G(2422, 2), /* Channel 3 */
  45. CHAN2G(2427, 3), /* Channel 4 */
  46. CHAN2G(2432, 4), /* Channel 5 */
  47. CHAN2G(2437, 5), /* Channel 6 */
  48. CHAN2G(2442, 6), /* Channel 7 */
  49. CHAN2G(2447, 7), /* Channel 8 */
  50. CHAN2G(2452, 8), /* Channel 9 */
  51. CHAN2G(2457, 9), /* Channel 10 */
  52. CHAN2G(2462, 10), /* Channel 11 */
  53. CHAN2G(2467, 11), /* Channel 12 */
  54. CHAN2G(2472, 12), /* Channel 13 */
  55. CHAN2G(2484, 13), /* Channel 14 */
  56. };
  57. static struct ieee80211_channel ath9k_5ghz_channels[] = {
  58. /* _We_ call this UNII 1 */
  59. CHAN5G(5180, 14), /* Channel 36 */
  60. CHAN5G(5200, 15), /* Channel 40 */
  61. CHAN5G(5220, 16), /* Channel 44 */
  62. CHAN5G(5240, 17), /* Channel 48 */
  63. /* _We_ call this UNII 2 */
  64. CHAN5G(5260, 18), /* Channel 52 */
  65. CHAN5G(5280, 19), /* Channel 56 */
  66. CHAN5G(5300, 20), /* Channel 60 */
  67. CHAN5G(5320, 21), /* Channel 64 */
  68. /* _We_ call this "Middle band" */
  69. CHAN5G(5500, 22), /* Channel 100 */
  70. CHAN5G(5520, 23), /* Channel 104 */
  71. CHAN5G(5540, 24), /* Channel 108 */
  72. CHAN5G(5560, 25), /* Channel 112 */
  73. CHAN5G(5580, 26), /* Channel 116 */
  74. CHAN5G(5600, 27), /* Channel 120 */
  75. CHAN5G(5620, 28), /* Channel 124 */
  76. CHAN5G(5640, 29), /* Channel 128 */
  77. CHAN5G(5660, 30), /* Channel 132 */
  78. CHAN5G(5680, 31), /* Channel 136 */
  79. CHAN5G(5700, 32), /* Channel 140 */
  80. /* _We_ call this UNII 3 */
  81. CHAN5G(5745, 33), /* Channel 149 */
  82. CHAN5G(5765, 34), /* Channel 153 */
  83. CHAN5G(5785, 35), /* Channel 157 */
  84. CHAN5G(5805, 36), /* Channel 161 */
  85. CHAN5G(5825, 37), /* Channel 165 */
  86. };
  87. /* Atheros hardware rate code addition for short premble */
  88. #define SHPCHECK(__hw_rate, __flags) \
  89. ((__flags & IEEE80211_RATE_SHORT_PREAMBLE) ? (__hw_rate | 0x04) : 0)
  90. #define RATE(_bitrate, _hw_rate, _flags) { \
  91. .bitrate = (_bitrate), \
  92. .flags = (_flags), \
  93. .hw_value = (_hw_rate), \
  94. .hw_value_short = (SHPCHECK(_hw_rate, _flags)) \
  95. }
  96. static struct ieee80211_rate ath9k_legacy_rates[] = {
  97. RATE(10, 0x1b, 0),
  98. RATE(20, 0x1a, IEEE80211_RATE_SHORT_PREAMBLE), /* shortp : 0x1e */
  99. RATE(55, 0x19, IEEE80211_RATE_SHORT_PREAMBLE), /* shortp: 0x1d */
  100. RATE(110, 0x18, IEEE80211_RATE_SHORT_PREAMBLE), /* short: 0x1c */
  101. RATE(60, 0x0b, 0),
  102. RATE(90, 0x0f, 0),
  103. RATE(120, 0x0a, 0),
  104. RATE(180, 0x0e, 0),
  105. RATE(240, 0x09, 0),
  106. RATE(360, 0x0d, 0),
  107. RATE(480, 0x08, 0),
  108. RATE(540, 0x0c, 0),
  109. };
  110. #ifdef CONFIG_MAC80211_LEDS
  111. static const struct ieee80211_tpt_blink ath9k_htc_tpt_blink[] = {
  112. { .throughput = 0 * 1024, .blink_time = 334 },
  113. { .throughput = 1 * 1024, .blink_time = 260 },
  114. { .throughput = 5 * 1024, .blink_time = 220 },
  115. { .throughput = 10 * 1024, .blink_time = 190 },
  116. { .throughput = 20 * 1024, .blink_time = 170 },
  117. { .throughput = 50 * 1024, .blink_time = 150 },
  118. { .throughput = 70 * 1024, .blink_time = 130 },
  119. { .throughput = 100 * 1024, .blink_time = 110 },
  120. { .throughput = 200 * 1024, .blink_time = 80 },
  121. { .throughput = 300 * 1024, .blink_time = 50 },
  122. };
  123. #endif
  124. static int ath9k_htc_wait_for_target(struct ath9k_htc_priv *priv)
  125. {
  126. int time_left;
  127. if (atomic_read(&priv->htc->tgt_ready) > 0) {
  128. atomic_dec(&priv->htc->tgt_ready);
  129. return 0;
  130. }
  131. /* Firmware can take up to 50ms to get ready, to be safe use 1 second */
  132. time_left = wait_for_completion_timeout(&priv->htc->target_wait, HZ);
  133. if (!time_left) {
  134. dev_err(priv->dev, "ath9k_htc: Target is unresponsive\n");
  135. return -ETIMEDOUT;
  136. }
  137. atomic_dec(&priv->htc->tgt_ready);
  138. return 0;
  139. }
  140. static void ath9k_deinit_priv(struct ath9k_htc_priv *priv)
  141. {
  142. ath9k_hw_deinit(priv->ah);
  143. kfree(priv->ah);
  144. priv->ah = NULL;
  145. }
  146. static void ath9k_deinit_device(struct ath9k_htc_priv *priv)
  147. {
  148. struct ieee80211_hw *hw = priv->hw;
  149. wiphy_rfkill_stop_polling(hw->wiphy);
  150. ath9k_deinit_leds(priv);
  151. ieee80211_unregister_hw(hw);
  152. ath9k_rx_cleanup(priv);
  153. ath9k_tx_cleanup(priv);
  154. ath9k_deinit_priv(priv);
  155. }
  156. static inline int ath9k_htc_connect_svc(struct ath9k_htc_priv *priv,
  157. u16 service_id,
  158. void (*tx) (void *,
  159. struct sk_buff *,
  160. enum htc_endpoint_id,
  161. bool txok),
  162. enum htc_endpoint_id *ep_id)
  163. {
  164. struct htc_service_connreq req;
  165. memset(&req, 0, sizeof(struct htc_service_connreq));
  166. req.service_id = service_id;
  167. req.ep_callbacks.priv = priv;
  168. req.ep_callbacks.rx = ath9k_htc_rxep;
  169. req.ep_callbacks.tx = tx;
  170. return htc_connect_service(priv->htc, &req, ep_id);
  171. }
  172. static int ath9k_init_htc_services(struct ath9k_htc_priv *priv, u16 devid,
  173. u32 drv_info)
  174. {
  175. int ret;
  176. /* WMI CMD*/
  177. ret = ath9k_wmi_connect(priv->htc, priv->wmi, &priv->wmi_cmd_ep);
  178. if (ret)
  179. goto err;
  180. /* Beacon */
  181. ret = ath9k_htc_connect_svc(priv, WMI_BEACON_SVC, ath9k_htc_beaconep,
  182. &priv->beacon_ep);
  183. if (ret)
  184. goto err;
  185. /* CAB */
  186. ret = ath9k_htc_connect_svc(priv, WMI_CAB_SVC, ath9k_htc_txep,
  187. &priv->cab_ep);
  188. if (ret)
  189. goto err;
  190. /* UAPSD */
  191. ret = ath9k_htc_connect_svc(priv, WMI_UAPSD_SVC, ath9k_htc_txep,
  192. &priv->uapsd_ep);
  193. if (ret)
  194. goto err;
  195. /* MGMT */
  196. ret = ath9k_htc_connect_svc(priv, WMI_MGMT_SVC, ath9k_htc_txep,
  197. &priv->mgmt_ep);
  198. if (ret)
  199. goto err;
  200. /* DATA BE */
  201. ret = ath9k_htc_connect_svc(priv, WMI_DATA_BE_SVC, ath9k_htc_txep,
  202. &priv->data_be_ep);
  203. if (ret)
  204. goto err;
  205. /* DATA BK */
  206. ret = ath9k_htc_connect_svc(priv, WMI_DATA_BK_SVC, ath9k_htc_txep,
  207. &priv->data_bk_ep);
  208. if (ret)
  209. goto err;
  210. /* DATA VI */
  211. ret = ath9k_htc_connect_svc(priv, WMI_DATA_VI_SVC, ath9k_htc_txep,
  212. &priv->data_vi_ep);
  213. if (ret)
  214. goto err;
  215. /* DATA VO */
  216. ret = ath9k_htc_connect_svc(priv, WMI_DATA_VO_SVC, ath9k_htc_txep,
  217. &priv->data_vo_ep);
  218. if (ret)
  219. goto err;
  220. /*
  221. * Setup required credits before initializing HTC.
  222. * This is a bit hacky, but, since queuing is done in
  223. * the HIF layer, shouldn't matter much.
  224. */
  225. if (IS_AR7010_DEVICE(drv_info))
  226. priv->htc->credits = 45;
  227. else
  228. priv->htc->credits = 33;
  229. ret = htc_init(priv->htc);
  230. if (ret)
  231. goto err;
  232. dev_info(priv->dev, "ath9k_htc: HTC initialized with %d credits\n",
  233. priv->htc->credits);
  234. return 0;
  235. err:
  236. dev_err(priv->dev, "ath9k_htc: Unable to initialize HTC services\n");
  237. return ret;
  238. }
  239. static void ath9k_reg_notifier(struct wiphy *wiphy,
  240. struct regulatory_request *request)
  241. {
  242. struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
  243. struct ath9k_htc_priv *priv = hw->priv;
  244. ath_reg_notifier_apply(wiphy, request,
  245. ath9k_hw_regulatory(priv->ah));
  246. }
  247. static unsigned int ath9k_regread(void *hw_priv, u32 reg_offset)
  248. {
  249. struct ath_hw *ah = (struct ath_hw *) hw_priv;
  250. struct ath_common *common = ath9k_hw_common(ah);
  251. struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
  252. __be32 val, reg = cpu_to_be32(reg_offset);
  253. int r;
  254. r = ath9k_wmi_cmd(priv->wmi, WMI_REG_READ_CMDID,
  255. (u8 *) &reg, sizeof(reg),
  256. (u8 *) &val, sizeof(val),
  257. 100);
  258. if (unlikely(r)) {
  259. ath_dbg(common, WMI, "REGISTER READ FAILED: (0x%04x, %d)\n",
  260. reg_offset, r);
  261. return -EIO;
  262. }
  263. return be32_to_cpu(val);
  264. }
  265. static void ath9k_multi_regread(void *hw_priv, u32 *addr,
  266. u32 *val, u16 count)
  267. {
  268. struct ath_hw *ah = (struct ath_hw *) hw_priv;
  269. struct ath_common *common = ath9k_hw_common(ah);
  270. struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
  271. __be32 tmpaddr[8];
  272. __be32 tmpval[8];
  273. int i, ret;
  274. for (i = 0; i < count; i++) {
  275. tmpaddr[i] = cpu_to_be32(addr[i]);
  276. }
  277. ret = ath9k_wmi_cmd(priv->wmi, WMI_REG_READ_CMDID,
  278. (u8 *)tmpaddr , sizeof(u32) * count,
  279. (u8 *)tmpval, sizeof(u32) * count,
  280. 100);
  281. if (unlikely(ret)) {
  282. ath_dbg(common, WMI,
  283. "Multiple REGISTER READ FAILED (count: %d)\n", count);
  284. }
  285. for (i = 0; i < count; i++) {
  286. val[i] = be32_to_cpu(tmpval[i]);
  287. }
  288. }
  289. static void ath9k_regwrite_single(void *hw_priv, u32 val, u32 reg_offset)
  290. {
  291. struct ath_hw *ah = (struct ath_hw *) hw_priv;
  292. struct ath_common *common = ath9k_hw_common(ah);
  293. struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
  294. const __be32 buf[2] = {
  295. cpu_to_be32(reg_offset),
  296. cpu_to_be32(val),
  297. };
  298. int r;
  299. r = ath9k_wmi_cmd(priv->wmi, WMI_REG_WRITE_CMDID,
  300. (u8 *) &buf, sizeof(buf),
  301. (u8 *) &val, sizeof(val),
  302. 100);
  303. if (unlikely(r)) {
  304. ath_dbg(common, WMI, "REGISTER WRITE FAILED:(0x%04x, %d)\n",
  305. reg_offset, r);
  306. }
  307. }
  308. static void ath9k_regwrite_buffer(void *hw_priv, u32 val, u32 reg_offset)
  309. {
  310. struct ath_hw *ah = (struct ath_hw *) hw_priv;
  311. struct ath_common *common = ath9k_hw_common(ah);
  312. struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
  313. u32 rsp_status;
  314. int r;
  315. mutex_lock(&priv->wmi->multi_write_mutex);
  316. /* Store the register/value */
  317. priv->wmi->multi_write[priv->wmi->multi_write_idx].reg =
  318. cpu_to_be32(reg_offset);
  319. priv->wmi->multi_write[priv->wmi->multi_write_idx].val =
  320. cpu_to_be32(val);
  321. priv->wmi->multi_write_idx++;
  322. /* If the buffer is full, send it out. */
  323. if (priv->wmi->multi_write_idx == MAX_CMD_NUMBER) {
  324. r = ath9k_wmi_cmd(priv->wmi, WMI_REG_WRITE_CMDID,
  325. (u8 *) &priv->wmi->multi_write,
  326. sizeof(struct register_write) * priv->wmi->multi_write_idx,
  327. (u8 *) &rsp_status, sizeof(rsp_status),
  328. 100);
  329. if (unlikely(r)) {
  330. ath_dbg(common, WMI,
  331. "REGISTER WRITE FAILED, multi len: %d\n",
  332. priv->wmi->multi_write_idx);
  333. }
  334. priv->wmi->multi_write_idx = 0;
  335. }
  336. mutex_unlock(&priv->wmi->multi_write_mutex);
  337. }
  338. static void ath9k_regwrite(void *hw_priv, u32 val, u32 reg_offset)
  339. {
  340. struct ath_hw *ah = (struct ath_hw *) hw_priv;
  341. struct ath_common *common = ath9k_hw_common(ah);
  342. struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
  343. if (atomic_read(&priv->wmi->mwrite_cnt))
  344. ath9k_regwrite_buffer(hw_priv, val, reg_offset);
  345. else
  346. ath9k_regwrite_single(hw_priv, val, reg_offset);
  347. }
  348. static void ath9k_enable_regwrite_buffer(void *hw_priv)
  349. {
  350. struct ath_hw *ah = (struct ath_hw *) hw_priv;
  351. struct ath_common *common = ath9k_hw_common(ah);
  352. struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
  353. atomic_inc(&priv->wmi->mwrite_cnt);
  354. }
  355. static void ath9k_regwrite_flush(void *hw_priv)
  356. {
  357. struct ath_hw *ah = (struct ath_hw *) hw_priv;
  358. struct ath_common *common = ath9k_hw_common(ah);
  359. struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
  360. u32 rsp_status;
  361. int r;
  362. atomic_dec(&priv->wmi->mwrite_cnt);
  363. mutex_lock(&priv->wmi->multi_write_mutex);
  364. if (priv->wmi->multi_write_idx) {
  365. r = ath9k_wmi_cmd(priv->wmi, WMI_REG_WRITE_CMDID,
  366. (u8 *) &priv->wmi->multi_write,
  367. sizeof(struct register_write) * priv->wmi->multi_write_idx,
  368. (u8 *) &rsp_status, sizeof(rsp_status),
  369. 100);
  370. if (unlikely(r)) {
  371. ath_dbg(common, WMI,
  372. "REGISTER WRITE FAILED, multi len: %d\n",
  373. priv->wmi->multi_write_idx);
  374. }
  375. priv->wmi->multi_write_idx = 0;
  376. }
  377. mutex_unlock(&priv->wmi->multi_write_mutex);
  378. }
  379. static u32 ath9k_reg_rmw(void *hw_priv, u32 reg_offset, u32 set, u32 clr)
  380. {
  381. u32 val;
  382. val = ath9k_regread(hw_priv, reg_offset);
  383. val &= ~clr;
  384. val |= set;
  385. ath9k_regwrite(hw_priv, val, reg_offset);
  386. return val;
  387. }
  388. static void ath_usb_read_cachesize(struct ath_common *common, int *csz)
  389. {
  390. *csz = L1_CACHE_BYTES >> 2;
  391. }
  392. static bool ath_usb_eeprom_read(struct ath_common *common, u32 off, u16 *data)
  393. {
  394. struct ath_hw *ah = (struct ath_hw *) common->ah;
  395. (void)REG_READ(ah, AR5416_EEPROM_OFFSET + (off << AR5416_EEPROM_S));
  396. if (!ath9k_hw_wait(ah,
  397. AR_EEPROM_STATUS_DATA,
  398. AR_EEPROM_STATUS_DATA_BUSY |
  399. AR_EEPROM_STATUS_DATA_PROT_ACCESS, 0,
  400. AH_WAIT_TIMEOUT))
  401. return false;
  402. *data = MS(REG_READ(ah, AR_EEPROM_STATUS_DATA),
  403. AR_EEPROM_STATUS_DATA_VAL);
  404. return true;
  405. }
  406. static const struct ath_bus_ops ath9k_usb_bus_ops = {
  407. .ath_bus_type = ATH_USB,
  408. .read_cachesize = ath_usb_read_cachesize,
  409. .eeprom_read = ath_usb_eeprom_read,
  410. };
  411. static void setup_ht_cap(struct ath9k_htc_priv *priv,
  412. struct ieee80211_sta_ht_cap *ht_info)
  413. {
  414. struct ath_common *common = ath9k_hw_common(priv->ah);
  415. u8 tx_streams, rx_streams;
  416. int i;
  417. ht_info->ht_supported = true;
  418. ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
  419. IEEE80211_HT_CAP_SM_PS |
  420. IEEE80211_HT_CAP_SGI_40 |
  421. IEEE80211_HT_CAP_DSSSCCK40;
  422. if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_SGI_20)
  423. ht_info->cap |= IEEE80211_HT_CAP_SGI_20;
  424. ht_info->cap |= (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT);
  425. ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
  426. ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8;
  427. memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
  428. /* ath9k_htc supports only 1 or 2 stream devices */
  429. tx_streams = ath9k_cmn_count_streams(priv->ah->txchainmask, 2);
  430. rx_streams = ath9k_cmn_count_streams(priv->ah->rxchainmask, 2);
  431. ath_dbg(common, CONFIG, "TX streams %d, RX streams: %d\n",
  432. tx_streams, rx_streams);
  433. if (tx_streams >= 2)
  434. ht_info->cap |= IEEE80211_HT_CAP_TX_STBC;
  435. if (tx_streams != rx_streams) {
  436. ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
  437. ht_info->mcs.tx_params |= ((tx_streams - 1) <<
  438. IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
  439. }
  440. for (i = 0; i < rx_streams; i++)
  441. ht_info->mcs.rx_mask[i] = 0xff;
  442. ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED;
  443. }
  444. static int ath9k_init_queues(struct ath9k_htc_priv *priv)
  445. {
  446. struct ath_common *common = ath9k_hw_common(priv->ah);
  447. int i;
  448. for (i = 0; i < ARRAY_SIZE(priv->hwq_map); i++)
  449. priv->hwq_map[i] = -1;
  450. priv->beaconq = ath9k_hw_beaconq_setup(priv->ah);
  451. if (priv->beaconq == -1) {
  452. ath_err(common, "Unable to setup BEACON xmit queue\n");
  453. goto err;
  454. }
  455. priv->cabq = ath9k_htc_cabq_setup(priv);
  456. if (priv->cabq == -1) {
  457. ath_err(common, "Unable to setup CAB xmit queue\n");
  458. goto err;
  459. }
  460. if (!ath9k_htc_txq_setup(priv, IEEE80211_AC_BE)) {
  461. ath_err(common, "Unable to setup xmit queue for BE traffic\n");
  462. goto err;
  463. }
  464. if (!ath9k_htc_txq_setup(priv, IEEE80211_AC_BK)) {
  465. ath_err(common, "Unable to setup xmit queue for BK traffic\n");
  466. goto err;
  467. }
  468. if (!ath9k_htc_txq_setup(priv, IEEE80211_AC_VI)) {
  469. ath_err(common, "Unable to setup xmit queue for VI traffic\n");
  470. goto err;
  471. }
  472. if (!ath9k_htc_txq_setup(priv, IEEE80211_AC_VO)) {
  473. ath_err(common, "Unable to setup xmit queue for VO traffic\n");
  474. goto err;
  475. }
  476. return 0;
  477. err:
  478. return -EINVAL;
  479. }
  480. static void ath9k_init_channels_rates(struct ath9k_htc_priv *priv)
  481. {
  482. if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) {
  483. priv->sbands[IEEE80211_BAND_2GHZ].channels =
  484. ath9k_2ghz_channels;
  485. priv->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
  486. priv->sbands[IEEE80211_BAND_2GHZ].n_channels =
  487. ARRAY_SIZE(ath9k_2ghz_channels);
  488. priv->sbands[IEEE80211_BAND_2GHZ].bitrates = ath9k_legacy_rates;
  489. priv->sbands[IEEE80211_BAND_2GHZ].n_bitrates =
  490. ARRAY_SIZE(ath9k_legacy_rates);
  491. }
  492. if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) {
  493. priv->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_channels;
  494. priv->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
  495. priv->sbands[IEEE80211_BAND_5GHZ].n_channels =
  496. ARRAY_SIZE(ath9k_5ghz_channels);
  497. priv->sbands[IEEE80211_BAND_5GHZ].bitrates =
  498. ath9k_legacy_rates + 4;
  499. priv->sbands[IEEE80211_BAND_5GHZ].n_bitrates =
  500. ARRAY_SIZE(ath9k_legacy_rates) - 4;
  501. }
  502. }
  503. static void ath9k_init_misc(struct ath9k_htc_priv *priv)
  504. {
  505. struct ath_common *common = ath9k_hw_common(priv->ah);
  506. memcpy(common->bssidmask, ath_bcast_mac, ETH_ALEN);
  507. priv->ah->opmode = NL80211_IFTYPE_STATION;
  508. }
  509. static int ath9k_init_priv(struct ath9k_htc_priv *priv,
  510. u16 devid, char *product,
  511. u32 drv_info)
  512. {
  513. struct ath_hw *ah = NULL;
  514. struct ath_common *common;
  515. int i, ret = 0, csz = 0;
  516. set_bit(OP_INVALID, &priv->op_flags);
  517. ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL);
  518. if (!ah)
  519. return -ENOMEM;
  520. ah->hw_version.devid = devid;
  521. ah->hw_version.usbdev = drv_info;
  522. ah->ah_flags |= AH_USE_EEPROM;
  523. ah->reg_ops.read = ath9k_regread;
  524. ah->reg_ops.multi_read = ath9k_multi_regread;
  525. ah->reg_ops.write = ath9k_regwrite;
  526. ah->reg_ops.enable_write_buffer = ath9k_enable_regwrite_buffer;
  527. ah->reg_ops.write_flush = ath9k_regwrite_flush;
  528. ah->reg_ops.rmw = ath9k_reg_rmw;
  529. priv->ah = ah;
  530. common = ath9k_hw_common(ah);
  531. common->ops = &ah->reg_ops;
  532. common->bus_ops = &ath9k_usb_bus_ops;
  533. common->ah = ah;
  534. common->hw = priv->hw;
  535. common->priv = priv;
  536. common->debug_mask = ath9k_debug;
  537. common->btcoex_enabled = ath9k_htc_btcoex_enable == 1;
  538. spin_lock_init(&priv->beacon_lock);
  539. spin_lock_init(&priv->tx.tx_lock);
  540. mutex_init(&priv->mutex);
  541. mutex_init(&priv->htc_pm_lock);
  542. tasklet_init(&priv->rx_tasklet, ath9k_rx_tasklet,
  543. (unsigned long)priv);
  544. tasklet_init(&priv->tx_failed_tasklet, ath9k_tx_failed_tasklet,
  545. (unsigned long)priv);
  546. INIT_DELAYED_WORK(&priv->ani_work, ath9k_htc_ani_work);
  547. INIT_WORK(&priv->ps_work, ath9k_ps_work);
  548. INIT_WORK(&priv->fatal_work, ath9k_fatal_work);
  549. setup_timer(&priv->tx.cleanup_timer, ath9k_htc_tx_cleanup_timer,
  550. (unsigned long)priv);
  551. /*
  552. * Cache line size is used to size and align various
  553. * structures used to communicate with the hardware.
  554. */
  555. ath_read_cachesize(common, &csz);
  556. common->cachelsz = csz << 2; /* convert to bytes */
  557. ret = ath9k_hw_init(ah);
  558. if (ret) {
  559. ath_err(common,
  560. "Unable to initialize hardware; initialization status: %d\n",
  561. ret);
  562. goto err_hw;
  563. }
  564. ret = ath9k_init_queues(priv);
  565. if (ret)
  566. goto err_queues;
  567. for (i = 0; i < ATH9K_HTC_MAX_BCN_VIF; i++)
  568. priv->cur_beacon_conf.bslot[i] = NULL;
  569. ath9k_cmn_init_crypto(ah);
  570. ath9k_init_channels_rates(priv);
  571. ath9k_init_misc(priv);
  572. ath9k_htc_init_btcoex(priv, product);
  573. return 0;
  574. err_queues:
  575. ath9k_hw_deinit(ah);
  576. err_hw:
  577. kfree(ah);
  578. priv->ah = NULL;
  579. return ret;
  580. }
  581. static const struct ieee80211_iface_limit if_limits[] = {
  582. { .max = 2, .types = BIT(NL80211_IFTYPE_STATION) |
  583. BIT(NL80211_IFTYPE_P2P_CLIENT) },
  584. { .max = 2, .types = BIT(NL80211_IFTYPE_AP) |
  585. #ifdef CONFIG_MAC80211_MESH
  586. BIT(NL80211_IFTYPE_MESH_POINT) |
  587. #endif
  588. BIT(NL80211_IFTYPE_P2P_GO) },
  589. };
  590. static const struct ieee80211_iface_combination if_comb = {
  591. .limits = if_limits,
  592. .n_limits = ARRAY_SIZE(if_limits),
  593. .max_interfaces = 2,
  594. .num_different_channels = 1,
  595. };
  596. static void ath9k_set_hw_capab(struct ath9k_htc_priv *priv,
  597. struct ieee80211_hw *hw)
  598. {
  599. struct ath_common *common = ath9k_hw_common(priv->ah);
  600. struct base_eep_header *pBase;
  601. hw->flags = IEEE80211_HW_SIGNAL_DBM |
  602. IEEE80211_HW_AMPDU_AGGREGATION |
  603. IEEE80211_HW_SPECTRUM_MGMT |
  604. IEEE80211_HW_HAS_RATE_CONTROL |
  605. IEEE80211_HW_RX_INCLUDES_FCS |
  606. IEEE80211_HW_SUPPORTS_PS |
  607. IEEE80211_HW_PS_NULLFUNC_STACK |
  608. IEEE80211_HW_REPORTS_TX_ACK_STATUS |
  609. IEEE80211_HW_MFP_CAPABLE |
  610. IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
  611. hw->wiphy->interface_modes =
  612. BIT(NL80211_IFTYPE_STATION) |
  613. BIT(NL80211_IFTYPE_ADHOC) |
  614. BIT(NL80211_IFTYPE_AP) |
  615. BIT(NL80211_IFTYPE_P2P_GO) |
  616. BIT(NL80211_IFTYPE_P2P_CLIENT) |
  617. BIT(NL80211_IFTYPE_MESH_POINT);
  618. hw->wiphy->iface_combinations = &if_comb;
  619. hw->wiphy->n_iface_combinations = 1;
  620. hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
  621. hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN |
  622. WIPHY_FLAG_HAS_REMAIN_ON_CHANNEL;
  623. hw->queues = 4;
  624. hw->channel_change_time = 5000;
  625. hw->max_listen_interval = 1;
  626. hw->vif_data_size = sizeof(struct ath9k_htc_vif);
  627. hw->sta_data_size = sizeof(struct ath9k_htc_sta);
  628. /* tx_frame_hdr is larger than tx_mgmt_hdr anyway */
  629. hw->extra_tx_headroom = sizeof(struct tx_frame_hdr) +
  630. sizeof(struct htc_frame_hdr) + 4;
  631. if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
  632. hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
  633. &priv->sbands[IEEE80211_BAND_2GHZ];
  634. if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)
  635. hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
  636. &priv->sbands[IEEE80211_BAND_5GHZ];
  637. if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
  638. if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
  639. setup_ht_cap(priv,
  640. &priv->sbands[IEEE80211_BAND_2GHZ].ht_cap);
  641. if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)
  642. setup_ht_cap(priv,
  643. &priv->sbands[IEEE80211_BAND_5GHZ].ht_cap);
  644. }
  645. pBase = ath9k_htc_get_eeprom_base(priv);
  646. if (pBase) {
  647. hw->wiphy->available_antennas_rx = pBase->rxMask;
  648. hw->wiphy->available_antennas_tx = pBase->txMask;
  649. }
  650. SET_IEEE80211_PERM_ADDR(hw, common->macaddr);
  651. }
  652. static int ath9k_init_firmware_version(struct ath9k_htc_priv *priv)
  653. {
  654. struct ieee80211_hw *hw = priv->hw;
  655. struct wmi_fw_version cmd_rsp;
  656. int ret;
  657. memset(&cmd_rsp, 0, sizeof(cmd_rsp));
  658. WMI_CMD(WMI_GET_FW_VERSION);
  659. if (ret)
  660. return -EINVAL;
  661. priv->fw_version_major = be16_to_cpu(cmd_rsp.major);
  662. priv->fw_version_minor = be16_to_cpu(cmd_rsp.minor);
  663. snprintf(hw->wiphy->fw_version, sizeof(hw->wiphy->fw_version), "%d.%d",
  664. priv->fw_version_major,
  665. priv->fw_version_minor);
  666. dev_info(priv->dev, "ath9k_htc: FW Version: %d.%d\n",
  667. priv->fw_version_major,
  668. priv->fw_version_minor);
  669. /*
  670. * Check if the available FW matches the driver's
  671. * required version.
  672. */
  673. if (priv->fw_version_major != MAJOR_VERSION_REQ ||
  674. priv->fw_version_minor < MINOR_VERSION_REQ) {
  675. dev_err(priv->dev, "ath9k_htc: Please upgrade to FW version %d.%d\n",
  676. MAJOR_VERSION_REQ, MINOR_VERSION_REQ);
  677. return -EINVAL;
  678. }
  679. return 0;
  680. }
  681. static int ath9k_init_device(struct ath9k_htc_priv *priv,
  682. u16 devid, char *product, u32 drv_info)
  683. {
  684. struct ieee80211_hw *hw = priv->hw;
  685. struct ath_common *common;
  686. struct ath_hw *ah;
  687. int error = 0;
  688. struct ath_regulatory *reg;
  689. char hw_name[64];
  690. /* Bring up device */
  691. error = ath9k_init_priv(priv, devid, product, drv_info);
  692. if (error != 0)
  693. goto err_init;
  694. ah = priv->ah;
  695. common = ath9k_hw_common(ah);
  696. ath9k_set_hw_capab(priv, hw);
  697. error = ath9k_init_firmware_version(priv);
  698. if (error != 0)
  699. goto err_fw;
  700. /* Initialize regulatory */
  701. error = ath_regd_init(&common->regulatory, priv->hw->wiphy,
  702. ath9k_reg_notifier);
  703. if (error)
  704. goto err_regd;
  705. reg = &common->regulatory;
  706. /* Setup TX */
  707. error = ath9k_tx_init(priv);
  708. if (error != 0)
  709. goto err_tx;
  710. /* Setup RX */
  711. error = ath9k_rx_init(priv);
  712. if (error != 0)
  713. goto err_rx;
  714. ath9k_hw_disable(priv->ah);
  715. #ifdef CONFIG_MAC80211_LEDS
  716. /* must be initialized before ieee80211_register_hw */
  717. priv->led_cdev.default_trigger = ieee80211_create_tpt_led_trigger(priv->hw,
  718. IEEE80211_TPT_LEDTRIG_FL_RADIO, ath9k_htc_tpt_blink,
  719. ARRAY_SIZE(ath9k_htc_tpt_blink));
  720. #endif
  721. /* Register with mac80211 */
  722. error = ieee80211_register_hw(hw);
  723. if (error)
  724. goto err_register;
  725. /* Handle world regulatory */
  726. if (!ath_is_world_regd(reg)) {
  727. error = regulatory_hint(hw->wiphy, reg->alpha2);
  728. if (error)
  729. goto err_world;
  730. }
  731. error = ath9k_htc_init_debug(priv->ah);
  732. if (error) {
  733. ath_err(common, "Unable to create debugfs files\n");
  734. goto err_world;
  735. }
  736. ath_dbg(common, CONFIG,
  737. "WMI:%d, BCN:%d, CAB:%d, UAPSD:%d, MGMT:%d, BE:%d, BK:%d, VI:%d, VO:%d\n",
  738. priv->wmi_cmd_ep,
  739. priv->beacon_ep,
  740. priv->cab_ep,
  741. priv->uapsd_ep,
  742. priv->mgmt_ep,
  743. priv->data_be_ep,
  744. priv->data_bk_ep,
  745. priv->data_vi_ep,
  746. priv->data_vo_ep);
  747. ath9k_hw_name(priv->ah, hw_name, sizeof(hw_name));
  748. wiphy_info(hw->wiphy, "%s\n", hw_name);
  749. ath9k_init_leds(priv);
  750. ath9k_start_rfkill_poll(priv);
  751. return 0;
  752. err_world:
  753. ieee80211_unregister_hw(hw);
  754. err_register:
  755. ath9k_rx_cleanup(priv);
  756. err_rx:
  757. ath9k_tx_cleanup(priv);
  758. err_tx:
  759. /* Nothing */
  760. err_regd:
  761. /* Nothing */
  762. err_fw:
  763. ath9k_deinit_priv(priv);
  764. err_init:
  765. return error;
  766. }
  767. int ath9k_htc_probe_device(struct htc_target *htc_handle, struct device *dev,
  768. u16 devid, char *product, u32 drv_info)
  769. {
  770. struct ieee80211_hw *hw;
  771. struct ath9k_htc_priv *priv;
  772. int ret;
  773. hw = ieee80211_alloc_hw(sizeof(struct ath9k_htc_priv), &ath9k_htc_ops);
  774. if (!hw)
  775. return -ENOMEM;
  776. priv = hw->priv;
  777. priv->hw = hw;
  778. priv->htc = htc_handle;
  779. priv->dev = dev;
  780. htc_handle->drv_priv = priv;
  781. SET_IEEE80211_DEV(hw, priv->dev);
  782. ret = ath9k_htc_wait_for_target(priv);
  783. if (ret)
  784. goto err_free;
  785. priv->wmi = ath9k_init_wmi(priv);
  786. if (!priv->wmi) {
  787. ret = -EINVAL;
  788. goto err_free;
  789. }
  790. ret = ath9k_init_htc_services(priv, devid, drv_info);
  791. if (ret)
  792. goto err_init;
  793. ret = ath9k_init_device(priv, devid, product, drv_info);
  794. if (ret)
  795. goto err_init;
  796. return 0;
  797. err_init:
  798. ath9k_deinit_wmi(priv);
  799. err_free:
  800. ieee80211_free_hw(hw);
  801. return ret;
  802. }
  803. void ath9k_htc_disconnect_device(struct htc_target *htc_handle, bool hotunplug)
  804. {
  805. if (htc_handle->drv_priv) {
  806. /* Check if the device has been yanked out. */
  807. if (hotunplug)
  808. htc_handle->drv_priv->ah->ah_flags |= AH_UNPLUGGED;
  809. ath9k_deinit_device(htc_handle->drv_priv);
  810. ath9k_deinit_wmi(htc_handle->drv_priv);
  811. ieee80211_free_hw(htc_handle->drv_priv->hw);
  812. }
  813. }
  814. #ifdef CONFIG_PM
  815. void ath9k_htc_suspend(struct htc_target *htc_handle)
  816. {
  817. ath9k_htc_setpower(htc_handle->drv_priv, ATH9K_PM_FULL_SLEEP);
  818. }
  819. int ath9k_htc_resume(struct htc_target *htc_handle)
  820. {
  821. struct ath9k_htc_priv *priv = htc_handle->drv_priv;
  822. int ret;
  823. ret = ath9k_htc_wait_for_target(priv);
  824. if (ret)
  825. return ret;
  826. ret = ath9k_init_htc_services(priv, priv->ah->hw_version.devid,
  827. priv->ah->hw_version.usbdev);
  828. return ret;
  829. }
  830. #endif
  831. static int __init ath9k_htc_init(void)
  832. {
  833. if (ath9k_hif_usb_init() < 0) {
  834. pr_err("No USB devices found, driver not installed\n");
  835. return -ENODEV;
  836. }
  837. return 0;
  838. }
  839. module_init(ath9k_htc_init);
  840. static void __exit ath9k_htc_exit(void)
  841. {
  842. ath9k_hif_usb_exit();
  843. pr_info("Driver unloaded\n");
  844. }
  845. module_exit(ath9k_htc_exit);