ax88179_178a.c 37 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458
  1. /*
  2. * ASIX AX88179/178A USB 3.0/2.0 to Gigabit Ethernet Devices
  3. *
  4. * Copyright (C) 2011-2013 ASIX
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License
  8. * as published by the Free Software Foundation; either version 2
  9. * of the License, or (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19. */
  20. #include <linux/module.h>
  21. #include <linux/etherdevice.h>
  22. #include <linux/mii.h>
  23. #include <linux/usb.h>
  24. #include <linux/crc32.h>
  25. #include <linux/usb/usbnet.h>
  26. #define AX88179_PHY_ID 0x03
  27. #define AX_EEPROM_LEN 0x100
  28. #define AX88179_EEPROM_MAGIC 0x17900b95
  29. #define AX_MCAST_FLTSIZE 8
  30. #define AX_MAX_MCAST 64
  31. #define AX_INT_PPLS_LINK ((u32)BIT(16))
  32. #define AX_RXHDR_L4_TYPE_MASK 0x1c
  33. #define AX_RXHDR_L4_TYPE_UDP 4
  34. #define AX_RXHDR_L4_TYPE_TCP 16
  35. #define AX_RXHDR_L3CSUM_ERR 2
  36. #define AX_RXHDR_L4CSUM_ERR 1
  37. #define AX_RXHDR_CRC_ERR ((u32)BIT(29))
  38. #define AX_RXHDR_DROP_ERR ((u32)BIT(31))
  39. #define AX_ACCESS_MAC 0x01
  40. #define AX_ACCESS_PHY 0x02
  41. #define AX_ACCESS_EEPROM 0x04
  42. #define AX_ACCESS_EFUS 0x05
  43. #define AX_PAUSE_WATERLVL_HIGH 0x54
  44. #define AX_PAUSE_WATERLVL_LOW 0x55
  45. #define PHYSICAL_LINK_STATUS 0x02
  46. #define AX_USB_SS 0x04
  47. #define AX_USB_HS 0x02
  48. #define GENERAL_STATUS 0x03
  49. /* Check AX88179 version. UA1:Bit2 = 0, UA2:Bit2 = 1 */
  50. #define AX_SECLD 0x04
  51. #define AX_SROM_ADDR 0x07
  52. #define AX_SROM_CMD 0x0a
  53. #define EEP_RD 0x04
  54. #define EEP_BUSY 0x10
  55. #define AX_SROM_DATA_LOW 0x08
  56. #define AX_SROM_DATA_HIGH 0x09
  57. #define AX_RX_CTL 0x0b
  58. #define AX_RX_CTL_DROPCRCERR 0x0100
  59. #define AX_RX_CTL_IPE 0x0200
  60. #define AX_RX_CTL_START 0x0080
  61. #define AX_RX_CTL_AP 0x0020
  62. #define AX_RX_CTL_AM 0x0010
  63. #define AX_RX_CTL_AB 0x0008
  64. #define AX_RX_CTL_AMALL 0x0002
  65. #define AX_RX_CTL_PRO 0x0001
  66. #define AX_RX_CTL_STOP 0x0000
  67. #define AX_NODE_ID 0x10
  68. #define AX_MULFLTARY 0x16
  69. #define AX_MEDIUM_STATUS_MODE 0x22
  70. #define AX_MEDIUM_GIGAMODE 0x01
  71. #define AX_MEDIUM_FULL_DUPLEX 0x02
  72. #define AX_MEDIUM_EN_125MHZ 0x08
  73. #define AX_MEDIUM_RXFLOW_CTRLEN 0x10
  74. #define AX_MEDIUM_TXFLOW_CTRLEN 0x20
  75. #define AX_MEDIUM_RECEIVE_EN 0x100
  76. #define AX_MEDIUM_PS 0x200
  77. #define AX_MEDIUM_JUMBO_EN 0x8040
  78. #define AX_MONITOR_MOD 0x24
  79. #define AX_MONITOR_MODE_RWLC 0x02
  80. #define AX_MONITOR_MODE_RWMP 0x04
  81. #define AX_MONITOR_MODE_PMEPOL 0x20
  82. #define AX_MONITOR_MODE_PMETYPE 0x40
  83. #define AX_GPIO_CTRL 0x25
  84. #define AX_GPIO_CTRL_GPIO3EN 0x80
  85. #define AX_GPIO_CTRL_GPIO2EN 0x40
  86. #define AX_GPIO_CTRL_GPIO1EN 0x20
  87. #define AX_PHYPWR_RSTCTL 0x26
  88. #define AX_PHYPWR_RSTCTL_BZ 0x0010
  89. #define AX_PHYPWR_RSTCTL_IPRL 0x0020
  90. #define AX_PHYPWR_RSTCTL_AT 0x1000
  91. #define AX_RX_BULKIN_QCTRL 0x2e
  92. #define AX_CLK_SELECT 0x33
  93. #define AX_CLK_SELECT_BCS 0x01
  94. #define AX_CLK_SELECT_ACS 0x02
  95. #define AX_CLK_SELECT_ULR 0x08
  96. #define AX_RXCOE_CTL 0x34
  97. #define AX_RXCOE_IP 0x01
  98. #define AX_RXCOE_TCP 0x02
  99. #define AX_RXCOE_UDP 0x04
  100. #define AX_RXCOE_TCPV6 0x20
  101. #define AX_RXCOE_UDPV6 0x40
  102. #define AX_TXCOE_CTL 0x35
  103. #define AX_TXCOE_IP 0x01
  104. #define AX_TXCOE_TCP 0x02
  105. #define AX_TXCOE_UDP 0x04
  106. #define AX_TXCOE_TCPV6 0x20
  107. #define AX_TXCOE_UDPV6 0x40
  108. #define AX_LEDCTRL 0x73
  109. #define GMII_PHY_PHYSR 0x11
  110. #define GMII_PHY_PHYSR_SMASK 0xc000
  111. #define GMII_PHY_PHYSR_GIGA 0x8000
  112. #define GMII_PHY_PHYSR_100 0x4000
  113. #define GMII_PHY_PHYSR_FULL 0x2000
  114. #define GMII_PHY_PHYSR_LINK 0x400
  115. #define GMII_LED_ACT 0x1a
  116. #define GMII_LED_ACTIVE_MASK 0xff8f
  117. #define GMII_LED0_ACTIVE BIT(4)
  118. #define GMII_LED1_ACTIVE BIT(5)
  119. #define GMII_LED2_ACTIVE BIT(6)
  120. #define GMII_LED_LINK 0x1c
  121. #define GMII_LED_LINK_MASK 0xf888
  122. #define GMII_LED0_LINK_10 BIT(0)
  123. #define GMII_LED0_LINK_100 BIT(1)
  124. #define GMII_LED0_LINK_1000 BIT(2)
  125. #define GMII_LED1_LINK_10 BIT(4)
  126. #define GMII_LED1_LINK_100 BIT(5)
  127. #define GMII_LED1_LINK_1000 BIT(6)
  128. #define GMII_LED2_LINK_10 BIT(8)
  129. #define GMII_LED2_LINK_100 BIT(9)
  130. #define GMII_LED2_LINK_1000 BIT(10)
  131. #define LED0_ACTIVE BIT(0)
  132. #define LED0_LINK_10 BIT(1)
  133. #define LED0_LINK_100 BIT(2)
  134. #define LED0_LINK_1000 BIT(3)
  135. #define LED0_FD BIT(4)
  136. #define LED0_USB3_MASK 0x001f
  137. #define LED1_ACTIVE BIT(5)
  138. #define LED1_LINK_10 BIT(6)
  139. #define LED1_LINK_100 BIT(7)
  140. #define LED1_LINK_1000 BIT(8)
  141. #define LED1_FD BIT(9)
  142. #define LED1_USB3_MASK 0x03e0
  143. #define LED2_ACTIVE BIT(10)
  144. #define LED2_LINK_1000 BIT(13)
  145. #define LED2_LINK_100 BIT(12)
  146. #define LED2_LINK_10 BIT(11)
  147. #define LED2_FD BIT(14)
  148. #define LED_VALID BIT(15)
  149. #define LED2_USB3_MASK 0x7c00
  150. #define GMII_PHYPAGE 0x1e
  151. #define GMII_PHY_PAGE_SELECT 0x1f
  152. #define GMII_PHY_PGSEL_EXT 0x0007
  153. #define GMII_PHY_PGSEL_PAGE0 0x0000
  154. struct ax88179_data {
  155. u16 rxctl;
  156. u16 reserved;
  157. };
  158. struct ax88179_int_data {
  159. __le32 intdata1;
  160. __le32 intdata2;
  161. };
  162. static const struct {
  163. unsigned char ctrl, timer_l, timer_h, size, ifg;
  164. } AX88179_BULKIN_SIZE[] = {
  165. {7, 0x4f, 0, 0x12, 0xff},
  166. {7, 0x20, 3, 0x16, 0xff},
  167. {7, 0xae, 7, 0x18, 0xff},
  168. {7, 0xcc, 0x4c, 0x18, 8},
  169. };
  170. static int __ax88179_read_cmd(struct usbnet *dev, u8 cmd, u16 value, u16 index,
  171. u16 size, void *data, int in_pm)
  172. {
  173. int ret;
  174. int (*fn)(struct usbnet *, u8, u8, u16, u16, void *, u16);
  175. BUG_ON(!dev);
  176. if (!in_pm)
  177. fn = usbnet_read_cmd;
  178. else
  179. fn = usbnet_read_cmd_nopm;
  180. ret = fn(dev, cmd, USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  181. value, index, data, size);
  182. if (unlikely(ret < 0))
  183. netdev_warn(dev->net, "Failed to read reg index 0x%04x: %d\n",
  184. index, ret);
  185. return ret;
  186. }
  187. static int __ax88179_write_cmd(struct usbnet *dev, u8 cmd, u16 value, u16 index,
  188. u16 size, void *data, int in_pm)
  189. {
  190. int ret;
  191. int (*fn)(struct usbnet *, u8, u8, u16, u16, const void *, u16);
  192. BUG_ON(!dev);
  193. if (!in_pm)
  194. fn = usbnet_write_cmd;
  195. else
  196. fn = usbnet_write_cmd_nopm;
  197. ret = fn(dev, cmd, USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  198. value, index, data, size);
  199. if (unlikely(ret < 0))
  200. netdev_warn(dev->net, "Failed to write reg index 0x%04x: %d\n",
  201. index, ret);
  202. return ret;
  203. }
  204. static void ax88179_write_cmd_async(struct usbnet *dev, u8 cmd, u16 value,
  205. u16 index, u16 size, void *data)
  206. {
  207. u16 buf;
  208. if (2 == size) {
  209. buf = *((u16 *)data);
  210. cpu_to_le16s(&buf);
  211. usbnet_write_cmd_async(dev, cmd, USB_DIR_OUT | USB_TYPE_VENDOR |
  212. USB_RECIP_DEVICE, value, index, &buf,
  213. size);
  214. } else {
  215. usbnet_write_cmd_async(dev, cmd, USB_DIR_OUT | USB_TYPE_VENDOR |
  216. USB_RECIP_DEVICE, value, index, data,
  217. size);
  218. }
  219. }
  220. static int ax88179_read_cmd_nopm(struct usbnet *dev, u8 cmd, u16 value,
  221. u16 index, u16 size, void *data)
  222. {
  223. int ret;
  224. if (2 == size) {
  225. u16 buf;
  226. ret = __ax88179_read_cmd(dev, cmd, value, index, size, &buf, 1);
  227. le16_to_cpus(&buf);
  228. *((u16 *)data) = buf;
  229. } else if (4 == size) {
  230. u32 buf;
  231. ret = __ax88179_read_cmd(dev, cmd, value, index, size, &buf, 1);
  232. le32_to_cpus(&buf);
  233. *((u32 *)data) = buf;
  234. } else {
  235. ret = __ax88179_read_cmd(dev, cmd, value, index, size, data, 1);
  236. }
  237. return ret;
  238. }
  239. static int ax88179_write_cmd_nopm(struct usbnet *dev, u8 cmd, u16 value,
  240. u16 index, u16 size, void *data)
  241. {
  242. int ret;
  243. if (2 == size) {
  244. u16 buf;
  245. buf = *((u16 *)data);
  246. cpu_to_le16s(&buf);
  247. ret = __ax88179_write_cmd(dev, cmd, value, index,
  248. size, &buf, 1);
  249. } else {
  250. ret = __ax88179_write_cmd(dev, cmd, value, index,
  251. size, data, 1);
  252. }
  253. return ret;
  254. }
  255. static int ax88179_read_cmd(struct usbnet *dev, u8 cmd, u16 value, u16 index,
  256. u16 size, void *data)
  257. {
  258. int ret;
  259. if (2 == size) {
  260. u16 buf;
  261. ret = __ax88179_read_cmd(dev, cmd, value, index, size, &buf, 0);
  262. le16_to_cpus(&buf);
  263. *((u16 *)data) = buf;
  264. } else if (4 == size) {
  265. u32 buf;
  266. ret = __ax88179_read_cmd(dev, cmd, value, index, size, &buf, 0);
  267. le32_to_cpus(&buf);
  268. *((u32 *)data) = buf;
  269. } else {
  270. ret = __ax88179_read_cmd(dev, cmd, value, index, size, data, 0);
  271. }
  272. return ret;
  273. }
  274. static int ax88179_write_cmd(struct usbnet *dev, u8 cmd, u16 value, u16 index,
  275. u16 size, void *data)
  276. {
  277. int ret;
  278. if (2 == size) {
  279. u16 buf;
  280. buf = *((u16 *)data);
  281. cpu_to_le16s(&buf);
  282. ret = __ax88179_write_cmd(dev, cmd, value, index,
  283. size, &buf, 0);
  284. } else {
  285. ret = __ax88179_write_cmd(dev, cmd, value, index,
  286. size, data, 0);
  287. }
  288. return ret;
  289. }
  290. static void ax88179_status(struct usbnet *dev, struct urb *urb)
  291. {
  292. struct ax88179_int_data *event;
  293. u32 link;
  294. if (urb->actual_length < 8)
  295. return;
  296. event = urb->transfer_buffer;
  297. le32_to_cpus((void *)&event->intdata1);
  298. link = (((__force u32)event->intdata1) & AX_INT_PPLS_LINK) >> 16;
  299. if (netif_carrier_ok(dev->net) != link) {
  300. usbnet_link_change(dev, link, 1);
  301. netdev_info(dev->net, "ax88179 - Link status is: %d\n", link);
  302. }
  303. }
  304. static int ax88179_mdio_read(struct net_device *netdev, int phy_id, int loc)
  305. {
  306. struct usbnet *dev = netdev_priv(netdev);
  307. u16 res;
  308. ax88179_read_cmd(dev, AX_ACCESS_PHY, phy_id, (__u16)loc, 2, &res);
  309. return res;
  310. }
  311. static void ax88179_mdio_write(struct net_device *netdev, int phy_id, int loc,
  312. int val)
  313. {
  314. struct usbnet *dev = netdev_priv(netdev);
  315. u16 res = (u16) val;
  316. ax88179_write_cmd(dev, AX_ACCESS_PHY, phy_id, (__u16)loc, 2, &res);
  317. }
  318. static int ax88179_suspend(struct usb_interface *intf, pm_message_t message)
  319. {
  320. struct usbnet *dev = usb_get_intfdata(intf);
  321. u16 tmp16;
  322. u8 tmp8;
  323. usbnet_suspend(intf, message);
  324. /* Disable RX path */
  325. ax88179_read_cmd_nopm(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE,
  326. 2, 2, &tmp16);
  327. tmp16 &= ~AX_MEDIUM_RECEIVE_EN;
  328. ax88179_write_cmd_nopm(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE,
  329. 2, 2, &tmp16);
  330. /* Force bulk-in zero length */
  331. ax88179_read_cmd_nopm(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL,
  332. 2, 2, &tmp16);
  333. tmp16 |= AX_PHYPWR_RSTCTL_BZ | AX_PHYPWR_RSTCTL_IPRL;
  334. ax88179_write_cmd_nopm(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL,
  335. 2, 2, &tmp16);
  336. /* change clock */
  337. tmp8 = 0;
  338. ax88179_write_cmd_nopm(dev, AX_ACCESS_MAC, AX_CLK_SELECT, 1, 1, &tmp8);
  339. /* Configure RX control register => stop operation */
  340. tmp16 = AX_RX_CTL_STOP;
  341. ax88179_write_cmd_nopm(dev, AX_ACCESS_MAC, AX_RX_CTL, 2, 2, &tmp16);
  342. return 0;
  343. }
  344. /* This function is used to enable the autodetach function. */
  345. /* This function is determined by offset 0x43 of EEPROM */
  346. static int ax88179_auto_detach(struct usbnet *dev, int in_pm)
  347. {
  348. u16 tmp16;
  349. u8 tmp8;
  350. int (*fnr)(struct usbnet *, u8, u16, u16, u16, void *);
  351. int (*fnw)(struct usbnet *, u8, u16, u16, u16, void *);
  352. if (!in_pm) {
  353. fnr = ax88179_read_cmd;
  354. fnw = ax88179_write_cmd;
  355. } else {
  356. fnr = ax88179_read_cmd_nopm;
  357. fnw = ax88179_write_cmd_nopm;
  358. }
  359. if (fnr(dev, AX_ACCESS_EEPROM, 0x43, 1, 2, &tmp16) < 0)
  360. return 0;
  361. if ((tmp16 == 0xFFFF) || (!(tmp16 & 0x0100)))
  362. return 0;
  363. /* Enable Auto Detach bit */
  364. tmp8 = 0;
  365. fnr(dev, AX_ACCESS_MAC, AX_CLK_SELECT, 1, 1, &tmp8);
  366. tmp8 |= AX_CLK_SELECT_ULR;
  367. fnw(dev, AX_ACCESS_MAC, AX_CLK_SELECT, 1, 1, &tmp8);
  368. fnr(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 2, 2, &tmp16);
  369. tmp16 |= AX_PHYPWR_RSTCTL_AT;
  370. fnw(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 2, 2, &tmp16);
  371. return 0;
  372. }
  373. static int ax88179_resume(struct usb_interface *intf)
  374. {
  375. struct usbnet *dev = usb_get_intfdata(intf);
  376. u16 tmp16;
  377. u8 tmp8;
  378. usbnet_link_change(dev, 0, 0);
  379. /* Power up ethernet PHY */
  380. tmp16 = 0;
  381. ax88179_write_cmd_nopm(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL,
  382. 2, 2, &tmp16);
  383. udelay(1000);
  384. tmp16 = AX_PHYPWR_RSTCTL_IPRL;
  385. ax88179_write_cmd_nopm(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL,
  386. 2, 2, &tmp16);
  387. msleep(200);
  388. /* Ethernet PHY Auto Detach*/
  389. ax88179_auto_detach(dev, 1);
  390. /* Enable clock */
  391. ax88179_read_cmd_nopm(dev, AX_ACCESS_MAC, AX_CLK_SELECT, 1, 1, &tmp8);
  392. tmp8 |= AX_CLK_SELECT_ACS | AX_CLK_SELECT_BCS;
  393. ax88179_write_cmd_nopm(dev, AX_ACCESS_MAC, AX_CLK_SELECT, 1, 1, &tmp8);
  394. msleep(100);
  395. /* Configure RX control register => start operation */
  396. tmp16 = AX_RX_CTL_DROPCRCERR | AX_RX_CTL_IPE | AX_RX_CTL_START |
  397. AX_RX_CTL_AP | AX_RX_CTL_AMALL | AX_RX_CTL_AB;
  398. ax88179_write_cmd_nopm(dev, AX_ACCESS_MAC, AX_RX_CTL, 2, 2, &tmp16);
  399. return usbnet_resume(intf);
  400. }
  401. static void
  402. ax88179_get_wol(struct net_device *net, struct ethtool_wolinfo *wolinfo)
  403. {
  404. struct usbnet *dev = netdev_priv(net);
  405. u8 opt;
  406. if (ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_MONITOR_MOD,
  407. 1, 1, &opt) < 0) {
  408. wolinfo->supported = 0;
  409. wolinfo->wolopts = 0;
  410. return;
  411. }
  412. wolinfo->supported = WAKE_PHY | WAKE_MAGIC;
  413. wolinfo->wolopts = 0;
  414. if (opt & AX_MONITOR_MODE_RWLC)
  415. wolinfo->wolopts |= WAKE_PHY;
  416. if (opt & AX_MONITOR_MODE_RWMP)
  417. wolinfo->wolopts |= WAKE_MAGIC;
  418. }
  419. static int
  420. ax88179_set_wol(struct net_device *net, struct ethtool_wolinfo *wolinfo)
  421. {
  422. struct usbnet *dev = netdev_priv(net);
  423. u8 opt = 0;
  424. if (wolinfo->wolopts & WAKE_PHY)
  425. opt |= AX_MONITOR_MODE_RWLC;
  426. if (wolinfo->wolopts & WAKE_MAGIC)
  427. opt |= AX_MONITOR_MODE_RWMP;
  428. if (ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_MONITOR_MOD,
  429. 1, 1, &opt) < 0)
  430. return -EINVAL;
  431. return 0;
  432. }
  433. static int ax88179_get_eeprom_len(struct net_device *net)
  434. {
  435. return AX_EEPROM_LEN;
  436. }
  437. static int
  438. ax88179_get_eeprom(struct net_device *net, struct ethtool_eeprom *eeprom,
  439. u8 *data)
  440. {
  441. struct usbnet *dev = netdev_priv(net);
  442. u16 *eeprom_buff;
  443. int first_word, last_word;
  444. int i, ret;
  445. if (eeprom->len == 0)
  446. return -EINVAL;
  447. eeprom->magic = AX88179_EEPROM_MAGIC;
  448. first_word = eeprom->offset >> 1;
  449. last_word = (eeprom->offset + eeprom->len - 1) >> 1;
  450. eeprom_buff = kmalloc(sizeof(u16) * (last_word - first_word + 1),
  451. GFP_KERNEL);
  452. if (!eeprom_buff)
  453. return -ENOMEM;
  454. /* ax88179/178A returns 2 bytes from eeprom on read */
  455. for (i = first_word; i <= last_word; i++) {
  456. ret = __ax88179_read_cmd(dev, AX_ACCESS_EEPROM, i, 1, 2,
  457. &eeprom_buff[i - first_word],
  458. 0);
  459. if (ret < 0) {
  460. kfree(eeprom_buff);
  461. return -EIO;
  462. }
  463. }
  464. memcpy(data, (u8 *)eeprom_buff + (eeprom->offset & 1), eeprom->len);
  465. kfree(eeprom_buff);
  466. return 0;
  467. }
  468. static int ax88179_get_settings(struct net_device *net, struct ethtool_cmd *cmd)
  469. {
  470. struct usbnet *dev = netdev_priv(net);
  471. return mii_ethtool_gset(&dev->mii, cmd);
  472. }
  473. static int ax88179_set_settings(struct net_device *net, struct ethtool_cmd *cmd)
  474. {
  475. struct usbnet *dev = netdev_priv(net);
  476. return mii_ethtool_sset(&dev->mii, cmd);
  477. }
  478. static int ax88179_ioctl(struct net_device *net, struct ifreq *rq, int cmd)
  479. {
  480. struct usbnet *dev = netdev_priv(net);
  481. return generic_mii_ioctl(&dev->mii, if_mii(rq), cmd, NULL);
  482. }
  483. static const struct ethtool_ops ax88179_ethtool_ops = {
  484. .get_link = ethtool_op_get_link,
  485. .get_msglevel = usbnet_get_msglevel,
  486. .set_msglevel = usbnet_set_msglevel,
  487. .get_wol = ax88179_get_wol,
  488. .set_wol = ax88179_set_wol,
  489. .get_eeprom_len = ax88179_get_eeprom_len,
  490. .get_eeprom = ax88179_get_eeprom,
  491. .get_settings = ax88179_get_settings,
  492. .set_settings = ax88179_set_settings,
  493. .nway_reset = usbnet_nway_reset,
  494. };
  495. static void ax88179_set_multicast(struct net_device *net)
  496. {
  497. struct usbnet *dev = netdev_priv(net);
  498. struct ax88179_data *data = (struct ax88179_data *)dev->data;
  499. u8 *m_filter = ((u8 *)dev->data) + 12;
  500. data->rxctl = (AX_RX_CTL_START | AX_RX_CTL_AB | AX_RX_CTL_IPE);
  501. if (net->flags & IFF_PROMISC) {
  502. data->rxctl |= AX_RX_CTL_PRO;
  503. } else if (net->flags & IFF_ALLMULTI ||
  504. netdev_mc_count(net) > AX_MAX_MCAST) {
  505. data->rxctl |= AX_RX_CTL_AMALL;
  506. } else if (netdev_mc_empty(net)) {
  507. /* just broadcast and directed */
  508. } else {
  509. /* We use the 20 byte dev->data for our 8 byte filter buffer
  510. * to avoid allocating memory that is tricky to free later
  511. */
  512. u32 crc_bits;
  513. struct netdev_hw_addr *ha;
  514. memset(m_filter, 0, AX_MCAST_FLTSIZE);
  515. netdev_for_each_mc_addr(ha, net) {
  516. crc_bits = ether_crc(ETH_ALEN, ha->addr) >> 26;
  517. *(m_filter + (crc_bits >> 3)) |= (1 << (crc_bits & 7));
  518. }
  519. ax88179_write_cmd_async(dev, AX_ACCESS_MAC, AX_MULFLTARY,
  520. AX_MCAST_FLTSIZE, AX_MCAST_FLTSIZE,
  521. m_filter);
  522. data->rxctl |= AX_RX_CTL_AM;
  523. }
  524. ax88179_write_cmd_async(dev, AX_ACCESS_MAC, AX_RX_CTL,
  525. 2, 2, &data->rxctl);
  526. }
  527. static int
  528. ax88179_set_features(struct net_device *net, netdev_features_t features)
  529. {
  530. u8 tmp;
  531. struct usbnet *dev = netdev_priv(net);
  532. netdev_features_t changed = net->features ^ features;
  533. if (changed & NETIF_F_IP_CSUM) {
  534. ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_TXCOE_CTL, 1, 1, &tmp);
  535. tmp ^= AX_TXCOE_TCP | AX_TXCOE_UDP;
  536. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_TXCOE_CTL, 1, 1, &tmp);
  537. }
  538. if (changed & NETIF_F_IPV6_CSUM) {
  539. ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_TXCOE_CTL, 1, 1, &tmp);
  540. tmp ^= AX_TXCOE_TCPV6 | AX_TXCOE_UDPV6;
  541. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_TXCOE_CTL, 1, 1, &tmp);
  542. }
  543. if (changed & NETIF_F_RXCSUM) {
  544. ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_RXCOE_CTL, 1, 1, &tmp);
  545. tmp ^= AX_RXCOE_IP | AX_RXCOE_TCP | AX_RXCOE_UDP |
  546. AX_RXCOE_TCPV6 | AX_RXCOE_UDPV6;
  547. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_RXCOE_CTL, 1, 1, &tmp);
  548. }
  549. return 0;
  550. }
  551. static int ax88179_change_mtu(struct net_device *net, int new_mtu)
  552. {
  553. struct usbnet *dev = netdev_priv(net);
  554. u16 tmp16;
  555. if (new_mtu <= 0 || new_mtu > 4088)
  556. return -EINVAL;
  557. net->mtu = new_mtu;
  558. dev->hard_mtu = net->mtu + net->hard_header_len;
  559. if (net->mtu > 1500) {
  560. ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE,
  561. 2, 2, &tmp16);
  562. tmp16 |= AX_MEDIUM_JUMBO_EN;
  563. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE,
  564. 2, 2, &tmp16);
  565. } else {
  566. ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE,
  567. 2, 2, &tmp16);
  568. tmp16 &= ~AX_MEDIUM_JUMBO_EN;
  569. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE,
  570. 2, 2, &tmp16);
  571. }
  572. /* max qlen depend on hard_mtu and rx_urb_size */
  573. usbnet_update_max_qlen(dev);
  574. return 0;
  575. }
  576. static int ax88179_set_mac_addr(struct net_device *net, void *p)
  577. {
  578. struct usbnet *dev = netdev_priv(net);
  579. struct sockaddr *addr = p;
  580. if (netif_running(net))
  581. return -EBUSY;
  582. if (!is_valid_ether_addr(addr->sa_data))
  583. return -EADDRNOTAVAIL;
  584. memcpy(net->dev_addr, addr->sa_data, ETH_ALEN);
  585. /* Set the MAC address */
  586. return ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_NODE_ID, ETH_ALEN,
  587. ETH_ALEN, net->dev_addr);
  588. }
  589. static const struct net_device_ops ax88179_netdev_ops = {
  590. .ndo_open = usbnet_open,
  591. .ndo_stop = usbnet_stop,
  592. .ndo_start_xmit = usbnet_start_xmit,
  593. .ndo_tx_timeout = usbnet_tx_timeout,
  594. .ndo_change_mtu = ax88179_change_mtu,
  595. .ndo_set_mac_address = ax88179_set_mac_addr,
  596. .ndo_validate_addr = eth_validate_addr,
  597. .ndo_do_ioctl = ax88179_ioctl,
  598. .ndo_set_rx_mode = ax88179_set_multicast,
  599. .ndo_set_features = ax88179_set_features,
  600. };
  601. static int ax88179_check_eeprom(struct usbnet *dev)
  602. {
  603. u8 i, buf, eeprom[20];
  604. u16 csum, delay = HZ / 10;
  605. unsigned long jtimeout;
  606. /* Read EEPROM content */
  607. for (i = 0; i < 6; i++) {
  608. buf = i;
  609. if (ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_SROM_ADDR,
  610. 1, 1, &buf) < 0)
  611. return -EINVAL;
  612. buf = EEP_RD;
  613. if (ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_SROM_CMD,
  614. 1, 1, &buf) < 0)
  615. return -EINVAL;
  616. jtimeout = jiffies + delay;
  617. do {
  618. ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_SROM_CMD,
  619. 1, 1, &buf);
  620. if (time_after(jiffies, jtimeout))
  621. return -EINVAL;
  622. } while (buf & EEP_BUSY);
  623. __ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_SROM_DATA_LOW,
  624. 2, 2, &eeprom[i * 2], 0);
  625. if ((i == 0) && (eeprom[0] == 0xFF))
  626. return -EINVAL;
  627. }
  628. csum = eeprom[6] + eeprom[7] + eeprom[8] + eeprom[9];
  629. csum = (csum >> 8) + (csum & 0xff);
  630. if ((csum + eeprom[10]) != 0xff)
  631. return -EINVAL;
  632. return 0;
  633. }
  634. static int ax88179_check_efuse(struct usbnet *dev, u16 *ledmode)
  635. {
  636. u8 i;
  637. u8 efuse[64];
  638. u16 csum = 0;
  639. if (ax88179_read_cmd(dev, AX_ACCESS_EFUS, 0, 64, 64, efuse) < 0)
  640. return -EINVAL;
  641. if (*efuse == 0xFF)
  642. return -EINVAL;
  643. for (i = 0; i < 64; i++)
  644. csum = csum + efuse[i];
  645. while (csum > 255)
  646. csum = (csum & 0x00FF) + ((csum >> 8) & 0x00FF);
  647. if (csum != 0xFF)
  648. return -EINVAL;
  649. *ledmode = (efuse[51] << 8) | efuse[52];
  650. return 0;
  651. }
  652. static int ax88179_convert_old_led(struct usbnet *dev, u16 *ledvalue)
  653. {
  654. u16 led;
  655. /* Loaded the old eFuse LED Mode */
  656. if (ax88179_read_cmd(dev, AX_ACCESS_EEPROM, 0x3C, 1, 2, &led) < 0)
  657. return -EINVAL;
  658. led >>= 8;
  659. switch (led) {
  660. case 0xFF:
  661. led = LED0_ACTIVE | LED1_LINK_10 | LED1_LINK_100 |
  662. LED1_LINK_1000 | LED2_ACTIVE | LED2_LINK_10 |
  663. LED2_LINK_100 | LED2_LINK_1000 | LED_VALID;
  664. break;
  665. case 0xFE:
  666. led = LED0_ACTIVE | LED1_LINK_1000 | LED2_LINK_100 | LED_VALID;
  667. break;
  668. case 0xFD:
  669. led = LED0_ACTIVE | LED1_LINK_1000 | LED2_LINK_100 |
  670. LED2_LINK_10 | LED_VALID;
  671. break;
  672. case 0xFC:
  673. led = LED0_ACTIVE | LED1_ACTIVE | LED1_LINK_1000 | LED2_ACTIVE |
  674. LED2_LINK_100 | LED2_LINK_10 | LED_VALID;
  675. break;
  676. default:
  677. led = LED0_ACTIVE | LED1_LINK_10 | LED1_LINK_100 |
  678. LED1_LINK_1000 | LED2_ACTIVE | LED2_LINK_10 |
  679. LED2_LINK_100 | LED2_LINK_1000 | LED_VALID;
  680. break;
  681. }
  682. *ledvalue = led;
  683. return 0;
  684. }
  685. static int ax88179_led_setting(struct usbnet *dev)
  686. {
  687. u8 ledfd, value = 0;
  688. u16 tmp, ledact, ledlink, ledvalue = 0, delay = HZ / 10;
  689. unsigned long jtimeout;
  690. /* Check AX88179 version. UA1 or UA2*/
  691. ax88179_read_cmd(dev, AX_ACCESS_MAC, GENERAL_STATUS, 1, 1, &value);
  692. if (!(value & AX_SECLD)) { /* UA1 */
  693. value = AX_GPIO_CTRL_GPIO3EN | AX_GPIO_CTRL_GPIO2EN |
  694. AX_GPIO_CTRL_GPIO1EN;
  695. if (ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_GPIO_CTRL,
  696. 1, 1, &value) < 0)
  697. return -EINVAL;
  698. }
  699. /* Check EEPROM */
  700. if (!ax88179_check_eeprom(dev)) {
  701. value = 0x42;
  702. if (ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_SROM_ADDR,
  703. 1, 1, &value) < 0)
  704. return -EINVAL;
  705. value = EEP_RD;
  706. if (ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_SROM_CMD,
  707. 1, 1, &value) < 0)
  708. return -EINVAL;
  709. jtimeout = jiffies + delay;
  710. do {
  711. ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_SROM_CMD,
  712. 1, 1, &value);
  713. if (time_after(jiffies, jtimeout))
  714. return -EINVAL;
  715. } while (value & EEP_BUSY);
  716. ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_SROM_DATA_HIGH,
  717. 1, 1, &value);
  718. ledvalue = (value << 8);
  719. ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_SROM_DATA_LOW,
  720. 1, 1, &value);
  721. ledvalue |= value;
  722. /* load internal ROM for defaule setting */
  723. if ((ledvalue == 0xFFFF) || ((ledvalue & LED_VALID) == 0))
  724. ax88179_convert_old_led(dev, &ledvalue);
  725. } else if (!ax88179_check_efuse(dev, &ledvalue)) {
  726. if ((ledvalue == 0xFFFF) || ((ledvalue & LED_VALID) == 0))
  727. ax88179_convert_old_led(dev, &ledvalue);
  728. } else {
  729. ax88179_convert_old_led(dev, &ledvalue);
  730. }
  731. tmp = GMII_PHY_PGSEL_EXT;
  732. ax88179_write_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID,
  733. GMII_PHY_PAGE_SELECT, 2, &tmp);
  734. tmp = 0x2c;
  735. ax88179_write_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID,
  736. GMII_PHYPAGE, 2, &tmp);
  737. ax88179_read_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID,
  738. GMII_LED_ACT, 2, &ledact);
  739. ax88179_read_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID,
  740. GMII_LED_LINK, 2, &ledlink);
  741. ledact &= GMII_LED_ACTIVE_MASK;
  742. ledlink &= GMII_LED_LINK_MASK;
  743. if (ledvalue & LED0_ACTIVE)
  744. ledact |= GMII_LED0_ACTIVE;
  745. if (ledvalue & LED1_ACTIVE)
  746. ledact |= GMII_LED1_ACTIVE;
  747. if (ledvalue & LED2_ACTIVE)
  748. ledact |= GMII_LED2_ACTIVE;
  749. if (ledvalue & LED0_LINK_10)
  750. ledlink |= GMII_LED0_LINK_10;
  751. if (ledvalue & LED1_LINK_10)
  752. ledlink |= GMII_LED1_LINK_10;
  753. if (ledvalue & LED2_LINK_10)
  754. ledlink |= GMII_LED2_LINK_10;
  755. if (ledvalue & LED0_LINK_100)
  756. ledlink |= GMII_LED0_LINK_100;
  757. if (ledvalue & LED1_LINK_100)
  758. ledlink |= GMII_LED1_LINK_100;
  759. if (ledvalue & LED2_LINK_100)
  760. ledlink |= GMII_LED2_LINK_100;
  761. if (ledvalue & LED0_LINK_1000)
  762. ledlink |= GMII_LED0_LINK_1000;
  763. if (ledvalue & LED1_LINK_1000)
  764. ledlink |= GMII_LED1_LINK_1000;
  765. if (ledvalue & LED2_LINK_1000)
  766. ledlink |= GMII_LED2_LINK_1000;
  767. tmp = ledact;
  768. ax88179_write_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID,
  769. GMII_LED_ACT, 2, &tmp);
  770. tmp = ledlink;
  771. ax88179_write_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID,
  772. GMII_LED_LINK, 2, &tmp);
  773. tmp = GMII_PHY_PGSEL_PAGE0;
  774. ax88179_write_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID,
  775. GMII_PHY_PAGE_SELECT, 2, &tmp);
  776. /* LED full duplex setting */
  777. ledfd = 0;
  778. if (ledvalue & LED0_FD)
  779. ledfd |= 0x01;
  780. else if ((ledvalue & LED0_USB3_MASK) == 0)
  781. ledfd |= 0x02;
  782. if (ledvalue & LED1_FD)
  783. ledfd |= 0x04;
  784. else if ((ledvalue & LED1_USB3_MASK) == 0)
  785. ledfd |= 0x08;
  786. if (ledvalue & LED2_FD)
  787. ledfd |= 0x10;
  788. else if ((ledvalue & LED2_USB3_MASK) == 0)
  789. ledfd |= 0x20;
  790. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_LEDCTRL, 1, 1, &ledfd);
  791. return 0;
  792. }
  793. static int ax88179_bind(struct usbnet *dev, struct usb_interface *intf)
  794. {
  795. u8 buf[5];
  796. u16 *tmp16;
  797. u8 *tmp;
  798. struct ax88179_data *ax179_data = (struct ax88179_data *)dev->data;
  799. usbnet_get_endpoints(dev, intf);
  800. tmp16 = (u16 *)buf;
  801. tmp = (u8 *)buf;
  802. memset(ax179_data, 0, sizeof(*ax179_data));
  803. /* Power up ethernet PHY */
  804. *tmp16 = 0;
  805. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 2, 2, tmp16);
  806. *tmp16 = AX_PHYPWR_RSTCTL_IPRL;
  807. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 2, 2, tmp16);
  808. msleep(200);
  809. *tmp = AX_CLK_SELECT_ACS | AX_CLK_SELECT_BCS;
  810. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_CLK_SELECT, 1, 1, tmp);
  811. msleep(100);
  812. ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_NODE_ID, ETH_ALEN,
  813. ETH_ALEN, dev->net->dev_addr);
  814. memcpy(dev->net->perm_addr, dev->net->dev_addr, ETH_ALEN);
  815. /* RX bulk configuration */
  816. memcpy(tmp, &AX88179_BULKIN_SIZE[0], 5);
  817. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_RX_BULKIN_QCTRL, 5, 5, tmp);
  818. dev->rx_urb_size = 1024 * 20;
  819. *tmp = 0x34;
  820. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_PAUSE_WATERLVL_LOW, 1, 1, tmp);
  821. *tmp = 0x52;
  822. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_PAUSE_WATERLVL_HIGH,
  823. 1, 1, tmp);
  824. dev->net->netdev_ops = &ax88179_netdev_ops;
  825. dev->net->ethtool_ops = &ax88179_ethtool_ops;
  826. dev->net->needed_headroom = 8;
  827. /* Initialize MII structure */
  828. dev->mii.dev = dev->net;
  829. dev->mii.mdio_read = ax88179_mdio_read;
  830. dev->mii.mdio_write = ax88179_mdio_write;
  831. dev->mii.phy_id_mask = 0xff;
  832. dev->mii.reg_num_mask = 0xff;
  833. dev->mii.phy_id = 0x03;
  834. dev->mii.supports_gmii = 1;
  835. if (usb_device_no_sg_constraint(dev->udev))
  836. dev->can_dma_sg = 1;
  837. dev->net->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
  838. NETIF_F_RXCSUM;
  839. dev->net->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
  840. NETIF_F_RXCSUM;
  841. if (dev->can_dma_sg) {
  842. dev->net->features |= NETIF_F_SG | NETIF_F_TSO;
  843. dev->net->hw_features |= NETIF_F_SG | NETIF_F_TSO;
  844. }
  845. /* Enable checksum offload */
  846. *tmp = AX_RXCOE_IP | AX_RXCOE_TCP | AX_RXCOE_UDP |
  847. AX_RXCOE_TCPV6 | AX_RXCOE_UDPV6;
  848. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_RXCOE_CTL, 1, 1, tmp);
  849. *tmp = AX_TXCOE_IP | AX_TXCOE_TCP | AX_TXCOE_UDP |
  850. AX_TXCOE_TCPV6 | AX_TXCOE_UDPV6;
  851. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_TXCOE_CTL, 1, 1, tmp);
  852. /* Configure RX control register => start operation */
  853. *tmp16 = AX_RX_CTL_DROPCRCERR | AX_RX_CTL_IPE | AX_RX_CTL_START |
  854. AX_RX_CTL_AP | AX_RX_CTL_AMALL | AX_RX_CTL_AB;
  855. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_RX_CTL, 2, 2, tmp16);
  856. *tmp = AX_MONITOR_MODE_PMETYPE | AX_MONITOR_MODE_PMEPOL |
  857. AX_MONITOR_MODE_RWMP;
  858. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_MONITOR_MOD, 1, 1, tmp);
  859. /* Configure default medium type => giga */
  860. *tmp16 = AX_MEDIUM_RECEIVE_EN | AX_MEDIUM_TXFLOW_CTRLEN |
  861. AX_MEDIUM_RXFLOW_CTRLEN | AX_MEDIUM_FULL_DUPLEX |
  862. AX_MEDIUM_GIGAMODE;
  863. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE,
  864. 2, 2, tmp16);
  865. ax88179_led_setting(dev);
  866. /* Restart autoneg */
  867. mii_nway_restart(&dev->mii);
  868. usbnet_link_change(dev, 0, 0);
  869. return 0;
  870. }
  871. static void ax88179_unbind(struct usbnet *dev, struct usb_interface *intf)
  872. {
  873. u16 tmp16;
  874. /* Configure RX control register => stop operation */
  875. tmp16 = AX_RX_CTL_STOP;
  876. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_RX_CTL, 2, 2, &tmp16);
  877. tmp16 = 0;
  878. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_CLK_SELECT, 1, 1, &tmp16);
  879. /* Power down ethernet PHY */
  880. tmp16 = 0;
  881. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 2, 2, &tmp16);
  882. }
  883. static void
  884. ax88179_rx_checksum(struct sk_buff *skb, u32 *pkt_hdr)
  885. {
  886. skb->ip_summed = CHECKSUM_NONE;
  887. /* checksum error bit is set */
  888. if ((*pkt_hdr & AX_RXHDR_L3CSUM_ERR) ||
  889. (*pkt_hdr & AX_RXHDR_L4CSUM_ERR))
  890. return;
  891. /* It must be a TCP or UDP packet with a valid checksum */
  892. if (((*pkt_hdr & AX_RXHDR_L4_TYPE_MASK) == AX_RXHDR_L4_TYPE_TCP) ||
  893. ((*pkt_hdr & AX_RXHDR_L4_TYPE_MASK) == AX_RXHDR_L4_TYPE_UDP))
  894. skb->ip_summed = CHECKSUM_UNNECESSARY;
  895. }
  896. static int ax88179_rx_fixup(struct usbnet *dev, struct sk_buff *skb)
  897. {
  898. struct sk_buff *ax_skb;
  899. int pkt_cnt;
  900. u32 rx_hdr;
  901. u16 hdr_off;
  902. u32 *pkt_hdr;
  903. skb_trim(skb, skb->len - 4);
  904. memcpy(&rx_hdr, skb_tail_pointer(skb), 4);
  905. le32_to_cpus(&rx_hdr);
  906. pkt_cnt = (u16)rx_hdr;
  907. hdr_off = (u16)(rx_hdr >> 16);
  908. pkt_hdr = (u32 *)(skb->data + hdr_off);
  909. while (pkt_cnt--) {
  910. u16 pkt_len;
  911. le32_to_cpus(pkt_hdr);
  912. pkt_len = (*pkt_hdr >> 16) & 0x1fff;
  913. /* Check CRC or runt packet */
  914. if ((*pkt_hdr & AX_RXHDR_CRC_ERR) ||
  915. (*pkt_hdr & AX_RXHDR_DROP_ERR)) {
  916. skb_pull(skb, (pkt_len + 7) & 0xFFF8);
  917. pkt_hdr++;
  918. continue;
  919. }
  920. if (pkt_cnt == 0) {
  921. /* Skip IP alignment psudo header */
  922. skb_pull(skb, 2);
  923. skb->len = pkt_len;
  924. skb_set_tail_pointer(skb, pkt_len);
  925. skb->truesize = pkt_len + sizeof(struct sk_buff);
  926. ax88179_rx_checksum(skb, pkt_hdr);
  927. return 1;
  928. }
  929. ax_skb = skb_clone(skb, GFP_ATOMIC);
  930. if (ax_skb) {
  931. ax_skb->len = pkt_len;
  932. ax_skb->data = skb->data + 2;
  933. skb_set_tail_pointer(ax_skb, pkt_len);
  934. ax_skb->truesize = pkt_len + sizeof(struct sk_buff);
  935. ax88179_rx_checksum(ax_skb, pkt_hdr);
  936. usbnet_skb_return(dev, ax_skb);
  937. } else {
  938. return 0;
  939. }
  940. skb_pull(skb, (pkt_len + 7) & 0xFFF8);
  941. pkt_hdr++;
  942. }
  943. return 1;
  944. }
  945. static struct sk_buff *
  946. ax88179_tx_fixup(struct usbnet *dev, struct sk_buff *skb, gfp_t flags)
  947. {
  948. u32 tx_hdr1, tx_hdr2;
  949. int frame_size = dev->maxpacket;
  950. int mss = skb_shinfo(skb)->gso_size;
  951. int headroom;
  952. tx_hdr1 = skb->len;
  953. tx_hdr2 = mss;
  954. if (((skb->len + 8) % frame_size) == 0)
  955. tx_hdr2 |= 0x80008000; /* Enable padding */
  956. headroom = skb_headroom(skb) - 8;
  957. if ((skb_header_cloned(skb) || headroom < 0) &&
  958. pskb_expand_head(skb, headroom < 0 ? 8 : 0, 0, GFP_ATOMIC)) {
  959. dev_kfree_skb_any(skb);
  960. return NULL;
  961. }
  962. skb_push(skb, 4);
  963. cpu_to_le32s(&tx_hdr2);
  964. skb_copy_to_linear_data(skb, &tx_hdr2, 4);
  965. skb_push(skb, 4);
  966. cpu_to_le32s(&tx_hdr1);
  967. skb_copy_to_linear_data(skb, &tx_hdr1, 4);
  968. return skb;
  969. }
  970. static int ax88179_link_reset(struct usbnet *dev)
  971. {
  972. struct ax88179_data *ax179_data = (struct ax88179_data *)dev->data;
  973. u8 tmp[5], link_sts;
  974. u16 mode, tmp16, delay = HZ / 10;
  975. u32 tmp32 = 0x40000000;
  976. unsigned long jtimeout;
  977. jtimeout = jiffies + delay;
  978. while (tmp32 & 0x40000000) {
  979. mode = 0;
  980. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_RX_CTL, 2, 2, &mode);
  981. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_RX_CTL, 2, 2,
  982. &ax179_data->rxctl);
  983. /*link up, check the usb device control TX FIFO full or empty*/
  984. ax88179_read_cmd(dev, 0x81, 0x8c, 0, 4, &tmp32);
  985. if (time_after(jiffies, jtimeout))
  986. return 0;
  987. }
  988. mode = AX_MEDIUM_RECEIVE_EN | AX_MEDIUM_TXFLOW_CTRLEN |
  989. AX_MEDIUM_RXFLOW_CTRLEN;
  990. ax88179_read_cmd(dev, AX_ACCESS_MAC, PHYSICAL_LINK_STATUS,
  991. 1, 1, &link_sts);
  992. ax88179_read_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID,
  993. GMII_PHY_PHYSR, 2, &tmp16);
  994. if (!(tmp16 & GMII_PHY_PHYSR_LINK)) {
  995. return 0;
  996. } else if (GMII_PHY_PHYSR_GIGA == (tmp16 & GMII_PHY_PHYSR_SMASK)) {
  997. mode |= AX_MEDIUM_GIGAMODE | AX_MEDIUM_EN_125MHZ;
  998. if (dev->net->mtu > 1500)
  999. mode |= AX_MEDIUM_JUMBO_EN;
  1000. if (link_sts & AX_USB_SS)
  1001. memcpy(tmp, &AX88179_BULKIN_SIZE[0], 5);
  1002. else if (link_sts & AX_USB_HS)
  1003. memcpy(tmp, &AX88179_BULKIN_SIZE[1], 5);
  1004. else
  1005. memcpy(tmp, &AX88179_BULKIN_SIZE[3], 5);
  1006. } else if (GMII_PHY_PHYSR_100 == (tmp16 & GMII_PHY_PHYSR_SMASK)) {
  1007. mode |= AX_MEDIUM_PS;
  1008. if (link_sts & (AX_USB_SS | AX_USB_HS))
  1009. memcpy(tmp, &AX88179_BULKIN_SIZE[2], 5);
  1010. else
  1011. memcpy(tmp, &AX88179_BULKIN_SIZE[3], 5);
  1012. } else {
  1013. memcpy(tmp, &AX88179_BULKIN_SIZE[3], 5);
  1014. }
  1015. /* RX bulk configuration */
  1016. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_RX_BULKIN_QCTRL, 5, 5, tmp);
  1017. dev->rx_urb_size = (1024 * (tmp[3] + 2));
  1018. if (tmp16 & GMII_PHY_PHYSR_FULL)
  1019. mode |= AX_MEDIUM_FULL_DUPLEX;
  1020. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE,
  1021. 2, 2, &mode);
  1022. netif_carrier_on(dev->net);
  1023. return 0;
  1024. }
  1025. static int ax88179_reset(struct usbnet *dev)
  1026. {
  1027. u8 buf[5];
  1028. u16 *tmp16;
  1029. u8 *tmp;
  1030. tmp16 = (u16 *)buf;
  1031. tmp = (u8 *)buf;
  1032. /* Power up ethernet PHY */
  1033. *tmp16 = 0;
  1034. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 2, 2, tmp16);
  1035. *tmp16 = AX_PHYPWR_RSTCTL_IPRL;
  1036. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 2, 2, tmp16);
  1037. msleep(200);
  1038. *tmp = AX_CLK_SELECT_ACS | AX_CLK_SELECT_BCS;
  1039. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_CLK_SELECT, 1, 1, tmp);
  1040. msleep(100);
  1041. /* Ethernet PHY Auto Detach*/
  1042. ax88179_auto_detach(dev, 0);
  1043. ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_NODE_ID, ETH_ALEN, ETH_ALEN,
  1044. dev->net->dev_addr);
  1045. memcpy(dev->net->perm_addr, dev->net->dev_addr, ETH_ALEN);
  1046. /* RX bulk configuration */
  1047. memcpy(tmp, &AX88179_BULKIN_SIZE[0], 5);
  1048. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_RX_BULKIN_QCTRL, 5, 5, tmp);
  1049. dev->rx_urb_size = 1024 * 20;
  1050. *tmp = 0x34;
  1051. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_PAUSE_WATERLVL_LOW, 1, 1, tmp);
  1052. *tmp = 0x52;
  1053. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_PAUSE_WATERLVL_HIGH,
  1054. 1, 1, tmp);
  1055. dev->net->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
  1056. NETIF_F_RXCSUM;
  1057. dev->net->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
  1058. NETIF_F_RXCSUM;
  1059. /* Enable checksum offload */
  1060. *tmp = AX_RXCOE_IP | AX_RXCOE_TCP | AX_RXCOE_UDP |
  1061. AX_RXCOE_TCPV6 | AX_RXCOE_UDPV6;
  1062. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_RXCOE_CTL, 1, 1, tmp);
  1063. *tmp = AX_TXCOE_IP | AX_TXCOE_TCP | AX_TXCOE_UDP |
  1064. AX_TXCOE_TCPV6 | AX_TXCOE_UDPV6;
  1065. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_TXCOE_CTL, 1, 1, tmp);
  1066. /* Configure RX control register => start operation */
  1067. *tmp16 = AX_RX_CTL_DROPCRCERR | AX_RX_CTL_IPE | AX_RX_CTL_START |
  1068. AX_RX_CTL_AP | AX_RX_CTL_AMALL | AX_RX_CTL_AB;
  1069. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_RX_CTL, 2, 2, tmp16);
  1070. *tmp = AX_MONITOR_MODE_PMETYPE | AX_MONITOR_MODE_PMEPOL |
  1071. AX_MONITOR_MODE_RWMP;
  1072. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_MONITOR_MOD, 1, 1, tmp);
  1073. /* Configure default medium type => giga */
  1074. *tmp16 = AX_MEDIUM_RECEIVE_EN | AX_MEDIUM_TXFLOW_CTRLEN |
  1075. AX_MEDIUM_RXFLOW_CTRLEN | AX_MEDIUM_FULL_DUPLEX |
  1076. AX_MEDIUM_GIGAMODE;
  1077. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE,
  1078. 2, 2, tmp16);
  1079. ax88179_led_setting(dev);
  1080. /* Restart autoneg */
  1081. mii_nway_restart(&dev->mii);
  1082. usbnet_link_change(dev, 0, 0);
  1083. return 0;
  1084. }
  1085. static int ax88179_stop(struct usbnet *dev)
  1086. {
  1087. u16 tmp16;
  1088. ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE,
  1089. 2, 2, &tmp16);
  1090. tmp16 &= ~AX_MEDIUM_RECEIVE_EN;
  1091. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE,
  1092. 2, 2, &tmp16);
  1093. return 0;
  1094. }
  1095. static const struct driver_info ax88179_info = {
  1096. .description = "ASIX AX88179 USB 3.0 Gigabit Ethernet",
  1097. .bind = ax88179_bind,
  1098. .unbind = ax88179_unbind,
  1099. .status = ax88179_status,
  1100. .link_reset = ax88179_link_reset,
  1101. .reset = ax88179_reset,
  1102. .stop = ax88179_stop,
  1103. .flags = FLAG_ETHER | FLAG_FRAMING_AX,
  1104. .rx_fixup = ax88179_rx_fixup,
  1105. .tx_fixup = ax88179_tx_fixup,
  1106. };
  1107. static const struct driver_info ax88178a_info = {
  1108. .description = "ASIX AX88178A USB 2.0 Gigabit Ethernet",
  1109. .bind = ax88179_bind,
  1110. .unbind = ax88179_unbind,
  1111. .status = ax88179_status,
  1112. .link_reset = ax88179_link_reset,
  1113. .reset = ax88179_reset,
  1114. .stop = ax88179_stop,
  1115. .flags = FLAG_ETHER | FLAG_FRAMING_AX,
  1116. .rx_fixup = ax88179_rx_fixup,
  1117. .tx_fixup = ax88179_tx_fixup,
  1118. };
  1119. static const struct driver_info sitecom_info = {
  1120. .description = "Sitecom USB 3.0 to Gigabit Adapter",
  1121. .bind = ax88179_bind,
  1122. .unbind = ax88179_unbind,
  1123. .status = ax88179_status,
  1124. .link_reset = ax88179_link_reset,
  1125. .reset = ax88179_reset,
  1126. .stop = ax88179_stop,
  1127. .flags = FLAG_ETHER | FLAG_FRAMING_AX,
  1128. .rx_fixup = ax88179_rx_fixup,
  1129. .tx_fixup = ax88179_tx_fixup,
  1130. };
  1131. static const struct driver_info samsung_info = {
  1132. .description = "Samsung USB Ethernet Adapter",
  1133. .bind = ax88179_bind,
  1134. .unbind = ax88179_unbind,
  1135. .status = ax88179_status,
  1136. .link_reset = ax88179_link_reset,
  1137. .reset = ax88179_reset,
  1138. .stop = ax88179_stop,
  1139. .flags = FLAG_ETHER | FLAG_FRAMING_AX,
  1140. .rx_fixup = ax88179_rx_fixup,
  1141. .tx_fixup = ax88179_tx_fixup,
  1142. };
  1143. static const struct usb_device_id products[] = {
  1144. {
  1145. /* ASIX AX88179 10/100/1000 */
  1146. USB_DEVICE(0x0b95, 0x1790),
  1147. .driver_info = (unsigned long)&ax88179_info,
  1148. }, {
  1149. /* ASIX AX88178A 10/100/1000 */
  1150. USB_DEVICE(0x0b95, 0x178a),
  1151. .driver_info = (unsigned long)&ax88178a_info,
  1152. }, {
  1153. /* Sitecom USB 3.0 to Gigabit Adapter */
  1154. USB_DEVICE(0x0df6, 0x0072),
  1155. .driver_info = (unsigned long)&sitecom_info,
  1156. }, {
  1157. /* Samsung USB Ethernet Adapter */
  1158. USB_DEVICE(0x04e8, 0xa100),
  1159. .driver_info = (unsigned long)&samsung_info,
  1160. },
  1161. { },
  1162. };
  1163. MODULE_DEVICE_TABLE(usb, products);
  1164. static struct usb_driver ax88179_178a_driver = {
  1165. .name = "ax88179_178a",
  1166. .id_table = products,
  1167. .probe = usbnet_probe,
  1168. .suspend = ax88179_suspend,
  1169. .resume = ax88179_resume,
  1170. .reset_resume = ax88179_resume,
  1171. .disconnect = usbnet_disconnect,
  1172. .supports_autosuspend = 1,
  1173. .disable_hub_initiated_lpm = 1,
  1174. };
  1175. module_usb_driver(ax88179_178a_driver);
  1176. MODULE_DESCRIPTION("ASIX AX88179/178A based USB 3.0/2.0 Gigabit Ethernet Devices");
  1177. MODULE_LICENSE("GPL");