cpsw.c 63 KB

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  1. /*
  2. * Texas Instruments Ethernet Switch Driver
  3. *
  4. * Copyright (C) 2012 Texas Instruments
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License as
  8. * published by the Free Software Foundation version 2.
  9. *
  10. * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  11. * kind, whether express or implied; without even the implied warranty
  12. * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. */
  15. #include <linux/kernel.h>
  16. #include <linux/io.h>
  17. #include <linux/clk.h>
  18. #include <linux/timer.h>
  19. #include <linux/module.h>
  20. #include <linux/platform_device.h>
  21. #include <linux/irqreturn.h>
  22. #include <linux/interrupt.h>
  23. #include <linux/if_ether.h>
  24. #include <linux/etherdevice.h>
  25. #include <linux/netdevice.h>
  26. #include <linux/net_tstamp.h>
  27. #include <linux/phy.h>
  28. #include <linux/workqueue.h>
  29. #include <linux/delay.h>
  30. #include <linux/pm_runtime.h>
  31. #include <linux/of.h>
  32. #include <linux/of_net.h>
  33. #include <linux/of_device.h>
  34. #include <linux/if_vlan.h>
  35. #include <linux/pinctrl/consumer.h>
  36. #include "cpsw.h"
  37. #include "cpsw_ale.h"
  38. #include "cpts.h"
  39. #include "davinci_cpdma.h"
  40. #define CPSW_DEBUG (NETIF_MSG_HW | NETIF_MSG_WOL | \
  41. NETIF_MSG_DRV | NETIF_MSG_LINK | \
  42. NETIF_MSG_IFUP | NETIF_MSG_INTR | \
  43. NETIF_MSG_PROBE | NETIF_MSG_TIMER | \
  44. NETIF_MSG_IFDOWN | NETIF_MSG_RX_ERR | \
  45. NETIF_MSG_TX_ERR | NETIF_MSG_TX_DONE | \
  46. NETIF_MSG_PKTDATA | NETIF_MSG_TX_QUEUED | \
  47. NETIF_MSG_RX_STATUS)
  48. #define cpsw_info(priv, type, format, ...) \
  49. do { \
  50. if (netif_msg_##type(priv) && net_ratelimit()) \
  51. dev_info(priv->dev, format, ## __VA_ARGS__); \
  52. } while (0)
  53. #define cpsw_err(priv, type, format, ...) \
  54. do { \
  55. if (netif_msg_##type(priv) && net_ratelimit()) \
  56. dev_err(priv->dev, format, ## __VA_ARGS__); \
  57. } while (0)
  58. #define cpsw_dbg(priv, type, format, ...) \
  59. do { \
  60. if (netif_msg_##type(priv) && net_ratelimit()) \
  61. dev_dbg(priv->dev, format, ## __VA_ARGS__); \
  62. } while (0)
  63. #define cpsw_notice(priv, type, format, ...) \
  64. do { \
  65. if (netif_msg_##type(priv) && net_ratelimit()) \
  66. dev_notice(priv->dev, format, ## __VA_ARGS__); \
  67. } while (0)
  68. #define ALE_ALL_PORTS 0x7
  69. #define CPSW_MAJOR_VERSION(reg) (reg >> 8 & 0x7)
  70. #define CPSW_MINOR_VERSION(reg) (reg & 0xff)
  71. #define CPSW_RTL_VERSION(reg) ((reg >> 11) & 0x1f)
  72. #define CPSW_VERSION_1 0x19010a
  73. #define CPSW_VERSION_2 0x19010c
  74. #define CPSW_VERSION_3 0x19010f
  75. #define CPSW_VERSION_4 0x190112
  76. #define HOST_PORT_NUM 0
  77. #define SLIVER_SIZE 0x40
  78. #define CPSW1_HOST_PORT_OFFSET 0x028
  79. #define CPSW1_SLAVE_OFFSET 0x050
  80. #define CPSW1_SLAVE_SIZE 0x040
  81. #define CPSW1_CPDMA_OFFSET 0x100
  82. #define CPSW1_STATERAM_OFFSET 0x200
  83. #define CPSW1_HW_STATS 0x400
  84. #define CPSW1_CPTS_OFFSET 0x500
  85. #define CPSW1_ALE_OFFSET 0x600
  86. #define CPSW1_SLIVER_OFFSET 0x700
  87. #define CPSW2_HOST_PORT_OFFSET 0x108
  88. #define CPSW2_SLAVE_OFFSET 0x200
  89. #define CPSW2_SLAVE_SIZE 0x100
  90. #define CPSW2_CPDMA_OFFSET 0x800
  91. #define CPSW2_HW_STATS 0x900
  92. #define CPSW2_STATERAM_OFFSET 0xa00
  93. #define CPSW2_CPTS_OFFSET 0xc00
  94. #define CPSW2_ALE_OFFSET 0xd00
  95. #define CPSW2_SLIVER_OFFSET 0xd80
  96. #define CPSW2_BD_OFFSET 0x2000
  97. #define CPDMA_RXTHRESH 0x0c0
  98. #define CPDMA_RXFREE 0x0e0
  99. #define CPDMA_TXHDP 0x00
  100. #define CPDMA_RXHDP 0x20
  101. #define CPDMA_TXCP 0x40
  102. #define CPDMA_RXCP 0x60
  103. #define CPSW_POLL_WEIGHT 64
  104. #define CPSW_MIN_PACKET_SIZE 60
  105. #define CPSW_MAX_PACKET_SIZE (1500 + 14 + 4 + 4)
  106. #define RX_PRIORITY_MAPPING 0x76543210
  107. #define TX_PRIORITY_MAPPING 0x33221100
  108. #define CPDMA_TX_PRIORITY_MAP 0x76543210
  109. #define CPSW_VLAN_AWARE BIT(1)
  110. #define CPSW_ALE_VLAN_AWARE 1
  111. #define CPSW_FIFO_NORMAL_MODE (0 << 15)
  112. #define CPSW_FIFO_DUAL_MAC_MODE (1 << 15)
  113. #define CPSW_FIFO_RATE_LIMIT_MODE (2 << 15)
  114. #define CPSW_INTPACEEN (0x3f << 16)
  115. #define CPSW_INTPRESCALE_MASK (0x7FF << 0)
  116. #define CPSW_CMINTMAX_CNT 63
  117. #define CPSW_CMINTMIN_CNT 2
  118. #define CPSW_CMINTMAX_INTVL (1000 / CPSW_CMINTMIN_CNT)
  119. #define CPSW_CMINTMIN_INTVL ((1000 / CPSW_CMINTMAX_CNT) + 1)
  120. #define cpsw_enable_irq(priv) \
  121. do { \
  122. u32 i; \
  123. for (i = 0; i < priv->num_irqs; i++) \
  124. enable_irq(priv->irqs_table[i]); \
  125. } while (0);
  126. #define cpsw_disable_irq(priv) \
  127. do { \
  128. u32 i; \
  129. for (i = 0; i < priv->num_irqs; i++) \
  130. disable_irq_nosync(priv->irqs_table[i]); \
  131. } while (0);
  132. #define cpsw_slave_index(priv) \
  133. ((priv->data.dual_emac) ? priv->emac_port : \
  134. priv->data.active_slave)
  135. static int debug_level;
  136. module_param(debug_level, int, 0);
  137. MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)");
  138. static int ale_ageout = 10;
  139. module_param(ale_ageout, int, 0);
  140. MODULE_PARM_DESC(ale_ageout, "cpsw ale ageout interval (seconds)");
  141. static int rx_packet_max = CPSW_MAX_PACKET_SIZE;
  142. module_param(rx_packet_max, int, 0);
  143. MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)");
  144. struct cpsw_wr_regs {
  145. u32 id_ver;
  146. u32 soft_reset;
  147. u32 control;
  148. u32 int_control;
  149. u32 rx_thresh_en;
  150. u32 rx_en;
  151. u32 tx_en;
  152. u32 misc_en;
  153. u32 mem_allign1[8];
  154. u32 rx_thresh_stat;
  155. u32 rx_stat;
  156. u32 tx_stat;
  157. u32 misc_stat;
  158. u32 mem_allign2[8];
  159. u32 rx_imax;
  160. u32 tx_imax;
  161. };
  162. struct cpsw_ss_regs {
  163. u32 id_ver;
  164. u32 control;
  165. u32 soft_reset;
  166. u32 stat_port_en;
  167. u32 ptype;
  168. u32 soft_idle;
  169. u32 thru_rate;
  170. u32 gap_thresh;
  171. u32 tx_start_wds;
  172. u32 flow_control;
  173. u32 vlan_ltype;
  174. u32 ts_ltype;
  175. u32 dlr_ltype;
  176. };
  177. /* CPSW_PORT_V1 */
  178. #define CPSW1_MAX_BLKS 0x00 /* Maximum FIFO Blocks */
  179. #define CPSW1_BLK_CNT 0x04 /* FIFO Block Usage Count (Read Only) */
  180. #define CPSW1_TX_IN_CTL 0x08 /* Transmit FIFO Control */
  181. #define CPSW1_PORT_VLAN 0x0c /* VLAN Register */
  182. #define CPSW1_TX_PRI_MAP 0x10 /* Tx Header Priority to Switch Pri Mapping */
  183. #define CPSW1_TS_CTL 0x14 /* Time Sync Control */
  184. #define CPSW1_TS_SEQ_LTYPE 0x18 /* Time Sync Sequence ID Offset and Msg Type */
  185. #define CPSW1_TS_VLAN 0x1c /* Time Sync VLAN1 and VLAN2 */
  186. /* CPSW_PORT_V2 */
  187. #define CPSW2_CONTROL 0x00 /* Control Register */
  188. #define CPSW2_MAX_BLKS 0x08 /* Maximum FIFO Blocks */
  189. #define CPSW2_BLK_CNT 0x0c /* FIFO Block Usage Count (Read Only) */
  190. #define CPSW2_TX_IN_CTL 0x10 /* Transmit FIFO Control */
  191. #define CPSW2_PORT_VLAN 0x14 /* VLAN Register */
  192. #define CPSW2_TX_PRI_MAP 0x18 /* Tx Header Priority to Switch Pri Mapping */
  193. #define CPSW2_TS_SEQ_MTYPE 0x1c /* Time Sync Sequence ID Offset and Msg Type */
  194. /* CPSW_PORT_V1 and V2 */
  195. #define SA_LO 0x20 /* CPGMAC_SL Source Address Low */
  196. #define SA_HI 0x24 /* CPGMAC_SL Source Address High */
  197. #define SEND_PERCENT 0x28 /* Transmit Queue Send Percentages */
  198. /* CPSW_PORT_V2 only */
  199. #define RX_DSCP_PRI_MAP0 0x30 /* Rx DSCP Priority to Rx Packet Mapping */
  200. #define RX_DSCP_PRI_MAP1 0x34 /* Rx DSCP Priority to Rx Packet Mapping */
  201. #define RX_DSCP_PRI_MAP2 0x38 /* Rx DSCP Priority to Rx Packet Mapping */
  202. #define RX_DSCP_PRI_MAP3 0x3c /* Rx DSCP Priority to Rx Packet Mapping */
  203. #define RX_DSCP_PRI_MAP4 0x40 /* Rx DSCP Priority to Rx Packet Mapping */
  204. #define RX_DSCP_PRI_MAP5 0x44 /* Rx DSCP Priority to Rx Packet Mapping */
  205. #define RX_DSCP_PRI_MAP6 0x48 /* Rx DSCP Priority to Rx Packet Mapping */
  206. #define RX_DSCP_PRI_MAP7 0x4c /* Rx DSCP Priority to Rx Packet Mapping */
  207. /* Bit definitions for the CPSW2_CONTROL register */
  208. #define PASS_PRI_TAGGED (1<<24) /* Pass Priority Tagged */
  209. #define VLAN_LTYPE2_EN (1<<21) /* VLAN LTYPE 2 enable */
  210. #define VLAN_LTYPE1_EN (1<<20) /* VLAN LTYPE 1 enable */
  211. #define DSCP_PRI_EN (1<<16) /* DSCP Priority Enable */
  212. #define TS_320 (1<<14) /* Time Sync Dest Port 320 enable */
  213. #define TS_319 (1<<13) /* Time Sync Dest Port 319 enable */
  214. #define TS_132 (1<<12) /* Time Sync Dest IP Addr 132 enable */
  215. #define TS_131 (1<<11) /* Time Sync Dest IP Addr 131 enable */
  216. #define TS_130 (1<<10) /* Time Sync Dest IP Addr 130 enable */
  217. #define TS_129 (1<<9) /* Time Sync Dest IP Addr 129 enable */
  218. #define TS_BIT8 (1<<8) /* ts_ttl_nonzero? */
  219. #define TS_ANNEX_D_EN (1<<4) /* Time Sync Annex D enable */
  220. #define TS_LTYPE2_EN (1<<3) /* Time Sync LTYPE 2 enable */
  221. #define TS_LTYPE1_EN (1<<2) /* Time Sync LTYPE 1 enable */
  222. #define TS_TX_EN (1<<1) /* Time Sync Transmit Enable */
  223. #define TS_RX_EN (1<<0) /* Time Sync Receive Enable */
  224. #define CTRL_TS_BITS \
  225. (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 | TS_BIT8 | \
  226. TS_ANNEX_D_EN | TS_LTYPE1_EN)
  227. #define CTRL_ALL_TS_MASK (CTRL_TS_BITS | TS_TX_EN | TS_RX_EN)
  228. #define CTRL_TX_TS_BITS (CTRL_TS_BITS | TS_TX_EN)
  229. #define CTRL_RX_TS_BITS (CTRL_TS_BITS | TS_RX_EN)
  230. /* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */
  231. #define TS_SEQ_ID_OFFSET_SHIFT (16) /* Time Sync Sequence ID Offset */
  232. #define TS_SEQ_ID_OFFSET_MASK (0x3f)
  233. #define TS_MSG_TYPE_EN_SHIFT (0) /* Time Sync Message Type Enable */
  234. #define TS_MSG_TYPE_EN_MASK (0xffff)
  235. /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */
  236. #define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3))
  237. /* Bit definitions for the CPSW1_TS_CTL register */
  238. #define CPSW_V1_TS_RX_EN BIT(0)
  239. #define CPSW_V1_TS_TX_EN BIT(4)
  240. #define CPSW_V1_MSG_TYPE_OFS 16
  241. /* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */
  242. #define CPSW_V1_SEQ_ID_OFS_SHIFT 16
  243. struct cpsw_host_regs {
  244. u32 max_blks;
  245. u32 blk_cnt;
  246. u32 tx_in_ctl;
  247. u32 port_vlan;
  248. u32 tx_pri_map;
  249. u32 cpdma_tx_pri_map;
  250. u32 cpdma_rx_chan_map;
  251. };
  252. struct cpsw_sliver_regs {
  253. u32 id_ver;
  254. u32 mac_control;
  255. u32 mac_status;
  256. u32 soft_reset;
  257. u32 rx_maxlen;
  258. u32 __reserved_0;
  259. u32 rx_pause;
  260. u32 tx_pause;
  261. u32 __reserved_1;
  262. u32 rx_pri_map;
  263. };
  264. struct cpsw_hw_stats {
  265. u32 rxgoodframes;
  266. u32 rxbroadcastframes;
  267. u32 rxmulticastframes;
  268. u32 rxpauseframes;
  269. u32 rxcrcerrors;
  270. u32 rxaligncodeerrors;
  271. u32 rxoversizedframes;
  272. u32 rxjabberframes;
  273. u32 rxundersizedframes;
  274. u32 rxfragments;
  275. u32 __pad_0[2];
  276. u32 rxoctets;
  277. u32 txgoodframes;
  278. u32 txbroadcastframes;
  279. u32 txmulticastframes;
  280. u32 txpauseframes;
  281. u32 txdeferredframes;
  282. u32 txcollisionframes;
  283. u32 txsinglecollframes;
  284. u32 txmultcollframes;
  285. u32 txexcessivecollisions;
  286. u32 txlatecollisions;
  287. u32 txunderrun;
  288. u32 txcarriersenseerrors;
  289. u32 txoctets;
  290. u32 octetframes64;
  291. u32 octetframes65t127;
  292. u32 octetframes128t255;
  293. u32 octetframes256t511;
  294. u32 octetframes512t1023;
  295. u32 octetframes1024tup;
  296. u32 netoctets;
  297. u32 rxsofoverruns;
  298. u32 rxmofoverruns;
  299. u32 rxdmaoverruns;
  300. };
  301. struct cpsw_slave {
  302. void __iomem *regs;
  303. struct cpsw_sliver_regs __iomem *sliver;
  304. int slave_num;
  305. u32 mac_control;
  306. struct cpsw_slave_data *data;
  307. struct phy_device *phy;
  308. struct net_device *ndev;
  309. u32 port_vlan;
  310. u32 open_stat;
  311. };
  312. static inline u32 slave_read(struct cpsw_slave *slave, u32 offset)
  313. {
  314. return __raw_readl(slave->regs + offset);
  315. }
  316. static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset)
  317. {
  318. __raw_writel(val, slave->regs + offset);
  319. }
  320. struct cpsw_priv {
  321. spinlock_t lock;
  322. struct platform_device *pdev;
  323. struct net_device *ndev;
  324. struct resource *cpsw_res;
  325. struct resource *cpsw_wr_res;
  326. struct napi_struct napi;
  327. struct device *dev;
  328. struct cpsw_platform_data data;
  329. struct cpsw_ss_regs __iomem *regs;
  330. struct cpsw_wr_regs __iomem *wr_regs;
  331. u8 __iomem *hw_stats;
  332. struct cpsw_host_regs __iomem *host_port_regs;
  333. u32 msg_enable;
  334. u32 version;
  335. u32 coal_intvl;
  336. u32 bus_freq_mhz;
  337. struct net_device_stats stats;
  338. int rx_packet_max;
  339. int host_port;
  340. struct clk *clk;
  341. u8 mac_addr[ETH_ALEN];
  342. struct cpsw_slave *slaves;
  343. struct cpdma_ctlr *dma;
  344. struct cpdma_chan *txch, *rxch;
  345. struct cpsw_ale *ale;
  346. /* snapshot of IRQ numbers */
  347. u32 irqs_table[4];
  348. u32 num_irqs;
  349. bool irq_enabled;
  350. struct cpts *cpts;
  351. u32 emac_port;
  352. };
  353. struct cpsw_stats {
  354. char stat_string[ETH_GSTRING_LEN];
  355. int type;
  356. int sizeof_stat;
  357. int stat_offset;
  358. };
  359. enum {
  360. CPSW_STATS,
  361. CPDMA_RX_STATS,
  362. CPDMA_TX_STATS,
  363. };
  364. #define CPSW_STAT(m) CPSW_STATS, \
  365. sizeof(((struct cpsw_hw_stats *)0)->m), \
  366. offsetof(struct cpsw_hw_stats, m)
  367. #define CPDMA_RX_STAT(m) CPDMA_RX_STATS, \
  368. sizeof(((struct cpdma_chan_stats *)0)->m), \
  369. offsetof(struct cpdma_chan_stats, m)
  370. #define CPDMA_TX_STAT(m) CPDMA_TX_STATS, \
  371. sizeof(((struct cpdma_chan_stats *)0)->m), \
  372. offsetof(struct cpdma_chan_stats, m)
  373. static const struct cpsw_stats cpsw_gstrings_stats[] = {
  374. { "Good Rx Frames", CPSW_STAT(rxgoodframes) },
  375. { "Broadcast Rx Frames", CPSW_STAT(rxbroadcastframes) },
  376. { "Multicast Rx Frames", CPSW_STAT(rxmulticastframes) },
  377. { "Pause Rx Frames", CPSW_STAT(rxpauseframes) },
  378. { "Rx CRC Errors", CPSW_STAT(rxcrcerrors) },
  379. { "Rx Align/Code Errors", CPSW_STAT(rxaligncodeerrors) },
  380. { "Oversize Rx Frames", CPSW_STAT(rxoversizedframes) },
  381. { "Rx Jabbers", CPSW_STAT(rxjabberframes) },
  382. { "Undersize (Short) Rx Frames", CPSW_STAT(rxundersizedframes) },
  383. { "Rx Fragments", CPSW_STAT(rxfragments) },
  384. { "Rx Octets", CPSW_STAT(rxoctets) },
  385. { "Good Tx Frames", CPSW_STAT(txgoodframes) },
  386. { "Broadcast Tx Frames", CPSW_STAT(txbroadcastframes) },
  387. { "Multicast Tx Frames", CPSW_STAT(txmulticastframes) },
  388. { "Pause Tx Frames", CPSW_STAT(txpauseframes) },
  389. { "Deferred Tx Frames", CPSW_STAT(txdeferredframes) },
  390. { "Collisions", CPSW_STAT(txcollisionframes) },
  391. { "Single Collision Tx Frames", CPSW_STAT(txsinglecollframes) },
  392. { "Multiple Collision Tx Frames", CPSW_STAT(txmultcollframes) },
  393. { "Excessive Collisions", CPSW_STAT(txexcessivecollisions) },
  394. { "Late Collisions", CPSW_STAT(txlatecollisions) },
  395. { "Tx Underrun", CPSW_STAT(txunderrun) },
  396. { "Carrier Sense Errors", CPSW_STAT(txcarriersenseerrors) },
  397. { "Tx Octets", CPSW_STAT(txoctets) },
  398. { "Rx + Tx 64 Octet Frames", CPSW_STAT(octetframes64) },
  399. { "Rx + Tx 65-127 Octet Frames", CPSW_STAT(octetframes65t127) },
  400. { "Rx + Tx 128-255 Octet Frames", CPSW_STAT(octetframes128t255) },
  401. { "Rx + Tx 256-511 Octet Frames", CPSW_STAT(octetframes256t511) },
  402. { "Rx + Tx 512-1023 Octet Frames", CPSW_STAT(octetframes512t1023) },
  403. { "Rx + Tx 1024-Up Octet Frames", CPSW_STAT(octetframes1024tup) },
  404. { "Net Octets", CPSW_STAT(netoctets) },
  405. { "Rx Start of Frame Overruns", CPSW_STAT(rxsofoverruns) },
  406. { "Rx Middle of Frame Overruns", CPSW_STAT(rxmofoverruns) },
  407. { "Rx DMA Overruns", CPSW_STAT(rxdmaoverruns) },
  408. { "Rx DMA chan: head_enqueue", CPDMA_RX_STAT(head_enqueue) },
  409. { "Rx DMA chan: tail_enqueue", CPDMA_RX_STAT(tail_enqueue) },
  410. { "Rx DMA chan: pad_enqueue", CPDMA_RX_STAT(pad_enqueue) },
  411. { "Rx DMA chan: misqueued", CPDMA_RX_STAT(misqueued) },
  412. { "Rx DMA chan: desc_alloc_fail", CPDMA_RX_STAT(desc_alloc_fail) },
  413. { "Rx DMA chan: pad_alloc_fail", CPDMA_RX_STAT(pad_alloc_fail) },
  414. { "Rx DMA chan: runt_receive_buf", CPDMA_RX_STAT(runt_receive_buff) },
  415. { "Rx DMA chan: runt_transmit_buf", CPDMA_RX_STAT(runt_transmit_buff) },
  416. { "Rx DMA chan: empty_dequeue", CPDMA_RX_STAT(empty_dequeue) },
  417. { "Rx DMA chan: busy_dequeue", CPDMA_RX_STAT(busy_dequeue) },
  418. { "Rx DMA chan: good_dequeue", CPDMA_RX_STAT(good_dequeue) },
  419. { "Rx DMA chan: requeue", CPDMA_RX_STAT(requeue) },
  420. { "Rx DMA chan: teardown_dequeue", CPDMA_RX_STAT(teardown_dequeue) },
  421. { "Tx DMA chan: head_enqueue", CPDMA_TX_STAT(head_enqueue) },
  422. { "Tx DMA chan: tail_enqueue", CPDMA_TX_STAT(tail_enqueue) },
  423. { "Tx DMA chan: pad_enqueue", CPDMA_TX_STAT(pad_enqueue) },
  424. { "Tx DMA chan: misqueued", CPDMA_TX_STAT(misqueued) },
  425. { "Tx DMA chan: desc_alloc_fail", CPDMA_TX_STAT(desc_alloc_fail) },
  426. { "Tx DMA chan: pad_alloc_fail", CPDMA_TX_STAT(pad_alloc_fail) },
  427. { "Tx DMA chan: runt_receive_buf", CPDMA_TX_STAT(runt_receive_buff) },
  428. { "Tx DMA chan: runt_transmit_buf", CPDMA_TX_STAT(runt_transmit_buff) },
  429. { "Tx DMA chan: empty_dequeue", CPDMA_TX_STAT(empty_dequeue) },
  430. { "Tx DMA chan: busy_dequeue", CPDMA_TX_STAT(busy_dequeue) },
  431. { "Tx DMA chan: good_dequeue", CPDMA_TX_STAT(good_dequeue) },
  432. { "Tx DMA chan: requeue", CPDMA_TX_STAT(requeue) },
  433. { "Tx DMA chan: teardown_dequeue", CPDMA_TX_STAT(teardown_dequeue) },
  434. };
  435. #define CPSW_STATS_LEN ARRAY_SIZE(cpsw_gstrings_stats)
  436. #define napi_to_priv(napi) container_of(napi, struct cpsw_priv, napi)
  437. #define for_each_slave(priv, func, arg...) \
  438. do { \
  439. struct cpsw_slave *slave; \
  440. int n; \
  441. if (priv->data.dual_emac) \
  442. (func)((priv)->slaves + priv->emac_port, ##arg);\
  443. else \
  444. for (n = (priv)->data.slaves, \
  445. slave = (priv)->slaves; \
  446. n; n--) \
  447. (func)(slave++, ##arg); \
  448. } while (0)
  449. #define cpsw_get_slave_ndev(priv, __slave_no__) \
  450. (priv->slaves[__slave_no__].ndev)
  451. #define cpsw_get_slave_priv(priv, __slave_no__) \
  452. ((priv->slaves[__slave_no__].ndev) ? \
  453. netdev_priv(priv->slaves[__slave_no__].ndev) : NULL) \
  454. #define cpsw_dual_emac_src_port_detect(status, priv, ndev, skb) \
  455. do { \
  456. if (!priv->data.dual_emac) \
  457. break; \
  458. if (CPDMA_RX_SOURCE_PORT(status) == 1) { \
  459. ndev = cpsw_get_slave_ndev(priv, 0); \
  460. priv = netdev_priv(ndev); \
  461. skb->dev = ndev; \
  462. } else if (CPDMA_RX_SOURCE_PORT(status) == 2) { \
  463. ndev = cpsw_get_slave_ndev(priv, 1); \
  464. priv = netdev_priv(ndev); \
  465. skb->dev = ndev; \
  466. } \
  467. } while (0)
  468. #define cpsw_add_mcast(priv, addr) \
  469. do { \
  470. if (priv->data.dual_emac) { \
  471. struct cpsw_slave *slave = priv->slaves + \
  472. priv->emac_port; \
  473. int slave_port = cpsw_get_slave_port(priv, \
  474. slave->slave_num); \
  475. cpsw_ale_add_mcast(priv->ale, addr, \
  476. 1 << slave_port | 1 << priv->host_port, \
  477. ALE_VLAN, slave->port_vlan, 0); \
  478. } else { \
  479. cpsw_ale_add_mcast(priv->ale, addr, \
  480. ALE_ALL_PORTS << priv->host_port, \
  481. 0, 0, 0); \
  482. } \
  483. } while (0)
  484. static inline int cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num)
  485. {
  486. if (priv->host_port == 0)
  487. return slave_num + 1;
  488. else
  489. return slave_num;
  490. }
  491. static void cpsw_ndo_set_rx_mode(struct net_device *ndev)
  492. {
  493. struct cpsw_priv *priv = netdev_priv(ndev);
  494. if (ndev->flags & IFF_PROMISC) {
  495. /* Enable promiscuous mode */
  496. dev_err(priv->dev, "Ignoring Promiscuous mode\n");
  497. return;
  498. }
  499. /* Clear all mcast from ALE */
  500. cpsw_ale_flush_multicast(priv->ale, ALE_ALL_PORTS << priv->host_port);
  501. if (!netdev_mc_empty(ndev)) {
  502. struct netdev_hw_addr *ha;
  503. /* program multicast address list into ALE register */
  504. netdev_for_each_mc_addr(ha, ndev) {
  505. cpsw_add_mcast(priv, (u8 *)ha->addr);
  506. }
  507. }
  508. }
  509. static void cpsw_intr_enable(struct cpsw_priv *priv)
  510. {
  511. __raw_writel(0xFF, &priv->wr_regs->tx_en);
  512. __raw_writel(0xFF, &priv->wr_regs->rx_en);
  513. cpdma_ctlr_int_ctrl(priv->dma, true);
  514. return;
  515. }
  516. static void cpsw_intr_disable(struct cpsw_priv *priv)
  517. {
  518. __raw_writel(0, &priv->wr_regs->tx_en);
  519. __raw_writel(0, &priv->wr_regs->rx_en);
  520. cpdma_ctlr_int_ctrl(priv->dma, false);
  521. return;
  522. }
  523. void cpsw_tx_handler(void *token, int len, int status)
  524. {
  525. struct sk_buff *skb = token;
  526. struct net_device *ndev = skb->dev;
  527. struct cpsw_priv *priv = netdev_priv(ndev);
  528. /* Check whether the queue is stopped due to stalled tx dma, if the
  529. * queue is stopped then start the queue as we have free desc for tx
  530. */
  531. if (unlikely(netif_queue_stopped(ndev)))
  532. netif_wake_queue(ndev);
  533. cpts_tx_timestamp(priv->cpts, skb);
  534. priv->stats.tx_packets++;
  535. priv->stats.tx_bytes += len;
  536. dev_kfree_skb_any(skb);
  537. }
  538. void cpsw_rx_handler(void *token, int len, int status)
  539. {
  540. struct sk_buff *skb = token;
  541. struct sk_buff *new_skb;
  542. struct net_device *ndev = skb->dev;
  543. struct cpsw_priv *priv = netdev_priv(ndev);
  544. int ret = 0;
  545. cpsw_dual_emac_src_port_detect(status, priv, ndev, skb);
  546. if (unlikely(status < 0)) {
  547. /* the interface is going down, skbs are purged */
  548. dev_kfree_skb_any(skb);
  549. return;
  550. }
  551. new_skb = netdev_alloc_skb_ip_align(ndev, priv->rx_packet_max);
  552. if (new_skb) {
  553. skb_put(skb, len);
  554. cpts_rx_timestamp(priv->cpts, skb);
  555. skb->protocol = eth_type_trans(skb, ndev);
  556. netif_receive_skb(skb);
  557. priv->stats.rx_bytes += len;
  558. priv->stats.rx_packets++;
  559. } else {
  560. priv->stats.rx_dropped++;
  561. new_skb = skb;
  562. }
  563. ret = cpdma_chan_submit(priv->rxch, new_skb, new_skb->data,
  564. skb_tailroom(new_skb), 0);
  565. if (WARN_ON(ret < 0))
  566. dev_kfree_skb_any(new_skb);
  567. }
  568. static irqreturn_t cpsw_interrupt(int irq, void *dev_id)
  569. {
  570. struct cpsw_priv *priv = dev_id;
  571. cpsw_intr_disable(priv);
  572. if (priv->irq_enabled == true) {
  573. cpsw_disable_irq(priv);
  574. priv->irq_enabled = false;
  575. }
  576. if (netif_running(priv->ndev)) {
  577. napi_schedule(&priv->napi);
  578. return IRQ_HANDLED;
  579. }
  580. priv = cpsw_get_slave_priv(priv, 1);
  581. if (!priv)
  582. return IRQ_NONE;
  583. if (netif_running(priv->ndev)) {
  584. napi_schedule(&priv->napi);
  585. return IRQ_HANDLED;
  586. }
  587. return IRQ_NONE;
  588. }
  589. static int cpsw_poll(struct napi_struct *napi, int budget)
  590. {
  591. struct cpsw_priv *priv = napi_to_priv(napi);
  592. int num_tx, num_rx;
  593. num_tx = cpdma_chan_process(priv->txch, 128);
  594. if (num_tx)
  595. cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX);
  596. num_rx = cpdma_chan_process(priv->rxch, budget);
  597. if (num_rx < budget) {
  598. struct cpsw_priv *prim_cpsw;
  599. napi_complete(napi);
  600. cpsw_intr_enable(priv);
  601. cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX);
  602. prim_cpsw = cpsw_get_slave_priv(priv, 0);
  603. if (prim_cpsw->irq_enabled == false) {
  604. prim_cpsw->irq_enabled = true;
  605. cpsw_enable_irq(priv);
  606. }
  607. }
  608. if (num_rx || num_tx)
  609. cpsw_dbg(priv, intr, "poll %d rx, %d tx pkts\n",
  610. num_rx, num_tx);
  611. return num_rx;
  612. }
  613. static inline void soft_reset(const char *module, void __iomem *reg)
  614. {
  615. unsigned long timeout = jiffies + HZ;
  616. __raw_writel(1, reg);
  617. do {
  618. cpu_relax();
  619. } while ((__raw_readl(reg) & 1) && time_after(timeout, jiffies));
  620. WARN(__raw_readl(reg) & 1, "failed to soft-reset %s\n", module);
  621. }
  622. #define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \
  623. ((mac)[2] << 16) | ((mac)[3] << 24))
  624. #define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8))
  625. static void cpsw_set_slave_mac(struct cpsw_slave *slave,
  626. struct cpsw_priv *priv)
  627. {
  628. slave_write(slave, mac_hi(priv->mac_addr), SA_HI);
  629. slave_write(slave, mac_lo(priv->mac_addr), SA_LO);
  630. }
  631. static void _cpsw_adjust_link(struct cpsw_slave *slave,
  632. struct cpsw_priv *priv, bool *link)
  633. {
  634. struct phy_device *phy = slave->phy;
  635. u32 mac_control = 0;
  636. u32 slave_port;
  637. if (!phy)
  638. return;
  639. slave_port = cpsw_get_slave_port(priv, slave->slave_num);
  640. if (phy->link) {
  641. mac_control = priv->data.mac_control;
  642. /* enable forwarding */
  643. cpsw_ale_control_set(priv->ale, slave_port,
  644. ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
  645. if (phy->speed == 1000)
  646. mac_control |= BIT(7); /* GIGABITEN */
  647. if (phy->duplex)
  648. mac_control |= BIT(0); /* FULLDUPLEXEN */
  649. /* set speed_in input in case RMII mode is used in 100Mbps */
  650. if (phy->speed == 100)
  651. mac_control |= BIT(15);
  652. *link = true;
  653. } else {
  654. mac_control = 0;
  655. /* disable forwarding */
  656. cpsw_ale_control_set(priv->ale, slave_port,
  657. ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
  658. }
  659. if (mac_control != slave->mac_control) {
  660. phy_print_status(phy);
  661. __raw_writel(mac_control, &slave->sliver->mac_control);
  662. }
  663. slave->mac_control = mac_control;
  664. }
  665. static void cpsw_adjust_link(struct net_device *ndev)
  666. {
  667. struct cpsw_priv *priv = netdev_priv(ndev);
  668. bool link = false;
  669. for_each_slave(priv, _cpsw_adjust_link, priv, &link);
  670. if (link) {
  671. netif_carrier_on(ndev);
  672. if (netif_running(ndev))
  673. netif_wake_queue(ndev);
  674. } else {
  675. netif_carrier_off(ndev);
  676. netif_stop_queue(ndev);
  677. }
  678. }
  679. static int cpsw_get_coalesce(struct net_device *ndev,
  680. struct ethtool_coalesce *coal)
  681. {
  682. struct cpsw_priv *priv = netdev_priv(ndev);
  683. coal->rx_coalesce_usecs = priv->coal_intvl;
  684. return 0;
  685. }
  686. static int cpsw_set_coalesce(struct net_device *ndev,
  687. struct ethtool_coalesce *coal)
  688. {
  689. struct cpsw_priv *priv = netdev_priv(ndev);
  690. u32 int_ctrl;
  691. u32 num_interrupts = 0;
  692. u32 prescale = 0;
  693. u32 addnl_dvdr = 1;
  694. u32 coal_intvl = 0;
  695. if (!coal->rx_coalesce_usecs)
  696. return -EINVAL;
  697. coal_intvl = coal->rx_coalesce_usecs;
  698. int_ctrl = readl(&priv->wr_regs->int_control);
  699. prescale = priv->bus_freq_mhz * 4;
  700. if (coal_intvl < CPSW_CMINTMIN_INTVL)
  701. coal_intvl = CPSW_CMINTMIN_INTVL;
  702. if (coal_intvl > CPSW_CMINTMAX_INTVL) {
  703. /* Interrupt pacer works with 4us Pulse, we can
  704. * throttle further by dilating the 4us pulse.
  705. */
  706. addnl_dvdr = CPSW_INTPRESCALE_MASK / prescale;
  707. if (addnl_dvdr > 1) {
  708. prescale *= addnl_dvdr;
  709. if (coal_intvl > (CPSW_CMINTMAX_INTVL * addnl_dvdr))
  710. coal_intvl = (CPSW_CMINTMAX_INTVL
  711. * addnl_dvdr);
  712. } else {
  713. addnl_dvdr = 1;
  714. coal_intvl = CPSW_CMINTMAX_INTVL;
  715. }
  716. }
  717. num_interrupts = (1000 * addnl_dvdr) / coal_intvl;
  718. writel(num_interrupts, &priv->wr_regs->rx_imax);
  719. writel(num_interrupts, &priv->wr_regs->tx_imax);
  720. int_ctrl |= CPSW_INTPACEEN;
  721. int_ctrl &= (~CPSW_INTPRESCALE_MASK);
  722. int_ctrl |= (prescale & CPSW_INTPRESCALE_MASK);
  723. writel(int_ctrl, &priv->wr_regs->int_control);
  724. cpsw_notice(priv, timer, "Set coalesce to %d usecs.\n", coal_intvl);
  725. if (priv->data.dual_emac) {
  726. int i;
  727. for (i = 0; i < priv->data.slaves; i++) {
  728. priv = netdev_priv(priv->slaves[i].ndev);
  729. priv->coal_intvl = coal_intvl;
  730. }
  731. } else {
  732. priv->coal_intvl = coal_intvl;
  733. }
  734. return 0;
  735. }
  736. static int cpsw_get_sset_count(struct net_device *ndev, int sset)
  737. {
  738. switch (sset) {
  739. case ETH_SS_STATS:
  740. return CPSW_STATS_LEN;
  741. default:
  742. return -EOPNOTSUPP;
  743. }
  744. }
  745. static void cpsw_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
  746. {
  747. u8 *p = data;
  748. int i;
  749. switch (stringset) {
  750. case ETH_SS_STATS:
  751. for (i = 0; i < CPSW_STATS_LEN; i++) {
  752. memcpy(p, cpsw_gstrings_stats[i].stat_string,
  753. ETH_GSTRING_LEN);
  754. p += ETH_GSTRING_LEN;
  755. }
  756. break;
  757. }
  758. }
  759. static void cpsw_get_ethtool_stats(struct net_device *ndev,
  760. struct ethtool_stats *stats, u64 *data)
  761. {
  762. struct cpsw_priv *priv = netdev_priv(ndev);
  763. struct cpdma_chan_stats rx_stats;
  764. struct cpdma_chan_stats tx_stats;
  765. u32 val;
  766. u8 *p;
  767. int i;
  768. /* Collect Davinci CPDMA stats for Rx and Tx Channel */
  769. cpdma_chan_get_stats(priv->rxch, &rx_stats);
  770. cpdma_chan_get_stats(priv->txch, &tx_stats);
  771. for (i = 0; i < CPSW_STATS_LEN; i++) {
  772. switch (cpsw_gstrings_stats[i].type) {
  773. case CPSW_STATS:
  774. val = readl(priv->hw_stats +
  775. cpsw_gstrings_stats[i].stat_offset);
  776. data[i] = val;
  777. break;
  778. case CPDMA_RX_STATS:
  779. p = (u8 *)&rx_stats +
  780. cpsw_gstrings_stats[i].stat_offset;
  781. data[i] = *(u32 *)p;
  782. break;
  783. case CPDMA_TX_STATS:
  784. p = (u8 *)&tx_stats +
  785. cpsw_gstrings_stats[i].stat_offset;
  786. data[i] = *(u32 *)p;
  787. break;
  788. }
  789. }
  790. }
  791. static inline int __show_stat(char *buf, int maxlen, const char *name, u32 val)
  792. {
  793. static char *leader = "........................................";
  794. if (!val)
  795. return 0;
  796. else
  797. return snprintf(buf, maxlen, "%s %s %10d\n", name,
  798. leader + strlen(name), val);
  799. }
  800. static int cpsw_common_res_usage_state(struct cpsw_priv *priv)
  801. {
  802. u32 i;
  803. u32 usage_count = 0;
  804. if (!priv->data.dual_emac)
  805. return 0;
  806. for (i = 0; i < priv->data.slaves; i++)
  807. if (priv->slaves[i].open_stat)
  808. usage_count++;
  809. return usage_count;
  810. }
  811. static inline int cpsw_tx_packet_submit(struct net_device *ndev,
  812. struct cpsw_priv *priv, struct sk_buff *skb)
  813. {
  814. if (!priv->data.dual_emac)
  815. return cpdma_chan_submit(priv->txch, skb, skb->data,
  816. skb->len, 0);
  817. if (ndev == cpsw_get_slave_ndev(priv, 0))
  818. return cpdma_chan_submit(priv->txch, skb, skb->data,
  819. skb->len, 1);
  820. else
  821. return cpdma_chan_submit(priv->txch, skb, skb->data,
  822. skb->len, 2);
  823. }
  824. static inline void cpsw_add_dual_emac_def_ale_entries(
  825. struct cpsw_priv *priv, struct cpsw_slave *slave,
  826. u32 slave_port)
  827. {
  828. u32 port_mask = 1 << slave_port | 1 << priv->host_port;
  829. if (priv->version == CPSW_VERSION_1)
  830. slave_write(slave, slave->port_vlan, CPSW1_PORT_VLAN);
  831. else
  832. slave_write(slave, slave->port_vlan, CPSW2_PORT_VLAN);
  833. cpsw_ale_add_vlan(priv->ale, slave->port_vlan, port_mask,
  834. port_mask, port_mask, 0);
  835. cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
  836. port_mask, ALE_VLAN, slave->port_vlan, 0);
  837. cpsw_ale_add_ucast(priv->ale, priv->mac_addr,
  838. priv->host_port, ALE_VLAN, slave->port_vlan);
  839. }
  840. static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv)
  841. {
  842. char name[32];
  843. u32 slave_port;
  844. sprintf(name, "slave-%d", slave->slave_num);
  845. soft_reset(name, &slave->sliver->soft_reset);
  846. /* setup priority mapping */
  847. __raw_writel(RX_PRIORITY_MAPPING, &slave->sliver->rx_pri_map);
  848. switch (priv->version) {
  849. case CPSW_VERSION_1:
  850. slave_write(slave, TX_PRIORITY_MAPPING, CPSW1_TX_PRI_MAP);
  851. break;
  852. case CPSW_VERSION_2:
  853. case CPSW_VERSION_3:
  854. case CPSW_VERSION_4:
  855. slave_write(slave, TX_PRIORITY_MAPPING, CPSW2_TX_PRI_MAP);
  856. break;
  857. }
  858. /* setup max packet size, and mac address */
  859. __raw_writel(priv->rx_packet_max, &slave->sliver->rx_maxlen);
  860. cpsw_set_slave_mac(slave, priv);
  861. slave->mac_control = 0; /* no link yet */
  862. slave_port = cpsw_get_slave_port(priv, slave->slave_num);
  863. if (priv->data.dual_emac)
  864. cpsw_add_dual_emac_def_ale_entries(priv, slave, slave_port);
  865. else
  866. cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
  867. 1 << slave_port, 0, 0, ALE_MCAST_FWD_2);
  868. slave->phy = phy_connect(priv->ndev, slave->data->phy_id,
  869. &cpsw_adjust_link, slave->data->phy_if);
  870. if (IS_ERR(slave->phy)) {
  871. dev_err(priv->dev, "phy %s not found on slave %d\n",
  872. slave->data->phy_id, slave->slave_num);
  873. slave->phy = NULL;
  874. } else {
  875. dev_info(priv->dev, "phy found : id is : 0x%x\n",
  876. slave->phy->phy_id);
  877. phy_start(slave->phy);
  878. }
  879. }
  880. static inline void cpsw_add_default_vlan(struct cpsw_priv *priv)
  881. {
  882. const int vlan = priv->data.default_vlan;
  883. const int port = priv->host_port;
  884. u32 reg;
  885. int i;
  886. reg = (priv->version == CPSW_VERSION_1) ? CPSW1_PORT_VLAN :
  887. CPSW2_PORT_VLAN;
  888. writel(vlan, &priv->host_port_regs->port_vlan);
  889. for (i = 0; i < priv->data.slaves; i++)
  890. slave_write(priv->slaves + i, vlan, reg);
  891. cpsw_ale_add_vlan(priv->ale, vlan, ALE_ALL_PORTS << port,
  892. ALE_ALL_PORTS << port, ALE_ALL_PORTS << port,
  893. (ALE_PORT_1 | ALE_PORT_2) << port);
  894. }
  895. static void cpsw_init_host_port(struct cpsw_priv *priv)
  896. {
  897. u32 control_reg;
  898. u32 fifo_mode;
  899. /* soft reset the controller and initialize ale */
  900. soft_reset("cpsw", &priv->regs->soft_reset);
  901. cpsw_ale_start(priv->ale);
  902. /* switch to vlan unaware mode */
  903. cpsw_ale_control_set(priv->ale, priv->host_port, ALE_VLAN_AWARE,
  904. CPSW_ALE_VLAN_AWARE);
  905. control_reg = readl(&priv->regs->control);
  906. control_reg |= CPSW_VLAN_AWARE;
  907. writel(control_reg, &priv->regs->control);
  908. fifo_mode = (priv->data.dual_emac) ? CPSW_FIFO_DUAL_MAC_MODE :
  909. CPSW_FIFO_NORMAL_MODE;
  910. writel(fifo_mode, &priv->host_port_regs->tx_in_ctl);
  911. /* setup host port priority mapping */
  912. __raw_writel(CPDMA_TX_PRIORITY_MAP,
  913. &priv->host_port_regs->cpdma_tx_pri_map);
  914. __raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map);
  915. cpsw_ale_control_set(priv->ale, priv->host_port,
  916. ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
  917. if (!priv->data.dual_emac) {
  918. cpsw_ale_add_ucast(priv->ale, priv->mac_addr, priv->host_port,
  919. 0, 0);
  920. cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
  921. 1 << priv->host_port, 0, 0, ALE_MCAST_FWD_2);
  922. }
  923. }
  924. static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_priv *priv)
  925. {
  926. if (!slave->phy)
  927. return;
  928. phy_stop(slave->phy);
  929. phy_disconnect(slave->phy);
  930. slave->phy = NULL;
  931. }
  932. static int cpsw_ndo_open(struct net_device *ndev)
  933. {
  934. struct cpsw_priv *priv = netdev_priv(ndev);
  935. struct cpsw_priv *prim_cpsw;
  936. int i, ret;
  937. u32 reg;
  938. if (!cpsw_common_res_usage_state(priv))
  939. cpsw_intr_disable(priv);
  940. netif_carrier_off(ndev);
  941. pm_runtime_get_sync(&priv->pdev->dev);
  942. reg = priv->version;
  943. dev_info(priv->dev, "initializing cpsw version %d.%d (%d)\n",
  944. CPSW_MAJOR_VERSION(reg), CPSW_MINOR_VERSION(reg),
  945. CPSW_RTL_VERSION(reg));
  946. /* initialize host and slave ports */
  947. if (!cpsw_common_res_usage_state(priv))
  948. cpsw_init_host_port(priv);
  949. for_each_slave(priv, cpsw_slave_open, priv);
  950. /* Add default VLAN */
  951. if (!priv->data.dual_emac)
  952. cpsw_add_default_vlan(priv);
  953. if (!cpsw_common_res_usage_state(priv)) {
  954. /* setup tx dma to fixed prio and zero offset */
  955. cpdma_control_set(priv->dma, CPDMA_TX_PRIO_FIXED, 1);
  956. cpdma_control_set(priv->dma, CPDMA_RX_BUFFER_OFFSET, 0);
  957. /* disable priority elevation */
  958. __raw_writel(0, &priv->regs->ptype);
  959. /* enable statistics collection only on all ports */
  960. __raw_writel(0x7, &priv->regs->stat_port_en);
  961. if (WARN_ON(!priv->data.rx_descs))
  962. priv->data.rx_descs = 128;
  963. for (i = 0; i < priv->data.rx_descs; i++) {
  964. struct sk_buff *skb;
  965. ret = -ENOMEM;
  966. skb = __netdev_alloc_skb_ip_align(priv->ndev,
  967. priv->rx_packet_max, GFP_KERNEL);
  968. if (!skb)
  969. goto err_cleanup;
  970. ret = cpdma_chan_submit(priv->rxch, skb, skb->data,
  971. skb_tailroom(skb), 0);
  972. if (ret < 0) {
  973. kfree_skb(skb);
  974. goto err_cleanup;
  975. }
  976. }
  977. /* continue even if we didn't manage to submit all
  978. * receive descs
  979. */
  980. cpsw_info(priv, ifup, "submitted %d rx descriptors\n", i);
  981. }
  982. /* Enable Interrupt pacing if configured */
  983. if (priv->coal_intvl != 0) {
  984. struct ethtool_coalesce coal;
  985. coal.rx_coalesce_usecs = (priv->coal_intvl << 4);
  986. cpsw_set_coalesce(ndev, &coal);
  987. }
  988. prim_cpsw = cpsw_get_slave_priv(priv, 0);
  989. if (prim_cpsw->irq_enabled == false) {
  990. if ((priv == prim_cpsw) || !netif_running(prim_cpsw->ndev)) {
  991. prim_cpsw->irq_enabled = true;
  992. cpsw_enable_irq(prim_cpsw);
  993. }
  994. }
  995. napi_enable(&priv->napi);
  996. cpdma_ctlr_start(priv->dma);
  997. cpsw_intr_enable(priv);
  998. cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX);
  999. cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX);
  1000. if (priv->data.dual_emac)
  1001. priv->slaves[priv->emac_port].open_stat = true;
  1002. return 0;
  1003. err_cleanup:
  1004. cpdma_ctlr_stop(priv->dma);
  1005. for_each_slave(priv, cpsw_slave_stop, priv);
  1006. pm_runtime_put_sync(&priv->pdev->dev);
  1007. netif_carrier_off(priv->ndev);
  1008. return ret;
  1009. }
  1010. static int cpsw_ndo_stop(struct net_device *ndev)
  1011. {
  1012. struct cpsw_priv *priv = netdev_priv(ndev);
  1013. cpsw_info(priv, ifdown, "shutting down cpsw device\n");
  1014. netif_stop_queue(priv->ndev);
  1015. napi_disable(&priv->napi);
  1016. netif_carrier_off(priv->ndev);
  1017. if (cpsw_common_res_usage_state(priv) <= 1) {
  1018. cpsw_intr_disable(priv);
  1019. cpdma_ctlr_int_ctrl(priv->dma, false);
  1020. cpdma_ctlr_stop(priv->dma);
  1021. cpsw_ale_stop(priv->ale);
  1022. }
  1023. for_each_slave(priv, cpsw_slave_stop, priv);
  1024. pm_runtime_put_sync(&priv->pdev->dev);
  1025. if (priv->data.dual_emac)
  1026. priv->slaves[priv->emac_port].open_stat = false;
  1027. return 0;
  1028. }
  1029. static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb,
  1030. struct net_device *ndev)
  1031. {
  1032. struct cpsw_priv *priv = netdev_priv(ndev);
  1033. int ret;
  1034. ndev->trans_start = jiffies;
  1035. if (skb_padto(skb, CPSW_MIN_PACKET_SIZE)) {
  1036. cpsw_err(priv, tx_err, "packet pad failed\n");
  1037. priv->stats.tx_dropped++;
  1038. return NETDEV_TX_OK;
  1039. }
  1040. if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
  1041. priv->cpts->tx_enable)
  1042. skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
  1043. skb_tx_timestamp(skb);
  1044. ret = cpsw_tx_packet_submit(ndev, priv, skb);
  1045. if (unlikely(ret != 0)) {
  1046. cpsw_err(priv, tx_err, "desc submit failed\n");
  1047. goto fail;
  1048. }
  1049. /* If there is no more tx desc left free then we need to
  1050. * tell the kernel to stop sending us tx frames.
  1051. */
  1052. if (unlikely(!cpdma_check_free_tx_desc(priv->txch)))
  1053. netif_stop_queue(ndev);
  1054. return NETDEV_TX_OK;
  1055. fail:
  1056. priv->stats.tx_dropped++;
  1057. netif_stop_queue(ndev);
  1058. return NETDEV_TX_BUSY;
  1059. }
  1060. static void cpsw_ndo_change_rx_flags(struct net_device *ndev, int flags)
  1061. {
  1062. /*
  1063. * The switch cannot operate in promiscuous mode without substantial
  1064. * headache. For promiscuous mode to work, we would need to put the
  1065. * ALE in bypass mode and route all traffic to the host port.
  1066. * Subsequently, the host will need to operate as a "bridge", learn,
  1067. * and flood as needed. For now, we simply complain here and
  1068. * do nothing about it :-)
  1069. */
  1070. if ((flags & IFF_PROMISC) && (ndev->flags & IFF_PROMISC))
  1071. dev_err(&ndev->dev, "promiscuity ignored!\n");
  1072. /*
  1073. * The switch cannot filter multicast traffic unless it is configured
  1074. * in "VLAN Aware" mode. Unfortunately, VLAN awareness requires a
  1075. * whole bunch of additional logic that this driver does not implement
  1076. * at present.
  1077. */
  1078. if ((flags & IFF_ALLMULTI) && !(ndev->flags & IFF_ALLMULTI))
  1079. dev_err(&ndev->dev, "multicast traffic cannot be filtered!\n");
  1080. }
  1081. #ifdef CONFIG_TI_CPTS
  1082. static void cpsw_hwtstamp_v1(struct cpsw_priv *priv)
  1083. {
  1084. struct cpsw_slave *slave = &priv->slaves[priv->data.active_slave];
  1085. u32 ts_en, seq_id;
  1086. if (!priv->cpts->tx_enable && !priv->cpts->rx_enable) {
  1087. slave_write(slave, 0, CPSW1_TS_CTL);
  1088. return;
  1089. }
  1090. seq_id = (30 << CPSW_V1_SEQ_ID_OFS_SHIFT) | ETH_P_1588;
  1091. ts_en = EVENT_MSG_BITS << CPSW_V1_MSG_TYPE_OFS;
  1092. if (priv->cpts->tx_enable)
  1093. ts_en |= CPSW_V1_TS_TX_EN;
  1094. if (priv->cpts->rx_enable)
  1095. ts_en |= CPSW_V1_TS_RX_EN;
  1096. slave_write(slave, ts_en, CPSW1_TS_CTL);
  1097. slave_write(slave, seq_id, CPSW1_TS_SEQ_LTYPE);
  1098. }
  1099. static void cpsw_hwtstamp_v2(struct cpsw_priv *priv)
  1100. {
  1101. struct cpsw_slave *slave;
  1102. u32 ctrl, mtype;
  1103. if (priv->data.dual_emac)
  1104. slave = &priv->slaves[priv->emac_port];
  1105. else
  1106. slave = &priv->slaves[priv->data.active_slave];
  1107. ctrl = slave_read(slave, CPSW2_CONTROL);
  1108. ctrl &= ~CTRL_ALL_TS_MASK;
  1109. if (priv->cpts->tx_enable)
  1110. ctrl |= CTRL_TX_TS_BITS;
  1111. if (priv->cpts->rx_enable)
  1112. ctrl |= CTRL_RX_TS_BITS;
  1113. mtype = (30 << TS_SEQ_ID_OFFSET_SHIFT) | EVENT_MSG_BITS;
  1114. slave_write(slave, mtype, CPSW2_TS_SEQ_MTYPE);
  1115. slave_write(slave, ctrl, CPSW2_CONTROL);
  1116. __raw_writel(ETH_P_1588, &priv->regs->ts_ltype);
  1117. }
  1118. static int cpsw_hwtstamp_ioctl(struct net_device *dev, struct ifreq *ifr)
  1119. {
  1120. struct cpsw_priv *priv = netdev_priv(dev);
  1121. struct cpts *cpts = priv->cpts;
  1122. struct hwtstamp_config cfg;
  1123. if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
  1124. return -EFAULT;
  1125. /* reserved for future extensions */
  1126. if (cfg.flags)
  1127. return -EINVAL;
  1128. switch (cfg.tx_type) {
  1129. case HWTSTAMP_TX_OFF:
  1130. cpts->tx_enable = 0;
  1131. break;
  1132. case HWTSTAMP_TX_ON:
  1133. cpts->tx_enable = 1;
  1134. break;
  1135. default:
  1136. return -ERANGE;
  1137. }
  1138. switch (cfg.rx_filter) {
  1139. case HWTSTAMP_FILTER_NONE:
  1140. cpts->rx_enable = 0;
  1141. break;
  1142. case HWTSTAMP_FILTER_ALL:
  1143. case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
  1144. case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
  1145. case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
  1146. return -ERANGE;
  1147. case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
  1148. case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
  1149. case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
  1150. case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
  1151. case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
  1152. case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
  1153. case HWTSTAMP_FILTER_PTP_V2_EVENT:
  1154. case HWTSTAMP_FILTER_PTP_V2_SYNC:
  1155. case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
  1156. cpts->rx_enable = 1;
  1157. cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
  1158. break;
  1159. default:
  1160. return -ERANGE;
  1161. }
  1162. switch (priv->version) {
  1163. case CPSW_VERSION_1:
  1164. cpsw_hwtstamp_v1(priv);
  1165. break;
  1166. case CPSW_VERSION_2:
  1167. cpsw_hwtstamp_v2(priv);
  1168. break;
  1169. default:
  1170. return -ENOTSUPP;
  1171. }
  1172. return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
  1173. }
  1174. #endif /*CONFIG_TI_CPTS*/
  1175. static int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
  1176. {
  1177. struct cpsw_priv *priv = netdev_priv(dev);
  1178. struct mii_ioctl_data *data = if_mii(req);
  1179. int slave_no = cpsw_slave_index(priv);
  1180. if (!netif_running(dev))
  1181. return -EINVAL;
  1182. switch (cmd) {
  1183. #ifdef CONFIG_TI_CPTS
  1184. case SIOCSHWTSTAMP:
  1185. return cpsw_hwtstamp_ioctl(dev, req);
  1186. #endif
  1187. case SIOCGMIIPHY:
  1188. data->phy_id = priv->slaves[slave_no].phy->addr;
  1189. break;
  1190. default:
  1191. return -ENOTSUPP;
  1192. }
  1193. return 0;
  1194. }
  1195. static void cpsw_ndo_tx_timeout(struct net_device *ndev)
  1196. {
  1197. struct cpsw_priv *priv = netdev_priv(ndev);
  1198. cpsw_err(priv, tx_err, "transmit timeout, restarting dma\n");
  1199. priv->stats.tx_errors++;
  1200. cpsw_intr_disable(priv);
  1201. cpdma_ctlr_int_ctrl(priv->dma, false);
  1202. cpdma_chan_stop(priv->txch);
  1203. cpdma_chan_start(priv->txch);
  1204. cpdma_ctlr_int_ctrl(priv->dma, true);
  1205. cpsw_intr_enable(priv);
  1206. cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX);
  1207. cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX);
  1208. }
  1209. static int cpsw_ndo_set_mac_address(struct net_device *ndev, void *p)
  1210. {
  1211. struct cpsw_priv *priv = netdev_priv(ndev);
  1212. struct sockaddr *addr = (struct sockaddr *)p;
  1213. int flags = 0;
  1214. u16 vid = 0;
  1215. if (!is_valid_ether_addr(addr->sa_data))
  1216. return -EADDRNOTAVAIL;
  1217. if (priv->data.dual_emac) {
  1218. vid = priv->slaves[priv->emac_port].port_vlan;
  1219. flags = ALE_VLAN;
  1220. }
  1221. cpsw_ale_del_ucast(priv->ale, priv->mac_addr, priv->host_port,
  1222. flags, vid);
  1223. cpsw_ale_add_ucast(priv->ale, addr->sa_data, priv->host_port,
  1224. flags, vid);
  1225. memcpy(priv->mac_addr, addr->sa_data, ETH_ALEN);
  1226. memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
  1227. for_each_slave(priv, cpsw_set_slave_mac, priv);
  1228. return 0;
  1229. }
  1230. static struct net_device_stats *cpsw_ndo_get_stats(struct net_device *ndev)
  1231. {
  1232. struct cpsw_priv *priv = netdev_priv(ndev);
  1233. return &priv->stats;
  1234. }
  1235. #ifdef CONFIG_NET_POLL_CONTROLLER
  1236. static void cpsw_ndo_poll_controller(struct net_device *ndev)
  1237. {
  1238. struct cpsw_priv *priv = netdev_priv(ndev);
  1239. cpsw_intr_disable(priv);
  1240. cpdma_ctlr_int_ctrl(priv->dma, false);
  1241. cpsw_interrupt(ndev->irq, priv);
  1242. cpdma_ctlr_int_ctrl(priv->dma, true);
  1243. cpsw_intr_enable(priv);
  1244. cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX);
  1245. cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX);
  1246. }
  1247. #endif
  1248. static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv,
  1249. unsigned short vid)
  1250. {
  1251. int ret;
  1252. ret = cpsw_ale_add_vlan(priv->ale, vid,
  1253. ALE_ALL_PORTS << priv->host_port,
  1254. 0, ALE_ALL_PORTS << priv->host_port,
  1255. (ALE_PORT_1 | ALE_PORT_2) << priv->host_port);
  1256. if (ret != 0)
  1257. return ret;
  1258. ret = cpsw_ale_add_ucast(priv->ale, priv->mac_addr,
  1259. priv->host_port, ALE_VLAN, vid);
  1260. if (ret != 0)
  1261. goto clean_vid;
  1262. ret = cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
  1263. ALE_ALL_PORTS << priv->host_port,
  1264. ALE_VLAN, vid, 0);
  1265. if (ret != 0)
  1266. goto clean_vlan_ucast;
  1267. return 0;
  1268. clean_vlan_ucast:
  1269. cpsw_ale_del_ucast(priv->ale, priv->mac_addr,
  1270. priv->host_port, ALE_VLAN, vid);
  1271. clean_vid:
  1272. cpsw_ale_del_vlan(priv->ale, vid, 0);
  1273. return ret;
  1274. }
  1275. static int cpsw_ndo_vlan_rx_add_vid(struct net_device *ndev,
  1276. __be16 proto, u16 vid)
  1277. {
  1278. struct cpsw_priv *priv = netdev_priv(ndev);
  1279. if (vid == priv->data.default_vlan)
  1280. return 0;
  1281. dev_info(priv->dev, "Adding vlanid %d to vlan filter\n", vid);
  1282. return cpsw_add_vlan_ale_entry(priv, vid);
  1283. }
  1284. static int cpsw_ndo_vlan_rx_kill_vid(struct net_device *ndev,
  1285. __be16 proto, u16 vid)
  1286. {
  1287. struct cpsw_priv *priv = netdev_priv(ndev);
  1288. int ret;
  1289. if (vid == priv->data.default_vlan)
  1290. return 0;
  1291. dev_info(priv->dev, "removing vlanid %d from vlan filter\n", vid);
  1292. ret = cpsw_ale_del_vlan(priv->ale, vid, 0);
  1293. if (ret != 0)
  1294. return ret;
  1295. ret = cpsw_ale_del_ucast(priv->ale, priv->mac_addr,
  1296. priv->host_port, ALE_VLAN, vid);
  1297. if (ret != 0)
  1298. return ret;
  1299. return cpsw_ale_del_mcast(priv->ale, priv->ndev->broadcast,
  1300. 0, ALE_VLAN, vid);
  1301. }
  1302. static const struct net_device_ops cpsw_netdev_ops = {
  1303. .ndo_open = cpsw_ndo_open,
  1304. .ndo_stop = cpsw_ndo_stop,
  1305. .ndo_start_xmit = cpsw_ndo_start_xmit,
  1306. .ndo_change_rx_flags = cpsw_ndo_change_rx_flags,
  1307. .ndo_set_mac_address = cpsw_ndo_set_mac_address,
  1308. .ndo_do_ioctl = cpsw_ndo_ioctl,
  1309. .ndo_validate_addr = eth_validate_addr,
  1310. .ndo_change_mtu = eth_change_mtu,
  1311. .ndo_tx_timeout = cpsw_ndo_tx_timeout,
  1312. .ndo_get_stats = cpsw_ndo_get_stats,
  1313. .ndo_set_rx_mode = cpsw_ndo_set_rx_mode,
  1314. #ifdef CONFIG_NET_POLL_CONTROLLER
  1315. .ndo_poll_controller = cpsw_ndo_poll_controller,
  1316. #endif
  1317. .ndo_vlan_rx_add_vid = cpsw_ndo_vlan_rx_add_vid,
  1318. .ndo_vlan_rx_kill_vid = cpsw_ndo_vlan_rx_kill_vid,
  1319. };
  1320. static void cpsw_get_drvinfo(struct net_device *ndev,
  1321. struct ethtool_drvinfo *info)
  1322. {
  1323. struct cpsw_priv *priv = netdev_priv(ndev);
  1324. strlcpy(info->driver, "TI CPSW Driver v1.0", sizeof(info->driver));
  1325. strlcpy(info->version, "1.0", sizeof(info->version));
  1326. strlcpy(info->bus_info, priv->pdev->name, sizeof(info->bus_info));
  1327. }
  1328. static u32 cpsw_get_msglevel(struct net_device *ndev)
  1329. {
  1330. struct cpsw_priv *priv = netdev_priv(ndev);
  1331. return priv->msg_enable;
  1332. }
  1333. static void cpsw_set_msglevel(struct net_device *ndev, u32 value)
  1334. {
  1335. struct cpsw_priv *priv = netdev_priv(ndev);
  1336. priv->msg_enable = value;
  1337. }
  1338. static int cpsw_get_ts_info(struct net_device *ndev,
  1339. struct ethtool_ts_info *info)
  1340. {
  1341. #ifdef CONFIG_TI_CPTS
  1342. struct cpsw_priv *priv = netdev_priv(ndev);
  1343. info->so_timestamping =
  1344. SOF_TIMESTAMPING_TX_HARDWARE |
  1345. SOF_TIMESTAMPING_TX_SOFTWARE |
  1346. SOF_TIMESTAMPING_RX_HARDWARE |
  1347. SOF_TIMESTAMPING_RX_SOFTWARE |
  1348. SOF_TIMESTAMPING_SOFTWARE |
  1349. SOF_TIMESTAMPING_RAW_HARDWARE;
  1350. info->phc_index = priv->cpts->phc_index;
  1351. info->tx_types =
  1352. (1 << HWTSTAMP_TX_OFF) |
  1353. (1 << HWTSTAMP_TX_ON);
  1354. info->rx_filters =
  1355. (1 << HWTSTAMP_FILTER_NONE) |
  1356. (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
  1357. #else
  1358. info->so_timestamping =
  1359. SOF_TIMESTAMPING_TX_SOFTWARE |
  1360. SOF_TIMESTAMPING_RX_SOFTWARE |
  1361. SOF_TIMESTAMPING_SOFTWARE;
  1362. info->phc_index = -1;
  1363. info->tx_types = 0;
  1364. info->rx_filters = 0;
  1365. #endif
  1366. return 0;
  1367. }
  1368. static int cpsw_get_settings(struct net_device *ndev,
  1369. struct ethtool_cmd *ecmd)
  1370. {
  1371. struct cpsw_priv *priv = netdev_priv(ndev);
  1372. int slave_no = cpsw_slave_index(priv);
  1373. if (priv->slaves[slave_no].phy)
  1374. return phy_ethtool_gset(priv->slaves[slave_no].phy, ecmd);
  1375. else
  1376. return -EOPNOTSUPP;
  1377. }
  1378. static int cpsw_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
  1379. {
  1380. struct cpsw_priv *priv = netdev_priv(ndev);
  1381. int slave_no = cpsw_slave_index(priv);
  1382. if (priv->slaves[slave_no].phy)
  1383. return phy_ethtool_sset(priv->slaves[slave_no].phy, ecmd);
  1384. else
  1385. return -EOPNOTSUPP;
  1386. }
  1387. static void cpsw_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
  1388. {
  1389. struct cpsw_priv *priv = netdev_priv(ndev);
  1390. int slave_no = cpsw_slave_index(priv);
  1391. wol->supported = 0;
  1392. wol->wolopts = 0;
  1393. if (priv->slaves[slave_no].phy)
  1394. phy_ethtool_get_wol(priv->slaves[slave_no].phy, wol);
  1395. }
  1396. static int cpsw_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
  1397. {
  1398. struct cpsw_priv *priv = netdev_priv(ndev);
  1399. int slave_no = cpsw_slave_index(priv);
  1400. if (priv->slaves[slave_no].phy)
  1401. return phy_ethtool_set_wol(priv->slaves[slave_no].phy, wol);
  1402. else
  1403. return -EOPNOTSUPP;
  1404. }
  1405. static const struct ethtool_ops cpsw_ethtool_ops = {
  1406. .get_drvinfo = cpsw_get_drvinfo,
  1407. .get_msglevel = cpsw_get_msglevel,
  1408. .set_msglevel = cpsw_set_msglevel,
  1409. .get_link = ethtool_op_get_link,
  1410. .get_ts_info = cpsw_get_ts_info,
  1411. .get_settings = cpsw_get_settings,
  1412. .set_settings = cpsw_set_settings,
  1413. .get_coalesce = cpsw_get_coalesce,
  1414. .set_coalesce = cpsw_set_coalesce,
  1415. .get_sset_count = cpsw_get_sset_count,
  1416. .get_strings = cpsw_get_strings,
  1417. .get_ethtool_stats = cpsw_get_ethtool_stats,
  1418. .get_wol = cpsw_get_wol,
  1419. .set_wol = cpsw_set_wol,
  1420. };
  1421. static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv,
  1422. u32 slave_reg_ofs, u32 sliver_reg_ofs)
  1423. {
  1424. void __iomem *regs = priv->regs;
  1425. int slave_num = slave->slave_num;
  1426. struct cpsw_slave_data *data = priv->data.slave_data + slave_num;
  1427. slave->data = data;
  1428. slave->regs = regs + slave_reg_ofs;
  1429. slave->sliver = regs + sliver_reg_ofs;
  1430. slave->port_vlan = data->dual_emac_res_vlan;
  1431. }
  1432. static int cpsw_probe_dt(struct cpsw_platform_data *data,
  1433. struct platform_device *pdev)
  1434. {
  1435. struct device_node *node = pdev->dev.of_node;
  1436. struct device_node *slave_node;
  1437. int i = 0, ret;
  1438. u32 prop;
  1439. if (!node)
  1440. return -EINVAL;
  1441. if (of_property_read_u32(node, "slaves", &prop)) {
  1442. pr_err("Missing slaves property in the DT.\n");
  1443. return -EINVAL;
  1444. }
  1445. data->slaves = prop;
  1446. if (of_property_read_u32(node, "active_slave", &prop)) {
  1447. pr_err("Missing active_slave property in the DT.\n");
  1448. ret = -EINVAL;
  1449. goto error_ret;
  1450. }
  1451. data->active_slave = prop;
  1452. if (of_property_read_u32(node, "cpts_clock_mult", &prop)) {
  1453. pr_err("Missing cpts_clock_mult property in the DT.\n");
  1454. ret = -EINVAL;
  1455. goto error_ret;
  1456. }
  1457. data->cpts_clock_mult = prop;
  1458. if (of_property_read_u32(node, "cpts_clock_shift", &prop)) {
  1459. pr_err("Missing cpts_clock_shift property in the DT.\n");
  1460. ret = -EINVAL;
  1461. goto error_ret;
  1462. }
  1463. data->cpts_clock_shift = prop;
  1464. data->slave_data = kcalloc(data->slaves, sizeof(struct cpsw_slave_data),
  1465. GFP_KERNEL);
  1466. if (!data->slave_data)
  1467. return -EINVAL;
  1468. if (of_property_read_u32(node, "cpdma_channels", &prop)) {
  1469. pr_err("Missing cpdma_channels property in the DT.\n");
  1470. ret = -EINVAL;
  1471. goto error_ret;
  1472. }
  1473. data->channels = prop;
  1474. if (of_property_read_u32(node, "ale_entries", &prop)) {
  1475. pr_err("Missing ale_entries property in the DT.\n");
  1476. ret = -EINVAL;
  1477. goto error_ret;
  1478. }
  1479. data->ale_entries = prop;
  1480. if (of_property_read_u32(node, "bd_ram_size", &prop)) {
  1481. pr_err("Missing bd_ram_size property in the DT.\n");
  1482. ret = -EINVAL;
  1483. goto error_ret;
  1484. }
  1485. data->bd_ram_size = prop;
  1486. if (of_property_read_u32(node, "rx_descs", &prop)) {
  1487. pr_err("Missing rx_descs property in the DT.\n");
  1488. ret = -EINVAL;
  1489. goto error_ret;
  1490. }
  1491. data->rx_descs = prop;
  1492. if (of_property_read_u32(node, "mac_control", &prop)) {
  1493. pr_err("Missing mac_control property in the DT.\n");
  1494. ret = -EINVAL;
  1495. goto error_ret;
  1496. }
  1497. data->mac_control = prop;
  1498. if (of_property_read_bool(node, "dual_emac"))
  1499. data->dual_emac = 1;
  1500. /*
  1501. * Populate all the child nodes here...
  1502. */
  1503. ret = of_platform_populate(node, NULL, NULL, &pdev->dev);
  1504. /* We do not want to force this, as in some cases may not have child */
  1505. if (ret)
  1506. pr_warn("Doesn't have any child node\n");
  1507. for_each_child_of_node(node, slave_node) {
  1508. struct cpsw_slave_data *slave_data = data->slave_data + i;
  1509. const void *mac_addr = NULL;
  1510. u32 phyid;
  1511. int lenp;
  1512. const __be32 *parp;
  1513. struct device_node *mdio_node;
  1514. struct platform_device *mdio;
  1515. /* This is no slave child node, continue */
  1516. if (strcmp(slave_node->name, "slave"))
  1517. continue;
  1518. parp = of_get_property(slave_node, "phy_id", &lenp);
  1519. if ((parp == NULL) || (lenp != (sizeof(void *) * 2))) {
  1520. pr_err("Missing slave[%d] phy_id property\n", i);
  1521. ret = -EINVAL;
  1522. goto error_ret;
  1523. }
  1524. mdio_node = of_find_node_by_phandle(be32_to_cpup(parp));
  1525. phyid = be32_to_cpup(parp+1);
  1526. mdio = of_find_device_by_node(mdio_node);
  1527. snprintf(slave_data->phy_id, sizeof(slave_data->phy_id),
  1528. PHY_ID_FMT, mdio->name, phyid);
  1529. mac_addr = of_get_mac_address(slave_node);
  1530. if (mac_addr)
  1531. memcpy(slave_data->mac_addr, mac_addr, ETH_ALEN);
  1532. slave_data->phy_if = of_get_phy_mode(slave_node);
  1533. if (data->dual_emac) {
  1534. if (of_property_read_u32(slave_node, "dual_emac_res_vlan",
  1535. &prop)) {
  1536. pr_err("Missing dual_emac_res_vlan in DT.\n");
  1537. slave_data->dual_emac_res_vlan = i+1;
  1538. pr_err("Using %d as Reserved VLAN for %d slave\n",
  1539. slave_data->dual_emac_res_vlan, i);
  1540. } else {
  1541. slave_data->dual_emac_res_vlan = prop;
  1542. }
  1543. }
  1544. i++;
  1545. }
  1546. return 0;
  1547. error_ret:
  1548. kfree(data->slave_data);
  1549. return ret;
  1550. }
  1551. static int cpsw_probe_dual_emac(struct platform_device *pdev,
  1552. struct cpsw_priv *priv)
  1553. {
  1554. struct cpsw_platform_data *data = &priv->data;
  1555. struct net_device *ndev;
  1556. struct cpsw_priv *priv_sl2;
  1557. int ret = 0, i;
  1558. ndev = alloc_etherdev(sizeof(struct cpsw_priv));
  1559. if (!ndev) {
  1560. pr_err("cpsw: error allocating net_device\n");
  1561. return -ENOMEM;
  1562. }
  1563. priv_sl2 = netdev_priv(ndev);
  1564. spin_lock_init(&priv_sl2->lock);
  1565. priv_sl2->data = *data;
  1566. priv_sl2->pdev = pdev;
  1567. priv_sl2->ndev = ndev;
  1568. priv_sl2->dev = &ndev->dev;
  1569. priv_sl2->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
  1570. priv_sl2->rx_packet_max = max(rx_packet_max, 128);
  1571. if (is_valid_ether_addr(data->slave_data[1].mac_addr)) {
  1572. memcpy(priv_sl2->mac_addr, data->slave_data[1].mac_addr,
  1573. ETH_ALEN);
  1574. pr_info("cpsw: Detected MACID = %pM\n", priv_sl2->mac_addr);
  1575. } else {
  1576. random_ether_addr(priv_sl2->mac_addr);
  1577. pr_info("cpsw: Random MACID = %pM\n", priv_sl2->mac_addr);
  1578. }
  1579. memcpy(ndev->dev_addr, priv_sl2->mac_addr, ETH_ALEN);
  1580. priv_sl2->slaves = priv->slaves;
  1581. priv_sl2->clk = priv->clk;
  1582. priv_sl2->coal_intvl = 0;
  1583. priv_sl2->bus_freq_mhz = priv->bus_freq_mhz;
  1584. priv_sl2->cpsw_res = priv->cpsw_res;
  1585. priv_sl2->regs = priv->regs;
  1586. priv_sl2->host_port = priv->host_port;
  1587. priv_sl2->host_port_regs = priv->host_port_regs;
  1588. priv_sl2->wr_regs = priv->wr_regs;
  1589. priv_sl2->hw_stats = priv->hw_stats;
  1590. priv_sl2->dma = priv->dma;
  1591. priv_sl2->txch = priv->txch;
  1592. priv_sl2->rxch = priv->rxch;
  1593. priv_sl2->ale = priv->ale;
  1594. priv_sl2->emac_port = 1;
  1595. priv->slaves[1].ndev = ndev;
  1596. priv_sl2->cpts = priv->cpts;
  1597. priv_sl2->version = priv->version;
  1598. for (i = 0; i < priv->num_irqs; i++) {
  1599. priv_sl2->irqs_table[i] = priv->irqs_table[i];
  1600. priv_sl2->num_irqs = priv->num_irqs;
  1601. }
  1602. ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
  1603. ndev->netdev_ops = &cpsw_netdev_ops;
  1604. SET_ETHTOOL_OPS(ndev, &cpsw_ethtool_ops);
  1605. netif_napi_add(ndev, &priv_sl2->napi, cpsw_poll, CPSW_POLL_WEIGHT);
  1606. /* register the network device */
  1607. SET_NETDEV_DEV(ndev, &pdev->dev);
  1608. ret = register_netdev(ndev);
  1609. if (ret) {
  1610. pr_err("cpsw: error registering net device\n");
  1611. free_netdev(ndev);
  1612. ret = -ENODEV;
  1613. }
  1614. return ret;
  1615. }
  1616. static int cpsw_probe(struct platform_device *pdev)
  1617. {
  1618. struct cpsw_platform_data *data;
  1619. struct net_device *ndev;
  1620. struct cpsw_priv *priv;
  1621. struct cpdma_params dma_params;
  1622. struct cpsw_ale_params ale_params;
  1623. void __iomem *ss_regs, *wr_regs;
  1624. struct resource *res;
  1625. u32 slave_offset, sliver_offset, slave_size;
  1626. int ret = 0, i, k = 0;
  1627. ndev = alloc_etherdev(sizeof(struct cpsw_priv));
  1628. if (!ndev) {
  1629. pr_err("error allocating net_device\n");
  1630. return -ENOMEM;
  1631. }
  1632. platform_set_drvdata(pdev, ndev);
  1633. priv = netdev_priv(ndev);
  1634. spin_lock_init(&priv->lock);
  1635. priv->pdev = pdev;
  1636. priv->ndev = ndev;
  1637. priv->dev = &ndev->dev;
  1638. priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
  1639. priv->rx_packet_max = max(rx_packet_max, 128);
  1640. priv->cpts = devm_kzalloc(&pdev->dev, sizeof(struct cpts), GFP_KERNEL);
  1641. priv->irq_enabled = true;
  1642. if (!priv->cpts) {
  1643. pr_err("error allocating cpts\n");
  1644. goto clean_ndev_ret;
  1645. }
  1646. /*
  1647. * This may be required here for child devices.
  1648. */
  1649. pm_runtime_enable(&pdev->dev);
  1650. /* Select default pin state */
  1651. pinctrl_pm_select_default_state(&pdev->dev);
  1652. if (cpsw_probe_dt(&priv->data, pdev)) {
  1653. pr_err("cpsw: platform data missing\n");
  1654. ret = -ENODEV;
  1655. goto clean_ndev_ret;
  1656. }
  1657. data = &priv->data;
  1658. if (is_valid_ether_addr(data->slave_data[0].mac_addr)) {
  1659. memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN);
  1660. pr_info("Detected MACID = %pM\n", priv->mac_addr);
  1661. } else {
  1662. eth_random_addr(priv->mac_addr);
  1663. pr_info("Random MACID = %pM\n", priv->mac_addr);
  1664. }
  1665. memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
  1666. priv->slaves = kzalloc(sizeof(struct cpsw_slave) * data->slaves,
  1667. GFP_KERNEL);
  1668. if (!priv->slaves) {
  1669. ret = -EBUSY;
  1670. goto clean_ndev_ret;
  1671. }
  1672. for (i = 0; i < data->slaves; i++)
  1673. priv->slaves[i].slave_num = i;
  1674. priv->slaves[0].ndev = ndev;
  1675. priv->emac_port = 0;
  1676. priv->clk = clk_get(&pdev->dev, "fck");
  1677. if (IS_ERR(priv->clk)) {
  1678. dev_err(&pdev->dev, "fck is not found\n");
  1679. ret = -ENODEV;
  1680. goto clean_slave_ret;
  1681. }
  1682. priv->coal_intvl = 0;
  1683. priv->bus_freq_mhz = clk_get_rate(priv->clk) / 1000000;
  1684. priv->cpsw_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1685. if (!priv->cpsw_res) {
  1686. dev_err(priv->dev, "error getting i/o resource\n");
  1687. ret = -ENOENT;
  1688. goto clean_clk_ret;
  1689. }
  1690. if (!request_mem_region(priv->cpsw_res->start,
  1691. resource_size(priv->cpsw_res), ndev->name)) {
  1692. dev_err(priv->dev, "failed request i/o region\n");
  1693. ret = -ENXIO;
  1694. goto clean_clk_ret;
  1695. }
  1696. ss_regs = ioremap(priv->cpsw_res->start, resource_size(priv->cpsw_res));
  1697. if (!ss_regs) {
  1698. dev_err(priv->dev, "unable to map i/o region\n");
  1699. goto clean_cpsw_iores_ret;
  1700. }
  1701. priv->regs = ss_regs;
  1702. priv->version = __raw_readl(&priv->regs->id_ver);
  1703. priv->host_port = HOST_PORT_NUM;
  1704. priv->cpsw_wr_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
  1705. if (!priv->cpsw_wr_res) {
  1706. dev_err(priv->dev, "error getting i/o resource\n");
  1707. ret = -ENOENT;
  1708. goto clean_iomap_ret;
  1709. }
  1710. if (!request_mem_region(priv->cpsw_wr_res->start,
  1711. resource_size(priv->cpsw_wr_res), ndev->name)) {
  1712. dev_err(priv->dev, "failed request i/o region\n");
  1713. ret = -ENXIO;
  1714. goto clean_iomap_ret;
  1715. }
  1716. wr_regs = ioremap(priv->cpsw_wr_res->start,
  1717. resource_size(priv->cpsw_wr_res));
  1718. if (!wr_regs) {
  1719. dev_err(priv->dev, "unable to map i/o region\n");
  1720. goto clean_cpsw_wr_iores_ret;
  1721. }
  1722. priv->wr_regs = wr_regs;
  1723. memset(&dma_params, 0, sizeof(dma_params));
  1724. memset(&ale_params, 0, sizeof(ale_params));
  1725. switch (priv->version) {
  1726. case CPSW_VERSION_1:
  1727. priv->host_port_regs = ss_regs + CPSW1_HOST_PORT_OFFSET;
  1728. priv->cpts->reg = ss_regs + CPSW1_CPTS_OFFSET;
  1729. priv->hw_stats = ss_regs + CPSW1_HW_STATS;
  1730. dma_params.dmaregs = ss_regs + CPSW1_CPDMA_OFFSET;
  1731. dma_params.txhdp = ss_regs + CPSW1_STATERAM_OFFSET;
  1732. ale_params.ale_regs = ss_regs + CPSW1_ALE_OFFSET;
  1733. slave_offset = CPSW1_SLAVE_OFFSET;
  1734. slave_size = CPSW1_SLAVE_SIZE;
  1735. sliver_offset = CPSW1_SLIVER_OFFSET;
  1736. dma_params.desc_mem_phys = 0;
  1737. break;
  1738. case CPSW_VERSION_2:
  1739. case CPSW_VERSION_3:
  1740. case CPSW_VERSION_4:
  1741. priv->host_port_regs = ss_regs + CPSW2_HOST_PORT_OFFSET;
  1742. priv->cpts->reg = ss_regs + CPSW2_CPTS_OFFSET;
  1743. priv->hw_stats = ss_regs + CPSW2_HW_STATS;
  1744. dma_params.dmaregs = ss_regs + CPSW2_CPDMA_OFFSET;
  1745. dma_params.txhdp = ss_regs + CPSW2_STATERAM_OFFSET;
  1746. ale_params.ale_regs = ss_regs + CPSW2_ALE_OFFSET;
  1747. slave_offset = CPSW2_SLAVE_OFFSET;
  1748. slave_size = CPSW2_SLAVE_SIZE;
  1749. sliver_offset = CPSW2_SLIVER_OFFSET;
  1750. dma_params.desc_mem_phys =
  1751. (u32 __force) priv->cpsw_res->start + CPSW2_BD_OFFSET;
  1752. break;
  1753. default:
  1754. dev_err(priv->dev, "unknown version 0x%08x\n", priv->version);
  1755. ret = -ENODEV;
  1756. goto clean_cpsw_wr_iores_ret;
  1757. }
  1758. for (i = 0; i < priv->data.slaves; i++) {
  1759. struct cpsw_slave *slave = &priv->slaves[i];
  1760. cpsw_slave_init(slave, priv, slave_offset, sliver_offset);
  1761. slave_offset += slave_size;
  1762. sliver_offset += SLIVER_SIZE;
  1763. }
  1764. dma_params.dev = &pdev->dev;
  1765. dma_params.rxthresh = dma_params.dmaregs + CPDMA_RXTHRESH;
  1766. dma_params.rxfree = dma_params.dmaregs + CPDMA_RXFREE;
  1767. dma_params.rxhdp = dma_params.txhdp + CPDMA_RXHDP;
  1768. dma_params.txcp = dma_params.txhdp + CPDMA_TXCP;
  1769. dma_params.rxcp = dma_params.txhdp + CPDMA_RXCP;
  1770. dma_params.num_chan = data->channels;
  1771. dma_params.has_soft_reset = true;
  1772. dma_params.min_packet_size = CPSW_MIN_PACKET_SIZE;
  1773. dma_params.desc_mem_size = data->bd_ram_size;
  1774. dma_params.desc_align = 16;
  1775. dma_params.has_ext_regs = true;
  1776. dma_params.desc_hw_addr = dma_params.desc_mem_phys;
  1777. priv->dma = cpdma_ctlr_create(&dma_params);
  1778. if (!priv->dma) {
  1779. dev_err(priv->dev, "error initializing dma\n");
  1780. ret = -ENOMEM;
  1781. goto clean_wr_iomap_ret;
  1782. }
  1783. priv->txch = cpdma_chan_create(priv->dma, tx_chan_num(0),
  1784. cpsw_tx_handler);
  1785. priv->rxch = cpdma_chan_create(priv->dma, rx_chan_num(0),
  1786. cpsw_rx_handler);
  1787. if (WARN_ON(!priv->txch || !priv->rxch)) {
  1788. dev_err(priv->dev, "error initializing dma channels\n");
  1789. ret = -ENOMEM;
  1790. goto clean_dma_ret;
  1791. }
  1792. ale_params.dev = &ndev->dev;
  1793. ale_params.ale_ageout = ale_ageout;
  1794. ale_params.ale_entries = data->ale_entries;
  1795. ale_params.ale_ports = data->slaves;
  1796. priv->ale = cpsw_ale_create(&ale_params);
  1797. if (!priv->ale) {
  1798. dev_err(priv->dev, "error initializing ale engine\n");
  1799. ret = -ENODEV;
  1800. goto clean_dma_ret;
  1801. }
  1802. ndev->irq = platform_get_irq(pdev, 0);
  1803. if (ndev->irq < 0) {
  1804. dev_err(priv->dev, "error getting irq resource\n");
  1805. ret = -ENOENT;
  1806. goto clean_ale_ret;
  1807. }
  1808. while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, k))) {
  1809. for (i = res->start; i <= res->end; i++) {
  1810. if (request_irq(i, cpsw_interrupt, 0,
  1811. dev_name(&pdev->dev), priv)) {
  1812. dev_err(priv->dev, "error attaching irq\n");
  1813. goto clean_ale_ret;
  1814. }
  1815. priv->irqs_table[k] = i;
  1816. priv->num_irqs = k + 1;
  1817. }
  1818. k++;
  1819. }
  1820. ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
  1821. ndev->netdev_ops = &cpsw_netdev_ops;
  1822. SET_ETHTOOL_OPS(ndev, &cpsw_ethtool_ops);
  1823. netif_napi_add(ndev, &priv->napi, cpsw_poll, CPSW_POLL_WEIGHT);
  1824. /* register the network device */
  1825. SET_NETDEV_DEV(ndev, &pdev->dev);
  1826. ret = register_netdev(ndev);
  1827. if (ret) {
  1828. dev_err(priv->dev, "error registering net device\n");
  1829. ret = -ENODEV;
  1830. goto clean_irq_ret;
  1831. }
  1832. if (cpts_register(&pdev->dev, priv->cpts,
  1833. data->cpts_clock_mult, data->cpts_clock_shift))
  1834. dev_err(priv->dev, "error registering cpts device\n");
  1835. cpsw_notice(priv, probe, "initialized device (regs %x, irq %d)\n",
  1836. priv->cpsw_res->start, ndev->irq);
  1837. if (priv->data.dual_emac) {
  1838. ret = cpsw_probe_dual_emac(pdev, priv);
  1839. if (ret) {
  1840. cpsw_err(priv, probe, "error probe slave 2 emac interface\n");
  1841. goto clean_irq_ret;
  1842. }
  1843. }
  1844. return 0;
  1845. clean_irq_ret:
  1846. for (i = 0; i < priv->num_irqs; i++)
  1847. free_irq(priv->irqs_table[i], priv);
  1848. clean_ale_ret:
  1849. cpsw_ale_destroy(priv->ale);
  1850. clean_dma_ret:
  1851. cpdma_chan_destroy(priv->txch);
  1852. cpdma_chan_destroy(priv->rxch);
  1853. cpdma_ctlr_destroy(priv->dma);
  1854. clean_wr_iomap_ret:
  1855. iounmap(priv->wr_regs);
  1856. clean_cpsw_wr_iores_ret:
  1857. release_mem_region(priv->cpsw_wr_res->start,
  1858. resource_size(priv->cpsw_wr_res));
  1859. clean_iomap_ret:
  1860. iounmap(priv->regs);
  1861. clean_cpsw_iores_ret:
  1862. release_mem_region(priv->cpsw_res->start,
  1863. resource_size(priv->cpsw_res));
  1864. clean_clk_ret:
  1865. clk_put(priv->clk);
  1866. clean_slave_ret:
  1867. pm_runtime_disable(&pdev->dev);
  1868. kfree(priv->slaves);
  1869. clean_ndev_ret:
  1870. kfree(priv->data.slave_data);
  1871. free_netdev(priv->ndev);
  1872. return ret;
  1873. }
  1874. static int cpsw_remove(struct platform_device *pdev)
  1875. {
  1876. struct net_device *ndev = platform_get_drvdata(pdev);
  1877. struct cpsw_priv *priv = netdev_priv(ndev);
  1878. int i;
  1879. if (priv->data.dual_emac)
  1880. unregister_netdev(cpsw_get_slave_ndev(priv, 1));
  1881. unregister_netdev(ndev);
  1882. cpts_unregister(priv->cpts);
  1883. for (i = 0; i < priv->num_irqs; i++)
  1884. free_irq(priv->irqs_table[i], priv);
  1885. cpsw_ale_destroy(priv->ale);
  1886. cpdma_chan_destroy(priv->txch);
  1887. cpdma_chan_destroy(priv->rxch);
  1888. cpdma_ctlr_destroy(priv->dma);
  1889. iounmap(priv->regs);
  1890. release_mem_region(priv->cpsw_res->start,
  1891. resource_size(priv->cpsw_res));
  1892. iounmap(priv->wr_regs);
  1893. release_mem_region(priv->cpsw_wr_res->start,
  1894. resource_size(priv->cpsw_wr_res));
  1895. pm_runtime_disable(&pdev->dev);
  1896. clk_put(priv->clk);
  1897. kfree(priv->slaves);
  1898. kfree(priv->data.slave_data);
  1899. if (priv->data.dual_emac)
  1900. free_netdev(cpsw_get_slave_ndev(priv, 1));
  1901. free_netdev(ndev);
  1902. return 0;
  1903. }
  1904. static int cpsw_suspend(struct device *dev)
  1905. {
  1906. struct platform_device *pdev = to_platform_device(dev);
  1907. struct net_device *ndev = platform_get_drvdata(pdev);
  1908. struct cpsw_priv *priv = netdev_priv(ndev);
  1909. if (netif_running(ndev))
  1910. cpsw_ndo_stop(ndev);
  1911. soft_reset("sliver 0", &priv->slaves[0].sliver->soft_reset);
  1912. soft_reset("sliver 1", &priv->slaves[1].sliver->soft_reset);
  1913. pm_runtime_put_sync(&pdev->dev);
  1914. /* Select sleep pin state */
  1915. pinctrl_pm_select_sleep_state(&pdev->dev);
  1916. return 0;
  1917. }
  1918. static int cpsw_resume(struct device *dev)
  1919. {
  1920. struct platform_device *pdev = to_platform_device(dev);
  1921. struct net_device *ndev = platform_get_drvdata(pdev);
  1922. pm_runtime_get_sync(&pdev->dev);
  1923. /* Select default pin state */
  1924. pinctrl_pm_select_default_state(&pdev->dev);
  1925. if (netif_running(ndev))
  1926. cpsw_ndo_open(ndev);
  1927. return 0;
  1928. }
  1929. static const struct dev_pm_ops cpsw_pm_ops = {
  1930. .suspend = cpsw_suspend,
  1931. .resume = cpsw_resume,
  1932. };
  1933. static const struct of_device_id cpsw_of_mtable[] = {
  1934. { .compatible = "ti,cpsw", },
  1935. { /* sentinel */ },
  1936. };
  1937. MODULE_DEVICE_TABLE(of, cpsw_of_mtable);
  1938. static struct platform_driver cpsw_driver = {
  1939. .driver = {
  1940. .name = "cpsw",
  1941. .owner = THIS_MODULE,
  1942. .pm = &cpsw_pm_ops,
  1943. .of_match_table = of_match_ptr(cpsw_of_mtable),
  1944. },
  1945. .probe = cpsw_probe,
  1946. .remove = cpsw_remove,
  1947. };
  1948. static int __init cpsw_init(void)
  1949. {
  1950. return platform_driver_register(&cpsw_driver);
  1951. }
  1952. late_initcall(cpsw_init);
  1953. static void __exit cpsw_exit(void)
  1954. {
  1955. platform_driver_unregister(&cpsw_driver);
  1956. }
  1957. module_exit(cpsw_exit);
  1958. MODULE_LICENSE("GPL");
  1959. MODULE_AUTHOR("Cyril Chemparathy <cyril@ti.com>");
  1960. MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>");
  1961. MODULE_DESCRIPTION("TI CPSW Ethernet driver");