r8169.c 174 KB

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  1. /*
  2. * r8169.c: RealTek 8169/8168/8101 ethernet driver.
  3. *
  4. * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
  5. * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
  6. * Copyright (c) a lot of people too. Please respect their work.
  7. *
  8. * See MAINTAINERS file for support contact information.
  9. */
  10. #include <linux/module.h>
  11. #include <linux/moduleparam.h>
  12. #include <linux/pci.h>
  13. #include <linux/netdevice.h>
  14. #include <linux/etherdevice.h>
  15. #include <linux/delay.h>
  16. #include <linux/ethtool.h>
  17. #include <linux/mii.h>
  18. #include <linux/if_vlan.h>
  19. #include <linux/crc32.h>
  20. #include <linux/in.h>
  21. #include <linux/ip.h>
  22. #include <linux/tcp.h>
  23. #include <linux/init.h>
  24. #include <linux/interrupt.h>
  25. #include <linux/dma-mapping.h>
  26. #include <linux/pm_runtime.h>
  27. #include <linux/firmware.h>
  28. #include <linux/pci-aspm.h>
  29. #include <linux/prefetch.h>
  30. #include <asm/io.h>
  31. #include <asm/irq.h>
  32. #define RTL8169_VERSION "2.3LK-NAPI"
  33. #define MODULENAME "r8169"
  34. #define PFX MODULENAME ": "
  35. #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
  36. #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
  37. #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
  38. #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
  39. #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
  40. #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
  41. #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
  42. #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
  43. #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw"
  44. #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw"
  45. #define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw"
  46. #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw"
  47. #define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw"
  48. #define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw"
  49. #define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw"
  50. #ifdef RTL8169_DEBUG
  51. #define assert(expr) \
  52. if (!(expr)) { \
  53. printk( "Assertion failed! %s,%s,%s,line=%d\n", \
  54. #expr,__FILE__,__func__,__LINE__); \
  55. }
  56. #define dprintk(fmt, args...) \
  57. do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
  58. #else
  59. #define assert(expr) do {} while (0)
  60. #define dprintk(fmt, args...) do {} while (0)
  61. #endif /* RTL8169_DEBUG */
  62. #define R8169_MSG_DEFAULT \
  63. (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
  64. #define TX_SLOTS_AVAIL(tp) \
  65. (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
  66. /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
  67. #define TX_FRAGS_READY_FOR(tp,nr_frags) \
  68. (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
  69. /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  70. The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  71. static const int multicast_filter_limit = 32;
  72. #define MAX_READ_REQUEST_SHIFT 12
  73. #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */
  74. #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
  75. #define R8169_REGS_SIZE 256
  76. #define R8169_NAPI_WEIGHT 64
  77. #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
  78. #define NUM_RX_DESC 256U /* Number of Rx descriptor registers */
  79. #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
  80. #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
  81. #define RTL8169_TX_TIMEOUT (6*HZ)
  82. #define RTL8169_PHY_TIMEOUT (10*HZ)
  83. /* write/read MMIO register */
  84. #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
  85. #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
  86. #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
  87. #define RTL_R8(reg) readb (ioaddr + (reg))
  88. #define RTL_R16(reg) readw (ioaddr + (reg))
  89. #define RTL_R32(reg) readl (ioaddr + (reg))
  90. enum mac_version {
  91. RTL_GIGA_MAC_VER_01 = 0,
  92. RTL_GIGA_MAC_VER_02,
  93. RTL_GIGA_MAC_VER_03,
  94. RTL_GIGA_MAC_VER_04,
  95. RTL_GIGA_MAC_VER_05,
  96. RTL_GIGA_MAC_VER_06,
  97. RTL_GIGA_MAC_VER_07,
  98. RTL_GIGA_MAC_VER_08,
  99. RTL_GIGA_MAC_VER_09,
  100. RTL_GIGA_MAC_VER_10,
  101. RTL_GIGA_MAC_VER_11,
  102. RTL_GIGA_MAC_VER_12,
  103. RTL_GIGA_MAC_VER_13,
  104. RTL_GIGA_MAC_VER_14,
  105. RTL_GIGA_MAC_VER_15,
  106. RTL_GIGA_MAC_VER_16,
  107. RTL_GIGA_MAC_VER_17,
  108. RTL_GIGA_MAC_VER_18,
  109. RTL_GIGA_MAC_VER_19,
  110. RTL_GIGA_MAC_VER_20,
  111. RTL_GIGA_MAC_VER_21,
  112. RTL_GIGA_MAC_VER_22,
  113. RTL_GIGA_MAC_VER_23,
  114. RTL_GIGA_MAC_VER_24,
  115. RTL_GIGA_MAC_VER_25,
  116. RTL_GIGA_MAC_VER_26,
  117. RTL_GIGA_MAC_VER_27,
  118. RTL_GIGA_MAC_VER_28,
  119. RTL_GIGA_MAC_VER_29,
  120. RTL_GIGA_MAC_VER_30,
  121. RTL_GIGA_MAC_VER_31,
  122. RTL_GIGA_MAC_VER_32,
  123. RTL_GIGA_MAC_VER_33,
  124. RTL_GIGA_MAC_VER_34,
  125. RTL_GIGA_MAC_VER_35,
  126. RTL_GIGA_MAC_VER_36,
  127. RTL_GIGA_MAC_VER_37,
  128. RTL_GIGA_MAC_VER_38,
  129. RTL_GIGA_MAC_VER_39,
  130. RTL_GIGA_MAC_VER_40,
  131. RTL_GIGA_MAC_VER_41,
  132. RTL_GIGA_MAC_VER_42,
  133. RTL_GIGA_MAC_VER_43,
  134. RTL_GIGA_MAC_VER_44,
  135. RTL_GIGA_MAC_NONE = 0xff,
  136. };
  137. enum rtl_tx_desc_version {
  138. RTL_TD_0 = 0,
  139. RTL_TD_1 = 1,
  140. };
  141. #define JUMBO_1K ETH_DATA_LEN
  142. #define JUMBO_4K (4*1024 - ETH_HLEN - 2)
  143. #define JUMBO_6K (6*1024 - ETH_HLEN - 2)
  144. #define JUMBO_7K (7*1024 - ETH_HLEN - 2)
  145. #define JUMBO_9K (9*1024 - ETH_HLEN - 2)
  146. #define _R(NAME,TD,FW,SZ,B) { \
  147. .name = NAME, \
  148. .txd_version = TD, \
  149. .fw_name = FW, \
  150. .jumbo_max = SZ, \
  151. .jumbo_tx_csum = B \
  152. }
  153. static const struct {
  154. const char *name;
  155. enum rtl_tx_desc_version txd_version;
  156. const char *fw_name;
  157. u16 jumbo_max;
  158. bool jumbo_tx_csum;
  159. } rtl_chip_infos[] = {
  160. /* PCI devices. */
  161. [RTL_GIGA_MAC_VER_01] =
  162. _R("RTL8169", RTL_TD_0, NULL, JUMBO_7K, true),
  163. [RTL_GIGA_MAC_VER_02] =
  164. _R("RTL8169s", RTL_TD_0, NULL, JUMBO_7K, true),
  165. [RTL_GIGA_MAC_VER_03] =
  166. _R("RTL8110s", RTL_TD_0, NULL, JUMBO_7K, true),
  167. [RTL_GIGA_MAC_VER_04] =
  168. _R("RTL8169sb/8110sb", RTL_TD_0, NULL, JUMBO_7K, true),
  169. [RTL_GIGA_MAC_VER_05] =
  170. _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
  171. [RTL_GIGA_MAC_VER_06] =
  172. _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
  173. /* PCI-E devices. */
  174. [RTL_GIGA_MAC_VER_07] =
  175. _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
  176. [RTL_GIGA_MAC_VER_08] =
  177. _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
  178. [RTL_GIGA_MAC_VER_09] =
  179. _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
  180. [RTL_GIGA_MAC_VER_10] =
  181. _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
  182. [RTL_GIGA_MAC_VER_11] =
  183. _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
  184. [RTL_GIGA_MAC_VER_12] =
  185. _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
  186. [RTL_GIGA_MAC_VER_13] =
  187. _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
  188. [RTL_GIGA_MAC_VER_14] =
  189. _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
  190. [RTL_GIGA_MAC_VER_15] =
  191. _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
  192. [RTL_GIGA_MAC_VER_16] =
  193. _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
  194. [RTL_GIGA_MAC_VER_17] =
  195. _R("RTL8168b/8111b", RTL_TD_1, NULL, JUMBO_4K, false),
  196. [RTL_GIGA_MAC_VER_18] =
  197. _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
  198. [RTL_GIGA_MAC_VER_19] =
  199. _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
  200. [RTL_GIGA_MAC_VER_20] =
  201. _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
  202. [RTL_GIGA_MAC_VER_21] =
  203. _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
  204. [RTL_GIGA_MAC_VER_22] =
  205. _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
  206. [RTL_GIGA_MAC_VER_23] =
  207. _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
  208. [RTL_GIGA_MAC_VER_24] =
  209. _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
  210. [RTL_GIGA_MAC_VER_25] =
  211. _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_1,
  212. JUMBO_9K, false),
  213. [RTL_GIGA_MAC_VER_26] =
  214. _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_2,
  215. JUMBO_9K, false),
  216. [RTL_GIGA_MAC_VER_27] =
  217. _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
  218. [RTL_GIGA_MAC_VER_28] =
  219. _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
  220. [RTL_GIGA_MAC_VER_29] =
  221. _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
  222. JUMBO_1K, true),
  223. [RTL_GIGA_MAC_VER_30] =
  224. _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
  225. JUMBO_1K, true),
  226. [RTL_GIGA_MAC_VER_31] =
  227. _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
  228. [RTL_GIGA_MAC_VER_32] =
  229. _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_1,
  230. JUMBO_9K, false),
  231. [RTL_GIGA_MAC_VER_33] =
  232. _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_2,
  233. JUMBO_9K, false),
  234. [RTL_GIGA_MAC_VER_34] =
  235. _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3,
  236. JUMBO_9K, false),
  237. [RTL_GIGA_MAC_VER_35] =
  238. _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_1,
  239. JUMBO_9K, false),
  240. [RTL_GIGA_MAC_VER_36] =
  241. _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_2,
  242. JUMBO_9K, false),
  243. [RTL_GIGA_MAC_VER_37] =
  244. _R("RTL8402", RTL_TD_1, FIRMWARE_8402_1,
  245. JUMBO_1K, true),
  246. [RTL_GIGA_MAC_VER_38] =
  247. _R("RTL8411", RTL_TD_1, FIRMWARE_8411_1,
  248. JUMBO_9K, false),
  249. [RTL_GIGA_MAC_VER_39] =
  250. _R("RTL8106e", RTL_TD_1, FIRMWARE_8106E_1,
  251. JUMBO_1K, true),
  252. [RTL_GIGA_MAC_VER_40] =
  253. _R("RTL8168g/8111g", RTL_TD_1, FIRMWARE_8168G_2,
  254. JUMBO_9K, false),
  255. [RTL_GIGA_MAC_VER_41] =
  256. _R("RTL8168g/8111g", RTL_TD_1, NULL, JUMBO_9K, false),
  257. [RTL_GIGA_MAC_VER_42] =
  258. _R("RTL8168g/8111g", RTL_TD_1, FIRMWARE_8168G_3,
  259. JUMBO_9K, false),
  260. [RTL_GIGA_MAC_VER_43] =
  261. _R("RTL8106e", RTL_TD_1, FIRMWARE_8106E_2,
  262. JUMBO_1K, true),
  263. [RTL_GIGA_MAC_VER_44] =
  264. _R("RTL8411", RTL_TD_1, FIRMWARE_8411_2,
  265. JUMBO_9K, false),
  266. };
  267. #undef _R
  268. enum cfg_version {
  269. RTL_CFG_0 = 0x00,
  270. RTL_CFG_1,
  271. RTL_CFG_2
  272. };
  273. static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
  274. { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
  275. { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
  276. { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
  277. { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
  278. { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
  279. { PCI_VENDOR_ID_DLINK, 0x4300,
  280. PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0, RTL_CFG_1 },
  281. { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
  282. { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302), 0, 0, RTL_CFG_0 },
  283. { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
  284. { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
  285. { PCI_VENDOR_ID_LINKSYS, 0x1032,
  286. PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
  287. { 0x0001, 0x8168,
  288. PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
  289. {0,},
  290. };
  291. MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
  292. static int rx_buf_sz = 16383;
  293. static int use_dac;
  294. static struct {
  295. u32 msg_enable;
  296. } debug = { -1 };
  297. enum rtl_registers {
  298. MAC0 = 0, /* Ethernet hardware address. */
  299. MAC4 = 4,
  300. MAR0 = 8, /* Multicast filter. */
  301. CounterAddrLow = 0x10,
  302. CounterAddrHigh = 0x14,
  303. TxDescStartAddrLow = 0x20,
  304. TxDescStartAddrHigh = 0x24,
  305. TxHDescStartAddrLow = 0x28,
  306. TxHDescStartAddrHigh = 0x2c,
  307. FLASH = 0x30,
  308. ERSR = 0x36,
  309. ChipCmd = 0x37,
  310. TxPoll = 0x38,
  311. IntrMask = 0x3c,
  312. IntrStatus = 0x3e,
  313. TxConfig = 0x40,
  314. #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
  315. #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
  316. RxConfig = 0x44,
  317. #define RX128_INT_EN (1 << 15) /* 8111c and later */
  318. #define RX_MULTI_EN (1 << 14) /* 8111c only */
  319. #define RXCFG_FIFO_SHIFT 13
  320. /* No threshold before first PCI xfer */
  321. #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
  322. #define RX_EARLY_OFF (1 << 11)
  323. #define RXCFG_DMA_SHIFT 8
  324. /* Unlimited maximum PCI burst. */
  325. #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
  326. RxMissed = 0x4c,
  327. Cfg9346 = 0x50,
  328. Config0 = 0x51,
  329. Config1 = 0x52,
  330. Config2 = 0x53,
  331. #define PME_SIGNAL (1 << 5) /* 8168c and later */
  332. Config3 = 0x54,
  333. Config4 = 0x55,
  334. Config5 = 0x56,
  335. MultiIntr = 0x5c,
  336. PHYAR = 0x60,
  337. PHYstatus = 0x6c,
  338. RxMaxSize = 0xda,
  339. CPlusCmd = 0xe0,
  340. IntrMitigate = 0xe2,
  341. RxDescAddrLow = 0xe4,
  342. RxDescAddrHigh = 0xe8,
  343. EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
  344. #define NoEarlyTx 0x3f /* Max value : no early transmit. */
  345. MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
  346. #define TxPacketMax (8064 >> 7)
  347. #define EarlySize 0x27
  348. FuncEvent = 0xf0,
  349. FuncEventMask = 0xf4,
  350. FuncPresetState = 0xf8,
  351. FuncForceEvent = 0xfc,
  352. };
  353. enum rtl8110_registers {
  354. TBICSR = 0x64,
  355. TBI_ANAR = 0x68,
  356. TBI_LPAR = 0x6a,
  357. };
  358. enum rtl8168_8101_registers {
  359. CSIDR = 0x64,
  360. CSIAR = 0x68,
  361. #define CSIAR_FLAG 0x80000000
  362. #define CSIAR_WRITE_CMD 0x80000000
  363. #define CSIAR_BYTE_ENABLE 0x0f
  364. #define CSIAR_BYTE_ENABLE_SHIFT 12
  365. #define CSIAR_ADDR_MASK 0x0fff
  366. #define CSIAR_FUNC_CARD 0x00000000
  367. #define CSIAR_FUNC_SDIO 0x00010000
  368. #define CSIAR_FUNC_NIC 0x00020000
  369. #define CSIAR_FUNC_NIC2 0x00010000
  370. PMCH = 0x6f,
  371. EPHYAR = 0x80,
  372. #define EPHYAR_FLAG 0x80000000
  373. #define EPHYAR_WRITE_CMD 0x80000000
  374. #define EPHYAR_REG_MASK 0x1f
  375. #define EPHYAR_REG_SHIFT 16
  376. #define EPHYAR_DATA_MASK 0xffff
  377. DLLPR = 0xd0,
  378. #define PFM_EN (1 << 6)
  379. DBG_REG = 0xd1,
  380. #define FIX_NAK_1 (1 << 4)
  381. #define FIX_NAK_2 (1 << 3)
  382. TWSI = 0xd2,
  383. MCU = 0xd3,
  384. #define NOW_IS_OOB (1 << 7)
  385. #define TX_EMPTY (1 << 5)
  386. #define RX_EMPTY (1 << 4)
  387. #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY)
  388. #define EN_NDP (1 << 3)
  389. #define EN_OOB_RESET (1 << 2)
  390. #define LINK_LIST_RDY (1 << 1)
  391. EFUSEAR = 0xdc,
  392. #define EFUSEAR_FLAG 0x80000000
  393. #define EFUSEAR_WRITE_CMD 0x80000000
  394. #define EFUSEAR_READ_CMD 0x00000000
  395. #define EFUSEAR_REG_MASK 0x03ff
  396. #define EFUSEAR_REG_SHIFT 8
  397. #define EFUSEAR_DATA_MASK 0xff
  398. };
  399. enum rtl8168_registers {
  400. LED_FREQ = 0x1a,
  401. EEE_LED = 0x1b,
  402. ERIDR = 0x70,
  403. ERIAR = 0x74,
  404. #define ERIAR_FLAG 0x80000000
  405. #define ERIAR_WRITE_CMD 0x80000000
  406. #define ERIAR_READ_CMD 0x00000000
  407. #define ERIAR_ADDR_BYTE_ALIGN 4
  408. #define ERIAR_TYPE_SHIFT 16
  409. #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
  410. #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
  411. #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
  412. #define ERIAR_MASK_SHIFT 12
  413. #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
  414. #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
  415. #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT)
  416. #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
  417. EPHY_RXER_NUM = 0x7c,
  418. OCPDR = 0xb0, /* OCP GPHY access */
  419. #define OCPDR_WRITE_CMD 0x80000000
  420. #define OCPDR_READ_CMD 0x00000000
  421. #define OCPDR_REG_MASK 0x7f
  422. #define OCPDR_GPHY_REG_SHIFT 16
  423. #define OCPDR_DATA_MASK 0xffff
  424. OCPAR = 0xb4,
  425. #define OCPAR_FLAG 0x80000000
  426. #define OCPAR_GPHY_WRITE_CMD 0x8000f060
  427. #define OCPAR_GPHY_READ_CMD 0x0000f060
  428. GPHY_OCP = 0xb8,
  429. RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
  430. MISC = 0xf0, /* 8168e only. */
  431. #define TXPLA_RST (1 << 29)
  432. #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */
  433. #define PWM_EN (1 << 22)
  434. #define RXDV_GATED_EN (1 << 19)
  435. #define EARLY_TALLY_EN (1 << 16)
  436. };
  437. enum rtl_register_content {
  438. /* InterruptStatusBits */
  439. SYSErr = 0x8000,
  440. PCSTimeout = 0x4000,
  441. SWInt = 0x0100,
  442. TxDescUnavail = 0x0080,
  443. RxFIFOOver = 0x0040,
  444. LinkChg = 0x0020,
  445. RxOverflow = 0x0010,
  446. TxErr = 0x0008,
  447. TxOK = 0x0004,
  448. RxErr = 0x0002,
  449. RxOK = 0x0001,
  450. /* RxStatusDesc */
  451. RxBOVF = (1 << 24),
  452. RxFOVF = (1 << 23),
  453. RxRWT = (1 << 22),
  454. RxRES = (1 << 21),
  455. RxRUNT = (1 << 20),
  456. RxCRC = (1 << 19),
  457. /* ChipCmdBits */
  458. StopReq = 0x80,
  459. CmdReset = 0x10,
  460. CmdRxEnb = 0x08,
  461. CmdTxEnb = 0x04,
  462. RxBufEmpty = 0x01,
  463. /* TXPoll register p.5 */
  464. HPQ = 0x80, /* Poll cmd on the high prio queue */
  465. NPQ = 0x40, /* Poll cmd on the low prio queue */
  466. FSWInt = 0x01, /* Forced software interrupt */
  467. /* Cfg9346Bits */
  468. Cfg9346_Lock = 0x00,
  469. Cfg9346_Unlock = 0xc0,
  470. /* rx_mode_bits */
  471. AcceptErr = 0x20,
  472. AcceptRunt = 0x10,
  473. AcceptBroadcast = 0x08,
  474. AcceptMulticast = 0x04,
  475. AcceptMyPhys = 0x02,
  476. AcceptAllPhys = 0x01,
  477. #define RX_CONFIG_ACCEPT_MASK 0x3f
  478. /* TxConfigBits */
  479. TxInterFrameGapShift = 24,
  480. TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
  481. /* Config1 register p.24 */
  482. LEDS1 = (1 << 7),
  483. LEDS0 = (1 << 6),
  484. Speed_down = (1 << 4),
  485. MEMMAP = (1 << 3),
  486. IOMAP = (1 << 2),
  487. VPD = (1 << 1),
  488. PMEnable = (1 << 0), /* Power Management Enable */
  489. /* Config2 register p. 25 */
  490. ClkReqEn = (1 << 7), /* Clock Request Enable */
  491. MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */
  492. PCI_Clock_66MHz = 0x01,
  493. PCI_Clock_33MHz = 0x00,
  494. /* Config3 register p.25 */
  495. MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
  496. LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
  497. Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */
  498. Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
  499. /* Config4 register */
  500. Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */
  501. /* Config5 register p.27 */
  502. BWF = (1 << 6), /* Accept Broadcast wakeup frame */
  503. MWF = (1 << 5), /* Accept Multicast wakeup frame */
  504. UWF = (1 << 4), /* Accept Unicast wakeup frame */
  505. Spi_en = (1 << 3),
  506. LanWake = (1 << 1), /* LanWake enable/disable */
  507. PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
  508. ASPM_en = (1 << 0), /* ASPM enable */
  509. /* TBICSR p.28 */
  510. TBIReset = 0x80000000,
  511. TBILoopback = 0x40000000,
  512. TBINwEnable = 0x20000000,
  513. TBINwRestart = 0x10000000,
  514. TBILinkOk = 0x02000000,
  515. TBINwComplete = 0x01000000,
  516. /* CPlusCmd p.31 */
  517. EnableBist = (1 << 15), // 8168 8101
  518. Mac_dbgo_oe = (1 << 14), // 8168 8101
  519. Normal_mode = (1 << 13), // unused
  520. Force_half_dup = (1 << 12), // 8168 8101
  521. Force_rxflow_en = (1 << 11), // 8168 8101
  522. Force_txflow_en = (1 << 10), // 8168 8101
  523. Cxpl_dbg_sel = (1 << 9), // 8168 8101
  524. ASF = (1 << 8), // 8168 8101
  525. PktCntrDisable = (1 << 7), // 8168 8101
  526. Mac_dbgo_sel = 0x001c, // 8168
  527. RxVlan = (1 << 6),
  528. RxChkSum = (1 << 5),
  529. PCIDAC = (1 << 4),
  530. PCIMulRW = (1 << 3),
  531. INTT_0 = 0x0000, // 8168
  532. INTT_1 = 0x0001, // 8168
  533. INTT_2 = 0x0002, // 8168
  534. INTT_3 = 0x0003, // 8168
  535. /* rtl8169_PHYstatus */
  536. TBI_Enable = 0x80,
  537. TxFlowCtrl = 0x40,
  538. RxFlowCtrl = 0x20,
  539. _1000bpsF = 0x10,
  540. _100bps = 0x08,
  541. _10bps = 0x04,
  542. LinkStatus = 0x02,
  543. FullDup = 0x01,
  544. /* _TBICSRBit */
  545. TBILinkOK = 0x02000000,
  546. /* DumpCounterCommand */
  547. CounterDump = 0x8,
  548. };
  549. enum rtl_desc_bit {
  550. /* First doubleword. */
  551. DescOwn = (1 << 31), /* Descriptor is owned by NIC */
  552. RingEnd = (1 << 30), /* End of descriptor ring */
  553. FirstFrag = (1 << 29), /* First segment of a packet */
  554. LastFrag = (1 << 28), /* Final segment of a packet */
  555. };
  556. /* Generic case. */
  557. enum rtl_tx_desc_bit {
  558. /* First doubleword. */
  559. TD_LSO = (1 << 27), /* Large Send Offload */
  560. #define TD_MSS_MAX 0x07ffu /* MSS value */
  561. /* Second doubleword. */
  562. TxVlanTag = (1 << 17), /* Add VLAN tag */
  563. };
  564. /* 8169, 8168b and 810x except 8102e. */
  565. enum rtl_tx_desc_bit_0 {
  566. /* First doubleword. */
  567. #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
  568. TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
  569. TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
  570. TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
  571. };
  572. /* 8102e, 8168c and beyond. */
  573. enum rtl_tx_desc_bit_1 {
  574. /* Second doubleword. */
  575. #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
  576. TD1_IP_CS = (1 << 29), /* Calculate IP checksum */
  577. TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
  578. TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
  579. };
  580. static const struct rtl_tx_desc_info {
  581. struct {
  582. u32 udp;
  583. u32 tcp;
  584. } checksum;
  585. u16 mss_shift;
  586. u16 opts_offset;
  587. } tx_desc_info [] = {
  588. [RTL_TD_0] = {
  589. .checksum = {
  590. .udp = TD0_IP_CS | TD0_UDP_CS,
  591. .tcp = TD0_IP_CS | TD0_TCP_CS
  592. },
  593. .mss_shift = TD0_MSS_SHIFT,
  594. .opts_offset = 0
  595. },
  596. [RTL_TD_1] = {
  597. .checksum = {
  598. .udp = TD1_IP_CS | TD1_UDP_CS,
  599. .tcp = TD1_IP_CS | TD1_TCP_CS
  600. },
  601. .mss_shift = TD1_MSS_SHIFT,
  602. .opts_offset = 1
  603. }
  604. };
  605. enum rtl_rx_desc_bit {
  606. /* Rx private */
  607. PID1 = (1 << 18), /* Protocol ID bit 1/2 */
  608. PID0 = (1 << 17), /* Protocol ID bit 2/2 */
  609. #define RxProtoUDP (PID1)
  610. #define RxProtoTCP (PID0)
  611. #define RxProtoIP (PID1 | PID0)
  612. #define RxProtoMask RxProtoIP
  613. IPFail = (1 << 16), /* IP checksum failed */
  614. UDPFail = (1 << 15), /* UDP/IP checksum failed */
  615. TCPFail = (1 << 14), /* TCP/IP checksum failed */
  616. RxVlanTag = (1 << 16), /* VLAN tag available */
  617. };
  618. #define RsvdMask 0x3fffc000
  619. struct TxDesc {
  620. __le32 opts1;
  621. __le32 opts2;
  622. __le64 addr;
  623. };
  624. struct RxDesc {
  625. __le32 opts1;
  626. __le32 opts2;
  627. __le64 addr;
  628. };
  629. struct ring_info {
  630. struct sk_buff *skb;
  631. u32 len;
  632. u8 __pad[sizeof(void *) - sizeof(u32)];
  633. };
  634. enum features {
  635. RTL_FEATURE_WOL = (1 << 0),
  636. RTL_FEATURE_MSI = (1 << 1),
  637. RTL_FEATURE_GMII = (1 << 2),
  638. };
  639. struct rtl8169_counters {
  640. __le64 tx_packets;
  641. __le64 rx_packets;
  642. __le64 tx_errors;
  643. __le32 rx_errors;
  644. __le16 rx_missed;
  645. __le16 align_errors;
  646. __le32 tx_one_collision;
  647. __le32 tx_multi_collision;
  648. __le64 rx_unicast;
  649. __le64 rx_broadcast;
  650. __le32 rx_multicast;
  651. __le16 tx_aborted;
  652. __le16 tx_underun;
  653. };
  654. enum rtl_flag {
  655. RTL_FLAG_TASK_ENABLED,
  656. RTL_FLAG_TASK_SLOW_PENDING,
  657. RTL_FLAG_TASK_RESET_PENDING,
  658. RTL_FLAG_TASK_PHY_PENDING,
  659. RTL_FLAG_MAX
  660. };
  661. struct rtl8169_stats {
  662. u64 packets;
  663. u64 bytes;
  664. struct u64_stats_sync syncp;
  665. };
  666. struct rtl8169_private {
  667. void __iomem *mmio_addr; /* memory map physical address */
  668. struct pci_dev *pci_dev;
  669. struct net_device *dev;
  670. struct napi_struct napi;
  671. u32 msg_enable;
  672. u16 txd_version;
  673. u16 mac_version;
  674. u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
  675. u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
  676. u32 dirty_tx;
  677. struct rtl8169_stats rx_stats;
  678. struct rtl8169_stats tx_stats;
  679. struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
  680. struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
  681. dma_addr_t TxPhyAddr;
  682. dma_addr_t RxPhyAddr;
  683. void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
  684. struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
  685. struct timer_list timer;
  686. u16 cp_cmd;
  687. u16 event_slow;
  688. struct mdio_ops {
  689. void (*write)(struct rtl8169_private *, int, int);
  690. int (*read)(struct rtl8169_private *, int);
  691. } mdio_ops;
  692. struct pll_power_ops {
  693. void (*down)(struct rtl8169_private *);
  694. void (*up)(struct rtl8169_private *);
  695. } pll_power_ops;
  696. struct jumbo_ops {
  697. void (*enable)(struct rtl8169_private *);
  698. void (*disable)(struct rtl8169_private *);
  699. } jumbo_ops;
  700. struct csi_ops {
  701. void (*write)(struct rtl8169_private *, int, int);
  702. u32 (*read)(struct rtl8169_private *, int);
  703. } csi_ops;
  704. int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
  705. int (*get_settings)(struct net_device *, struct ethtool_cmd *);
  706. void (*phy_reset_enable)(struct rtl8169_private *tp);
  707. void (*hw_start)(struct net_device *);
  708. unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
  709. unsigned int (*link_ok)(void __iomem *);
  710. int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
  711. struct {
  712. DECLARE_BITMAP(flags, RTL_FLAG_MAX);
  713. struct mutex mutex;
  714. struct work_struct work;
  715. } wk;
  716. unsigned features;
  717. struct mii_if_info mii;
  718. struct rtl8169_counters counters;
  719. u32 saved_wolopts;
  720. u32 opts1_mask;
  721. struct rtl_fw {
  722. const struct firmware *fw;
  723. #define RTL_VER_SIZE 32
  724. char version[RTL_VER_SIZE];
  725. struct rtl_fw_phy_action {
  726. __le32 *code;
  727. size_t size;
  728. } phy_action;
  729. } *rtl_fw;
  730. #define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN)
  731. u32 ocp_base;
  732. };
  733. MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
  734. MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
  735. module_param(use_dac, int, 0);
  736. MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
  737. module_param_named(debug, debug.msg_enable, int, 0);
  738. MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
  739. MODULE_LICENSE("GPL");
  740. MODULE_VERSION(RTL8169_VERSION);
  741. MODULE_FIRMWARE(FIRMWARE_8168D_1);
  742. MODULE_FIRMWARE(FIRMWARE_8168D_2);
  743. MODULE_FIRMWARE(FIRMWARE_8168E_1);
  744. MODULE_FIRMWARE(FIRMWARE_8168E_2);
  745. MODULE_FIRMWARE(FIRMWARE_8168E_3);
  746. MODULE_FIRMWARE(FIRMWARE_8105E_1);
  747. MODULE_FIRMWARE(FIRMWARE_8168F_1);
  748. MODULE_FIRMWARE(FIRMWARE_8168F_2);
  749. MODULE_FIRMWARE(FIRMWARE_8402_1);
  750. MODULE_FIRMWARE(FIRMWARE_8411_1);
  751. MODULE_FIRMWARE(FIRMWARE_8411_2);
  752. MODULE_FIRMWARE(FIRMWARE_8106E_1);
  753. MODULE_FIRMWARE(FIRMWARE_8106E_2);
  754. MODULE_FIRMWARE(FIRMWARE_8168G_2);
  755. MODULE_FIRMWARE(FIRMWARE_8168G_3);
  756. static void rtl_lock_work(struct rtl8169_private *tp)
  757. {
  758. mutex_lock(&tp->wk.mutex);
  759. }
  760. static void rtl_unlock_work(struct rtl8169_private *tp)
  761. {
  762. mutex_unlock(&tp->wk.mutex);
  763. }
  764. static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
  765. {
  766. pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL,
  767. PCI_EXP_DEVCTL_READRQ, force);
  768. }
  769. struct rtl_cond {
  770. bool (*check)(struct rtl8169_private *);
  771. const char *msg;
  772. };
  773. static void rtl_udelay(unsigned int d)
  774. {
  775. udelay(d);
  776. }
  777. static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
  778. void (*delay)(unsigned int), unsigned int d, int n,
  779. bool high)
  780. {
  781. int i;
  782. for (i = 0; i < n; i++) {
  783. delay(d);
  784. if (c->check(tp) == high)
  785. return true;
  786. }
  787. netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
  788. c->msg, !high, n, d);
  789. return false;
  790. }
  791. static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
  792. const struct rtl_cond *c,
  793. unsigned int d, int n)
  794. {
  795. return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
  796. }
  797. static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
  798. const struct rtl_cond *c,
  799. unsigned int d, int n)
  800. {
  801. return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
  802. }
  803. static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
  804. const struct rtl_cond *c,
  805. unsigned int d, int n)
  806. {
  807. return rtl_loop_wait(tp, c, msleep, d, n, true);
  808. }
  809. static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
  810. const struct rtl_cond *c,
  811. unsigned int d, int n)
  812. {
  813. return rtl_loop_wait(tp, c, msleep, d, n, false);
  814. }
  815. #define DECLARE_RTL_COND(name) \
  816. static bool name ## _check(struct rtl8169_private *); \
  817. \
  818. static const struct rtl_cond name = { \
  819. .check = name ## _check, \
  820. .msg = #name \
  821. }; \
  822. \
  823. static bool name ## _check(struct rtl8169_private *tp)
  824. DECLARE_RTL_COND(rtl_ocpar_cond)
  825. {
  826. void __iomem *ioaddr = tp->mmio_addr;
  827. return RTL_R32(OCPAR) & OCPAR_FLAG;
  828. }
  829. static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
  830. {
  831. void __iomem *ioaddr = tp->mmio_addr;
  832. RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
  833. return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
  834. RTL_R32(OCPDR) : ~0;
  835. }
  836. static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
  837. {
  838. void __iomem *ioaddr = tp->mmio_addr;
  839. RTL_W32(OCPDR, data);
  840. RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
  841. rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
  842. }
  843. DECLARE_RTL_COND(rtl_eriar_cond)
  844. {
  845. void __iomem *ioaddr = tp->mmio_addr;
  846. return RTL_R32(ERIAR) & ERIAR_FLAG;
  847. }
  848. static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
  849. {
  850. void __iomem *ioaddr = tp->mmio_addr;
  851. RTL_W8(ERIDR, cmd);
  852. RTL_W32(ERIAR, 0x800010e8);
  853. msleep(2);
  854. if (!rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 5))
  855. return;
  856. ocp_write(tp, 0x1, 0x30, 0x00000001);
  857. }
  858. #define OOB_CMD_RESET 0x00
  859. #define OOB_CMD_DRIVER_START 0x05
  860. #define OOB_CMD_DRIVER_STOP 0x06
  861. static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
  862. {
  863. return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
  864. }
  865. DECLARE_RTL_COND(rtl_ocp_read_cond)
  866. {
  867. u16 reg;
  868. reg = rtl8168_get_ocp_reg(tp);
  869. return ocp_read(tp, 0x0f, reg) & 0x00000800;
  870. }
  871. static void rtl8168_driver_start(struct rtl8169_private *tp)
  872. {
  873. rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
  874. rtl_msleep_loop_wait_high(tp, &rtl_ocp_read_cond, 10, 10);
  875. }
  876. static void rtl8168_driver_stop(struct rtl8169_private *tp)
  877. {
  878. rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
  879. rtl_msleep_loop_wait_low(tp, &rtl_ocp_read_cond, 10, 10);
  880. }
  881. static int r8168dp_check_dash(struct rtl8169_private *tp)
  882. {
  883. u16 reg = rtl8168_get_ocp_reg(tp);
  884. return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
  885. }
  886. static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
  887. {
  888. if (reg & 0xffff0001) {
  889. netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
  890. return true;
  891. }
  892. return false;
  893. }
  894. DECLARE_RTL_COND(rtl_ocp_gphy_cond)
  895. {
  896. void __iomem *ioaddr = tp->mmio_addr;
  897. return RTL_R32(GPHY_OCP) & OCPAR_FLAG;
  898. }
  899. static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
  900. {
  901. void __iomem *ioaddr = tp->mmio_addr;
  902. if (rtl_ocp_reg_failure(tp, reg))
  903. return;
  904. RTL_W32(GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
  905. rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
  906. }
  907. static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
  908. {
  909. void __iomem *ioaddr = tp->mmio_addr;
  910. if (rtl_ocp_reg_failure(tp, reg))
  911. return 0;
  912. RTL_W32(GPHY_OCP, reg << 15);
  913. return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
  914. (RTL_R32(GPHY_OCP) & 0xffff) : ~0;
  915. }
  916. static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
  917. {
  918. void __iomem *ioaddr = tp->mmio_addr;
  919. if (rtl_ocp_reg_failure(tp, reg))
  920. return;
  921. RTL_W32(OCPDR, OCPAR_FLAG | (reg << 15) | data);
  922. }
  923. static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
  924. {
  925. void __iomem *ioaddr = tp->mmio_addr;
  926. if (rtl_ocp_reg_failure(tp, reg))
  927. return 0;
  928. RTL_W32(OCPDR, reg << 15);
  929. return RTL_R32(OCPDR);
  930. }
  931. #define OCP_STD_PHY_BASE 0xa400
  932. static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
  933. {
  934. if (reg == 0x1f) {
  935. tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
  936. return;
  937. }
  938. if (tp->ocp_base != OCP_STD_PHY_BASE)
  939. reg -= 0x10;
  940. r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
  941. }
  942. static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
  943. {
  944. if (tp->ocp_base != OCP_STD_PHY_BASE)
  945. reg -= 0x10;
  946. return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
  947. }
  948. static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
  949. {
  950. if (reg == 0x1f) {
  951. tp->ocp_base = value << 4;
  952. return;
  953. }
  954. r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
  955. }
  956. static int mac_mcu_read(struct rtl8169_private *tp, int reg)
  957. {
  958. return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
  959. }
  960. DECLARE_RTL_COND(rtl_phyar_cond)
  961. {
  962. void __iomem *ioaddr = tp->mmio_addr;
  963. return RTL_R32(PHYAR) & 0x80000000;
  964. }
  965. static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
  966. {
  967. void __iomem *ioaddr = tp->mmio_addr;
  968. RTL_W32(PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
  969. rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
  970. /*
  971. * According to hardware specs a 20us delay is required after write
  972. * complete indication, but before sending next command.
  973. */
  974. udelay(20);
  975. }
  976. static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
  977. {
  978. void __iomem *ioaddr = tp->mmio_addr;
  979. int value;
  980. RTL_W32(PHYAR, 0x0 | (reg & 0x1f) << 16);
  981. value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
  982. RTL_R32(PHYAR) & 0xffff : ~0;
  983. /*
  984. * According to hardware specs a 20us delay is required after read
  985. * complete indication, but before sending next command.
  986. */
  987. udelay(20);
  988. return value;
  989. }
  990. static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
  991. {
  992. void __iomem *ioaddr = tp->mmio_addr;
  993. RTL_W32(OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
  994. RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
  995. RTL_W32(EPHY_RXER_NUM, 0);
  996. rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
  997. }
  998. static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
  999. {
  1000. r8168dp_1_mdio_access(tp, reg,
  1001. OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
  1002. }
  1003. static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
  1004. {
  1005. void __iomem *ioaddr = tp->mmio_addr;
  1006. r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
  1007. mdelay(1);
  1008. RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
  1009. RTL_W32(EPHY_RXER_NUM, 0);
  1010. return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
  1011. RTL_R32(OCPDR) & OCPDR_DATA_MASK : ~0;
  1012. }
  1013. #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
  1014. static void r8168dp_2_mdio_start(void __iomem *ioaddr)
  1015. {
  1016. RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
  1017. }
  1018. static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
  1019. {
  1020. RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
  1021. }
  1022. static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
  1023. {
  1024. void __iomem *ioaddr = tp->mmio_addr;
  1025. r8168dp_2_mdio_start(ioaddr);
  1026. r8169_mdio_write(tp, reg, value);
  1027. r8168dp_2_mdio_stop(ioaddr);
  1028. }
  1029. static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
  1030. {
  1031. void __iomem *ioaddr = tp->mmio_addr;
  1032. int value;
  1033. r8168dp_2_mdio_start(ioaddr);
  1034. value = r8169_mdio_read(tp, reg);
  1035. r8168dp_2_mdio_stop(ioaddr);
  1036. return value;
  1037. }
  1038. static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
  1039. {
  1040. tp->mdio_ops.write(tp, location, val);
  1041. }
  1042. static int rtl_readphy(struct rtl8169_private *tp, int location)
  1043. {
  1044. return tp->mdio_ops.read(tp, location);
  1045. }
  1046. static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
  1047. {
  1048. rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
  1049. }
  1050. static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
  1051. {
  1052. int val;
  1053. val = rtl_readphy(tp, reg_addr);
  1054. rtl_writephy(tp, reg_addr, (val | p) & ~m);
  1055. }
  1056. static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
  1057. int val)
  1058. {
  1059. struct rtl8169_private *tp = netdev_priv(dev);
  1060. rtl_writephy(tp, location, val);
  1061. }
  1062. static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
  1063. {
  1064. struct rtl8169_private *tp = netdev_priv(dev);
  1065. return rtl_readphy(tp, location);
  1066. }
  1067. DECLARE_RTL_COND(rtl_ephyar_cond)
  1068. {
  1069. void __iomem *ioaddr = tp->mmio_addr;
  1070. return RTL_R32(EPHYAR) & EPHYAR_FLAG;
  1071. }
  1072. static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
  1073. {
  1074. void __iomem *ioaddr = tp->mmio_addr;
  1075. RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
  1076. (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
  1077. rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
  1078. udelay(10);
  1079. }
  1080. static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
  1081. {
  1082. void __iomem *ioaddr = tp->mmio_addr;
  1083. RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
  1084. return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
  1085. RTL_R32(EPHYAR) & EPHYAR_DATA_MASK : ~0;
  1086. }
  1087. static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
  1088. u32 val, int type)
  1089. {
  1090. void __iomem *ioaddr = tp->mmio_addr;
  1091. BUG_ON((addr & 3) || (mask == 0));
  1092. RTL_W32(ERIDR, val);
  1093. RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
  1094. rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
  1095. }
  1096. static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
  1097. {
  1098. void __iomem *ioaddr = tp->mmio_addr;
  1099. RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
  1100. return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
  1101. RTL_R32(ERIDR) : ~0;
  1102. }
  1103. static void rtl_w1w0_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
  1104. u32 m, int type)
  1105. {
  1106. u32 val;
  1107. val = rtl_eri_read(tp, addr, type);
  1108. rtl_eri_write(tp, addr, mask, (val & ~m) | p, type);
  1109. }
  1110. struct exgmac_reg {
  1111. u16 addr;
  1112. u16 mask;
  1113. u32 val;
  1114. };
  1115. static void rtl_write_exgmac_batch(struct rtl8169_private *tp,
  1116. const struct exgmac_reg *r, int len)
  1117. {
  1118. while (len-- > 0) {
  1119. rtl_eri_write(tp, r->addr, r->mask, r->val, ERIAR_EXGMAC);
  1120. r++;
  1121. }
  1122. }
  1123. DECLARE_RTL_COND(rtl_efusear_cond)
  1124. {
  1125. void __iomem *ioaddr = tp->mmio_addr;
  1126. return RTL_R32(EFUSEAR) & EFUSEAR_FLAG;
  1127. }
  1128. static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
  1129. {
  1130. void __iomem *ioaddr = tp->mmio_addr;
  1131. RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
  1132. return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
  1133. RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
  1134. }
  1135. static u16 rtl_get_events(struct rtl8169_private *tp)
  1136. {
  1137. void __iomem *ioaddr = tp->mmio_addr;
  1138. return RTL_R16(IntrStatus);
  1139. }
  1140. static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
  1141. {
  1142. void __iomem *ioaddr = tp->mmio_addr;
  1143. RTL_W16(IntrStatus, bits);
  1144. mmiowb();
  1145. }
  1146. static void rtl_irq_disable(struct rtl8169_private *tp)
  1147. {
  1148. void __iomem *ioaddr = tp->mmio_addr;
  1149. RTL_W16(IntrMask, 0);
  1150. mmiowb();
  1151. }
  1152. static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
  1153. {
  1154. void __iomem *ioaddr = tp->mmio_addr;
  1155. RTL_W16(IntrMask, bits);
  1156. }
  1157. #define RTL_EVENT_NAPI_RX (RxOK | RxErr)
  1158. #define RTL_EVENT_NAPI_TX (TxOK | TxErr)
  1159. #define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
  1160. static void rtl_irq_enable_all(struct rtl8169_private *tp)
  1161. {
  1162. rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
  1163. }
  1164. static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
  1165. {
  1166. void __iomem *ioaddr = tp->mmio_addr;
  1167. rtl_irq_disable(tp);
  1168. rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
  1169. RTL_R8(ChipCmd);
  1170. }
  1171. static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
  1172. {
  1173. void __iomem *ioaddr = tp->mmio_addr;
  1174. return RTL_R32(TBICSR) & TBIReset;
  1175. }
  1176. static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
  1177. {
  1178. return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
  1179. }
  1180. static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
  1181. {
  1182. return RTL_R32(TBICSR) & TBILinkOk;
  1183. }
  1184. static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
  1185. {
  1186. return RTL_R8(PHYstatus) & LinkStatus;
  1187. }
  1188. static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
  1189. {
  1190. void __iomem *ioaddr = tp->mmio_addr;
  1191. RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
  1192. }
  1193. static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
  1194. {
  1195. unsigned int val;
  1196. val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
  1197. rtl_writephy(tp, MII_BMCR, val & 0xffff);
  1198. }
  1199. static void rtl_link_chg_patch(struct rtl8169_private *tp)
  1200. {
  1201. void __iomem *ioaddr = tp->mmio_addr;
  1202. struct net_device *dev = tp->dev;
  1203. if (!netif_running(dev))
  1204. return;
  1205. if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
  1206. tp->mac_version == RTL_GIGA_MAC_VER_38) {
  1207. if (RTL_R8(PHYstatus) & _1000bpsF) {
  1208. rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
  1209. ERIAR_EXGMAC);
  1210. rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
  1211. ERIAR_EXGMAC);
  1212. } else if (RTL_R8(PHYstatus) & _100bps) {
  1213. rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
  1214. ERIAR_EXGMAC);
  1215. rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
  1216. ERIAR_EXGMAC);
  1217. } else {
  1218. rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
  1219. ERIAR_EXGMAC);
  1220. rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
  1221. ERIAR_EXGMAC);
  1222. }
  1223. /* Reset packet filter */
  1224. rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
  1225. ERIAR_EXGMAC);
  1226. rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
  1227. ERIAR_EXGMAC);
  1228. } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
  1229. tp->mac_version == RTL_GIGA_MAC_VER_36) {
  1230. if (RTL_R8(PHYstatus) & _1000bpsF) {
  1231. rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
  1232. ERIAR_EXGMAC);
  1233. rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
  1234. ERIAR_EXGMAC);
  1235. } else {
  1236. rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
  1237. ERIAR_EXGMAC);
  1238. rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
  1239. ERIAR_EXGMAC);
  1240. }
  1241. } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
  1242. if (RTL_R8(PHYstatus) & _10bps) {
  1243. rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02,
  1244. ERIAR_EXGMAC);
  1245. rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060,
  1246. ERIAR_EXGMAC);
  1247. } else {
  1248. rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000,
  1249. ERIAR_EXGMAC);
  1250. }
  1251. }
  1252. }
  1253. static void __rtl8169_check_link_status(struct net_device *dev,
  1254. struct rtl8169_private *tp,
  1255. void __iomem *ioaddr, bool pm)
  1256. {
  1257. if (tp->link_ok(ioaddr)) {
  1258. rtl_link_chg_patch(tp);
  1259. /* This is to cancel a scheduled suspend if there's one. */
  1260. if (pm)
  1261. pm_request_resume(&tp->pci_dev->dev);
  1262. netif_carrier_on(dev);
  1263. if (net_ratelimit())
  1264. netif_info(tp, ifup, dev, "link up\n");
  1265. } else {
  1266. netif_carrier_off(dev);
  1267. netif_info(tp, ifdown, dev, "link down\n");
  1268. if (pm)
  1269. pm_schedule_suspend(&tp->pci_dev->dev, 5000);
  1270. }
  1271. }
  1272. static void rtl8169_check_link_status(struct net_device *dev,
  1273. struct rtl8169_private *tp,
  1274. void __iomem *ioaddr)
  1275. {
  1276. __rtl8169_check_link_status(dev, tp, ioaddr, false);
  1277. }
  1278. #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
  1279. static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
  1280. {
  1281. void __iomem *ioaddr = tp->mmio_addr;
  1282. u8 options;
  1283. u32 wolopts = 0;
  1284. options = RTL_R8(Config1);
  1285. if (!(options & PMEnable))
  1286. return 0;
  1287. options = RTL_R8(Config3);
  1288. if (options & LinkUp)
  1289. wolopts |= WAKE_PHY;
  1290. if (options & MagicPacket)
  1291. wolopts |= WAKE_MAGIC;
  1292. options = RTL_R8(Config5);
  1293. if (options & UWF)
  1294. wolopts |= WAKE_UCAST;
  1295. if (options & BWF)
  1296. wolopts |= WAKE_BCAST;
  1297. if (options & MWF)
  1298. wolopts |= WAKE_MCAST;
  1299. return wolopts;
  1300. }
  1301. static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
  1302. {
  1303. struct rtl8169_private *tp = netdev_priv(dev);
  1304. rtl_lock_work(tp);
  1305. wol->supported = WAKE_ANY;
  1306. wol->wolopts = __rtl8169_get_wol(tp);
  1307. rtl_unlock_work(tp);
  1308. }
  1309. static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
  1310. {
  1311. void __iomem *ioaddr = tp->mmio_addr;
  1312. unsigned int i;
  1313. static const struct {
  1314. u32 opt;
  1315. u16 reg;
  1316. u8 mask;
  1317. } cfg[] = {
  1318. { WAKE_PHY, Config3, LinkUp },
  1319. { WAKE_MAGIC, Config3, MagicPacket },
  1320. { WAKE_UCAST, Config5, UWF },
  1321. { WAKE_BCAST, Config5, BWF },
  1322. { WAKE_MCAST, Config5, MWF },
  1323. { WAKE_ANY, Config5, LanWake }
  1324. };
  1325. u8 options;
  1326. RTL_W8(Cfg9346, Cfg9346_Unlock);
  1327. for (i = 0; i < ARRAY_SIZE(cfg); i++) {
  1328. options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
  1329. if (wolopts & cfg[i].opt)
  1330. options |= cfg[i].mask;
  1331. RTL_W8(cfg[i].reg, options);
  1332. }
  1333. switch (tp->mac_version) {
  1334. case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
  1335. options = RTL_R8(Config1) & ~PMEnable;
  1336. if (wolopts)
  1337. options |= PMEnable;
  1338. RTL_W8(Config1, options);
  1339. break;
  1340. default:
  1341. options = RTL_R8(Config2) & ~PME_SIGNAL;
  1342. if (wolopts)
  1343. options |= PME_SIGNAL;
  1344. RTL_W8(Config2, options);
  1345. break;
  1346. }
  1347. RTL_W8(Cfg9346, Cfg9346_Lock);
  1348. }
  1349. static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
  1350. {
  1351. struct rtl8169_private *tp = netdev_priv(dev);
  1352. rtl_lock_work(tp);
  1353. if (wol->wolopts)
  1354. tp->features |= RTL_FEATURE_WOL;
  1355. else
  1356. tp->features &= ~RTL_FEATURE_WOL;
  1357. __rtl8169_set_wol(tp, wol->wolopts);
  1358. rtl_unlock_work(tp);
  1359. device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
  1360. return 0;
  1361. }
  1362. static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
  1363. {
  1364. return rtl_chip_infos[tp->mac_version].fw_name;
  1365. }
  1366. static void rtl8169_get_drvinfo(struct net_device *dev,
  1367. struct ethtool_drvinfo *info)
  1368. {
  1369. struct rtl8169_private *tp = netdev_priv(dev);
  1370. struct rtl_fw *rtl_fw = tp->rtl_fw;
  1371. strlcpy(info->driver, MODULENAME, sizeof(info->driver));
  1372. strlcpy(info->version, RTL8169_VERSION, sizeof(info->version));
  1373. strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
  1374. BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
  1375. if (!IS_ERR_OR_NULL(rtl_fw))
  1376. strlcpy(info->fw_version, rtl_fw->version,
  1377. sizeof(info->fw_version));
  1378. }
  1379. static int rtl8169_get_regs_len(struct net_device *dev)
  1380. {
  1381. return R8169_REGS_SIZE;
  1382. }
  1383. static int rtl8169_set_speed_tbi(struct net_device *dev,
  1384. u8 autoneg, u16 speed, u8 duplex, u32 ignored)
  1385. {
  1386. struct rtl8169_private *tp = netdev_priv(dev);
  1387. void __iomem *ioaddr = tp->mmio_addr;
  1388. int ret = 0;
  1389. u32 reg;
  1390. reg = RTL_R32(TBICSR);
  1391. if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
  1392. (duplex == DUPLEX_FULL)) {
  1393. RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
  1394. } else if (autoneg == AUTONEG_ENABLE)
  1395. RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
  1396. else {
  1397. netif_warn(tp, link, dev,
  1398. "incorrect speed setting refused in TBI mode\n");
  1399. ret = -EOPNOTSUPP;
  1400. }
  1401. return ret;
  1402. }
  1403. static int rtl8169_set_speed_xmii(struct net_device *dev,
  1404. u8 autoneg, u16 speed, u8 duplex, u32 adv)
  1405. {
  1406. struct rtl8169_private *tp = netdev_priv(dev);
  1407. int giga_ctrl, bmcr;
  1408. int rc = -EINVAL;
  1409. rtl_writephy(tp, 0x1f, 0x0000);
  1410. if (autoneg == AUTONEG_ENABLE) {
  1411. int auto_nego;
  1412. auto_nego = rtl_readphy(tp, MII_ADVERTISE);
  1413. auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
  1414. ADVERTISE_100HALF | ADVERTISE_100FULL);
  1415. if (adv & ADVERTISED_10baseT_Half)
  1416. auto_nego |= ADVERTISE_10HALF;
  1417. if (adv & ADVERTISED_10baseT_Full)
  1418. auto_nego |= ADVERTISE_10FULL;
  1419. if (adv & ADVERTISED_100baseT_Half)
  1420. auto_nego |= ADVERTISE_100HALF;
  1421. if (adv & ADVERTISED_100baseT_Full)
  1422. auto_nego |= ADVERTISE_100FULL;
  1423. auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
  1424. giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
  1425. giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
  1426. /* The 8100e/8101e/8102e do Fast Ethernet only. */
  1427. if (tp->mii.supports_gmii) {
  1428. if (adv & ADVERTISED_1000baseT_Half)
  1429. giga_ctrl |= ADVERTISE_1000HALF;
  1430. if (adv & ADVERTISED_1000baseT_Full)
  1431. giga_ctrl |= ADVERTISE_1000FULL;
  1432. } else if (adv & (ADVERTISED_1000baseT_Half |
  1433. ADVERTISED_1000baseT_Full)) {
  1434. netif_info(tp, link, dev,
  1435. "PHY does not support 1000Mbps\n");
  1436. goto out;
  1437. }
  1438. bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
  1439. rtl_writephy(tp, MII_ADVERTISE, auto_nego);
  1440. rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
  1441. } else {
  1442. giga_ctrl = 0;
  1443. if (speed == SPEED_10)
  1444. bmcr = 0;
  1445. else if (speed == SPEED_100)
  1446. bmcr = BMCR_SPEED100;
  1447. else
  1448. goto out;
  1449. if (duplex == DUPLEX_FULL)
  1450. bmcr |= BMCR_FULLDPLX;
  1451. }
  1452. rtl_writephy(tp, MII_BMCR, bmcr);
  1453. if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
  1454. tp->mac_version == RTL_GIGA_MAC_VER_03) {
  1455. if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
  1456. rtl_writephy(tp, 0x17, 0x2138);
  1457. rtl_writephy(tp, 0x0e, 0x0260);
  1458. } else {
  1459. rtl_writephy(tp, 0x17, 0x2108);
  1460. rtl_writephy(tp, 0x0e, 0x0000);
  1461. }
  1462. }
  1463. rc = 0;
  1464. out:
  1465. return rc;
  1466. }
  1467. static int rtl8169_set_speed(struct net_device *dev,
  1468. u8 autoneg, u16 speed, u8 duplex, u32 advertising)
  1469. {
  1470. struct rtl8169_private *tp = netdev_priv(dev);
  1471. int ret;
  1472. ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
  1473. if (ret < 0)
  1474. goto out;
  1475. if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
  1476. (advertising & ADVERTISED_1000baseT_Full)) {
  1477. mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
  1478. }
  1479. out:
  1480. return ret;
  1481. }
  1482. static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  1483. {
  1484. struct rtl8169_private *tp = netdev_priv(dev);
  1485. int ret;
  1486. del_timer_sync(&tp->timer);
  1487. rtl_lock_work(tp);
  1488. ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
  1489. cmd->duplex, cmd->advertising);
  1490. rtl_unlock_work(tp);
  1491. return ret;
  1492. }
  1493. static netdev_features_t rtl8169_fix_features(struct net_device *dev,
  1494. netdev_features_t features)
  1495. {
  1496. struct rtl8169_private *tp = netdev_priv(dev);
  1497. if (dev->mtu > TD_MSS_MAX)
  1498. features &= ~NETIF_F_ALL_TSO;
  1499. if (dev->mtu > JUMBO_1K &&
  1500. !rtl_chip_infos[tp->mac_version].jumbo_tx_csum)
  1501. features &= ~NETIF_F_IP_CSUM;
  1502. return features;
  1503. }
  1504. static void __rtl8169_set_features(struct net_device *dev,
  1505. netdev_features_t features)
  1506. {
  1507. struct rtl8169_private *tp = netdev_priv(dev);
  1508. netdev_features_t changed = features ^ dev->features;
  1509. void __iomem *ioaddr = tp->mmio_addr;
  1510. if (!(changed & (NETIF_F_RXALL | NETIF_F_RXCSUM |
  1511. NETIF_F_HW_VLAN_CTAG_RX)))
  1512. return;
  1513. if (changed & (NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_RX)) {
  1514. if (features & NETIF_F_RXCSUM)
  1515. tp->cp_cmd |= RxChkSum;
  1516. else
  1517. tp->cp_cmd &= ~RxChkSum;
  1518. if (dev->features & NETIF_F_HW_VLAN_CTAG_RX)
  1519. tp->cp_cmd |= RxVlan;
  1520. else
  1521. tp->cp_cmd &= ~RxVlan;
  1522. RTL_W16(CPlusCmd, tp->cp_cmd);
  1523. RTL_R16(CPlusCmd);
  1524. }
  1525. if (changed & NETIF_F_RXALL) {
  1526. int tmp = (RTL_R32(RxConfig) & ~(AcceptErr | AcceptRunt));
  1527. if (features & NETIF_F_RXALL)
  1528. tmp |= (AcceptErr | AcceptRunt);
  1529. RTL_W32(RxConfig, tmp);
  1530. }
  1531. }
  1532. static int rtl8169_set_features(struct net_device *dev,
  1533. netdev_features_t features)
  1534. {
  1535. struct rtl8169_private *tp = netdev_priv(dev);
  1536. rtl_lock_work(tp);
  1537. __rtl8169_set_features(dev, features);
  1538. rtl_unlock_work(tp);
  1539. return 0;
  1540. }
  1541. static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
  1542. {
  1543. return (vlan_tx_tag_present(skb)) ?
  1544. TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
  1545. }
  1546. static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
  1547. {
  1548. u32 opts2 = le32_to_cpu(desc->opts2);
  1549. if (opts2 & RxVlanTag)
  1550. __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
  1551. }
  1552. static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
  1553. {
  1554. struct rtl8169_private *tp = netdev_priv(dev);
  1555. void __iomem *ioaddr = tp->mmio_addr;
  1556. u32 status;
  1557. cmd->supported =
  1558. SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
  1559. cmd->port = PORT_FIBRE;
  1560. cmd->transceiver = XCVR_INTERNAL;
  1561. status = RTL_R32(TBICSR);
  1562. cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
  1563. cmd->autoneg = !!(status & TBINwEnable);
  1564. ethtool_cmd_speed_set(cmd, SPEED_1000);
  1565. cmd->duplex = DUPLEX_FULL; /* Always set */
  1566. return 0;
  1567. }
  1568. static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
  1569. {
  1570. struct rtl8169_private *tp = netdev_priv(dev);
  1571. return mii_ethtool_gset(&tp->mii, cmd);
  1572. }
  1573. static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  1574. {
  1575. struct rtl8169_private *tp = netdev_priv(dev);
  1576. int rc;
  1577. rtl_lock_work(tp);
  1578. rc = tp->get_settings(dev, cmd);
  1579. rtl_unlock_work(tp);
  1580. return rc;
  1581. }
  1582. static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
  1583. void *p)
  1584. {
  1585. struct rtl8169_private *tp = netdev_priv(dev);
  1586. u32 __iomem *data = tp->mmio_addr;
  1587. u32 *dw = p;
  1588. int i;
  1589. rtl_lock_work(tp);
  1590. for (i = 0; i < R8169_REGS_SIZE; i += 4)
  1591. memcpy_fromio(dw++, data++, 4);
  1592. rtl_unlock_work(tp);
  1593. }
  1594. static u32 rtl8169_get_msglevel(struct net_device *dev)
  1595. {
  1596. struct rtl8169_private *tp = netdev_priv(dev);
  1597. return tp->msg_enable;
  1598. }
  1599. static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
  1600. {
  1601. struct rtl8169_private *tp = netdev_priv(dev);
  1602. tp->msg_enable = value;
  1603. }
  1604. static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
  1605. "tx_packets",
  1606. "rx_packets",
  1607. "tx_errors",
  1608. "rx_errors",
  1609. "rx_missed",
  1610. "align_errors",
  1611. "tx_single_collisions",
  1612. "tx_multi_collisions",
  1613. "unicast",
  1614. "broadcast",
  1615. "multicast",
  1616. "tx_aborted",
  1617. "tx_underrun",
  1618. };
  1619. static int rtl8169_get_sset_count(struct net_device *dev, int sset)
  1620. {
  1621. switch (sset) {
  1622. case ETH_SS_STATS:
  1623. return ARRAY_SIZE(rtl8169_gstrings);
  1624. default:
  1625. return -EOPNOTSUPP;
  1626. }
  1627. }
  1628. DECLARE_RTL_COND(rtl_counters_cond)
  1629. {
  1630. void __iomem *ioaddr = tp->mmio_addr;
  1631. return RTL_R32(CounterAddrLow) & CounterDump;
  1632. }
  1633. static void rtl8169_update_counters(struct net_device *dev)
  1634. {
  1635. struct rtl8169_private *tp = netdev_priv(dev);
  1636. void __iomem *ioaddr = tp->mmio_addr;
  1637. struct device *d = &tp->pci_dev->dev;
  1638. struct rtl8169_counters *counters;
  1639. dma_addr_t paddr;
  1640. u32 cmd;
  1641. /*
  1642. * Some chips are unable to dump tally counters when the receiver
  1643. * is disabled.
  1644. */
  1645. if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
  1646. return;
  1647. counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
  1648. if (!counters)
  1649. return;
  1650. RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
  1651. cmd = (u64)paddr & DMA_BIT_MASK(32);
  1652. RTL_W32(CounterAddrLow, cmd);
  1653. RTL_W32(CounterAddrLow, cmd | CounterDump);
  1654. if (rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000))
  1655. memcpy(&tp->counters, counters, sizeof(*counters));
  1656. RTL_W32(CounterAddrLow, 0);
  1657. RTL_W32(CounterAddrHigh, 0);
  1658. dma_free_coherent(d, sizeof(*counters), counters, paddr);
  1659. }
  1660. static void rtl8169_get_ethtool_stats(struct net_device *dev,
  1661. struct ethtool_stats *stats, u64 *data)
  1662. {
  1663. struct rtl8169_private *tp = netdev_priv(dev);
  1664. ASSERT_RTNL();
  1665. rtl8169_update_counters(dev);
  1666. data[0] = le64_to_cpu(tp->counters.tx_packets);
  1667. data[1] = le64_to_cpu(tp->counters.rx_packets);
  1668. data[2] = le64_to_cpu(tp->counters.tx_errors);
  1669. data[3] = le32_to_cpu(tp->counters.rx_errors);
  1670. data[4] = le16_to_cpu(tp->counters.rx_missed);
  1671. data[5] = le16_to_cpu(tp->counters.align_errors);
  1672. data[6] = le32_to_cpu(tp->counters.tx_one_collision);
  1673. data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
  1674. data[8] = le64_to_cpu(tp->counters.rx_unicast);
  1675. data[9] = le64_to_cpu(tp->counters.rx_broadcast);
  1676. data[10] = le32_to_cpu(tp->counters.rx_multicast);
  1677. data[11] = le16_to_cpu(tp->counters.tx_aborted);
  1678. data[12] = le16_to_cpu(tp->counters.tx_underun);
  1679. }
  1680. static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
  1681. {
  1682. switch(stringset) {
  1683. case ETH_SS_STATS:
  1684. memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
  1685. break;
  1686. }
  1687. }
  1688. static const struct ethtool_ops rtl8169_ethtool_ops = {
  1689. .get_drvinfo = rtl8169_get_drvinfo,
  1690. .get_regs_len = rtl8169_get_regs_len,
  1691. .get_link = ethtool_op_get_link,
  1692. .get_settings = rtl8169_get_settings,
  1693. .set_settings = rtl8169_set_settings,
  1694. .get_msglevel = rtl8169_get_msglevel,
  1695. .set_msglevel = rtl8169_set_msglevel,
  1696. .get_regs = rtl8169_get_regs,
  1697. .get_wol = rtl8169_get_wol,
  1698. .set_wol = rtl8169_set_wol,
  1699. .get_strings = rtl8169_get_strings,
  1700. .get_sset_count = rtl8169_get_sset_count,
  1701. .get_ethtool_stats = rtl8169_get_ethtool_stats,
  1702. .get_ts_info = ethtool_op_get_ts_info,
  1703. };
  1704. static void rtl8169_get_mac_version(struct rtl8169_private *tp,
  1705. struct net_device *dev, u8 default_version)
  1706. {
  1707. void __iomem *ioaddr = tp->mmio_addr;
  1708. /*
  1709. * The driver currently handles the 8168Bf and the 8168Be identically
  1710. * but they can be identified more specifically through the test below
  1711. * if needed:
  1712. *
  1713. * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
  1714. *
  1715. * Same thing for the 8101Eb and the 8101Ec:
  1716. *
  1717. * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
  1718. */
  1719. static const struct rtl_mac_info {
  1720. u32 mask;
  1721. u32 val;
  1722. int mac_version;
  1723. } mac_info[] = {
  1724. /* 8168G family. */
  1725. { 0x7cf00000, 0x5c800000, RTL_GIGA_MAC_VER_44 },
  1726. { 0x7cf00000, 0x50900000, RTL_GIGA_MAC_VER_42 },
  1727. { 0x7cf00000, 0x4c100000, RTL_GIGA_MAC_VER_41 },
  1728. { 0x7cf00000, 0x4c000000, RTL_GIGA_MAC_VER_40 },
  1729. /* 8168F family. */
  1730. { 0x7c800000, 0x48800000, RTL_GIGA_MAC_VER_38 },
  1731. { 0x7cf00000, 0x48100000, RTL_GIGA_MAC_VER_36 },
  1732. { 0x7cf00000, 0x48000000, RTL_GIGA_MAC_VER_35 },
  1733. /* 8168E family. */
  1734. { 0x7c800000, 0x2c800000, RTL_GIGA_MAC_VER_34 },
  1735. { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33 },
  1736. { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 },
  1737. { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 },
  1738. /* 8168D family. */
  1739. { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
  1740. { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
  1741. { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
  1742. /* 8168DP family. */
  1743. { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 },
  1744. { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 },
  1745. { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31 },
  1746. /* 8168C family. */
  1747. { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 },
  1748. { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
  1749. { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
  1750. { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
  1751. { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
  1752. { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
  1753. { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
  1754. { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
  1755. { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
  1756. /* 8168B family. */
  1757. { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
  1758. { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
  1759. { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
  1760. { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
  1761. /* 8101 family. */
  1762. { 0x7cf00000, 0x44900000, RTL_GIGA_MAC_VER_39 },
  1763. { 0x7c800000, 0x44800000, RTL_GIGA_MAC_VER_39 },
  1764. { 0x7c800000, 0x44000000, RTL_GIGA_MAC_VER_37 },
  1765. { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30 },
  1766. { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30 },
  1767. { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 },
  1768. { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 },
  1769. { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
  1770. { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
  1771. { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
  1772. { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
  1773. { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
  1774. { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
  1775. { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
  1776. { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
  1777. { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
  1778. { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
  1779. { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
  1780. { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
  1781. /* FIXME: where did these entries come from ? -- FR */
  1782. { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
  1783. { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
  1784. /* 8110 family. */
  1785. { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
  1786. { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
  1787. { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
  1788. { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
  1789. { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
  1790. { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
  1791. /* Catch-all */
  1792. { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
  1793. };
  1794. const struct rtl_mac_info *p = mac_info;
  1795. u32 reg;
  1796. reg = RTL_R32(TxConfig);
  1797. while ((reg & p->mask) != p->val)
  1798. p++;
  1799. tp->mac_version = p->mac_version;
  1800. if (tp->mac_version == RTL_GIGA_MAC_NONE) {
  1801. netif_notice(tp, probe, dev,
  1802. "unknown MAC, using family default\n");
  1803. tp->mac_version = default_version;
  1804. } else if (tp->mac_version == RTL_GIGA_MAC_VER_42) {
  1805. tp->mac_version = tp->mii.supports_gmii ?
  1806. RTL_GIGA_MAC_VER_42 :
  1807. RTL_GIGA_MAC_VER_43;
  1808. }
  1809. }
  1810. static void rtl8169_print_mac_version(struct rtl8169_private *tp)
  1811. {
  1812. dprintk("mac_version = 0x%02x\n", tp->mac_version);
  1813. }
  1814. struct phy_reg {
  1815. u16 reg;
  1816. u16 val;
  1817. };
  1818. static void rtl_writephy_batch(struct rtl8169_private *tp,
  1819. const struct phy_reg *regs, int len)
  1820. {
  1821. while (len-- > 0) {
  1822. rtl_writephy(tp, regs->reg, regs->val);
  1823. regs++;
  1824. }
  1825. }
  1826. #define PHY_READ 0x00000000
  1827. #define PHY_DATA_OR 0x10000000
  1828. #define PHY_DATA_AND 0x20000000
  1829. #define PHY_BJMPN 0x30000000
  1830. #define PHY_MDIO_CHG 0x40000000
  1831. #define PHY_CLEAR_READCOUNT 0x70000000
  1832. #define PHY_WRITE 0x80000000
  1833. #define PHY_READCOUNT_EQ_SKIP 0x90000000
  1834. #define PHY_COMP_EQ_SKIPN 0xa0000000
  1835. #define PHY_COMP_NEQ_SKIPN 0xb0000000
  1836. #define PHY_WRITE_PREVIOUS 0xc0000000
  1837. #define PHY_SKIPN 0xd0000000
  1838. #define PHY_DELAY_MS 0xe0000000
  1839. struct fw_info {
  1840. u32 magic;
  1841. char version[RTL_VER_SIZE];
  1842. __le32 fw_start;
  1843. __le32 fw_len;
  1844. u8 chksum;
  1845. } __packed;
  1846. #define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
  1847. static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
  1848. {
  1849. const struct firmware *fw = rtl_fw->fw;
  1850. struct fw_info *fw_info = (struct fw_info *)fw->data;
  1851. struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
  1852. char *version = rtl_fw->version;
  1853. bool rc = false;
  1854. if (fw->size < FW_OPCODE_SIZE)
  1855. goto out;
  1856. if (!fw_info->magic) {
  1857. size_t i, size, start;
  1858. u8 checksum = 0;
  1859. if (fw->size < sizeof(*fw_info))
  1860. goto out;
  1861. for (i = 0; i < fw->size; i++)
  1862. checksum += fw->data[i];
  1863. if (checksum != 0)
  1864. goto out;
  1865. start = le32_to_cpu(fw_info->fw_start);
  1866. if (start > fw->size)
  1867. goto out;
  1868. size = le32_to_cpu(fw_info->fw_len);
  1869. if (size > (fw->size - start) / FW_OPCODE_SIZE)
  1870. goto out;
  1871. memcpy(version, fw_info->version, RTL_VER_SIZE);
  1872. pa->code = (__le32 *)(fw->data + start);
  1873. pa->size = size;
  1874. } else {
  1875. if (fw->size % FW_OPCODE_SIZE)
  1876. goto out;
  1877. strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
  1878. pa->code = (__le32 *)fw->data;
  1879. pa->size = fw->size / FW_OPCODE_SIZE;
  1880. }
  1881. version[RTL_VER_SIZE - 1] = 0;
  1882. rc = true;
  1883. out:
  1884. return rc;
  1885. }
  1886. static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
  1887. struct rtl_fw_phy_action *pa)
  1888. {
  1889. bool rc = false;
  1890. size_t index;
  1891. for (index = 0; index < pa->size; index++) {
  1892. u32 action = le32_to_cpu(pa->code[index]);
  1893. u32 regno = (action & 0x0fff0000) >> 16;
  1894. switch(action & 0xf0000000) {
  1895. case PHY_READ:
  1896. case PHY_DATA_OR:
  1897. case PHY_DATA_AND:
  1898. case PHY_MDIO_CHG:
  1899. case PHY_CLEAR_READCOUNT:
  1900. case PHY_WRITE:
  1901. case PHY_WRITE_PREVIOUS:
  1902. case PHY_DELAY_MS:
  1903. break;
  1904. case PHY_BJMPN:
  1905. if (regno > index) {
  1906. netif_err(tp, ifup, tp->dev,
  1907. "Out of range of firmware\n");
  1908. goto out;
  1909. }
  1910. break;
  1911. case PHY_READCOUNT_EQ_SKIP:
  1912. if (index + 2 >= pa->size) {
  1913. netif_err(tp, ifup, tp->dev,
  1914. "Out of range of firmware\n");
  1915. goto out;
  1916. }
  1917. break;
  1918. case PHY_COMP_EQ_SKIPN:
  1919. case PHY_COMP_NEQ_SKIPN:
  1920. case PHY_SKIPN:
  1921. if (index + 1 + regno >= pa->size) {
  1922. netif_err(tp, ifup, tp->dev,
  1923. "Out of range of firmware\n");
  1924. goto out;
  1925. }
  1926. break;
  1927. default:
  1928. netif_err(tp, ifup, tp->dev,
  1929. "Invalid action 0x%08x\n", action);
  1930. goto out;
  1931. }
  1932. }
  1933. rc = true;
  1934. out:
  1935. return rc;
  1936. }
  1937. static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
  1938. {
  1939. struct net_device *dev = tp->dev;
  1940. int rc = -EINVAL;
  1941. if (!rtl_fw_format_ok(tp, rtl_fw)) {
  1942. netif_err(tp, ifup, dev, "invalid firwmare\n");
  1943. goto out;
  1944. }
  1945. if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
  1946. rc = 0;
  1947. out:
  1948. return rc;
  1949. }
  1950. static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
  1951. {
  1952. struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
  1953. struct mdio_ops org, *ops = &tp->mdio_ops;
  1954. u32 predata, count;
  1955. size_t index;
  1956. predata = count = 0;
  1957. org.write = ops->write;
  1958. org.read = ops->read;
  1959. for (index = 0; index < pa->size; ) {
  1960. u32 action = le32_to_cpu(pa->code[index]);
  1961. u32 data = action & 0x0000ffff;
  1962. u32 regno = (action & 0x0fff0000) >> 16;
  1963. if (!action)
  1964. break;
  1965. switch(action & 0xf0000000) {
  1966. case PHY_READ:
  1967. predata = rtl_readphy(tp, regno);
  1968. count++;
  1969. index++;
  1970. break;
  1971. case PHY_DATA_OR:
  1972. predata |= data;
  1973. index++;
  1974. break;
  1975. case PHY_DATA_AND:
  1976. predata &= data;
  1977. index++;
  1978. break;
  1979. case PHY_BJMPN:
  1980. index -= regno;
  1981. break;
  1982. case PHY_MDIO_CHG:
  1983. if (data == 0) {
  1984. ops->write = org.write;
  1985. ops->read = org.read;
  1986. } else if (data == 1) {
  1987. ops->write = mac_mcu_write;
  1988. ops->read = mac_mcu_read;
  1989. }
  1990. index++;
  1991. break;
  1992. case PHY_CLEAR_READCOUNT:
  1993. count = 0;
  1994. index++;
  1995. break;
  1996. case PHY_WRITE:
  1997. rtl_writephy(tp, regno, data);
  1998. index++;
  1999. break;
  2000. case PHY_READCOUNT_EQ_SKIP:
  2001. index += (count == data) ? 2 : 1;
  2002. break;
  2003. case PHY_COMP_EQ_SKIPN:
  2004. if (predata == data)
  2005. index += regno;
  2006. index++;
  2007. break;
  2008. case PHY_COMP_NEQ_SKIPN:
  2009. if (predata != data)
  2010. index += regno;
  2011. index++;
  2012. break;
  2013. case PHY_WRITE_PREVIOUS:
  2014. rtl_writephy(tp, regno, predata);
  2015. index++;
  2016. break;
  2017. case PHY_SKIPN:
  2018. index += regno + 1;
  2019. break;
  2020. case PHY_DELAY_MS:
  2021. mdelay(data);
  2022. index++;
  2023. break;
  2024. default:
  2025. BUG();
  2026. }
  2027. }
  2028. ops->write = org.write;
  2029. ops->read = org.read;
  2030. }
  2031. static void rtl_release_firmware(struct rtl8169_private *tp)
  2032. {
  2033. if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
  2034. release_firmware(tp->rtl_fw->fw);
  2035. kfree(tp->rtl_fw);
  2036. }
  2037. tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
  2038. }
  2039. static void rtl_apply_firmware(struct rtl8169_private *tp)
  2040. {
  2041. struct rtl_fw *rtl_fw = tp->rtl_fw;
  2042. /* TODO: release firmware once rtl_phy_write_fw signals failures. */
  2043. if (!IS_ERR_OR_NULL(rtl_fw))
  2044. rtl_phy_write_fw(tp, rtl_fw);
  2045. }
  2046. static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
  2047. {
  2048. if (rtl_readphy(tp, reg) != val)
  2049. netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
  2050. else
  2051. rtl_apply_firmware(tp);
  2052. }
  2053. static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
  2054. {
  2055. static const struct phy_reg phy_reg_init[] = {
  2056. { 0x1f, 0x0001 },
  2057. { 0x06, 0x006e },
  2058. { 0x08, 0x0708 },
  2059. { 0x15, 0x4000 },
  2060. { 0x18, 0x65c7 },
  2061. { 0x1f, 0x0001 },
  2062. { 0x03, 0x00a1 },
  2063. { 0x02, 0x0008 },
  2064. { 0x01, 0x0120 },
  2065. { 0x00, 0x1000 },
  2066. { 0x04, 0x0800 },
  2067. { 0x04, 0x0000 },
  2068. { 0x03, 0xff41 },
  2069. { 0x02, 0xdf60 },
  2070. { 0x01, 0x0140 },
  2071. { 0x00, 0x0077 },
  2072. { 0x04, 0x7800 },
  2073. { 0x04, 0x7000 },
  2074. { 0x03, 0x802f },
  2075. { 0x02, 0x4f02 },
  2076. { 0x01, 0x0409 },
  2077. { 0x00, 0xf0f9 },
  2078. { 0x04, 0x9800 },
  2079. { 0x04, 0x9000 },
  2080. { 0x03, 0xdf01 },
  2081. { 0x02, 0xdf20 },
  2082. { 0x01, 0xff95 },
  2083. { 0x00, 0xba00 },
  2084. { 0x04, 0xa800 },
  2085. { 0x04, 0xa000 },
  2086. { 0x03, 0xff41 },
  2087. { 0x02, 0xdf20 },
  2088. { 0x01, 0x0140 },
  2089. { 0x00, 0x00bb },
  2090. { 0x04, 0xb800 },
  2091. { 0x04, 0xb000 },
  2092. { 0x03, 0xdf41 },
  2093. { 0x02, 0xdc60 },
  2094. { 0x01, 0x6340 },
  2095. { 0x00, 0x007d },
  2096. { 0x04, 0xd800 },
  2097. { 0x04, 0xd000 },
  2098. { 0x03, 0xdf01 },
  2099. { 0x02, 0xdf20 },
  2100. { 0x01, 0x100a },
  2101. { 0x00, 0xa0ff },
  2102. { 0x04, 0xf800 },
  2103. { 0x04, 0xf000 },
  2104. { 0x1f, 0x0000 },
  2105. { 0x0b, 0x0000 },
  2106. { 0x00, 0x9200 }
  2107. };
  2108. rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
  2109. }
  2110. static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
  2111. {
  2112. static const struct phy_reg phy_reg_init[] = {
  2113. { 0x1f, 0x0002 },
  2114. { 0x01, 0x90d0 },
  2115. { 0x1f, 0x0000 }
  2116. };
  2117. rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
  2118. }
  2119. static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
  2120. {
  2121. struct pci_dev *pdev = tp->pci_dev;
  2122. if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
  2123. (pdev->subsystem_device != 0xe000))
  2124. return;
  2125. rtl_writephy(tp, 0x1f, 0x0001);
  2126. rtl_writephy(tp, 0x10, 0xf01b);
  2127. rtl_writephy(tp, 0x1f, 0x0000);
  2128. }
  2129. static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
  2130. {
  2131. static const struct phy_reg phy_reg_init[] = {
  2132. { 0x1f, 0x0001 },
  2133. { 0x04, 0x0000 },
  2134. { 0x03, 0x00a1 },
  2135. { 0x02, 0x0008 },
  2136. { 0x01, 0x0120 },
  2137. { 0x00, 0x1000 },
  2138. { 0x04, 0x0800 },
  2139. { 0x04, 0x9000 },
  2140. { 0x03, 0x802f },
  2141. { 0x02, 0x4f02 },
  2142. { 0x01, 0x0409 },
  2143. { 0x00, 0xf099 },
  2144. { 0x04, 0x9800 },
  2145. { 0x04, 0xa000 },
  2146. { 0x03, 0xdf01 },
  2147. { 0x02, 0xdf20 },
  2148. { 0x01, 0xff95 },
  2149. { 0x00, 0xba00 },
  2150. { 0x04, 0xa800 },
  2151. { 0x04, 0xf000 },
  2152. { 0x03, 0xdf01 },
  2153. { 0x02, 0xdf20 },
  2154. { 0x01, 0x101a },
  2155. { 0x00, 0xa0ff },
  2156. { 0x04, 0xf800 },
  2157. { 0x04, 0x0000 },
  2158. { 0x1f, 0x0000 },
  2159. { 0x1f, 0x0001 },
  2160. { 0x10, 0xf41b },
  2161. { 0x14, 0xfb54 },
  2162. { 0x18, 0xf5c7 },
  2163. { 0x1f, 0x0000 },
  2164. { 0x1f, 0x0001 },
  2165. { 0x17, 0x0cc0 },
  2166. { 0x1f, 0x0000 }
  2167. };
  2168. rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
  2169. rtl8169scd_hw_phy_config_quirk(tp);
  2170. }
  2171. static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
  2172. {
  2173. static const struct phy_reg phy_reg_init[] = {
  2174. { 0x1f, 0x0001 },
  2175. { 0x04, 0x0000 },
  2176. { 0x03, 0x00a1 },
  2177. { 0x02, 0x0008 },
  2178. { 0x01, 0x0120 },
  2179. { 0x00, 0x1000 },
  2180. { 0x04, 0x0800 },
  2181. { 0x04, 0x9000 },
  2182. { 0x03, 0x802f },
  2183. { 0x02, 0x4f02 },
  2184. { 0x01, 0x0409 },
  2185. { 0x00, 0xf099 },
  2186. { 0x04, 0x9800 },
  2187. { 0x04, 0xa000 },
  2188. { 0x03, 0xdf01 },
  2189. { 0x02, 0xdf20 },
  2190. { 0x01, 0xff95 },
  2191. { 0x00, 0xba00 },
  2192. { 0x04, 0xa800 },
  2193. { 0x04, 0xf000 },
  2194. { 0x03, 0xdf01 },
  2195. { 0x02, 0xdf20 },
  2196. { 0x01, 0x101a },
  2197. { 0x00, 0xa0ff },
  2198. { 0x04, 0xf800 },
  2199. { 0x04, 0x0000 },
  2200. { 0x1f, 0x0000 },
  2201. { 0x1f, 0x0001 },
  2202. { 0x0b, 0x8480 },
  2203. { 0x1f, 0x0000 },
  2204. { 0x1f, 0x0001 },
  2205. { 0x18, 0x67c7 },
  2206. { 0x04, 0x2000 },
  2207. { 0x03, 0x002f },
  2208. { 0x02, 0x4360 },
  2209. { 0x01, 0x0109 },
  2210. { 0x00, 0x3022 },
  2211. { 0x04, 0x2800 },
  2212. { 0x1f, 0x0000 },
  2213. { 0x1f, 0x0001 },
  2214. { 0x17, 0x0cc0 },
  2215. { 0x1f, 0x0000 }
  2216. };
  2217. rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
  2218. }
  2219. static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
  2220. {
  2221. static const struct phy_reg phy_reg_init[] = {
  2222. { 0x10, 0xf41b },
  2223. { 0x1f, 0x0000 }
  2224. };
  2225. rtl_writephy(tp, 0x1f, 0x0001);
  2226. rtl_patchphy(tp, 0x16, 1 << 0);
  2227. rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
  2228. }
  2229. static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
  2230. {
  2231. static const struct phy_reg phy_reg_init[] = {
  2232. { 0x1f, 0x0001 },
  2233. { 0x10, 0xf41b },
  2234. { 0x1f, 0x0000 }
  2235. };
  2236. rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
  2237. }
  2238. static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
  2239. {
  2240. static const struct phy_reg phy_reg_init[] = {
  2241. { 0x1f, 0x0000 },
  2242. { 0x1d, 0x0f00 },
  2243. { 0x1f, 0x0002 },
  2244. { 0x0c, 0x1ec8 },
  2245. { 0x1f, 0x0000 }
  2246. };
  2247. rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
  2248. }
  2249. static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
  2250. {
  2251. static const struct phy_reg phy_reg_init[] = {
  2252. { 0x1f, 0x0001 },
  2253. { 0x1d, 0x3d98 },
  2254. { 0x1f, 0x0000 }
  2255. };
  2256. rtl_writephy(tp, 0x1f, 0x0000);
  2257. rtl_patchphy(tp, 0x14, 1 << 5);
  2258. rtl_patchphy(tp, 0x0d, 1 << 5);
  2259. rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
  2260. }
  2261. static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
  2262. {
  2263. static const struct phy_reg phy_reg_init[] = {
  2264. { 0x1f, 0x0001 },
  2265. { 0x12, 0x2300 },
  2266. { 0x1f, 0x0002 },
  2267. { 0x00, 0x88d4 },
  2268. { 0x01, 0x82b1 },
  2269. { 0x03, 0x7002 },
  2270. { 0x08, 0x9e30 },
  2271. { 0x09, 0x01f0 },
  2272. { 0x0a, 0x5500 },
  2273. { 0x0c, 0x00c8 },
  2274. { 0x1f, 0x0003 },
  2275. { 0x12, 0xc096 },
  2276. { 0x16, 0x000a },
  2277. { 0x1f, 0x0000 },
  2278. { 0x1f, 0x0000 },
  2279. { 0x09, 0x2000 },
  2280. { 0x09, 0x0000 }
  2281. };
  2282. rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
  2283. rtl_patchphy(tp, 0x14, 1 << 5);
  2284. rtl_patchphy(tp, 0x0d, 1 << 5);
  2285. rtl_writephy(tp, 0x1f, 0x0000);
  2286. }
  2287. static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
  2288. {
  2289. static const struct phy_reg phy_reg_init[] = {
  2290. { 0x1f, 0x0001 },
  2291. { 0x12, 0x2300 },
  2292. { 0x03, 0x802f },
  2293. { 0x02, 0x4f02 },
  2294. { 0x01, 0x0409 },
  2295. { 0x00, 0xf099 },
  2296. { 0x04, 0x9800 },
  2297. { 0x04, 0x9000 },
  2298. { 0x1d, 0x3d98 },
  2299. { 0x1f, 0x0002 },
  2300. { 0x0c, 0x7eb8 },
  2301. { 0x06, 0x0761 },
  2302. { 0x1f, 0x0003 },
  2303. { 0x16, 0x0f0a },
  2304. { 0x1f, 0x0000 }
  2305. };
  2306. rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
  2307. rtl_patchphy(tp, 0x16, 1 << 0);
  2308. rtl_patchphy(tp, 0x14, 1 << 5);
  2309. rtl_patchphy(tp, 0x0d, 1 << 5);
  2310. rtl_writephy(tp, 0x1f, 0x0000);
  2311. }
  2312. static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
  2313. {
  2314. static const struct phy_reg phy_reg_init[] = {
  2315. { 0x1f, 0x0001 },
  2316. { 0x12, 0x2300 },
  2317. { 0x1d, 0x3d98 },
  2318. { 0x1f, 0x0002 },
  2319. { 0x0c, 0x7eb8 },
  2320. { 0x06, 0x5461 },
  2321. { 0x1f, 0x0003 },
  2322. { 0x16, 0x0f0a },
  2323. { 0x1f, 0x0000 }
  2324. };
  2325. rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
  2326. rtl_patchphy(tp, 0x16, 1 << 0);
  2327. rtl_patchphy(tp, 0x14, 1 << 5);
  2328. rtl_patchphy(tp, 0x0d, 1 << 5);
  2329. rtl_writephy(tp, 0x1f, 0x0000);
  2330. }
  2331. static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
  2332. {
  2333. rtl8168c_3_hw_phy_config(tp);
  2334. }
  2335. static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
  2336. {
  2337. static const struct phy_reg phy_reg_init_0[] = {
  2338. /* Channel Estimation */
  2339. { 0x1f, 0x0001 },
  2340. { 0x06, 0x4064 },
  2341. { 0x07, 0x2863 },
  2342. { 0x08, 0x059c },
  2343. { 0x09, 0x26b4 },
  2344. { 0x0a, 0x6a19 },
  2345. { 0x0b, 0xdcc8 },
  2346. { 0x10, 0xf06d },
  2347. { 0x14, 0x7f68 },
  2348. { 0x18, 0x7fd9 },
  2349. { 0x1c, 0xf0ff },
  2350. { 0x1d, 0x3d9c },
  2351. { 0x1f, 0x0003 },
  2352. { 0x12, 0xf49f },
  2353. { 0x13, 0x070b },
  2354. { 0x1a, 0x05ad },
  2355. { 0x14, 0x94c0 },
  2356. /*
  2357. * Tx Error Issue
  2358. * Enhance line driver power
  2359. */
  2360. { 0x1f, 0x0002 },
  2361. { 0x06, 0x5561 },
  2362. { 0x1f, 0x0005 },
  2363. { 0x05, 0x8332 },
  2364. { 0x06, 0x5561 },
  2365. /*
  2366. * Can not link to 1Gbps with bad cable
  2367. * Decrease SNR threshold form 21.07dB to 19.04dB
  2368. */
  2369. { 0x1f, 0x0001 },
  2370. { 0x17, 0x0cc0 },
  2371. { 0x1f, 0x0000 },
  2372. { 0x0d, 0xf880 }
  2373. };
  2374. rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
  2375. /*
  2376. * Rx Error Issue
  2377. * Fine Tune Switching regulator parameter
  2378. */
  2379. rtl_writephy(tp, 0x1f, 0x0002);
  2380. rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
  2381. rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
  2382. if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
  2383. static const struct phy_reg phy_reg_init[] = {
  2384. { 0x1f, 0x0002 },
  2385. { 0x05, 0x669a },
  2386. { 0x1f, 0x0005 },
  2387. { 0x05, 0x8330 },
  2388. { 0x06, 0x669a },
  2389. { 0x1f, 0x0002 }
  2390. };
  2391. int val;
  2392. rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
  2393. val = rtl_readphy(tp, 0x0d);
  2394. if ((val & 0x00ff) != 0x006c) {
  2395. static const u32 set[] = {
  2396. 0x0065, 0x0066, 0x0067, 0x0068,
  2397. 0x0069, 0x006a, 0x006b, 0x006c
  2398. };
  2399. int i;
  2400. rtl_writephy(tp, 0x1f, 0x0002);
  2401. val &= 0xff00;
  2402. for (i = 0; i < ARRAY_SIZE(set); i++)
  2403. rtl_writephy(tp, 0x0d, val | set[i]);
  2404. }
  2405. } else {
  2406. static const struct phy_reg phy_reg_init[] = {
  2407. { 0x1f, 0x0002 },
  2408. { 0x05, 0x6662 },
  2409. { 0x1f, 0x0005 },
  2410. { 0x05, 0x8330 },
  2411. { 0x06, 0x6662 }
  2412. };
  2413. rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
  2414. }
  2415. /* RSET couple improve */
  2416. rtl_writephy(tp, 0x1f, 0x0002);
  2417. rtl_patchphy(tp, 0x0d, 0x0300);
  2418. rtl_patchphy(tp, 0x0f, 0x0010);
  2419. /* Fine tune PLL performance */
  2420. rtl_writephy(tp, 0x1f, 0x0002);
  2421. rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
  2422. rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
  2423. rtl_writephy(tp, 0x1f, 0x0005);
  2424. rtl_writephy(tp, 0x05, 0x001b);
  2425. rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
  2426. rtl_writephy(tp, 0x1f, 0x0000);
  2427. }
  2428. static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
  2429. {
  2430. static const struct phy_reg phy_reg_init_0[] = {
  2431. /* Channel Estimation */
  2432. { 0x1f, 0x0001 },
  2433. { 0x06, 0x4064 },
  2434. { 0x07, 0x2863 },
  2435. { 0x08, 0x059c },
  2436. { 0x09, 0x26b4 },
  2437. { 0x0a, 0x6a19 },
  2438. { 0x0b, 0xdcc8 },
  2439. { 0x10, 0xf06d },
  2440. { 0x14, 0x7f68 },
  2441. { 0x18, 0x7fd9 },
  2442. { 0x1c, 0xf0ff },
  2443. { 0x1d, 0x3d9c },
  2444. { 0x1f, 0x0003 },
  2445. { 0x12, 0xf49f },
  2446. { 0x13, 0x070b },
  2447. { 0x1a, 0x05ad },
  2448. { 0x14, 0x94c0 },
  2449. /*
  2450. * Tx Error Issue
  2451. * Enhance line driver power
  2452. */
  2453. { 0x1f, 0x0002 },
  2454. { 0x06, 0x5561 },
  2455. { 0x1f, 0x0005 },
  2456. { 0x05, 0x8332 },
  2457. { 0x06, 0x5561 },
  2458. /*
  2459. * Can not link to 1Gbps with bad cable
  2460. * Decrease SNR threshold form 21.07dB to 19.04dB
  2461. */
  2462. { 0x1f, 0x0001 },
  2463. { 0x17, 0x0cc0 },
  2464. { 0x1f, 0x0000 },
  2465. { 0x0d, 0xf880 }
  2466. };
  2467. rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
  2468. if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
  2469. static const struct phy_reg phy_reg_init[] = {
  2470. { 0x1f, 0x0002 },
  2471. { 0x05, 0x669a },
  2472. { 0x1f, 0x0005 },
  2473. { 0x05, 0x8330 },
  2474. { 0x06, 0x669a },
  2475. { 0x1f, 0x0002 }
  2476. };
  2477. int val;
  2478. rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
  2479. val = rtl_readphy(tp, 0x0d);
  2480. if ((val & 0x00ff) != 0x006c) {
  2481. static const u32 set[] = {
  2482. 0x0065, 0x0066, 0x0067, 0x0068,
  2483. 0x0069, 0x006a, 0x006b, 0x006c
  2484. };
  2485. int i;
  2486. rtl_writephy(tp, 0x1f, 0x0002);
  2487. val &= 0xff00;
  2488. for (i = 0; i < ARRAY_SIZE(set); i++)
  2489. rtl_writephy(tp, 0x0d, val | set[i]);
  2490. }
  2491. } else {
  2492. static const struct phy_reg phy_reg_init[] = {
  2493. { 0x1f, 0x0002 },
  2494. { 0x05, 0x2642 },
  2495. { 0x1f, 0x0005 },
  2496. { 0x05, 0x8330 },
  2497. { 0x06, 0x2642 }
  2498. };
  2499. rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
  2500. }
  2501. /* Fine tune PLL performance */
  2502. rtl_writephy(tp, 0x1f, 0x0002);
  2503. rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
  2504. rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
  2505. /* Switching regulator Slew rate */
  2506. rtl_writephy(tp, 0x1f, 0x0002);
  2507. rtl_patchphy(tp, 0x0f, 0x0017);
  2508. rtl_writephy(tp, 0x1f, 0x0005);
  2509. rtl_writephy(tp, 0x05, 0x001b);
  2510. rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
  2511. rtl_writephy(tp, 0x1f, 0x0000);
  2512. }
  2513. static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
  2514. {
  2515. static const struct phy_reg phy_reg_init[] = {
  2516. { 0x1f, 0x0002 },
  2517. { 0x10, 0x0008 },
  2518. { 0x0d, 0x006c },
  2519. { 0x1f, 0x0000 },
  2520. { 0x0d, 0xf880 },
  2521. { 0x1f, 0x0001 },
  2522. { 0x17, 0x0cc0 },
  2523. { 0x1f, 0x0001 },
  2524. { 0x0b, 0xa4d8 },
  2525. { 0x09, 0x281c },
  2526. { 0x07, 0x2883 },
  2527. { 0x0a, 0x6b35 },
  2528. { 0x1d, 0x3da4 },
  2529. { 0x1c, 0xeffd },
  2530. { 0x14, 0x7f52 },
  2531. { 0x18, 0x7fc6 },
  2532. { 0x08, 0x0601 },
  2533. { 0x06, 0x4063 },
  2534. { 0x10, 0xf074 },
  2535. { 0x1f, 0x0003 },
  2536. { 0x13, 0x0789 },
  2537. { 0x12, 0xf4bd },
  2538. { 0x1a, 0x04fd },
  2539. { 0x14, 0x84b0 },
  2540. { 0x1f, 0x0000 },
  2541. { 0x00, 0x9200 },
  2542. { 0x1f, 0x0005 },
  2543. { 0x01, 0x0340 },
  2544. { 0x1f, 0x0001 },
  2545. { 0x04, 0x4000 },
  2546. { 0x03, 0x1d21 },
  2547. { 0x02, 0x0c32 },
  2548. { 0x01, 0x0200 },
  2549. { 0x00, 0x5554 },
  2550. { 0x04, 0x4800 },
  2551. { 0x04, 0x4000 },
  2552. { 0x04, 0xf000 },
  2553. { 0x03, 0xdf01 },
  2554. { 0x02, 0xdf20 },
  2555. { 0x01, 0x101a },
  2556. { 0x00, 0xa0ff },
  2557. { 0x04, 0xf800 },
  2558. { 0x04, 0xf000 },
  2559. { 0x1f, 0x0000 },
  2560. { 0x1f, 0x0007 },
  2561. { 0x1e, 0x0023 },
  2562. { 0x16, 0x0000 },
  2563. { 0x1f, 0x0000 }
  2564. };
  2565. rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
  2566. }
  2567. static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
  2568. {
  2569. static const struct phy_reg phy_reg_init[] = {
  2570. { 0x1f, 0x0001 },
  2571. { 0x17, 0x0cc0 },
  2572. { 0x1f, 0x0007 },
  2573. { 0x1e, 0x002d },
  2574. { 0x18, 0x0040 },
  2575. { 0x1f, 0x0000 }
  2576. };
  2577. rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
  2578. rtl_patchphy(tp, 0x0d, 1 << 5);
  2579. }
  2580. static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
  2581. {
  2582. static const struct phy_reg phy_reg_init[] = {
  2583. /* Enable Delay cap */
  2584. { 0x1f, 0x0005 },
  2585. { 0x05, 0x8b80 },
  2586. { 0x06, 0xc896 },
  2587. { 0x1f, 0x0000 },
  2588. /* Channel estimation fine tune */
  2589. { 0x1f, 0x0001 },
  2590. { 0x0b, 0x6c20 },
  2591. { 0x07, 0x2872 },
  2592. { 0x1c, 0xefff },
  2593. { 0x1f, 0x0003 },
  2594. { 0x14, 0x6420 },
  2595. { 0x1f, 0x0000 },
  2596. /* Update PFM & 10M TX idle timer */
  2597. { 0x1f, 0x0007 },
  2598. { 0x1e, 0x002f },
  2599. { 0x15, 0x1919 },
  2600. { 0x1f, 0x0000 },
  2601. { 0x1f, 0x0007 },
  2602. { 0x1e, 0x00ac },
  2603. { 0x18, 0x0006 },
  2604. { 0x1f, 0x0000 }
  2605. };
  2606. rtl_apply_firmware(tp);
  2607. rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
  2608. /* DCO enable for 10M IDLE Power */
  2609. rtl_writephy(tp, 0x1f, 0x0007);
  2610. rtl_writephy(tp, 0x1e, 0x0023);
  2611. rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
  2612. rtl_writephy(tp, 0x1f, 0x0000);
  2613. /* For impedance matching */
  2614. rtl_writephy(tp, 0x1f, 0x0002);
  2615. rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00);
  2616. rtl_writephy(tp, 0x1f, 0x0000);
  2617. /* PHY auto speed down */
  2618. rtl_writephy(tp, 0x1f, 0x0007);
  2619. rtl_writephy(tp, 0x1e, 0x002d);
  2620. rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000);
  2621. rtl_writephy(tp, 0x1f, 0x0000);
  2622. rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
  2623. rtl_writephy(tp, 0x1f, 0x0005);
  2624. rtl_writephy(tp, 0x05, 0x8b86);
  2625. rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
  2626. rtl_writephy(tp, 0x1f, 0x0000);
  2627. rtl_writephy(tp, 0x1f, 0x0005);
  2628. rtl_writephy(tp, 0x05, 0x8b85);
  2629. rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
  2630. rtl_writephy(tp, 0x1f, 0x0007);
  2631. rtl_writephy(tp, 0x1e, 0x0020);
  2632. rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100);
  2633. rtl_writephy(tp, 0x1f, 0x0006);
  2634. rtl_writephy(tp, 0x00, 0x5a00);
  2635. rtl_writephy(tp, 0x1f, 0x0000);
  2636. rtl_writephy(tp, 0x0d, 0x0007);
  2637. rtl_writephy(tp, 0x0e, 0x003c);
  2638. rtl_writephy(tp, 0x0d, 0x4007);
  2639. rtl_writephy(tp, 0x0e, 0x0000);
  2640. rtl_writephy(tp, 0x0d, 0x0000);
  2641. }
  2642. static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
  2643. {
  2644. const u16 w[] = {
  2645. addr[0] | (addr[1] << 8),
  2646. addr[2] | (addr[3] << 8),
  2647. addr[4] | (addr[5] << 8)
  2648. };
  2649. const struct exgmac_reg e[] = {
  2650. { .addr = 0xe0, ERIAR_MASK_1111, .val = w[0] | (w[1] << 16) },
  2651. { .addr = 0xe4, ERIAR_MASK_1111, .val = w[2] },
  2652. { .addr = 0xf0, ERIAR_MASK_1111, .val = w[0] << 16 },
  2653. { .addr = 0xf4, ERIAR_MASK_1111, .val = w[1] | (w[2] << 16) }
  2654. };
  2655. rtl_write_exgmac_batch(tp, e, ARRAY_SIZE(e));
  2656. }
  2657. static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
  2658. {
  2659. static const struct phy_reg phy_reg_init[] = {
  2660. /* Enable Delay cap */
  2661. { 0x1f, 0x0004 },
  2662. { 0x1f, 0x0007 },
  2663. { 0x1e, 0x00ac },
  2664. { 0x18, 0x0006 },
  2665. { 0x1f, 0x0002 },
  2666. { 0x1f, 0x0000 },
  2667. { 0x1f, 0x0000 },
  2668. /* Channel estimation fine tune */
  2669. { 0x1f, 0x0003 },
  2670. { 0x09, 0xa20f },
  2671. { 0x1f, 0x0000 },
  2672. { 0x1f, 0x0000 },
  2673. /* Green Setting */
  2674. { 0x1f, 0x0005 },
  2675. { 0x05, 0x8b5b },
  2676. { 0x06, 0x9222 },
  2677. { 0x05, 0x8b6d },
  2678. { 0x06, 0x8000 },
  2679. { 0x05, 0x8b76 },
  2680. { 0x06, 0x8000 },
  2681. { 0x1f, 0x0000 }
  2682. };
  2683. rtl_apply_firmware(tp);
  2684. rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
  2685. /* For 4-corner performance improve */
  2686. rtl_writephy(tp, 0x1f, 0x0005);
  2687. rtl_writephy(tp, 0x05, 0x8b80);
  2688. rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
  2689. rtl_writephy(tp, 0x1f, 0x0000);
  2690. /* PHY auto speed down */
  2691. rtl_writephy(tp, 0x1f, 0x0004);
  2692. rtl_writephy(tp, 0x1f, 0x0007);
  2693. rtl_writephy(tp, 0x1e, 0x002d);
  2694. rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
  2695. rtl_writephy(tp, 0x1f, 0x0002);
  2696. rtl_writephy(tp, 0x1f, 0x0000);
  2697. rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
  2698. /* improve 10M EEE waveform */
  2699. rtl_writephy(tp, 0x1f, 0x0005);
  2700. rtl_writephy(tp, 0x05, 0x8b86);
  2701. rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
  2702. rtl_writephy(tp, 0x1f, 0x0000);
  2703. /* Improve 2-pair detection performance */
  2704. rtl_writephy(tp, 0x1f, 0x0005);
  2705. rtl_writephy(tp, 0x05, 0x8b85);
  2706. rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
  2707. rtl_writephy(tp, 0x1f, 0x0000);
  2708. /* EEE setting */
  2709. rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003, ERIAR_EXGMAC);
  2710. rtl_writephy(tp, 0x1f, 0x0005);
  2711. rtl_writephy(tp, 0x05, 0x8b85);
  2712. rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
  2713. rtl_writephy(tp, 0x1f, 0x0004);
  2714. rtl_writephy(tp, 0x1f, 0x0007);
  2715. rtl_writephy(tp, 0x1e, 0x0020);
  2716. rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100);
  2717. rtl_writephy(tp, 0x1f, 0x0002);
  2718. rtl_writephy(tp, 0x1f, 0x0000);
  2719. rtl_writephy(tp, 0x0d, 0x0007);
  2720. rtl_writephy(tp, 0x0e, 0x003c);
  2721. rtl_writephy(tp, 0x0d, 0x4007);
  2722. rtl_writephy(tp, 0x0e, 0x0000);
  2723. rtl_writephy(tp, 0x0d, 0x0000);
  2724. /* Green feature */
  2725. rtl_writephy(tp, 0x1f, 0x0003);
  2726. rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
  2727. rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
  2728. rtl_writephy(tp, 0x1f, 0x0000);
  2729. /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
  2730. rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
  2731. }
  2732. static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
  2733. {
  2734. /* For 4-corner performance improve */
  2735. rtl_writephy(tp, 0x1f, 0x0005);
  2736. rtl_writephy(tp, 0x05, 0x8b80);
  2737. rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000);
  2738. rtl_writephy(tp, 0x1f, 0x0000);
  2739. /* PHY auto speed down */
  2740. rtl_writephy(tp, 0x1f, 0x0007);
  2741. rtl_writephy(tp, 0x1e, 0x002d);
  2742. rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
  2743. rtl_writephy(tp, 0x1f, 0x0000);
  2744. rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
  2745. /* Improve 10M EEE waveform */
  2746. rtl_writephy(tp, 0x1f, 0x0005);
  2747. rtl_writephy(tp, 0x05, 0x8b86);
  2748. rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
  2749. rtl_writephy(tp, 0x1f, 0x0000);
  2750. }
  2751. static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
  2752. {
  2753. static const struct phy_reg phy_reg_init[] = {
  2754. /* Channel estimation fine tune */
  2755. { 0x1f, 0x0003 },
  2756. { 0x09, 0xa20f },
  2757. { 0x1f, 0x0000 },
  2758. /* Modify green table for giga & fnet */
  2759. { 0x1f, 0x0005 },
  2760. { 0x05, 0x8b55 },
  2761. { 0x06, 0x0000 },
  2762. { 0x05, 0x8b5e },
  2763. { 0x06, 0x0000 },
  2764. { 0x05, 0x8b67 },
  2765. { 0x06, 0x0000 },
  2766. { 0x05, 0x8b70 },
  2767. { 0x06, 0x0000 },
  2768. { 0x1f, 0x0000 },
  2769. { 0x1f, 0x0007 },
  2770. { 0x1e, 0x0078 },
  2771. { 0x17, 0x0000 },
  2772. { 0x19, 0x00fb },
  2773. { 0x1f, 0x0000 },
  2774. /* Modify green table for 10M */
  2775. { 0x1f, 0x0005 },
  2776. { 0x05, 0x8b79 },
  2777. { 0x06, 0xaa00 },
  2778. { 0x1f, 0x0000 },
  2779. /* Disable hiimpedance detection (RTCT) */
  2780. { 0x1f, 0x0003 },
  2781. { 0x01, 0x328a },
  2782. { 0x1f, 0x0000 }
  2783. };
  2784. rtl_apply_firmware(tp);
  2785. rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
  2786. rtl8168f_hw_phy_config(tp);
  2787. /* Improve 2-pair detection performance */
  2788. rtl_writephy(tp, 0x1f, 0x0005);
  2789. rtl_writephy(tp, 0x05, 0x8b85);
  2790. rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
  2791. rtl_writephy(tp, 0x1f, 0x0000);
  2792. }
  2793. static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
  2794. {
  2795. rtl_apply_firmware(tp);
  2796. rtl8168f_hw_phy_config(tp);
  2797. }
  2798. static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
  2799. {
  2800. static const struct phy_reg phy_reg_init[] = {
  2801. /* Channel estimation fine tune */
  2802. { 0x1f, 0x0003 },
  2803. { 0x09, 0xa20f },
  2804. { 0x1f, 0x0000 },
  2805. /* Modify green table for giga & fnet */
  2806. { 0x1f, 0x0005 },
  2807. { 0x05, 0x8b55 },
  2808. { 0x06, 0x0000 },
  2809. { 0x05, 0x8b5e },
  2810. { 0x06, 0x0000 },
  2811. { 0x05, 0x8b67 },
  2812. { 0x06, 0x0000 },
  2813. { 0x05, 0x8b70 },
  2814. { 0x06, 0x0000 },
  2815. { 0x1f, 0x0000 },
  2816. { 0x1f, 0x0007 },
  2817. { 0x1e, 0x0078 },
  2818. { 0x17, 0x0000 },
  2819. { 0x19, 0x00aa },
  2820. { 0x1f, 0x0000 },
  2821. /* Modify green table for 10M */
  2822. { 0x1f, 0x0005 },
  2823. { 0x05, 0x8b79 },
  2824. { 0x06, 0xaa00 },
  2825. { 0x1f, 0x0000 },
  2826. /* Disable hiimpedance detection (RTCT) */
  2827. { 0x1f, 0x0003 },
  2828. { 0x01, 0x328a },
  2829. { 0x1f, 0x0000 }
  2830. };
  2831. rtl_apply_firmware(tp);
  2832. rtl8168f_hw_phy_config(tp);
  2833. /* Improve 2-pair detection performance */
  2834. rtl_writephy(tp, 0x1f, 0x0005);
  2835. rtl_writephy(tp, 0x05, 0x8b85);
  2836. rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
  2837. rtl_writephy(tp, 0x1f, 0x0000);
  2838. rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
  2839. /* Modify green table for giga */
  2840. rtl_writephy(tp, 0x1f, 0x0005);
  2841. rtl_writephy(tp, 0x05, 0x8b54);
  2842. rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0800);
  2843. rtl_writephy(tp, 0x05, 0x8b5d);
  2844. rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0800);
  2845. rtl_writephy(tp, 0x05, 0x8a7c);
  2846. rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
  2847. rtl_writephy(tp, 0x05, 0x8a7f);
  2848. rtl_w1w0_phy(tp, 0x06, 0x0100, 0x0000);
  2849. rtl_writephy(tp, 0x05, 0x8a82);
  2850. rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
  2851. rtl_writephy(tp, 0x05, 0x8a85);
  2852. rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
  2853. rtl_writephy(tp, 0x05, 0x8a88);
  2854. rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
  2855. rtl_writephy(tp, 0x1f, 0x0000);
  2856. /* uc same-seed solution */
  2857. rtl_writephy(tp, 0x1f, 0x0005);
  2858. rtl_writephy(tp, 0x05, 0x8b85);
  2859. rtl_w1w0_phy(tp, 0x06, 0x8000, 0x0000);
  2860. rtl_writephy(tp, 0x1f, 0x0000);
  2861. /* eee setting */
  2862. rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x00, 0x03, ERIAR_EXGMAC);
  2863. rtl_writephy(tp, 0x1f, 0x0005);
  2864. rtl_writephy(tp, 0x05, 0x8b85);
  2865. rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
  2866. rtl_writephy(tp, 0x1f, 0x0004);
  2867. rtl_writephy(tp, 0x1f, 0x0007);
  2868. rtl_writephy(tp, 0x1e, 0x0020);
  2869. rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100);
  2870. rtl_writephy(tp, 0x1f, 0x0000);
  2871. rtl_writephy(tp, 0x0d, 0x0007);
  2872. rtl_writephy(tp, 0x0e, 0x003c);
  2873. rtl_writephy(tp, 0x0d, 0x4007);
  2874. rtl_writephy(tp, 0x0e, 0x0000);
  2875. rtl_writephy(tp, 0x0d, 0x0000);
  2876. /* Green feature */
  2877. rtl_writephy(tp, 0x1f, 0x0003);
  2878. rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
  2879. rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
  2880. rtl_writephy(tp, 0x1f, 0x0000);
  2881. }
  2882. static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
  2883. {
  2884. rtl_apply_firmware(tp);
  2885. rtl_writephy(tp, 0x1f, 0x0a46);
  2886. if (rtl_readphy(tp, 0x10) & 0x0100) {
  2887. rtl_writephy(tp, 0x1f, 0x0bcc);
  2888. rtl_w1w0_phy(tp, 0x12, 0x0000, 0x8000);
  2889. } else {
  2890. rtl_writephy(tp, 0x1f, 0x0bcc);
  2891. rtl_w1w0_phy(tp, 0x12, 0x8000, 0x0000);
  2892. }
  2893. rtl_writephy(tp, 0x1f, 0x0a46);
  2894. if (rtl_readphy(tp, 0x13) & 0x0100) {
  2895. rtl_writephy(tp, 0x1f, 0x0c41);
  2896. rtl_w1w0_phy(tp, 0x15, 0x0002, 0x0000);
  2897. } else {
  2898. rtl_writephy(tp, 0x1f, 0x0c41);
  2899. rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0002);
  2900. }
  2901. /* Enable PHY auto speed down */
  2902. rtl_writephy(tp, 0x1f, 0x0a44);
  2903. rtl_w1w0_phy(tp, 0x11, 0x000c, 0x0000);
  2904. rtl_writephy(tp, 0x1f, 0x0bcc);
  2905. rtl_w1w0_phy(tp, 0x14, 0x0100, 0x0000);
  2906. rtl_writephy(tp, 0x1f, 0x0a44);
  2907. rtl_w1w0_phy(tp, 0x11, 0x00c0, 0x0000);
  2908. rtl_writephy(tp, 0x1f, 0x0a43);
  2909. rtl_writephy(tp, 0x13, 0x8084);
  2910. rtl_w1w0_phy(tp, 0x14, 0x0000, 0x6000);
  2911. rtl_w1w0_phy(tp, 0x10, 0x1003, 0x0000);
  2912. /* EEE auto-fallback function */
  2913. rtl_writephy(tp, 0x1f, 0x0a4b);
  2914. rtl_w1w0_phy(tp, 0x11, 0x0004, 0x0000);
  2915. /* Enable UC LPF tune function */
  2916. rtl_writephy(tp, 0x1f, 0x0a43);
  2917. rtl_writephy(tp, 0x13, 0x8012);
  2918. rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
  2919. rtl_writephy(tp, 0x1f, 0x0c42);
  2920. rtl_w1w0_phy(tp, 0x11, 0x4000, 0x2000);
  2921. /* Improve SWR Efficiency */
  2922. rtl_writephy(tp, 0x1f, 0x0bcd);
  2923. rtl_writephy(tp, 0x14, 0x5065);
  2924. rtl_writephy(tp, 0x14, 0xd065);
  2925. rtl_writephy(tp, 0x1f, 0x0bc8);
  2926. rtl_writephy(tp, 0x11, 0x5655);
  2927. rtl_writephy(tp, 0x1f, 0x0bcd);
  2928. rtl_writephy(tp, 0x14, 0x1065);
  2929. rtl_writephy(tp, 0x14, 0x9065);
  2930. rtl_writephy(tp, 0x14, 0x1065);
  2931. rtl_writephy(tp, 0x1f, 0x0000);
  2932. }
  2933. static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
  2934. {
  2935. rtl_apply_firmware(tp);
  2936. }
  2937. static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
  2938. {
  2939. static const struct phy_reg phy_reg_init[] = {
  2940. { 0x1f, 0x0003 },
  2941. { 0x08, 0x441d },
  2942. { 0x01, 0x9100 },
  2943. { 0x1f, 0x0000 }
  2944. };
  2945. rtl_writephy(tp, 0x1f, 0x0000);
  2946. rtl_patchphy(tp, 0x11, 1 << 12);
  2947. rtl_patchphy(tp, 0x19, 1 << 13);
  2948. rtl_patchphy(tp, 0x10, 1 << 15);
  2949. rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
  2950. }
  2951. static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
  2952. {
  2953. static const struct phy_reg phy_reg_init[] = {
  2954. { 0x1f, 0x0005 },
  2955. { 0x1a, 0x0000 },
  2956. { 0x1f, 0x0000 },
  2957. { 0x1f, 0x0004 },
  2958. { 0x1c, 0x0000 },
  2959. { 0x1f, 0x0000 },
  2960. { 0x1f, 0x0001 },
  2961. { 0x15, 0x7701 },
  2962. { 0x1f, 0x0000 }
  2963. };
  2964. /* Disable ALDPS before ram code */
  2965. rtl_writephy(tp, 0x1f, 0x0000);
  2966. rtl_writephy(tp, 0x18, 0x0310);
  2967. msleep(100);
  2968. rtl_apply_firmware(tp);
  2969. rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
  2970. }
  2971. static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
  2972. {
  2973. /* Disable ALDPS before setting firmware */
  2974. rtl_writephy(tp, 0x1f, 0x0000);
  2975. rtl_writephy(tp, 0x18, 0x0310);
  2976. msleep(20);
  2977. rtl_apply_firmware(tp);
  2978. /* EEE setting */
  2979. rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
  2980. rtl_writephy(tp, 0x1f, 0x0004);
  2981. rtl_writephy(tp, 0x10, 0x401f);
  2982. rtl_writephy(tp, 0x19, 0x7030);
  2983. rtl_writephy(tp, 0x1f, 0x0000);
  2984. }
  2985. static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
  2986. {
  2987. static const struct phy_reg phy_reg_init[] = {
  2988. { 0x1f, 0x0004 },
  2989. { 0x10, 0xc07f },
  2990. { 0x19, 0x7030 },
  2991. { 0x1f, 0x0000 }
  2992. };
  2993. /* Disable ALDPS before ram code */
  2994. rtl_writephy(tp, 0x1f, 0x0000);
  2995. rtl_writephy(tp, 0x18, 0x0310);
  2996. msleep(100);
  2997. rtl_apply_firmware(tp);
  2998. rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
  2999. rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
  3000. rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
  3001. }
  3002. static void rtl_hw_phy_config(struct net_device *dev)
  3003. {
  3004. struct rtl8169_private *tp = netdev_priv(dev);
  3005. rtl8169_print_mac_version(tp);
  3006. switch (tp->mac_version) {
  3007. case RTL_GIGA_MAC_VER_01:
  3008. break;
  3009. case RTL_GIGA_MAC_VER_02:
  3010. case RTL_GIGA_MAC_VER_03:
  3011. rtl8169s_hw_phy_config(tp);
  3012. break;
  3013. case RTL_GIGA_MAC_VER_04:
  3014. rtl8169sb_hw_phy_config(tp);
  3015. break;
  3016. case RTL_GIGA_MAC_VER_05:
  3017. rtl8169scd_hw_phy_config(tp);
  3018. break;
  3019. case RTL_GIGA_MAC_VER_06:
  3020. rtl8169sce_hw_phy_config(tp);
  3021. break;
  3022. case RTL_GIGA_MAC_VER_07:
  3023. case RTL_GIGA_MAC_VER_08:
  3024. case RTL_GIGA_MAC_VER_09:
  3025. rtl8102e_hw_phy_config(tp);
  3026. break;
  3027. case RTL_GIGA_MAC_VER_11:
  3028. rtl8168bb_hw_phy_config(tp);
  3029. break;
  3030. case RTL_GIGA_MAC_VER_12:
  3031. rtl8168bef_hw_phy_config(tp);
  3032. break;
  3033. case RTL_GIGA_MAC_VER_17:
  3034. rtl8168bef_hw_phy_config(tp);
  3035. break;
  3036. case RTL_GIGA_MAC_VER_18:
  3037. rtl8168cp_1_hw_phy_config(tp);
  3038. break;
  3039. case RTL_GIGA_MAC_VER_19:
  3040. rtl8168c_1_hw_phy_config(tp);
  3041. break;
  3042. case RTL_GIGA_MAC_VER_20:
  3043. rtl8168c_2_hw_phy_config(tp);
  3044. break;
  3045. case RTL_GIGA_MAC_VER_21:
  3046. rtl8168c_3_hw_phy_config(tp);
  3047. break;
  3048. case RTL_GIGA_MAC_VER_22:
  3049. rtl8168c_4_hw_phy_config(tp);
  3050. break;
  3051. case RTL_GIGA_MAC_VER_23:
  3052. case RTL_GIGA_MAC_VER_24:
  3053. rtl8168cp_2_hw_phy_config(tp);
  3054. break;
  3055. case RTL_GIGA_MAC_VER_25:
  3056. rtl8168d_1_hw_phy_config(tp);
  3057. break;
  3058. case RTL_GIGA_MAC_VER_26:
  3059. rtl8168d_2_hw_phy_config(tp);
  3060. break;
  3061. case RTL_GIGA_MAC_VER_27:
  3062. rtl8168d_3_hw_phy_config(tp);
  3063. break;
  3064. case RTL_GIGA_MAC_VER_28:
  3065. rtl8168d_4_hw_phy_config(tp);
  3066. break;
  3067. case RTL_GIGA_MAC_VER_29:
  3068. case RTL_GIGA_MAC_VER_30:
  3069. rtl8105e_hw_phy_config(tp);
  3070. break;
  3071. case RTL_GIGA_MAC_VER_31:
  3072. /* None. */
  3073. break;
  3074. case RTL_GIGA_MAC_VER_32:
  3075. case RTL_GIGA_MAC_VER_33:
  3076. rtl8168e_1_hw_phy_config(tp);
  3077. break;
  3078. case RTL_GIGA_MAC_VER_34:
  3079. rtl8168e_2_hw_phy_config(tp);
  3080. break;
  3081. case RTL_GIGA_MAC_VER_35:
  3082. rtl8168f_1_hw_phy_config(tp);
  3083. break;
  3084. case RTL_GIGA_MAC_VER_36:
  3085. rtl8168f_2_hw_phy_config(tp);
  3086. break;
  3087. case RTL_GIGA_MAC_VER_37:
  3088. rtl8402_hw_phy_config(tp);
  3089. break;
  3090. case RTL_GIGA_MAC_VER_38:
  3091. rtl8411_hw_phy_config(tp);
  3092. break;
  3093. case RTL_GIGA_MAC_VER_39:
  3094. rtl8106e_hw_phy_config(tp);
  3095. break;
  3096. case RTL_GIGA_MAC_VER_40:
  3097. rtl8168g_1_hw_phy_config(tp);
  3098. break;
  3099. case RTL_GIGA_MAC_VER_42:
  3100. case RTL_GIGA_MAC_VER_43:
  3101. case RTL_GIGA_MAC_VER_44:
  3102. rtl8168g_2_hw_phy_config(tp);
  3103. break;
  3104. case RTL_GIGA_MAC_VER_41:
  3105. default:
  3106. break;
  3107. }
  3108. }
  3109. static void rtl_phy_work(struct rtl8169_private *tp)
  3110. {
  3111. struct timer_list *timer = &tp->timer;
  3112. void __iomem *ioaddr = tp->mmio_addr;
  3113. unsigned long timeout = RTL8169_PHY_TIMEOUT;
  3114. assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
  3115. if (tp->phy_reset_pending(tp)) {
  3116. /*
  3117. * A busy loop could burn quite a few cycles on nowadays CPU.
  3118. * Let's delay the execution of the timer for a few ticks.
  3119. */
  3120. timeout = HZ/10;
  3121. goto out_mod_timer;
  3122. }
  3123. if (tp->link_ok(ioaddr))
  3124. return;
  3125. netif_dbg(tp, link, tp->dev, "PHY reset until link up\n");
  3126. tp->phy_reset_enable(tp);
  3127. out_mod_timer:
  3128. mod_timer(timer, jiffies + timeout);
  3129. }
  3130. static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
  3131. {
  3132. if (!test_and_set_bit(flag, tp->wk.flags))
  3133. schedule_work(&tp->wk.work);
  3134. }
  3135. static void rtl8169_phy_timer(unsigned long __opaque)
  3136. {
  3137. struct net_device *dev = (struct net_device *)__opaque;
  3138. struct rtl8169_private *tp = netdev_priv(dev);
  3139. rtl_schedule_task(tp, RTL_FLAG_TASK_PHY_PENDING);
  3140. }
  3141. static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
  3142. void __iomem *ioaddr)
  3143. {
  3144. iounmap(ioaddr);
  3145. pci_release_regions(pdev);
  3146. pci_clear_mwi(pdev);
  3147. pci_disable_device(pdev);
  3148. free_netdev(dev);
  3149. }
  3150. DECLARE_RTL_COND(rtl_phy_reset_cond)
  3151. {
  3152. return tp->phy_reset_pending(tp);
  3153. }
  3154. static void rtl8169_phy_reset(struct net_device *dev,
  3155. struct rtl8169_private *tp)
  3156. {
  3157. tp->phy_reset_enable(tp);
  3158. rtl_msleep_loop_wait_low(tp, &rtl_phy_reset_cond, 1, 100);
  3159. }
  3160. static bool rtl_tbi_enabled(struct rtl8169_private *tp)
  3161. {
  3162. void __iomem *ioaddr = tp->mmio_addr;
  3163. return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
  3164. (RTL_R8(PHYstatus) & TBI_Enable);
  3165. }
  3166. static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
  3167. {
  3168. void __iomem *ioaddr = tp->mmio_addr;
  3169. rtl_hw_phy_config(dev);
  3170. if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
  3171. dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
  3172. RTL_W8(0x82, 0x01);
  3173. }
  3174. pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
  3175. if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
  3176. pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
  3177. if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
  3178. dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
  3179. RTL_W8(0x82, 0x01);
  3180. dprintk("Set PHY Reg 0x0bh = 0x00h\n");
  3181. rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
  3182. }
  3183. rtl8169_phy_reset(dev, tp);
  3184. rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
  3185. ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
  3186. ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
  3187. (tp->mii.supports_gmii ?
  3188. ADVERTISED_1000baseT_Half |
  3189. ADVERTISED_1000baseT_Full : 0));
  3190. if (rtl_tbi_enabled(tp))
  3191. netif_info(tp, link, dev, "TBI auto-negotiating\n");
  3192. }
  3193. static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
  3194. {
  3195. void __iomem *ioaddr = tp->mmio_addr;
  3196. rtl_lock_work(tp);
  3197. RTL_W8(Cfg9346, Cfg9346_Unlock);
  3198. RTL_W32(MAC4, addr[4] | addr[5] << 8);
  3199. RTL_R32(MAC4);
  3200. RTL_W32(MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
  3201. RTL_R32(MAC0);
  3202. if (tp->mac_version == RTL_GIGA_MAC_VER_34)
  3203. rtl_rar_exgmac_set(tp, addr);
  3204. RTL_W8(Cfg9346, Cfg9346_Lock);
  3205. rtl_unlock_work(tp);
  3206. }
  3207. static int rtl_set_mac_address(struct net_device *dev, void *p)
  3208. {
  3209. struct rtl8169_private *tp = netdev_priv(dev);
  3210. struct sockaddr *addr = p;
  3211. if (!is_valid_ether_addr(addr->sa_data))
  3212. return -EADDRNOTAVAIL;
  3213. memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
  3214. rtl_rar_set(tp, dev->dev_addr);
  3215. return 0;
  3216. }
  3217. static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
  3218. {
  3219. struct rtl8169_private *tp = netdev_priv(dev);
  3220. struct mii_ioctl_data *data = if_mii(ifr);
  3221. return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
  3222. }
  3223. static int rtl_xmii_ioctl(struct rtl8169_private *tp,
  3224. struct mii_ioctl_data *data, int cmd)
  3225. {
  3226. switch (cmd) {
  3227. case SIOCGMIIPHY:
  3228. data->phy_id = 32; /* Internal PHY */
  3229. return 0;
  3230. case SIOCGMIIREG:
  3231. data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
  3232. return 0;
  3233. case SIOCSMIIREG:
  3234. rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
  3235. return 0;
  3236. }
  3237. return -EOPNOTSUPP;
  3238. }
  3239. static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
  3240. {
  3241. return -EOPNOTSUPP;
  3242. }
  3243. static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
  3244. {
  3245. if (tp->features & RTL_FEATURE_MSI) {
  3246. pci_disable_msi(pdev);
  3247. tp->features &= ~RTL_FEATURE_MSI;
  3248. }
  3249. }
  3250. static void rtl_init_mdio_ops(struct rtl8169_private *tp)
  3251. {
  3252. struct mdio_ops *ops = &tp->mdio_ops;
  3253. switch (tp->mac_version) {
  3254. case RTL_GIGA_MAC_VER_27:
  3255. ops->write = r8168dp_1_mdio_write;
  3256. ops->read = r8168dp_1_mdio_read;
  3257. break;
  3258. case RTL_GIGA_MAC_VER_28:
  3259. case RTL_GIGA_MAC_VER_31:
  3260. ops->write = r8168dp_2_mdio_write;
  3261. ops->read = r8168dp_2_mdio_read;
  3262. break;
  3263. case RTL_GIGA_MAC_VER_40:
  3264. case RTL_GIGA_MAC_VER_41:
  3265. case RTL_GIGA_MAC_VER_42:
  3266. case RTL_GIGA_MAC_VER_43:
  3267. case RTL_GIGA_MAC_VER_44:
  3268. ops->write = r8168g_mdio_write;
  3269. ops->read = r8168g_mdio_read;
  3270. break;
  3271. default:
  3272. ops->write = r8169_mdio_write;
  3273. ops->read = r8169_mdio_read;
  3274. break;
  3275. }
  3276. }
  3277. static void rtl_speed_down(struct rtl8169_private *tp)
  3278. {
  3279. u32 adv;
  3280. int lpa;
  3281. rtl_writephy(tp, 0x1f, 0x0000);
  3282. lpa = rtl_readphy(tp, MII_LPA);
  3283. if (lpa & (LPA_10HALF | LPA_10FULL))
  3284. adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full;
  3285. else if (lpa & (LPA_100HALF | LPA_100FULL))
  3286. adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
  3287. ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
  3288. else
  3289. adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
  3290. ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
  3291. (tp->mii.supports_gmii ?
  3292. ADVERTISED_1000baseT_Half |
  3293. ADVERTISED_1000baseT_Full : 0);
  3294. rtl8169_set_speed(tp->dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
  3295. adv);
  3296. }
  3297. static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
  3298. {
  3299. void __iomem *ioaddr = tp->mmio_addr;
  3300. switch (tp->mac_version) {
  3301. case RTL_GIGA_MAC_VER_25:
  3302. case RTL_GIGA_MAC_VER_26:
  3303. case RTL_GIGA_MAC_VER_29:
  3304. case RTL_GIGA_MAC_VER_30:
  3305. case RTL_GIGA_MAC_VER_32:
  3306. case RTL_GIGA_MAC_VER_33:
  3307. case RTL_GIGA_MAC_VER_34:
  3308. case RTL_GIGA_MAC_VER_37:
  3309. case RTL_GIGA_MAC_VER_38:
  3310. case RTL_GIGA_MAC_VER_39:
  3311. case RTL_GIGA_MAC_VER_40:
  3312. case RTL_GIGA_MAC_VER_41:
  3313. case RTL_GIGA_MAC_VER_42:
  3314. case RTL_GIGA_MAC_VER_43:
  3315. case RTL_GIGA_MAC_VER_44:
  3316. RTL_W32(RxConfig, RTL_R32(RxConfig) |
  3317. AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
  3318. break;
  3319. default:
  3320. break;
  3321. }
  3322. }
  3323. static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
  3324. {
  3325. if (!(__rtl8169_get_wol(tp) & WAKE_ANY))
  3326. return false;
  3327. rtl_speed_down(tp);
  3328. rtl_wol_suspend_quirk(tp);
  3329. return true;
  3330. }
  3331. static void r810x_phy_power_down(struct rtl8169_private *tp)
  3332. {
  3333. rtl_writephy(tp, 0x1f, 0x0000);
  3334. rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
  3335. }
  3336. static void r810x_phy_power_up(struct rtl8169_private *tp)
  3337. {
  3338. rtl_writephy(tp, 0x1f, 0x0000);
  3339. rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
  3340. }
  3341. static void r810x_pll_power_down(struct rtl8169_private *tp)
  3342. {
  3343. void __iomem *ioaddr = tp->mmio_addr;
  3344. if (rtl_wol_pll_power_down(tp))
  3345. return;
  3346. r810x_phy_power_down(tp);
  3347. switch (tp->mac_version) {
  3348. case RTL_GIGA_MAC_VER_07:
  3349. case RTL_GIGA_MAC_VER_08:
  3350. case RTL_GIGA_MAC_VER_09:
  3351. case RTL_GIGA_MAC_VER_10:
  3352. case RTL_GIGA_MAC_VER_13:
  3353. case RTL_GIGA_MAC_VER_16:
  3354. break;
  3355. default:
  3356. RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
  3357. break;
  3358. }
  3359. }
  3360. static void r810x_pll_power_up(struct rtl8169_private *tp)
  3361. {
  3362. void __iomem *ioaddr = tp->mmio_addr;
  3363. r810x_phy_power_up(tp);
  3364. switch (tp->mac_version) {
  3365. case RTL_GIGA_MAC_VER_07:
  3366. case RTL_GIGA_MAC_VER_08:
  3367. case RTL_GIGA_MAC_VER_09:
  3368. case RTL_GIGA_MAC_VER_10:
  3369. case RTL_GIGA_MAC_VER_13:
  3370. case RTL_GIGA_MAC_VER_16:
  3371. break;
  3372. default:
  3373. RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
  3374. break;
  3375. }
  3376. }
  3377. static void r8168_phy_power_up(struct rtl8169_private *tp)
  3378. {
  3379. rtl_writephy(tp, 0x1f, 0x0000);
  3380. switch (tp->mac_version) {
  3381. case RTL_GIGA_MAC_VER_11:
  3382. case RTL_GIGA_MAC_VER_12:
  3383. case RTL_GIGA_MAC_VER_17:
  3384. case RTL_GIGA_MAC_VER_18:
  3385. case RTL_GIGA_MAC_VER_19:
  3386. case RTL_GIGA_MAC_VER_20:
  3387. case RTL_GIGA_MAC_VER_21:
  3388. case RTL_GIGA_MAC_VER_22:
  3389. case RTL_GIGA_MAC_VER_23:
  3390. case RTL_GIGA_MAC_VER_24:
  3391. case RTL_GIGA_MAC_VER_25:
  3392. case RTL_GIGA_MAC_VER_26:
  3393. case RTL_GIGA_MAC_VER_27:
  3394. case RTL_GIGA_MAC_VER_28:
  3395. case RTL_GIGA_MAC_VER_31:
  3396. rtl_writephy(tp, 0x0e, 0x0000);
  3397. break;
  3398. default:
  3399. break;
  3400. }
  3401. rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
  3402. }
  3403. static void r8168_phy_power_down(struct rtl8169_private *tp)
  3404. {
  3405. rtl_writephy(tp, 0x1f, 0x0000);
  3406. switch (tp->mac_version) {
  3407. case RTL_GIGA_MAC_VER_32:
  3408. case RTL_GIGA_MAC_VER_33:
  3409. case RTL_GIGA_MAC_VER_40:
  3410. case RTL_GIGA_MAC_VER_41:
  3411. rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
  3412. break;
  3413. case RTL_GIGA_MAC_VER_11:
  3414. case RTL_GIGA_MAC_VER_12:
  3415. case RTL_GIGA_MAC_VER_17:
  3416. case RTL_GIGA_MAC_VER_18:
  3417. case RTL_GIGA_MAC_VER_19:
  3418. case RTL_GIGA_MAC_VER_20:
  3419. case RTL_GIGA_MAC_VER_21:
  3420. case RTL_GIGA_MAC_VER_22:
  3421. case RTL_GIGA_MAC_VER_23:
  3422. case RTL_GIGA_MAC_VER_24:
  3423. case RTL_GIGA_MAC_VER_25:
  3424. case RTL_GIGA_MAC_VER_26:
  3425. case RTL_GIGA_MAC_VER_27:
  3426. case RTL_GIGA_MAC_VER_28:
  3427. case RTL_GIGA_MAC_VER_31:
  3428. rtl_writephy(tp, 0x0e, 0x0200);
  3429. default:
  3430. rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
  3431. break;
  3432. }
  3433. }
  3434. static void r8168_pll_power_down(struct rtl8169_private *tp)
  3435. {
  3436. void __iomem *ioaddr = tp->mmio_addr;
  3437. if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
  3438. tp->mac_version == RTL_GIGA_MAC_VER_28 ||
  3439. tp->mac_version == RTL_GIGA_MAC_VER_31) &&
  3440. r8168dp_check_dash(tp)) {
  3441. return;
  3442. }
  3443. if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
  3444. tp->mac_version == RTL_GIGA_MAC_VER_24) &&
  3445. (RTL_R16(CPlusCmd) & ASF)) {
  3446. return;
  3447. }
  3448. if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
  3449. tp->mac_version == RTL_GIGA_MAC_VER_33)
  3450. rtl_ephy_write(tp, 0x19, 0xff64);
  3451. if (rtl_wol_pll_power_down(tp))
  3452. return;
  3453. r8168_phy_power_down(tp);
  3454. switch (tp->mac_version) {
  3455. case RTL_GIGA_MAC_VER_25:
  3456. case RTL_GIGA_MAC_VER_26:
  3457. case RTL_GIGA_MAC_VER_27:
  3458. case RTL_GIGA_MAC_VER_28:
  3459. case RTL_GIGA_MAC_VER_31:
  3460. case RTL_GIGA_MAC_VER_32:
  3461. case RTL_GIGA_MAC_VER_33:
  3462. RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
  3463. break;
  3464. case RTL_GIGA_MAC_VER_40:
  3465. case RTL_GIGA_MAC_VER_41:
  3466. rtl_w1w0_eri(tp, 0x1a8, ERIAR_MASK_1111, 0x00000000,
  3467. 0xfc000000, ERIAR_EXGMAC);
  3468. break;
  3469. }
  3470. }
  3471. static void r8168_pll_power_up(struct rtl8169_private *tp)
  3472. {
  3473. void __iomem *ioaddr = tp->mmio_addr;
  3474. switch (tp->mac_version) {
  3475. case RTL_GIGA_MAC_VER_25:
  3476. case RTL_GIGA_MAC_VER_26:
  3477. case RTL_GIGA_MAC_VER_27:
  3478. case RTL_GIGA_MAC_VER_28:
  3479. case RTL_GIGA_MAC_VER_31:
  3480. case RTL_GIGA_MAC_VER_32:
  3481. case RTL_GIGA_MAC_VER_33:
  3482. RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
  3483. break;
  3484. case RTL_GIGA_MAC_VER_40:
  3485. case RTL_GIGA_MAC_VER_41:
  3486. rtl_w1w0_eri(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000,
  3487. 0x00000000, ERIAR_EXGMAC);
  3488. break;
  3489. }
  3490. r8168_phy_power_up(tp);
  3491. }
  3492. static void rtl_generic_op(struct rtl8169_private *tp,
  3493. void (*op)(struct rtl8169_private *))
  3494. {
  3495. if (op)
  3496. op(tp);
  3497. }
  3498. static void rtl_pll_power_down(struct rtl8169_private *tp)
  3499. {
  3500. rtl_generic_op(tp, tp->pll_power_ops.down);
  3501. }
  3502. static void rtl_pll_power_up(struct rtl8169_private *tp)
  3503. {
  3504. rtl_generic_op(tp, tp->pll_power_ops.up);
  3505. }
  3506. static void rtl_init_pll_power_ops(struct rtl8169_private *tp)
  3507. {
  3508. struct pll_power_ops *ops = &tp->pll_power_ops;
  3509. switch (tp->mac_version) {
  3510. case RTL_GIGA_MAC_VER_07:
  3511. case RTL_GIGA_MAC_VER_08:
  3512. case RTL_GIGA_MAC_VER_09:
  3513. case RTL_GIGA_MAC_VER_10:
  3514. case RTL_GIGA_MAC_VER_16:
  3515. case RTL_GIGA_MAC_VER_29:
  3516. case RTL_GIGA_MAC_VER_30:
  3517. case RTL_GIGA_MAC_VER_37:
  3518. case RTL_GIGA_MAC_VER_39:
  3519. case RTL_GIGA_MAC_VER_43:
  3520. ops->down = r810x_pll_power_down;
  3521. ops->up = r810x_pll_power_up;
  3522. break;
  3523. case RTL_GIGA_MAC_VER_11:
  3524. case RTL_GIGA_MAC_VER_12:
  3525. case RTL_GIGA_MAC_VER_17:
  3526. case RTL_GIGA_MAC_VER_18:
  3527. case RTL_GIGA_MAC_VER_19:
  3528. case RTL_GIGA_MAC_VER_20:
  3529. case RTL_GIGA_MAC_VER_21:
  3530. case RTL_GIGA_MAC_VER_22:
  3531. case RTL_GIGA_MAC_VER_23:
  3532. case RTL_GIGA_MAC_VER_24:
  3533. case RTL_GIGA_MAC_VER_25:
  3534. case RTL_GIGA_MAC_VER_26:
  3535. case RTL_GIGA_MAC_VER_27:
  3536. case RTL_GIGA_MAC_VER_28:
  3537. case RTL_GIGA_MAC_VER_31:
  3538. case RTL_GIGA_MAC_VER_32:
  3539. case RTL_GIGA_MAC_VER_33:
  3540. case RTL_GIGA_MAC_VER_34:
  3541. case RTL_GIGA_MAC_VER_35:
  3542. case RTL_GIGA_MAC_VER_36:
  3543. case RTL_GIGA_MAC_VER_38:
  3544. case RTL_GIGA_MAC_VER_40:
  3545. case RTL_GIGA_MAC_VER_41:
  3546. case RTL_GIGA_MAC_VER_42:
  3547. case RTL_GIGA_MAC_VER_44:
  3548. ops->down = r8168_pll_power_down;
  3549. ops->up = r8168_pll_power_up;
  3550. break;
  3551. default:
  3552. ops->down = NULL;
  3553. ops->up = NULL;
  3554. break;
  3555. }
  3556. }
  3557. static void rtl_init_rxcfg(struct rtl8169_private *tp)
  3558. {
  3559. void __iomem *ioaddr = tp->mmio_addr;
  3560. switch (tp->mac_version) {
  3561. case RTL_GIGA_MAC_VER_01:
  3562. case RTL_GIGA_MAC_VER_02:
  3563. case RTL_GIGA_MAC_VER_03:
  3564. case RTL_GIGA_MAC_VER_04:
  3565. case RTL_GIGA_MAC_VER_05:
  3566. case RTL_GIGA_MAC_VER_06:
  3567. case RTL_GIGA_MAC_VER_10:
  3568. case RTL_GIGA_MAC_VER_11:
  3569. case RTL_GIGA_MAC_VER_12:
  3570. case RTL_GIGA_MAC_VER_13:
  3571. case RTL_GIGA_MAC_VER_14:
  3572. case RTL_GIGA_MAC_VER_15:
  3573. case RTL_GIGA_MAC_VER_16:
  3574. case RTL_GIGA_MAC_VER_17:
  3575. RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
  3576. break;
  3577. case RTL_GIGA_MAC_VER_18:
  3578. case RTL_GIGA_MAC_VER_19:
  3579. case RTL_GIGA_MAC_VER_20:
  3580. case RTL_GIGA_MAC_VER_21:
  3581. case RTL_GIGA_MAC_VER_22:
  3582. case RTL_GIGA_MAC_VER_23:
  3583. case RTL_GIGA_MAC_VER_24:
  3584. case RTL_GIGA_MAC_VER_34:
  3585. case RTL_GIGA_MAC_VER_35:
  3586. RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
  3587. break;
  3588. case RTL_GIGA_MAC_VER_40:
  3589. case RTL_GIGA_MAC_VER_41:
  3590. case RTL_GIGA_MAC_VER_42:
  3591. case RTL_GIGA_MAC_VER_43:
  3592. case RTL_GIGA_MAC_VER_44:
  3593. RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST | RX_EARLY_OFF);
  3594. break;
  3595. default:
  3596. RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST);
  3597. break;
  3598. }
  3599. }
  3600. static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
  3601. {
  3602. tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
  3603. }
  3604. static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
  3605. {
  3606. void __iomem *ioaddr = tp->mmio_addr;
  3607. RTL_W8(Cfg9346, Cfg9346_Unlock);
  3608. rtl_generic_op(tp, tp->jumbo_ops.enable);
  3609. RTL_W8(Cfg9346, Cfg9346_Lock);
  3610. }
  3611. static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
  3612. {
  3613. void __iomem *ioaddr = tp->mmio_addr;
  3614. RTL_W8(Cfg9346, Cfg9346_Unlock);
  3615. rtl_generic_op(tp, tp->jumbo_ops.disable);
  3616. RTL_W8(Cfg9346, Cfg9346_Lock);
  3617. }
  3618. static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
  3619. {
  3620. void __iomem *ioaddr = tp->mmio_addr;
  3621. RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
  3622. RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1);
  3623. rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
  3624. }
  3625. static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
  3626. {
  3627. void __iomem *ioaddr = tp->mmio_addr;
  3628. RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
  3629. RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1);
  3630. rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
  3631. }
  3632. static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
  3633. {
  3634. void __iomem *ioaddr = tp->mmio_addr;
  3635. RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
  3636. }
  3637. static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
  3638. {
  3639. void __iomem *ioaddr = tp->mmio_addr;
  3640. RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
  3641. }
  3642. static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
  3643. {
  3644. void __iomem *ioaddr = tp->mmio_addr;
  3645. RTL_W8(MaxTxPacketSize, 0x3f);
  3646. RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
  3647. RTL_W8(Config4, RTL_R8(Config4) | 0x01);
  3648. rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
  3649. }
  3650. static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
  3651. {
  3652. void __iomem *ioaddr = tp->mmio_addr;
  3653. RTL_W8(MaxTxPacketSize, 0x0c);
  3654. RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
  3655. RTL_W8(Config4, RTL_R8(Config4) & ~0x01);
  3656. rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
  3657. }
  3658. static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
  3659. {
  3660. rtl_tx_performance_tweak(tp->pci_dev,
  3661. (0x2 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
  3662. }
  3663. static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
  3664. {
  3665. rtl_tx_performance_tweak(tp->pci_dev,
  3666. (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
  3667. }
  3668. static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
  3669. {
  3670. void __iomem *ioaddr = tp->mmio_addr;
  3671. r8168b_0_hw_jumbo_enable(tp);
  3672. RTL_W8(Config4, RTL_R8(Config4) | (1 << 0));
  3673. }
  3674. static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
  3675. {
  3676. void __iomem *ioaddr = tp->mmio_addr;
  3677. r8168b_0_hw_jumbo_disable(tp);
  3678. RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
  3679. }
  3680. static void rtl_init_jumbo_ops(struct rtl8169_private *tp)
  3681. {
  3682. struct jumbo_ops *ops = &tp->jumbo_ops;
  3683. switch (tp->mac_version) {
  3684. case RTL_GIGA_MAC_VER_11:
  3685. ops->disable = r8168b_0_hw_jumbo_disable;
  3686. ops->enable = r8168b_0_hw_jumbo_enable;
  3687. break;
  3688. case RTL_GIGA_MAC_VER_12:
  3689. case RTL_GIGA_MAC_VER_17:
  3690. ops->disable = r8168b_1_hw_jumbo_disable;
  3691. ops->enable = r8168b_1_hw_jumbo_enable;
  3692. break;
  3693. case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
  3694. case RTL_GIGA_MAC_VER_19:
  3695. case RTL_GIGA_MAC_VER_20:
  3696. case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
  3697. case RTL_GIGA_MAC_VER_22:
  3698. case RTL_GIGA_MAC_VER_23:
  3699. case RTL_GIGA_MAC_VER_24:
  3700. case RTL_GIGA_MAC_VER_25:
  3701. case RTL_GIGA_MAC_VER_26:
  3702. ops->disable = r8168c_hw_jumbo_disable;
  3703. ops->enable = r8168c_hw_jumbo_enable;
  3704. break;
  3705. case RTL_GIGA_MAC_VER_27:
  3706. case RTL_GIGA_MAC_VER_28:
  3707. ops->disable = r8168dp_hw_jumbo_disable;
  3708. ops->enable = r8168dp_hw_jumbo_enable;
  3709. break;
  3710. case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
  3711. case RTL_GIGA_MAC_VER_32:
  3712. case RTL_GIGA_MAC_VER_33:
  3713. case RTL_GIGA_MAC_VER_34:
  3714. ops->disable = r8168e_hw_jumbo_disable;
  3715. ops->enable = r8168e_hw_jumbo_enable;
  3716. break;
  3717. /*
  3718. * No action needed for jumbo frames with 8169.
  3719. * No jumbo for 810x at all.
  3720. */
  3721. case RTL_GIGA_MAC_VER_40:
  3722. case RTL_GIGA_MAC_VER_41:
  3723. case RTL_GIGA_MAC_VER_42:
  3724. case RTL_GIGA_MAC_VER_43:
  3725. case RTL_GIGA_MAC_VER_44:
  3726. default:
  3727. ops->disable = NULL;
  3728. ops->enable = NULL;
  3729. break;
  3730. }
  3731. }
  3732. DECLARE_RTL_COND(rtl_chipcmd_cond)
  3733. {
  3734. void __iomem *ioaddr = tp->mmio_addr;
  3735. return RTL_R8(ChipCmd) & CmdReset;
  3736. }
  3737. static void rtl_hw_reset(struct rtl8169_private *tp)
  3738. {
  3739. void __iomem *ioaddr = tp->mmio_addr;
  3740. RTL_W8(ChipCmd, CmdReset);
  3741. rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
  3742. }
  3743. static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
  3744. {
  3745. struct rtl_fw *rtl_fw;
  3746. const char *name;
  3747. int rc = -ENOMEM;
  3748. name = rtl_lookup_firmware_name(tp);
  3749. if (!name)
  3750. goto out_no_firmware;
  3751. rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
  3752. if (!rtl_fw)
  3753. goto err_warn;
  3754. rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
  3755. if (rc < 0)
  3756. goto err_free;
  3757. rc = rtl_check_firmware(tp, rtl_fw);
  3758. if (rc < 0)
  3759. goto err_release_firmware;
  3760. tp->rtl_fw = rtl_fw;
  3761. out:
  3762. return;
  3763. err_release_firmware:
  3764. release_firmware(rtl_fw->fw);
  3765. err_free:
  3766. kfree(rtl_fw);
  3767. err_warn:
  3768. netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
  3769. name, rc);
  3770. out_no_firmware:
  3771. tp->rtl_fw = NULL;
  3772. goto out;
  3773. }
  3774. static void rtl_request_firmware(struct rtl8169_private *tp)
  3775. {
  3776. if (IS_ERR(tp->rtl_fw))
  3777. rtl_request_uncached_firmware(tp);
  3778. }
  3779. static void rtl_rx_close(struct rtl8169_private *tp)
  3780. {
  3781. void __iomem *ioaddr = tp->mmio_addr;
  3782. RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
  3783. }
  3784. DECLARE_RTL_COND(rtl_npq_cond)
  3785. {
  3786. void __iomem *ioaddr = tp->mmio_addr;
  3787. return RTL_R8(TxPoll) & NPQ;
  3788. }
  3789. DECLARE_RTL_COND(rtl_txcfg_empty_cond)
  3790. {
  3791. void __iomem *ioaddr = tp->mmio_addr;
  3792. return RTL_R32(TxConfig) & TXCFG_EMPTY;
  3793. }
  3794. static void rtl8169_hw_reset(struct rtl8169_private *tp)
  3795. {
  3796. void __iomem *ioaddr = tp->mmio_addr;
  3797. /* Disable interrupts */
  3798. rtl8169_irq_mask_and_ack(tp);
  3799. rtl_rx_close(tp);
  3800. if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
  3801. tp->mac_version == RTL_GIGA_MAC_VER_28 ||
  3802. tp->mac_version == RTL_GIGA_MAC_VER_31) {
  3803. rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
  3804. } else if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
  3805. tp->mac_version == RTL_GIGA_MAC_VER_35 ||
  3806. tp->mac_version == RTL_GIGA_MAC_VER_36 ||
  3807. tp->mac_version == RTL_GIGA_MAC_VER_37 ||
  3808. tp->mac_version == RTL_GIGA_MAC_VER_40 ||
  3809. tp->mac_version == RTL_GIGA_MAC_VER_41 ||
  3810. tp->mac_version == RTL_GIGA_MAC_VER_42 ||
  3811. tp->mac_version == RTL_GIGA_MAC_VER_43 ||
  3812. tp->mac_version == RTL_GIGA_MAC_VER_44 ||
  3813. tp->mac_version == RTL_GIGA_MAC_VER_38) {
  3814. RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
  3815. rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
  3816. } else {
  3817. RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
  3818. udelay(100);
  3819. }
  3820. rtl_hw_reset(tp);
  3821. }
  3822. static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
  3823. {
  3824. void __iomem *ioaddr = tp->mmio_addr;
  3825. /* Set DMA burst size and Interframe Gap Time */
  3826. RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
  3827. (InterFrameGap << TxInterFrameGapShift));
  3828. }
  3829. static void rtl_hw_start(struct net_device *dev)
  3830. {
  3831. struct rtl8169_private *tp = netdev_priv(dev);
  3832. tp->hw_start(dev);
  3833. rtl_irq_enable_all(tp);
  3834. }
  3835. static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
  3836. void __iomem *ioaddr)
  3837. {
  3838. /*
  3839. * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
  3840. * register to be written before TxDescAddrLow to work.
  3841. * Switching from MMIO to I/O access fixes the issue as well.
  3842. */
  3843. RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
  3844. RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
  3845. RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
  3846. RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
  3847. }
  3848. static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
  3849. {
  3850. u16 cmd;
  3851. cmd = RTL_R16(CPlusCmd);
  3852. RTL_W16(CPlusCmd, cmd);
  3853. return cmd;
  3854. }
  3855. static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
  3856. {
  3857. /* Low hurts. Let's disable the filtering. */
  3858. RTL_W16(RxMaxSize, rx_buf_sz + 1);
  3859. }
  3860. static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
  3861. {
  3862. static const struct rtl_cfg2_info {
  3863. u32 mac_version;
  3864. u32 clk;
  3865. u32 val;
  3866. } cfg2_info [] = {
  3867. { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
  3868. { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
  3869. { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
  3870. { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
  3871. };
  3872. const struct rtl_cfg2_info *p = cfg2_info;
  3873. unsigned int i;
  3874. u32 clk;
  3875. clk = RTL_R8(Config2) & PCI_Clock_66MHz;
  3876. for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
  3877. if ((p->mac_version == mac_version) && (p->clk == clk)) {
  3878. RTL_W32(0x7c, p->val);
  3879. break;
  3880. }
  3881. }
  3882. }
  3883. static void rtl_set_rx_mode(struct net_device *dev)
  3884. {
  3885. struct rtl8169_private *tp = netdev_priv(dev);
  3886. void __iomem *ioaddr = tp->mmio_addr;
  3887. u32 mc_filter[2]; /* Multicast hash filter */
  3888. int rx_mode;
  3889. u32 tmp = 0;
  3890. if (dev->flags & IFF_PROMISC) {
  3891. /* Unconditionally log net taps. */
  3892. netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
  3893. rx_mode =
  3894. AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
  3895. AcceptAllPhys;
  3896. mc_filter[1] = mc_filter[0] = 0xffffffff;
  3897. } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
  3898. (dev->flags & IFF_ALLMULTI)) {
  3899. /* Too many to filter perfectly -- accept all multicasts. */
  3900. rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
  3901. mc_filter[1] = mc_filter[0] = 0xffffffff;
  3902. } else {
  3903. struct netdev_hw_addr *ha;
  3904. rx_mode = AcceptBroadcast | AcceptMyPhys;
  3905. mc_filter[1] = mc_filter[0] = 0;
  3906. netdev_for_each_mc_addr(ha, dev) {
  3907. int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
  3908. mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
  3909. rx_mode |= AcceptMulticast;
  3910. }
  3911. }
  3912. if (dev->features & NETIF_F_RXALL)
  3913. rx_mode |= (AcceptErr | AcceptRunt);
  3914. tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
  3915. if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
  3916. u32 data = mc_filter[0];
  3917. mc_filter[0] = swab32(mc_filter[1]);
  3918. mc_filter[1] = swab32(data);
  3919. }
  3920. if (tp->mac_version == RTL_GIGA_MAC_VER_35)
  3921. mc_filter[1] = mc_filter[0] = 0xffffffff;
  3922. RTL_W32(MAR0 + 4, mc_filter[1]);
  3923. RTL_W32(MAR0 + 0, mc_filter[0]);
  3924. RTL_W32(RxConfig, tmp);
  3925. }
  3926. static void rtl_hw_start_8169(struct net_device *dev)
  3927. {
  3928. struct rtl8169_private *tp = netdev_priv(dev);
  3929. void __iomem *ioaddr = tp->mmio_addr;
  3930. struct pci_dev *pdev = tp->pci_dev;
  3931. if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
  3932. RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
  3933. pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
  3934. }
  3935. RTL_W8(Cfg9346, Cfg9346_Unlock);
  3936. if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
  3937. tp->mac_version == RTL_GIGA_MAC_VER_02 ||
  3938. tp->mac_version == RTL_GIGA_MAC_VER_03 ||
  3939. tp->mac_version == RTL_GIGA_MAC_VER_04)
  3940. RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
  3941. rtl_init_rxcfg(tp);
  3942. RTL_W8(EarlyTxThres, NoEarlyTx);
  3943. rtl_set_rx_max_size(ioaddr, rx_buf_sz);
  3944. if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
  3945. tp->mac_version == RTL_GIGA_MAC_VER_02 ||
  3946. tp->mac_version == RTL_GIGA_MAC_VER_03 ||
  3947. tp->mac_version == RTL_GIGA_MAC_VER_04)
  3948. rtl_set_rx_tx_config_registers(tp);
  3949. tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
  3950. if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
  3951. tp->mac_version == RTL_GIGA_MAC_VER_03) {
  3952. dprintk("Set MAC Reg C+CR Offset 0xE0. "
  3953. "Bit-3 and bit-14 MUST be 1\n");
  3954. tp->cp_cmd |= (1 << 14);
  3955. }
  3956. RTL_W16(CPlusCmd, tp->cp_cmd);
  3957. rtl8169_set_magic_reg(ioaddr, tp->mac_version);
  3958. /*
  3959. * Undocumented corner. Supposedly:
  3960. * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
  3961. */
  3962. RTL_W16(IntrMitigate, 0x0000);
  3963. rtl_set_rx_tx_desc_registers(tp, ioaddr);
  3964. if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
  3965. tp->mac_version != RTL_GIGA_MAC_VER_02 &&
  3966. tp->mac_version != RTL_GIGA_MAC_VER_03 &&
  3967. tp->mac_version != RTL_GIGA_MAC_VER_04) {
  3968. RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
  3969. rtl_set_rx_tx_config_registers(tp);
  3970. }
  3971. RTL_W8(Cfg9346, Cfg9346_Lock);
  3972. /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
  3973. RTL_R8(IntrMask);
  3974. RTL_W32(RxMissed, 0);
  3975. rtl_set_rx_mode(dev);
  3976. /* no early-rx interrupts */
  3977. RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
  3978. }
  3979. static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
  3980. {
  3981. if (tp->csi_ops.write)
  3982. tp->csi_ops.write(tp, addr, value);
  3983. }
  3984. static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
  3985. {
  3986. return tp->csi_ops.read ? tp->csi_ops.read(tp, addr) : ~0;
  3987. }
  3988. static void rtl_csi_access_enable(struct rtl8169_private *tp, u32 bits)
  3989. {
  3990. u32 csi;
  3991. csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
  3992. rtl_csi_write(tp, 0x070c, csi | bits);
  3993. }
  3994. static void rtl_csi_access_enable_1(struct rtl8169_private *tp)
  3995. {
  3996. rtl_csi_access_enable(tp, 0x17000000);
  3997. }
  3998. static void rtl_csi_access_enable_2(struct rtl8169_private *tp)
  3999. {
  4000. rtl_csi_access_enable(tp, 0x27000000);
  4001. }
  4002. DECLARE_RTL_COND(rtl_csiar_cond)
  4003. {
  4004. void __iomem *ioaddr = tp->mmio_addr;
  4005. return RTL_R32(CSIAR) & CSIAR_FLAG;
  4006. }
  4007. static void r8169_csi_write(struct rtl8169_private *tp, int addr, int value)
  4008. {
  4009. void __iomem *ioaddr = tp->mmio_addr;
  4010. RTL_W32(CSIDR, value);
  4011. RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
  4012. CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
  4013. rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
  4014. }
  4015. static u32 r8169_csi_read(struct rtl8169_private *tp, int addr)
  4016. {
  4017. void __iomem *ioaddr = tp->mmio_addr;
  4018. RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
  4019. CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
  4020. return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
  4021. RTL_R32(CSIDR) : ~0;
  4022. }
  4023. static void r8402_csi_write(struct rtl8169_private *tp, int addr, int value)
  4024. {
  4025. void __iomem *ioaddr = tp->mmio_addr;
  4026. RTL_W32(CSIDR, value);
  4027. RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
  4028. CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
  4029. CSIAR_FUNC_NIC);
  4030. rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
  4031. }
  4032. static u32 r8402_csi_read(struct rtl8169_private *tp, int addr)
  4033. {
  4034. void __iomem *ioaddr = tp->mmio_addr;
  4035. RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC |
  4036. CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
  4037. return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
  4038. RTL_R32(CSIDR) : ~0;
  4039. }
  4040. static void r8411_csi_write(struct rtl8169_private *tp, int addr, int value)
  4041. {
  4042. void __iomem *ioaddr = tp->mmio_addr;
  4043. RTL_W32(CSIDR, value);
  4044. RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
  4045. CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
  4046. CSIAR_FUNC_NIC2);
  4047. rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
  4048. }
  4049. static u32 r8411_csi_read(struct rtl8169_private *tp, int addr)
  4050. {
  4051. void __iomem *ioaddr = tp->mmio_addr;
  4052. RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC2 |
  4053. CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
  4054. return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
  4055. RTL_R32(CSIDR) : ~0;
  4056. }
  4057. static void rtl_init_csi_ops(struct rtl8169_private *tp)
  4058. {
  4059. struct csi_ops *ops = &tp->csi_ops;
  4060. switch (tp->mac_version) {
  4061. case RTL_GIGA_MAC_VER_01:
  4062. case RTL_GIGA_MAC_VER_02:
  4063. case RTL_GIGA_MAC_VER_03:
  4064. case RTL_GIGA_MAC_VER_04:
  4065. case RTL_GIGA_MAC_VER_05:
  4066. case RTL_GIGA_MAC_VER_06:
  4067. case RTL_GIGA_MAC_VER_10:
  4068. case RTL_GIGA_MAC_VER_11:
  4069. case RTL_GIGA_MAC_VER_12:
  4070. case RTL_GIGA_MAC_VER_13:
  4071. case RTL_GIGA_MAC_VER_14:
  4072. case RTL_GIGA_MAC_VER_15:
  4073. case RTL_GIGA_MAC_VER_16:
  4074. case RTL_GIGA_MAC_VER_17:
  4075. ops->write = NULL;
  4076. ops->read = NULL;
  4077. break;
  4078. case RTL_GIGA_MAC_VER_37:
  4079. case RTL_GIGA_MAC_VER_38:
  4080. ops->write = r8402_csi_write;
  4081. ops->read = r8402_csi_read;
  4082. break;
  4083. case RTL_GIGA_MAC_VER_44:
  4084. ops->write = r8411_csi_write;
  4085. ops->read = r8411_csi_read;
  4086. break;
  4087. default:
  4088. ops->write = r8169_csi_write;
  4089. ops->read = r8169_csi_read;
  4090. break;
  4091. }
  4092. }
  4093. struct ephy_info {
  4094. unsigned int offset;
  4095. u16 mask;
  4096. u16 bits;
  4097. };
  4098. static void rtl_ephy_init(struct rtl8169_private *tp, const struct ephy_info *e,
  4099. int len)
  4100. {
  4101. u16 w;
  4102. while (len-- > 0) {
  4103. w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
  4104. rtl_ephy_write(tp, e->offset, w);
  4105. e++;
  4106. }
  4107. }
  4108. static void rtl_disable_clock_request(struct pci_dev *pdev)
  4109. {
  4110. pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL,
  4111. PCI_EXP_LNKCTL_CLKREQ_EN);
  4112. }
  4113. static void rtl_enable_clock_request(struct pci_dev *pdev)
  4114. {
  4115. pcie_capability_set_word(pdev, PCI_EXP_LNKCTL,
  4116. PCI_EXP_LNKCTL_CLKREQ_EN);
  4117. }
  4118. #define R8168_CPCMD_QUIRK_MASK (\
  4119. EnableBist | \
  4120. Mac_dbgo_oe | \
  4121. Force_half_dup | \
  4122. Force_rxflow_en | \
  4123. Force_txflow_en | \
  4124. Cxpl_dbg_sel | \
  4125. ASF | \
  4126. PktCntrDisable | \
  4127. Mac_dbgo_sel)
  4128. static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
  4129. {
  4130. void __iomem *ioaddr = tp->mmio_addr;
  4131. struct pci_dev *pdev = tp->pci_dev;
  4132. RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
  4133. RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
  4134. if (tp->dev->mtu <= ETH_DATA_LEN) {
  4135. rtl_tx_performance_tweak(pdev, (0x5 << MAX_READ_REQUEST_SHIFT) |
  4136. PCI_EXP_DEVCTL_NOSNOOP_EN);
  4137. }
  4138. }
  4139. static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
  4140. {
  4141. void __iomem *ioaddr = tp->mmio_addr;
  4142. rtl_hw_start_8168bb(tp);
  4143. RTL_W8(MaxTxPacketSize, TxPacketMax);
  4144. RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
  4145. }
  4146. static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
  4147. {
  4148. void __iomem *ioaddr = tp->mmio_addr;
  4149. struct pci_dev *pdev = tp->pci_dev;
  4150. RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
  4151. RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
  4152. if (tp->dev->mtu <= ETH_DATA_LEN)
  4153. rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
  4154. rtl_disable_clock_request(pdev);
  4155. RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
  4156. }
  4157. static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
  4158. {
  4159. static const struct ephy_info e_info_8168cp[] = {
  4160. { 0x01, 0, 0x0001 },
  4161. { 0x02, 0x0800, 0x1000 },
  4162. { 0x03, 0, 0x0042 },
  4163. { 0x06, 0x0080, 0x0000 },
  4164. { 0x07, 0, 0x2000 }
  4165. };
  4166. rtl_csi_access_enable_2(tp);
  4167. rtl_ephy_init(tp, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
  4168. __rtl_hw_start_8168cp(tp);
  4169. }
  4170. static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
  4171. {
  4172. void __iomem *ioaddr = tp->mmio_addr;
  4173. struct pci_dev *pdev = tp->pci_dev;
  4174. rtl_csi_access_enable_2(tp);
  4175. RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
  4176. if (tp->dev->mtu <= ETH_DATA_LEN)
  4177. rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
  4178. RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
  4179. }
  4180. static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
  4181. {
  4182. void __iomem *ioaddr = tp->mmio_addr;
  4183. struct pci_dev *pdev = tp->pci_dev;
  4184. rtl_csi_access_enable_2(tp);
  4185. RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
  4186. /* Magic. */
  4187. RTL_W8(DBG_REG, 0x20);
  4188. RTL_W8(MaxTxPacketSize, TxPacketMax);
  4189. if (tp->dev->mtu <= ETH_DATA_LEN)
  4190. rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
  4191. RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
  4192. }
  4193. static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
  4194. {
  4195. void __iomem *ioaddr = tp->mmio_addr;
  4196. static const struct ephy_info e_info_8168c_1[] = {
  4197. { 0x02, 0x0800, 0x1000 },
  4198. { 0x03, 0, 0x0002 },
  4199. { 0x06, 0x0080, 0x0000 }
  4200. };
  4201. rtl_csi_access_enable_2(tp);
  4202. RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
  4203. rtl_ephy_init(tp, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
  4204. __rtl_hw_start_8168cp(tp);
  4205. }
  4206. static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
  4207. {
  4208. static const struct ephy_info e_info_8168c_2[] = {
  4209. { 0x01, 0, 0x0001 },
  4210. { 0x03, 0x0400, 0x0220 }
  4211. };
  4212. rtl_csi_access_enable_2(tp);
  4213. rtl_ephy_init(tp, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
  4214. __rtl_hw_start_8168cp(tp);
  4215. }
  4216. static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
  4217. {
  4218. rtl_hw_start_8168c_2(tp);
  4219. }
  4220. static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
  4221. {
  4222. rtl_csi_access_enable_2(tp);
  4223. __rtl_hw_start_8168cp(tp);
  4224. }
  4225. static void rtl_hw_start_8168d(struct rtl8169_private *tp)
  4226. {
  4227. void __iomem *ioaddr = tp->mmio_addr;
  4228. struct pci_dev *pdev = tp->pci_dev;
  4229. rtl_csi_access_enable_2(tp);
  4230. rtl_disable_clock_request(pdev);
  4231. RTL_W8(MaxTxPacketSize, TxPacketMax);
  4232. if (tp->dev->mtu <= ETH_DATA_LEN)
  4233. rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
  4234. RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
  4235. }
  4236. static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
  4237. {
  4238. void __iomem *ioaddr = tp->mmio_addr;
  4239. struct pci_dev *pdev = tp->pci_dev;
  4240. rtl_csi_access_enable_1(tp);
  4241. if (tp->dev->mtu <= ETH_DATA_LEN)
  4242. rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
  4243. RTL_W8(MaxTxPacketSize, TxPacketMax);
  4244. rtl_disable_clock_request(pdev);
  4245. }
  4246. static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
  4247. {
  4248. void __iomem *ioaddr = tp->mmio_addr;
  4249. struct pci_dev *pdev = tp->pci_dev;
  4250. static const struct ephy_info e_info_8168d_4[] = {
  4251. { 0x0b, ~0, 0x48 },
  4252. { 0x19, 0x20, 0x50 },
  4253. { 0x0c, ~0, 0x20 }
  4254. };
  4255. int i;
  4256. rtl_csi_access_enable_1(tp);
  4257. rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
  4258. RTL_W8(MaxTxPacketSize, TxPacketMax);
  4259. for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
  4260. const struct ephy_info *e = e_info_8168d_4 + i;
  4261. u16 w;
  4262. w = rtl_ephy_read(tp, e->offset);
  4263. rtl_ephy_write(tp, 0x03, (w & e->mask) | e->bits);
  4264. }
  4265. rtl_enable_clock_request(pdev);
  4266. }
  4267. static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
  4268. {
  4269. void __iomem *ioaddr = tp->mmio_addr;
  4270. struct pci_dev *pdev = tp->pci_dev;
  4271. static const struct ephy_info e_info_8168e_1[] = {
  4272. { 0x00, 0x0200, 0x0100 },
  4273. { 0x00, 0x0000, 0x0004 },
  4274. { 0x06, 0x0002, 0x0001 },
  4275. { 0x06, 0x0000, 0x0030 },
  4276. { 0x07, 0x0000, 0x2000 },
  4277. { 0x00, 0x0000, 0x0020 },
  4278. { 0x03, 0x5800, 0x2000 },
  4279. { 0x03, 0x0000, 0x0001 },
  4280. { 0x01, 0x0800, 0x1000 },
  4281. { 0x07, 0x0000, 0x4000 },
  4282. { 0x1e, 0x0000, 0x2000 },
  4283. { 0x19, 0xffff, 0xfe6c },
  4284. { 0x0a, 0x0000, 0x0040 }
  4285. };
  4286. rtl_csi_access_enable_2(tp);
  4287. rtl_ephy_init(tp, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
  4288. if (tp->dev->mtu <= ETH_DATA_LEN)
  4289. rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
  4290. RTL_W8(MaxTxPacketSize, TxPacketMax);
  4291. rtl_disable_clock_request(pdev);
  4292. /* Reset tx FIFO pointer */
  4293. RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
  4294. RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
  4295. RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
  4296. }
  4297. static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
  4298. {
  4299. void __iomem *ioaddr = tp->mmio_addr;
  4300. struct pci_dev *pdev = tp->pci_dev;
  4301. static const struct ephy_info e_info_8168e_2[] = {
  4302. { 0x09, 0x0000, 0x0080 },
  4303. { 0x19, 0x0000, 0x0224 }
  4304. };
  4305. rtl_csi_access_enable_1(tp);
  4306. rtl_ephy_init(tp, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
  4307. if (tp->dev->mtu <= ETH_DATA_LEN)
  4308. rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
  4309. rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
  4310. rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
  4311. rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
  4312. rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
  4313. rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
  4314. rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
  4315. rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
  4316. rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
  4317. RTL_W8(MaxTxPacketSize, EarlySize);
  4318. rtl_disable_clock_request(pdev);
  4319. RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
  4320. RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
  4321. /* Adjust EEE LED frequency */
  4322. RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
  4323. RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
  4324. RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
  4325. RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
  4326. }
  4327. static void rtl_hw_start_8168f(struct rtl8169_private *tp)
  4328. {
  4329. void __iomem *ioaddr = tp->mmio_addr;
  4330. struct pci_dev *pdev = tp->pci_dev;
  4331. rtl_csi_access_enable_2(tp);
  4332. rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
  4333. rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
  4334. rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
  4335. rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
  4336. rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
  4337. rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
  4338. rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
  4339. rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
  4340. rtl_w1w0_eri(tp, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
  4341. rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
  4342. rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
  4343. RTL_W8(MaxTxPacketSize, EarlySize);
  4344. rtl_disable_clock_request(pdev);
  4345. RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
  4346. RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
  4347. RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
  4348. RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
  4349. RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
  4350. }
  4351. static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
  4352. {
  4353. void __iomem *ioaddr = tp->mmio_addr;
  4354. static const struct ephy_info e_info_8168f_1[] = {
  4355. { 0x06, 0x00c0, 0x0020 },
  4356. { 0x08, 0x0001, 0x0002 },
  4357. { 0x09, 0x0000, 0x0080 },
  4358. { 0x19, 0x0000, 0x0224 }
  4359. };
  4360. rtl_hw_start_8168f(tp);
  4361. rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
  4362. rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
  4363. /* Adjust EEE LED frequency */
  4364. RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
  4365. }
  4366. static void rtl_hw_start_8411(struct rtl8169_private *tp)
  4367. {
  4368. static const struct ephy_info e_info_8168f_1[] = {
  4369. { 0x06, 0x00c0, 0x0020 },
  4370. { 0x0f, 0xffff, 0x5200 },
  4371. { 0x1e, 0x0000, 0x4000 },
  4372. { 0x19, 0x0000, 0x0224 }
  4373. };
  4374. rtl_hw_start_8168f(tp);
  4375. rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
  4376. rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000, ERIAR_EXGMAC);
  4377. }
  4378. static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
  4379. {
  4380. void __iomem *ioaddr = tp->mmio_addr;
  4381. struct pci_dev *pdev = tp->pci_dev;
  4382. RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
  4383. rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x080002, ERIAR_EXGMAC);
  4384. rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
  4385. rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
  4386. rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
  4387. rtl_csi_access_enable_1(tp);
  4388. rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
  4389. rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
  4390. rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
  4391. rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f, ERIAR_EXGMAC);
  4392. RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
  4393. RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
  4394. RTL_W8(MaxTxPacketSize, EarlySize);
  4395. rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
  4396. rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
  4397. /* Adjust EEE LED frequency */
  4398. RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
  4399. rtl_w1w0_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
  4400. rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
  4401. }
  4402. static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
  4403. {
  4404. void __iomem *ioaddr = tp->mmio_addr;
  4405. static const struct ephy_info e_info_8168g_2[] = {
  4406. { 0x00, 0x0000, 0x0008 },
  4407. { 0x0c, 0x3df0, 0x0200 },
  4408. { 0x19, 0xffff, 0xfc00 },
  4409. { 0x1e, 0xffff, 0x20eb }
  4410. };
  4411. rtl_hw_start_8168g_1(tp);
  4412. /* disable aspm and clock request before access ephy */
  4413. RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
  4414. RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
  4415. rtl_ephy_init(tp, e_info_8168g_2, ARRAY_SIZE(e_info_8168g_2));
  4416. }
  4417. static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
  4418. {
  4419. void __iomem *ioaddr = tp->mmio_addr;
  4420. static const struct ephy_info e_info_8411_2[] = {
  4421. { 0x00, 0x0000, 0x0008 },
  4422. { 0x0c, 0x3df0, 0x0200 },
  4423. { 0x0f, 0xffff, 0x5200 },
  4424. { 0x19, 0x0020, 0x0000 },
  4425. { 0x1e, 0x0000, 0x2000 }
  4426. };
  4427. rtl_hw_start_8168g_1(tp);
  4428. /* disable aspm and clock request before access ephy */
  4429. RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
  4430. RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
  4431. rtl_ephy_init(tp, e_info_8411_2, ARRAY_SIZE(e_info_8411_2));
  4432. }
  4433. static void rtl_hw_start_8168(struct net_device *dev)
  4434. {
  4435. struct rtl8169_private *tp = netdev_priv(dev);
  4436. void __iomem *ioaddr = tp->mmio_addr;
  4437. RTL_W8(Cfg9346, Cfg9346_Unlock);
  4438. RTL_W8(MaxTxPacketSize, TxPacketMax);
  4439. rtl_set_rx_max_size(ioaddr, rx_buf_sz);
  4440. tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
  4441. RTL_W16(CPlusCmd, tp->cp_cmd);
  4442. RTL_W16(IntrMitigate, 0x5151);
  4443. /* Work around for RxFIFO overflow. */
  4444. if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
  4445. tp->event_slow |= RxFIFOOver | PCSTimeout;
  4446. tp->event_slow &= ~RxOverflow;
  4447. }
  4448. rtl_set_rx_tx_desc_registers(tp, ioaddr);
  4449. rtl_set_rx_tx_config_registers(tp);
  4450. RTL_R8(IntrMask);
  4451. switch (tp->mac_version) {
  4452. case RTL_GIGA_MAC_VER_11:
  4453. rtl_hw_start_8168bb(tp);
  4454. break;
  4455. case RTL_GIGA_MAC_VER_12:
  4456. case RTL_GIGA_MAC_VER_17:
  4457. rtl_hw_start_8168bef(tp);
  4458. break;
  4459. case RTL_GIGA_MAC_VER_18:
  4460. rtl_hw_start_8168cp_1(tp);
  4461. break;
  4462. case RTL_GIGA_MAC_VER_19:
  4463. rtl_hw_start_8168c_1(tp);
  4464. break;
  4465. case RTL_GIGA_MAC_VER_20:
  4466. rtl_hw_start_8168c_2(tp);
  4467. break;
  4468. case RTL_GIGA_MAC_VER_21:
  4469. rtl_hw_start_8168c_3(tp);
  4470. break;
  4471. case RTL_GIGA_MAC_VER_22:
  4472. rtl_hw_start_8168c_4(tp);
  4473. break;
  4474. case RTL_GIGA_MAC_VER_23:
  4475. rtl_hw_start_8168cp_2(tp);
  4476. break;
  4477. case RTL_GIGA_MAC_VER_24:
  4478. rtl_hw_start_8168cp_3(tp);
  4479. break;
  4480. case RTL_GIGA_MAC_VER_25:
  4481. case RTL_GIGA_MAC_VER_26:
  4482. case RTL_GIGA_MAC_VER_27:
  4483. rtl_hw_start_8168d(tp);
  4484. break;
  4485. case RTL_GIGA_MAC_VER_28:
  4486. rtl_hw_start_8168d_4(tp);
  4487. break;
  4488. case RTL_GIGA_MAC_VER_31:
  4489. rtl_hw_start_8168dp(tp);
  4490. break;
  4491. case RTL_GIGA_MAC_VER_32:
  4492. case RTL_GIGA_MAC_VER_33:
  4493. rtl_hw_start_8168e_1(tp);
  4494. break;
  4495. case RTL_GIGA_MAC_VER_34:
  4496. rtl_hw_start_8168e_2(tp);
  4497. break;
  4498. case RTL_GIGA_MAC_VER_35:
  4499. case RTL_GIGA_MAC_VER_36:
  4500. rtl_hw_start_8168f_1(tp);
  4501. break;
  4502. case RTL_GIGA_MAC_VER_38:
  4503. rtl_hw_start_8411(tp);
  4504. break;
  4505. case RTL_GIGA_MAC_VER_40:
  4506. case RTL_GIGA_MAC_VER_41:
  4507. rtl_hw_start_8168g_1(tp);
  4508. break;
  4509. case RTL_GIGA_MAC_VER_42:
  4510. rtl_hw_start_8168g_2(tp);
  4511. break;
  4512. case RTL_GIGA_MAC_VER_44:
  4513. rtl_hw_start_8411_2(tp);
  4514. break;
  4515. default:
  4516. printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
  4517. dev->name, tp->mac_version);
  4518. break;
  4519. }
  4520. RTL_W8(Cfg9346, Cfg9346_Lock);
  4521. RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
  4522. rtl_set_rx_mode(dev);
  4523. RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
  4524. }
  4525. #define R810X_CPCMD_QUIRK_MASK (\
  4526. EnableBist | \
  4527. Mac_dbgo_oe | \
  4528. Force_half_dup | \
  4529. Force_rxflow_en | \
  4530. Force_txflow_en | \
  4531. Cxpl_dbg_sel | \
  4532. ASF | \
  4533. PktCntrDisable | \
  4534. Mac_dbgo_sel)
  4535. static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
  4536. {
  4537. void __iomem *ioaddr = tp->mmio_addr;
  4538. struct pci_dev *pdev = tp->pci_dev;
  4539. static const struct ephy_info e_info_8102e_1[] = {
  4540. { 0x01, 0, 0x6e65 },
  4541. { 0x02, 0, 0x091f },
  4542. { 0x03, 0, 0xc2f9 },
  4543. { 0x06, 0, 0xafb5 },
  4544. { 0x07, 0, 0x0e00 },
  4545. { 0x19, 0, 0xec80 },
  4546. { 0x01, 0, 0x2e65 },
  4547. { 0x01, 0, 0x6e65 }
  4548. };
  4549. u8 cfg1;
  4550. rtl_csi_access_enable_2(tp);
  4551. RTL_W8(DBG_REG, FIX_NAK_1);
  4552. rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
  4553. RTL_W8(Config1,
  4554. LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
  4555. RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
  4556. cfg1 = RTL_R8(Config1);
  4557. if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
  4558. RTL_W8(Config1, cfg1 & ~LEDS0);
  4559. rtl_ephy_init(tp, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
  4560. }
  4561. static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
  4562. {
  4563. void __iomem *ioaddr = tp->mmio_addr;
  4564. struct pci_dev *pdev = tp->pci_dev;
  4565. rtl_csi_access_enable_2(tp);
  4566. rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
  4567. RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
  4568. RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
  4569. }
  4570. static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
  4571. {
  4572. rtl_hw_start_8102e_2(tp);
  4573. rtl_ephy_write(tp, 0x03, 0xc2f9);
  4574. }
  4575. static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
  4576. {
  4577. void __iomem *ioaddr = tp->mmio_addr;
  4578. static const struct ephy_info e_info_8105e_1[] = {
  4579. { 0x07, 0, 0x4000 },
  4580. { 0x19, 0, 0x0200 },
  4581. { 0x19, 0, 0x0020 },
  4582. { 0x1e, 0, 0x2000 },
  4583. { 0x03, 0, 0x0001 },
  4584. { 0x19, 0, 0x0100 },
  4585. { 0x19, 0, 0x0004 },
  4586. { 0x0a, 0, 0x0020 }
  4587. };
  4588. /* Force LAN exit from ASPM if Rx/Tx are not idle */
  4589. RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
  4590. /* Disable Early Tally Counter */
  4591. RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
  4592. RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
  4593. RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
  4594. rtl_ephy_init(tp, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
  4595. }
  4596. static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
  4597. {
  4598. rtl_hw_start_8105e_1(tp);
  4599. rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
  4600. }
  4601. static void rtl_hw_start_8402(struct rtl8169_private *tp)
  4602. {
  4603. void __iomem *ioaddr = tp->mmio_addr;
  4604. static const struct ephy_info e_info_8402[] = {
  4605. { 0x19, 0xffff, 0xff64 },
  4606. { 0x1e, 0, 0x4000 }
  4607. };
  4608. rtl_csi_access_enable_2(tp);
  4609. /* Force LAN exit from ASPM if Rx/Tx are not idle */
  4610. RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
  4611. RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
  4612. RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
  4613. rtl_ephy_init(tp, e_info_8402, ARRAY_SIZE(e_info_8402));
  4614. rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
  4615. rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC);
  4616. rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC);
  4617. rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
  4618. rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
  4619. rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
  4620. rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
  4621. rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00, ERIAR_EXGMAC);
  4622. }
  4623. static void rtl_hw_start_8106(struct rtl8169_private *tp)
  4624. {
  4625. void __iomem *ioaddr = tp->mmio_addr;
  4626. /* Force LAN exit from ASPM if Rx/Tx are not idle */
  4627. RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
  4628. RTL_W32(MISC, (RTL_R32(MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
  4629. RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
  4630. RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
  4631. }
  4632. static void rtl_hw_start_8101(struct net_device *dev)
  4633. {
  4634. struct rtl8169_private *tp = netdev_priv(dev);
  4635. void __iomem *ioaddr = tp->mmio_addr;
  4636. struct pci_dev *pdev = tp->pci_dev;
  4637. if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
  4638. tp->event_slow &= ~RxFIFOOver;
  4639. if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
  4640. tp->mac_version == RTL_GIGA_MAC_VER_16)
  4641. pcie_capability_set_word(pdev, PCI_EXP_DEVCTL,
  4642. PCI_EXP_DEVCTL_NOSNOOP_EN);
  4643. RTL_W8(Cfg9346, Cfg9346_Unlock);
  4644. RTL_W8(MaxTxPacketSize, TxPacketMax);
  4645. rtl_set_rx_max_size(ioaddr, rx_buf_sz);
  4646. tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
  4647. RTL_W16(CPlusCmd, tp->cp_cmd);
  4648. rtl_set_rx_tx_desc_registers(tp, ioaddr);
  4649. rtl_set_rx_tx_config_registers(tp);
  4650. switch (tp->mac_version) {
  4651. case RTL_GIGA_MAC_VER_07:
  4652. rtl_hw_start_8102e_1(tp);
  4653. break;
  4654. case RTL_GIGA_MAC_VER_08:
  4655. rtl_hw_start_8102e_3(tp);
  4656. break;
  4657. case RTL_GIGA_MAC_VER_09:
  4658. rtl_hw_start_8102e_2(tp);
  4659. break;
  4660. case RTL_GIGA_MAC_VER_29:
  4661. rtl_hw_start_8105e_1(tp);
  4662. break;
  4663. case RTL_GIGA_MAC_VER_30:
  4664. rtl_hw_start_8105e_2(tp);
  4665. break;
  4666. case RTL_GIGA_MAC_VER_37:
  4667. rtl_hw_start_8402(tp);
  4668. break;
  4669. case RTL_GIGA_MAC_VER_39:
  4670. rtl_hw_start_8106(tp);
  4671. break;
  4672. case RTL_GIGA_MAC_VER_43:
  4673. rtl_hw_start_8168g_2(tp);
  4674. break;
  4675. }
  4676. RTL_W8(Cfg9346, Cfg9346_Lock);
  4677. RTL_W16(IntrMitigate, 0x0000);
  4678. RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
  4679. rtl_set_rx_mode(dev);
  4680. RTL_R8(IntrMask);
  4681. RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
  4682. }
  4683. static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
  4684. {
  4685. struct rtl8169_private *tp = netdev_priv(dev);
  4686. if (new_mtu < ETH_ZLEN ||
  4687. new_mtu > rtl_chip_infos[tp->mac_version].jumbo_max)
  4688. return -EINVAL;
  4689. if (new_mtu > ETH_DATA_LEN)
  4690. rtl_hw_jumbo_enable(tp);
  4691. else
  4692. rtl_hw_jumbo_disable(tp);
  4693. dev->mtu = new_mtu;
  4694. netdev_update_features(dev);
  4695. return 0;
  4696. }
  4697. static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
  4698. {
  4699. desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
  4700. desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
  4701. }
  4702. static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
  4703. void **data_buff, struct RxDesc *desc)
  4704. {
  4705. dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
  4706. DMA_FROM_DEVICE);
  4707. kfree(*data_buff);
  4708. *data_buff = NULL;
  4709. rtl8169_make_unusable_by_asic(desc);
  4710. }
  4711. static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
  4712. {
  4713. u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
  4714. desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
  4715. }
  4716. static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
  4717. u32 rx_buf_sz)
  4718. {
  4719. desc->addr = cpu_to_le64(mapping);
  4720. wmb();
  4721. rtl8169_mark_to_asic(desc, rx_buf_sz);
  4722. }
  4723. static inline void *rtl8169_align(void *data)
  4724. {
  4725. return (void *)ALIGN((long)data, 16);
  4726. }
  4727. static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
  4728. struct RxDesc *desc)
  4729. {
  4730. void *data;
  4731. dma_addr_t mapping;
  4732. struct device *d = &tp->pci_dev->dev;
  4733. struct net_device *dev = tp->dev;
  4734. int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
  4735. data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
  4736. if (!data)
  4737. return NULL;
  4738. if (rtl8169_align(data) != data) {
  4739. kfree(data);
  4740. data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
  4741. if (!data)
  4742. return NULL;
  4743. }
  4744. mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
  4745. DMA_FROM_DEVICE);
  4746. if (unlikely(dma_mapping_error(d, mapping))) {
  4747. if (net_ratelimit())
  4748. netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
  4749. goto err_out;
  4750. }
  4751. rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
  4752. return data;
  4753. err_out:
  4754. kfree(data);
  4755. return NULL;
  4756. }
  4757. static void rtl8169_rx_clear(struct rtl8169_private *tp)
  4758. {
  4759. unsigned int i;
  4760. for (i = 0; i < NUM_RX_DESC; i++) {
  4761. if (tp->Rx_databuff[i]) {
  4762. rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
  4763. tp->RxDescArray + i);
  4764. }
  4765. }
  4766. }
  4767. static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
  4768. {
  4769. desc->opts1 |= cpu_to_le32(RingEnd);
  4770. }
  4771. static int rtl8169_rx_fill(struct rtl8169_private *tp)
  4772. {
  4773. unsigned int i;
  4774. for (i = 0; i < NUM_RX_DESC; i++) {
  4775. void *data;
  4776. if (tp->Rx_databuff[i])
  4777. continue;
  4778. data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
  4779. if (!data) {
  4780. rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
  4781. goto err_out;
  4782. }
  4783. tp->Rx_databuff[i] = data;
  4784. }
  4785. rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
  4786. return 0;
  4787. err_out:
  4788. rtl8169_rx_clear(tp);
  4789. return -ENOMEM;
  4790. }
  4791. static int rtl8169_init_ring(struct net_device *dev)
  4792. {
  4793. struct rtl8169_private *tp = netdev_priv(dev);
  4794. rtl8169_init_ring_indexes(tp);
  4795. memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
  4796. memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
  4797. return rtl8169_rx_fill(tp);
  4798. }
  4799. static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
  4800. struct TxDesc *desc)
  4801. {
  4802. unsigned int len = tx_skb->len;
  4803. dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
  4804. desc->opts1 = 0x00;
  4805. desc->opts2 = 0x00;
  4806. desc->addr = 0x00;
  4807. tx_skb->len = 0;
  4808. }
  4809. static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
  4810. unsigned int n)
  4811. {
  4812. unsigned int i;
  4813. for (i = 0; i < n; i++) {
  4814. unsigned int entry = (start + i) % NUM_TX_DESC;
  4815. struct ring_info *tx_skb = tp->tx_skb + entry;
  4816. unsigned int len = tx_skb->len;
  4817. if (len) {
  4818. struct sk_buff *skb = tx_skb->skb;
  4819. rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
  4820. tp->TxDescArray + entry);
  4821. if (skb) {
  4822. tp->dev->stats.tx_dropped++;
  4823. dev_kfree_skb(skb);
  4824. tx_skb->skb = NULL;
  4825. }
  4826. }
  4827. }
  4828. }
  4829. static void rtl8169_tx_clear(struct rtl8169_private *tp)
  4830. {
  4831. rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
  4832. tp->cur_tx = tp->dirty_tx = 0;
  4833. }
  4834. static void rtl_reset_work(struct rtl8169_private *tp)
  4835. {
  4836. struct net_device *dev = tp->dev;
  4837. int i;
  4838. napi_disable(&tp->napi);
  4839. netif_stop_queue(dev);
  4840. synchronize_sched();
  4841. rtl8169_hw_reset(tp);
  4842. for (i = 0; i < NUM_RX_DESC; i++)
  4843. rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
  4844. rtl8169_tx_clear(tp);
  4845. rtl8169_init_ring_indexes(tp);
  4846. napi_enable(&tp->napi);
  4847. rtl_hw_start(dev);
  4848. netif_wake_queue(dev);
  4849. rtl8169_check_link_status(dev, tp, tp->mmio_addr);
  4850. }
  4851. static void rtl8169_tx_timeout(struct net_device *dev)
  4852. {
  4853. struct rtl8169_private *tp = netdev_priv(dev);
  4854. rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
  4855. }
  4856. static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
  4857. u32 *opts)
  4858. {
  4859. struct skb_shared_info *info = skb_shinfo(skb);
  4860. unsigned int cur_frag, entry;
  4861. struct TxDesc * uninitialized_var(txd);
  4862. struct device *d = &tp->pci_dev->dev;
  4863. entry = tp->cur_tx;
  4864. for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
  4865. const skb_frag_t *frag = info->frags + cur_frag;
  4866. dma_addr_t mapping;
  4867. u32 status, len;
  4868. void *addr;
  4869. entry = (entry + 1) % NUM_TX_DESC;
  4870. txd = tp->TxDescArray + entry;
  4871. len = skb_frag_size(frag);
  4872. addr = skb_frag_address(frag);
  4873. mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
  4874. if (unlikely(dma_mapping_error(d, mapping))) {
  4875. if (net_ratelimit())
  4876. netif_err(tp, drv, tp->dev,
  4877. "Failed to map TX fragments DMA!\n");
  4878. goto err_out;
  4879. }
  4880. /* Anti gcc 2.95.3 bugware (sic) */
  4881. status = opts[0] | len |
  4882. (RingEnd * !((entry + 1) % NUM_TX_DESC));
  4883. txd->opts1 = cpu_to_le32(status);
  4884. txd->opts2 = cpu_to_le32(opts[1]);
  4885. txd->addr = cpu_to_le64(mapping);
  4886. tp->tx_skb[entry].len = len;
  4887. }
  4888. if (cur_frag) {
  4889. tp->tx_skb[entry].skb = skb;
  4890. txd->opts1 |= cpu_to_le32(LastFrag);
  4891. }
  4892. return cur_frag;
  4893. err_out:
  4894. rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
  4895. return -EIO;
  4896. }
  4897. static bool rtl_skb_pad(struct sk_buff *skb)
  4898. {
  4899. if (skb_padto(skb, ETH_ZLEN))
  4900. return false;
  4901. skb_put(skb, ETH_ZLEN - skb->len);
  4902. return true;
  4903. }
  4904. static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
  4905. {
  4906. return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
  4907. }
  4908. static inline bool rtl8169_tso_csum(struct rtl8169_private *tp,
  4909. struct sk_buff *skb, u32 *opts)
  4910. {
  4911. const struct rtl_tx_desc_info *info = tx_desc_info + tp->txd_version;
  4912. u32 mss = skb_shinfo(skb)->gso_size;
  4913. int offset = info->opts_offset;
  4914. if (mss) {
  4915. opts[0] |= TD_LSO;
  4916. opts[offset] |= min(mss, TD_MSS_MAX) << info->mss_shift;
  4917. } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
  4918. const struct iphdr *ip = ip_hdr(skb);
  4919. if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
  4920. return skb_checksum_help(skb) == 0 && rtl_skb_pad(skb);
  4921. if (ip->protocol == IPPROTO_TCP)
  4922. opts[offset] |= info->checksum.tcp;
  4923. else if (ip->protocol == IPPROTO_UDP)
  4924. opts[offset] |= info->checksum.udp;
  4925. else
  4926. WARN_ON_ONCE(1);
  4927. } else {
  4928. if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
  4929. return rtl_skb_pad(skb);
  4930. }
  4931. return true;
  4932. }
  4933. static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
  4934. struct net_device *dev)
  4935. {
  4936. struct rtl8169_private *tp = netdev_priv(dev);
  4937. unsigned int entry = tp->cur_tx % NUM_TX_DESC;
  4938. struct TxDesc *txd = tp->TxDescArray + entry;
  4939. void __iomem *ioaddr = tp->mmio_addr;
  4940. struct device *d = &tp->pci_dev->dev;
  4941. dma_addr_t mapping;
  4942. u32 status, len;
  4943. u32 opts[2];
  4944. int frags;
  4945. if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) {
  4946. netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
  4947. goto err_stop_0;
  4948. }
  4949. if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
  4950. goto err_stop_0;
  4951. opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb));
  4952. opts[0] = DescOwn;
  4953. if (!rtl8169_tso_csum(tp, skb, opts))
  4954. goto err_update_stats;
  4955. len = skb_headlen(skb);
  4956. mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
  4957. if (unlikely(dma_mapping_error(d, mapping))) {
  4958. if (net_ratelimit())
  4959. netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
  4960. goto err_dma_0;
  4961. }
  4962. tp->tx_skb[entry].len = len;
  4963. txd->addr = cpu_to_le64(mapping);
  4964. frags = rtl8169_xmit_frags(tp, skb, opts);
  4965. if (frags < 0)
  4966. goto err_dma_1;
  4967. else if (frags)
  4968. opts[0] |= FirstFrag;
  4969. else {
  4970. opts[0] |= FirstFrag | LastFrag;
  4971. tp->tx_skb[entry].skb = skb;
  4972. }
  4973. txd->opts2 = cpu_to_le32(opts[1]);
  4974. skb_tx_timestamp(skb);
  4975. wmb();
  4976. /* Anti gcc 2.95.3 bugware (sic) */
  4977. status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
  4978. txd->opts1 = cpu_to_le32(status);
  4979. tp->cur_tx += frags + 1;
  4980. wmb();
  4981. RTL_W8(TxPoll, NPQ);
  4982. mmiowb();
  4983. if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
  4984. /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
  4985. * not miss a ring update when it notices a stopped queue.
  4986. */
  4987. smp_wmb();
  4988. netif_stop_queue(dev);
  4989. /* Sync with rtl_tx:
  4990. * - publish queue status and cur_tx ring index (write barrier)
  4991. * - refresh dirty_tx ring index (read barrier).
  4992. * May the current thread have a pessimistic view of the ring
  4993. * status and forget to wake up queue, a racing rtl_tx thread
  4994. * can't.
  4995. */
  4996. smp_mb();
  4997. if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS))
  4998. netif_wake_queue(dev);
  4999. }
  5000. return NETDEV_TX_OK;
  5001. err_dma_1:
  5002. rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
  5003. err_dma_0:
  5004. dev_kfree_skb(skb);
  5005. err_update_stats:
  5006. dev->stats.tx_dropped++;
  5007. return NETDEV_TX_OK;
  5008. err_stop_0:
  5009. netif_stop_queue(dev);
  5010. dev->stats.tx_dropped++;
  5011. return NETDEV_TX_BUSY;
  5012. }
  5013. static void rtl8169_pcierr_interrupt(struct net_device *dev)
  5014. {
  5015. struct rtl8169_private *tp = netdev_priv(dev);
  5016. struct pci_dev *pdev = tp->pci_dev;
  5017. u16 pci_status, pci_cmd;
  5018. pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
  5019. pci_read_config_word(pdev, PCI_STATUS, &pci_status);
  5020. netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
  5021. pci_cmd, pci_status);
  5022. /*
  5023. * The recovery sequence below admits a very elaborated explanation:
  5024. * - it seems to work;
  5025. * - I did not see what else could be done;
  5026. * - it makes iop3xx happy.
  5027. *
  5028. * Feel free to adjust to your needs.
  5029. */
  5030. if (pdev->broken_parity_status)
  5031. pci_cmd &= ~PCI_COMMAND_PARITY;
  5032. else
  5033. pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
  5034. pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
  5035. pci_write_config_word(pdev, PCI_STATUS,
  5036. pci_status & (PCI_STATUS_DETECTED_PARITY |
  5037. PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
  5038. PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
  5039. /* The infamous DAC f*ckup only happens at boot time */
  5040. if ((tp->cp_cmd & PCIDAC) && !tp->cur_rx) {
  5041. void __iomem *ioaddr = tp->mmio_addr;
  5042. netif_info(tp, intr, dev, "disabling PCI DAC\n");
  5043. tp->cp_cmd &= ~PCIDAC;
  5044. RTL_W16(CPlusCmd, tp->cp_cmd);
  5045. dev->features &= ~NETIF_F_HIGHDMA;
  5046. }
  5047. rtl8169_hw_reset(tp);
  5048. rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
  5049. }
  5050. static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
  5051. {
  5052. unsigned int dirty_tx, tx_left;
  5053. dirty_tx = tp->dirty_tx;
  5054. smp_rmb();
  5055. tx_left = tp->cur_tx - dirty_tx;
  5056. while (tx_left > 0) {
  5057. unsigned int entry = dirty_tx % NUM_TX_DESC;
  5058. struct ring_info *tx_skb = tp->tx_skb + entry;
  5059. u32 status;
  5060. rmb();
  5061. status = le32_to_cpu(tp->TxDescArray[entry].opts1);
  5062. if (status & DescOwn)
  5063. break;
  5064. rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
  5065. tp->TxDescArray + entry);
  5066. if (status & LastFrag) {
  5067. u64_stats_update_begin(&tp->tx_stats.syncp);
  5068. tp->tx_stats.packets++;
  5069. tp->tx_stats.bytes += tx_skb->skb->len;
  5070. u64_stats_update_end(&tp->tx_stats.syncp);
  5071. dev_kfree_skb(tx_skb->skb);
  5072. tx_skb->skb = NULL;
  5073. }
  5074. dirty_tx++;
  5075. tx_left--;
  5076. }
  5077. if (tp->dirty_tx != dirty_tx) {
  5078. tp->dirty_tx = dirty_tx;
  5079. /* Sync with rtl8169_start_xmit:
  5080. * - publish dirty_tx ring index (write barrier)
  5081. * - refresh cur_tx ring index and queue status (read barrier)
  5082. * May the current thread miss the stopped queue condition,
  5083. * a racing xmit thread can only have a right view of the
  5084. * ring status.
  5085. */
  5086. smp_mb();
  5087. if (netif_queue_stopped(dev) &&
  5088. TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
  5089. netif_wake_queue(dev);
  5090. }
  5091. /*
  5092. * 8168 hack: TxPoll requests are lost when the Tx packets are
  5093. * too close. Let's kick an extra TxPoll request when a burst
  5094. * of start_xmit activity is detected (if it is not detected,
  5095. * it is slow enough). -- FR
  5096. */
  5097. if (tp->cur_tx != dirty_tx) {
  5098. void __iomem *ioaddr = tp->mmio_addr;
  5099. RTL_W8(TxPoll, NPQ);
  5100. }
  5101. }
  5102. }
  5103. static inline int rtl8169_fragmented_frame(u32 status)
  5104. {
  5105. return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
  5106. }
  5107. static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
  5108. {
  5109. u32 status = opts1 & RxProtoMask;
  5110. if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
  5111. ((status == RxProtoUDP) && !(opts1 & UDPFail)))
  5112. skb->ip_summed = CHECKSUM_UNNECESSARY;
  5113. else
  5114. skb_checksum_none_assert(skb);
  5115. }
  5116. static struct sk_buff *rtl8169_try_rx_copy(void *data,
  5117. struct rtl8169_private *tp,
  5118. int pkt_size,
  5119. dma_addr_t addr)
  5120. {
  5121. struct sk_buff *skb;
  5122. struct device *d = &tp->pci_dev->dev;
  5123. data = rtl8169_align(data);
  5124. dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
  5125. prefetch(data);
  5126. skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
  5127. if (skb)
  5128. memcpy(skb->data, data, pkt_size);
  5129. dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
  5130. return skb;
  5131. }
  5132. static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
  5133. {
  5134. unsigned int cur_rx, rx_left;
  5135. unsigned int count;
  5136. cur_rx = tp->cur_rx;
  5137. for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
  5138. unsigned int entry = cur_rx % NUM_RX_DESC;
  5139. struct RxDesc *desc = tp->RxDescArray + entry;
  5140. u32 status;
  5141. rmb();
  5142. status = le32_to_cpu(desc->opts1) & tp->opts1_mask;
  5143. if (status & DescOwn)
  5144. break;
  5145. if (unlikely(status & RxRES)) {
  5146. netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
  5147. status);
  5148. dev->stats.rx_errors++;
  5149. if (status & (RxRWT | RxRUNT))
  5150. dev->stats.rx_length_errors++;
  5151. if (status & RxCRC)
  5152. dev->stats.rx_crc_errors++;
  5153. if (status & RxFOVF) {
  5154. rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
  5155. dev->stats.rx_fifo_errors++;
  5156. }
  5157. if ((status & (RxRUNT | RxCRC)) &&
  5158. !(status & (RxRWT | RxFOVF)) &&
  5159. (dev->features & NETIF_F_RXALL))
  5160. goto process_pkt;
  5161. } else {
  5162. struct sk_buff *skb;
  5163. dma_addr_t addr;
  5164. int pkt_size;
  5165. process_pkt:
  5166. addr = le64_to_cpu(desc->addr);
  5167. if (likely(!(dev->features & NETIF_F_RXFCS)))
  5168. pkt_size = (status & 0x00003fff) - 4;
  5169. else
  5170. pkt_size = status & 0x00003fff;
  5171. /*
  5172. * The driver does not support incoming fragmented
  5173. * frames. They are seen as a symptom of over-mtu
  5174. * sized frames.
  5175. */
  5176. if (unlikely(rtl8169_fragmented_frame(status))) {
  5177. dev->stats.rx_dropped++;
  5178. dev->stats.rx_length_errors++;
  5179. goto release_descriptor;
  5180. }
  5181. skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
  5182. tp, pkt_size, addr);
  5183. if (!skb) {
  5184. dev->stats.rx_dropped++;
  5185. goto release_descriptor;
  5186. }
  5187. rtl8169_rx_csum(skb, status);
  5188. skb_put(skb, pkt_size);
  5189. skb->protocol = eth_type_trans(skb, dev);
  5190. rtl8169_rx_vlan_tag(desc, skb);
  5191. napi_gro_receive(&tp->napi, skb);
  5192. u64_stats_update_begin(&tp->rx_stats.syncp);
  5193. tp->rx_stats.packets++;
  5194. tp->rx_stats.bytes += pkt_size;
  5195. u64_stats_update_end(&tp->rx_stats.syncp);
  5196. }
  5197. release_descriptor:
  5198. desc->opts2 = 0;
  5199. wmb();
  5200. rtl8169_mark_to_asic(desc, rx_buf_sz);
  5201. }
  5202. count = cur_rx - tp->cur_rx;
  5203. tp->cur_rx = cur_rx;
  5204. return count;
  5205. }
  5206. static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
  5207. {
  5208. struct net_device *dev = dev_instance;
  5209. struct rtl8169_private *tp = netdev_priv(dev);
  5210. int handled = 0;
  5211. u16 status;
  5212. status = rtl_get_events(tp);
  5213. if (status && status != 0xffff) {
  5214. status &= RTL_EVENT_NAPI | tp->event_slow;
  5215. if (status) {
  5216. handled = 1;
  5217. rtl_irq_disable(tp);
  5218. napi_schedule(&tp->napi);
  5219. }
  5220. }
  5221. return IRQ_RETVAL(handled);
  5222. }
  5223. /*
  5224. * Workqueue context.
  5225. */
  5226. static void rtl_slow_event_work(struct rtl8169_private *tp)
  5227. {
  5228. struct net_device *dev = tp->dev;
  5229. u16 status;
  5230. status = rtl_get_events(tp) & tp->event_slow;
  5231. rtl_ack_events(tp, status);
  5232. if (unlikely(status & RxFIFOOver)) {
  5233. switch (tp->mac_version) {
  5234. /* Work around for rx fifo overflow */
  5235. case RTL_GIGA_MAC_VER_11:
  5236. netif_stop_queue(dev);
  5237. /* XXX - Hack alert. See rtl_task(). */
  5238. set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
  5239. default:
  5240. break;
  5241. }
  5242. }
  5243. if (unlikely(status & SYSErr))
  5244. rtl8169_pcierr_interrupt(dev);
  5245. if (status & LinkChg)
  5246. __rtl8169_check_link_status(dev, tp, tp->mmio_addr, true);
  5247. rtl_irq_enable_all(tp);
  5248. }
  5249. static void rtl_task(struct work_struct *work)
  5250. {
  5251. static const struct {
  5252. int bitnr;
  5253. void (*action)(struct rtl8169_private *);
  5254. } rtl_work[] = {
  5255. /* XXX - keep rtl_slow_event_work() as first element. */
  5256. { RTL_FLAG_TASK_SLOW_PENDING, rtl_slow_event_work },
  5257. { RTL_FLAG_TASK_RESET_PENDING, rtl_reset_work },
  5258. { RTL_FLAG_TASK_PHY_PENDING, rtl_phy_work }
  5259. };
  5260. struct rtl8169_private *tp =
  5261. container_of(work, struct rtl8169_private, wk.work);
  5262. struct net_device *dev = tp->dev;
  5263. int i;
  5264. rtl_lock_work(tp);
  5265. if (!netif_running(dev) ||
  5266. !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
  5267. goto out_unlock;
  5268. for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
  5269. bool pending;
  5270. pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
  5271. if (pending)
  5272. rtl_work[i].action(tp);
  5273. }
  5274. out_unlock:
  5275. rtl_unlock_work(tp);
  5276. }
  5277. static int rtl8169_poll(struct napi_struct *napi, int budget)
  5278. {
  5279. struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
  5280. struct net_device *dev = tp->dev;
  5281. u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow;
  5282. int work_done= 0;
  5283. u16 status;
  5284. status = rtl_get_events(tp);
  5285. rtl_ack_events(tp, status & ~tp->event_slow);
  5286. if (status & RTL_EVENT_NAPI_RX)
  5287. work_done = rtl_rx(dev, tp, (u32) budget);
  5288. if (status & RTL_EVENT_NAPI_TX)
  5289. rtl_tx(dev, tp);
  5290. if (status & tp->event_slow) {
  5291. enable_mask &= ~tp->event_slow;
  5292. rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING);
  5293. }
  5294. if (work_done < budget) {
  5295. napi_complete(napi);
  5296. rtl_irq_enable(tp, enable_mask);
  5297. mmiowb();
  5298. }
  5299. return work_done;
  5300. }
  5301. static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
  5302. {
  5303. struct rtl8169_private *tp = netdev_priv(dev);
  5304. if (tp->mac_version > RTL_GIGA_MAC_VER_06)
  5305. return;
  5306. dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
  5307. RTL_W32(RxMissed, 0);
  5308. }
  5309. static void rtl8169_down(struct net_device *dev)
  5310. {
  5311. struct rtl8169_private *tp = netdev_priv(dev);
  5312. void __iomem *ioaddr = tp->mmio_addr;
  5313. del_timer_sync(&tp->timer);
  5314. napi_disable(&tp->napi);
  5315. netif_stop_queue(dev);
  5316. rtl8169_hw_reset(tp);
  5317. /*
  5318. * At this point device interrupts can not be enabled in any function,
  5319. * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
  5320. * and napi is disabled (rtl8169_poll).
  5321. */
  5322. rtl8169_rx_missed(dev, ioaddr);
  5323. /* Give a racing hard_start_xmit a few cycles to complete. */
  5324. synchronize_sched();
  5325. rtl8169_tx_clear(tp);
  5326. rtl8169_rx_clear(tp);
  5327. rtl_pll_power_down(tp);
  5328. }
  5329. static int rtl8169_close(struct net_device *dev)
  5330. {
  5331. struct rtl8169_private *tp = netdev_priv(dev);
  5332. struct pci_dev *pdev = tp->pci_dev;
  5333. pm_runtime_get_sync(&pdev->dev);
  5334. /* Update counters before going down */
  5335. rtl8169_update_counters(dev);
  5336. rtl_lock_work(tp);
  5337. clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
  5338. rtl8169_down(dev);
  5339. rtl_unlock_work(tp);
  5340. cancel_work_sync(&tp->wk.work);
  5341. free_irq(pdev->irq, dev);
  5342. dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
  5343. tp->RxPhyAddr);
  5344. dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
  5345. tp->TxPhyAddr);
  5346. tp->TxDescArray = NULL;
  5347. tp->RxDescArray = NULL;
  5348. pm_runtime_put_sync(&pdev->dev);
  5349. return 0;
  5350. }
  5351. #ifdef CONFIG_NET_POLL_CONTROLLER
  5352. static void rtl8169_netpoll(struct net_device *dev)
  5353. {
  5354. struct rtl8169_private *tp = netdev_priv(dev);
  5355. rtl8169_interrupt(tp->pci_dev->irq, dev);
  5356. }
  5357. #endif
  5358. static int rtl_open(struct net_device *dev)
  5359. {
  5360. struct rtl8169_private *tp = netdev_priv(dev);
  5361. void __iomem *ioaddr = tp->mmio_addr;
  5362. struct pci_dev *pdev = tp->pci_dev;
  5363. int retval = -ENOMEM;
  5364. pm_runtime_get_sync(&pdev->dev);
  5365. /*
  5366. * Rx and Tx descriptors needs 256 bytes alignment.
  5367. * dma_alloc_coherent provides more.
  5368. */
  5369. tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
  5370. &tp->TxPhyAddr, GFP_KERNEL);
  5371. if (!tp->TxDescArray)
  5372. goto err_pm_runtime_put;
  5373. tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
  5374. &tp->RxPhyAddr, GFP_KERNEL);
  5375. if (!tp->RxDescArray)
  5376. goto err_free_tx_0;
  5377. retval = rtl8169_init_ring(dev);
  5378. if (retval < 0)
  5379. goto err_free_rx_1;
  5380. INIT_WORK(&tp->wk.work, rtl_task);
  5381. smp_mb();
  5382. rtl_request_firmware(tp);
  5383. retval = request_irq(pdev->irq, rtl8169_interrupt,
  5384. (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
  5385. dev->name, dev);
  5386. if (retval < 0)
  5387. goto err_release_fw_2;
  5388. rtl_lock_work(tp);
  5389. set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
  5390. napi_enable(&tp->napi);
  5391. rtl8169_init_phy(dev, tp);
  5392. __rtl8169_set_features(dev, dev->features);
  5393. rtl_pll_power_up(tp);
  5394. rtl_hw_start(dev);
  5395. netif_start_queue(dev);
  5396. rtl_unlock_work(tp);
  5397. tp->saved_wolopts = 0;
  5398. pm_runtime_put_noidle(&pdev->dev);
  5399. rtl8169_check_link_status(dev, tp, ioaddr);
  5400. out:
  5401. return retval;
  5402. err_release_fw_2:
  5403. rtl_release_firmware(tp);
  5404. rtl8169_rx_clear(tp);
  5405. err_free_rx_1:
  5406. dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
  5407. tp->RxPhyAddr);
  5408. tp->RxDescArray = NULL;
  5409. err_free_tx_0:
  5410. dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
  5411. tp->TxPhyAddr);
  5412. tp->TxDescArray = NULL;
  5413. err_pm_runtime_put:
  5414. pm_runtime_put_noidle(&pdev->dev);
  5415. goto out;
  5416. }
  5417. static struct rtnl_link_stats64 *
  5418. rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
  5419. {
  5420. struct rtl8169_private *tp = netdev_priv(dev);
  5421. void __iomem *ioaddr = tp->mmio_addr;
  5422. unsigned int start;
  5423. if (netif_running(dev))
  5424. rtl8169_rx_missed(dev, ioaddr);
  5425. do {
  5426. start = u64_stats_fetch_begin_bh(&tp->rx_stats.syncp);
  5427. stats->rx_packets = tp->rx_stats.packets;
  5428. stats->rx_bytes = tp->rx_stats.bytes;
  5429. } while (u64_stats_fetch_retry_bh(&tp->rx_stats.syncp, start));
  5430. do {
  5431. start = u64_stats_fetch_begin_bh(&tp->tx_stats.syncp);
  5432. stats->tx_packets = tp->tx_stats.packets;
  5433. stats->tx_bytes = tp->tx_stats.bytes;
  5434. } while (u64_stats_fetch_retry_bh(&tp->tx_stats.syncp, start));
  5435. stats->rx_dropped = dev->stats.rx_dropped;
  5436. stats->tx_dropped = dev->stats.tx_dropped;
  5437. stats->rx_length_errors = dev->stats.rx_length_errors;
  5438. stats->rx_errors = dev->stats.rx_errors;
  5439. stats->rx_crc_errors = dev->stats.rx_crc_errors;
  5440. stats->rx_fifo_errors = dev->stats.rx_fifo_errors;
  5441. stats->rx_missed_errors = dev->stats.rx_missed_errors;
  5442. return stats;
  5443. }
  5444. static void rtl8169_net_suspend(struct net_device *dev)
  5445. {
  5446. struct rtl8169_private *tp = netdev_priv(dev);
  5447. if (!netif_running(dev))
  5448. return;
  5449. netif_device_detach(dev);
  5450. netif_stop_queue(dev);
  5451. rtl_lock_work(tp);
  5452. napi_disable(&tp->napi);
  5453. clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
  5454. rtl_unlock_work(tp);
  5455. rtl_pll_power_down(tp);
  5456. }
  5457. #ifdef CONFIG_PM
  5458. static int rtl8169_suspend(struct device *device)
  5459. {
  5460. struct pci_dev *pdev = to_pci_dev(device);
  5461. struct net_device *dev = pci_get_drvdata(pdev);
  5462. rtl8169_net_suspend(dev);
  5463. return 0;
  5464. }
  5465. static void __rtl8169_resume(struct net_device *dev)
  5466. {
  5467. struct rtl8169_private *tp = netdev_priv(dev);
  5468. netif_device_attach(dev);
  5469. rtl_pll_power_up(tp);
  5470. rtl_lock_work(tp);
  5471. napi_enable(&tp->napi);
  5472. set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
  5473. rtl_unlock_work(tp);
  5474. rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
  5475. }
  5476. static int rtl8169_resume(struct device *device)
  5477. {
  5478. struct pci_dev *pdev = to_pci_dev(device);
  5479. struct net_device *dev = pci_get_drvdata(pdev);
  5480. struct rtl8169_private *tp = netdev_priv(dev);
  5481. rtl8169_init_phy(dev, tp);
  5482. if (netif_running(dev))
  5483. __rtl8169_resume(dev);
  5484. return 0;
  5485. }
  5486. static int rtl8169_runtime_suspend(struct device *device)
  5487. {
  5488. struct pci_dev *pdev = to_pci_dev(device);
  5489. struct net_device *dev = pci_get_drvdata(pdev);
  5490. struct rtl8169_private *tp = netdev_priv(dev);
  5491. if (!tp->TxDescArray)
  5492. return 0;
  5493. rtl_lock_work(tp);
  5494. tp->saved_wolopts = __rtl8169_get_wol(tp);
  5495. __rtl8169_set_wol(tp, WAKE_ANY);
  5496. rtl_unlock_work(tp);
  5497. rtl8169_net_suspend(dev);
  5498. return 0;
  5499. }
  5500. static int rtl8169_runtime_resume(struct device *device)
  5501. {
  5502. struct pci_dev *pdev = to_pci_dev(device);
  5503. struct net_device *dev = pci_get_drvdata(pdev);
  5504. struct rtl8169_private *tp = netdev_priv(dev);
  5505. if (!tp->TxDescArray)
  5506. return 0;
  5507. rtl_lock_work(tp);
  5508. __rtl8169_set_wol(tp, tp->saved_wolopts);
  5509. tp->saved_wolopts = 0;
  5510. rtl_unlock_work(tp);
  5511. rtl8169_init_phy(dev, tp);
  5512. __rtl8169_resume(dev);
  5513. return 0;
  5514. }
  5515. static int rtl8169_runtime_idle(struct device *device)
  5516. {
  5517. struct pci_dev *pdev = to_pci_dev(device);
  5518. struct net_device *dev = pci_get_drvdata(pdev);
  5519. struct rtl8169_private *tp = netdev_priv(dev);
  5520. return tp->TxDescArray ? -EBUSY : 0;
  5521. }
  5522. static const struct dev_pm_ops rtl8169_pm_ops = {
  5523. .suspend = rtl8169_suspend,
  5524. .resume = rtl8169_resume,
  5525. .freeze = rtl8169_suspend,
  5526. .thaw = rtl8169_resume,
  5527. .poweroff = rtl8169_suspend,
  5528. .restore = rtl8169_resume,
  5529. .runtime_suspend = rtl8169_runtime_suspend,
  5530. .runtime_resume = rtl8169_runtime_resume,
  5531. .runtime_idle = rtl8169_runtime_idle,
  5532. };
  5533. #define RTL8169_PM_OPS (&rtl8169_pm_ops)
  5534. #else /* !CONFIG_PM */
  5535. #define RTL8169_PM_OPS NULL
  5536. #endif /* !CONFIG_PM */
  5537. static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
  5538. {
  5539. void __iomem *ioaddr = tp->mmio_addr;
  5540. /* WoL fails with 8168b when the receiver is disabled. */
  5541. switch (tp->mac_version) {
  5542. case RTL_GIGA_MAC_VER_11:
  5543. case RTL_GIGA_MAC_VER_12:
  5544. case RTL_GIGA_MAC_VER_17:
  5545. pci_clear_master(tp->pci_dev);
  5546. RTL_W8(ChipCmd, CmdRxEnb);
  5547. /* PCI commit */
  5548. RTL_R8(ChipCmd);
  5549. break;
  5550. default:
  5551. break;
  5552. }
  5553. }
  5554. static void rtl_shutdown(struct pci_dev *pdev)
  5555. {
  5556. struct net_device *dev = pci_get_drvdata(pdev);
  5557. struct rtl8169_private *tp = netdev_priv(dev);
  5558. struct device *d = &pdev->dev;
  5559. pm_runtime_get_sync(d);
  5560. rtl8169_net_suspend(dev);
  5561. /* Restore original MAC address */
  5562. rtl_rar_set(tp, dev->perm_addr);
  5563. rtl8169_hw_reset(tp);
  5564. if (system_state == SYSTEM_POWER_OFF) {
  5565. if (__rtl8169_get_wol(tp) & WAKE_ANY) {
  5566. rtl_wol_suspend_quirk(tp);
  5567. rtl_wol_shutdown_quirk(tp);
  5568. }
  5569. pci_wake_from_d3(pdev, true);
  5570. pci_set_power_state(pdev, PCI_D3hot);
  5571. }
  5572. pm_runtime_put_noidle(d);
  5573. }
  5574. static void rtl_remove_one(struct pci_dev *pdev)
  5575. {
  5576. struct net_device *dev = pci_get_drvdata(pdev);
  5577. struct rtl8169_private *tp = netdev_priv(dev);
  5578. if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
  5579. tp->mac_version == RTL_GIGA_MAC_VER_28 ||
  5580. tp->mac_version == RTL_GIGA_MAC_VER_31) {
  5581. rtl8168_driver_stop(tp);
  5582. }
  5583. netif_napi_del(&tp->napi);
  5584. unregister_netdev(dev);
  5585. rtl_release_firmware(tp);
  5586. if (pci_dev_run_wake(pdev))
  5587. pm_runtime_get_noresume(&pdev->dev);
  5588. /* restore original MAC address */
  5589. rtl_rar_set(tp, dev->perm_addr);
  5590. rtl_disable_msi(pdev, tp);
  5591. rtl8169_release_board(pdev, dev, tp->mmio_addr);
  5592. pci_set_drvdata(pdev, NULL);
  5593. }
  5594. static const struct net_device_ops rtl_netdev_ops = {
  5595. .ndo_open = rtl_open,
  5596. .ndo_stop = rtl8169_close,
  5597. .ndo_get_stats64 = rtl8169_get_stats64,
  5598. .ndo_start_xmit = rtl8169_start_xmit,
  5599. .ndo_tx_timeout = rtl8169_tx_timeout,
  5600. .ndo_validate_addr = eth_validate_addr,
  5601. .ndo_change_mtu = rtl8169_change_mtu,
  5602. .ndo_fix_features = rtl8169_fix_features,
  5603. .ndo_set_features = rtl8169_set_features,
  5604. .ndo_set_mac_address = rtl_set_mac_address,
  5605. .ndo_do_ioctl = rtl8169_ioctl,
  5606. .ndo_set_rx_mode = rtl_set_rx_mode,
  5607. #ifdef CONFIG_NET_POLL_CONTROLLER
  5608. .ndo_poll_controller = rtl8169_netpoll,
  5609. #endif
  5610. };
  5611. static const struct rtl_cfg_info {
  5612. void (*hw_start)(struct net_device *);
  5613. unsigned int region;
  5614. unsigned int align;
  5615. u16 event_slow;
  5616. unsigned features;
  5617. u8 default_ver;
  5618. } rtl_cfg_infos [] = {
  5619. [RTL_CFG_0] = {
  5620. .hw_start = rtl_hw_start_8169,
  5621. .region = 1,
  5622. .align = 0,
  5623. .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
  5624. .features = RTL_FEATURE_GMII,
  5625. .default_ver = RTL_GIGA_MAC_VER_01,
  5626. },
  5627. [RTL_CFG_1] = {
  5628. .hw_start = rtl_hw_start_8168,
  5629. .region = 2,
  5630. .align = 8,
  5631. .event_slow = SYSErr | LinkChg | RxOverflow,
  5632. .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
  5633. .default_ver = RTL_GIGA_MAC_VER_11,
  5634. },
  5635. [RTL_CFG_2] = {
  5636. .hw_start = rtl_hw_start_8101,
  5637. .region = 2,
  5638. .align = 8,
  5639. .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver |
  5640. PCSTimeout,
  5641. .features = RTL_FEATURE_MSI,
  5642. .default_ver = RTL_GIGA_MAC_VER_13,
  5643. }
  5644. };
  5645. /* Cfg9346_Unlock assumed. */
  5646. static unsigned rtl_try_msi(struct rtl8169_private *tp,
  5647. const struct rtl_cfg_info *cfg)
  5648. {
  5649. void __iomem *ioaddr = tp->mmio_addr;
  5650. unsigned msi = 0;
  5651. u8 cfg2;
  5652. cfg2 = RTL_R8(Config2) & ~MSIEnable;
  5653. if (cfg->features & RTL_FEATURE_MSI) {
  5654. if (pci_enable_msi(tp->pci_dev)) {
  5655. netif_info(tp, hw, tp->dev, "no MSI. Back to INTx.\n");
  5656. } else {
  5657. cfg2 |= MSIEnable;
  5658. msi = RTL_FEATURE_MSI;
  5659. }
  5660. }
  5661. if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
  5662. RTL_W8(Config2, cfg2);
  5663. return msi;
  5664. }
  5665. DECLARE_RTL_COND(rtl_link_list_ready_cond)
  5666. {
  5667. void __iomem *ioaddr = tp->mmio_addr;
  5668. return RTL_R8(MCU) & LINK_LIST_RDY;
  5669. }
  5670. DECLARE_RTL_COND(rtl_rxtx_empty_cond)
  5671. {
  5672. void __iomem *ioaddr = tp->mmio_addr;
  5673. return (RTL_R8(MCU) & RXTX_EMPTY) == RXTX_EMPTY;
  5674. }
  5675. static void rtl_hw_init_8168g(struct rtl8169_private *tp)
  5676. {
  5677. void __iomem *ioaddr = tp->mmio_addr;
  5678. u32 data;
  5679. tp->ocp_base = OCP_STD_PHY_BASE;
  5680. RTL_W32(MISC, RTL_R32(MISC) | RXDV_GATED_EN);
  5681. if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
  5682. return;
  5683. if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
  5684. return;
  5685. RTL_W8(ChipCmd, RTL_R8(ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
  5686. msleep(1);
  5687. RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
  5688. data = r8168_mac_ocp_read(tp, 0xe8de);
  5689. data &= ~(1 << 14);
  5690. r8168_mac_ocp_write(tp, 0xe8de, data);
  5691. if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
  5692. return;
  5693. data = r8168_mac_ocp_read(tp, 0xe8de);
  5694. data |= (1 << 15);
  5695. r8168_mac_ocp_write(tp, 0xe8de, data);
  5696. if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
  5697. return;
  5698. }
  5699. static void rtl_hw_initialize(struct rtl8169_private *tp)
  5700. {
  5701. switch (tp->mac_version) {
  5702. case RTL_GIGA_MAC_VER_40:
  5703. case RTL_GIGA_MAC_VER_41:
  5704. case RTL_GIGA_MAC_VER_42:
  5705. case RTL_GIGA_MAC_VER_43:
  5706. case RTL_GIGA_MAC_VER_44:
  5707. rtl_hw_init_8168g(tp);
  5708. break;
  5709. default:
  5710. break;
  5711. }
  5712. }
  5713. static int
  5714. rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
  5715. {
  5716. const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
  5717. const unsigned int region = cfg->region;
  5718. struct rtl8169_private *tp;
  5719. struct mii_if_info *mii;
  5720. struct net_device *dev;
  5721. void __iomem *ioaddr;
  5722. int chipset, i;
  5723. int rc;
  5724. if (netif_msg_drv(&debug)) {
  5725. printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
  5726. MODULENAME, RTL8169_VERSION);
  5727. }
  5728. dev = alloc_etherdev(sizeof (*tp));
  5729. if (!dev) {
  5730. rc = -ENOMEM;
  5731. goto out;
  5732. }
  5733. SET_NETDEV_DEV(dev, &pdev->dev);
  5734. dev->netdev_ops = &rtl_netdev_ops;
  5735. tp = netdev_priv(dev);
  5736. tp->dev = dev;
  5737. tp->pci_dev = pdev;
  5738. tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
  5739. mii = &tp->mii;
  5740. mii->dev = dev;
  5741. mii->mdio_read = rtl_mdio_read;
  5742. mii->mdio_write = rtl_mdio_write;
  5743. mii->phy_id_mask = 0x1f;
  5744. mii->reg_num_mask = 0x1f;
  5745. mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
  5746. /* disable ASPM completely as that cause random device stop working
  5747. * problems as well as full system hangs for some PCIe devices users */
  5748. pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
  5749. PCIE_LINK_STATE_CLKPM);
  5750. /* enable device (incl. PCI PM wakeup and hotplug setup) */
  5751. rc = pci_enable_device(pdev);
  5752. if (rc < 0) {
  5753. netif_err(tp, probe, dev, "enable failure\n");
  5754. goto err_out_free_dev_1;
  5755. }
  5756. if (pci_set_mwi(pdev) < 0)
  5757. netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
  5758. /* make sure PCI base addr 1 is MMIO */
  5759. if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
  5760. netif_err(tp, probe, dev,
  5761. "region #%d not an MMIO resource, aborting\n",
  5762. region);
  5763. rc = -ENODEV;
  5764. goto err_out_mwi_2;
  5765. }
  5766. /* check for weird/broken PCI region reporting */
  5767. if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
  5768. netif_err(tp, probe, dev,
  5769. "Invalid PCI region size(s), aborting\n");
  5770. rc = -ENODEV;
  5771. goto err_out_mwi_2;
  5772. }
  5773. rc = pci_request_regions(pdev, MODULENAME);
  5774. if (rc < 0) {
  5775. netif_err(tp, probe, dev, "could not request regions\n");
  5776. goto err_out_mwi_2;
  5777. }
  5778. tp->cp_cmd = RxChkSum;
  5779. if ((sizeof(dma_addr_t) > 4) &&
  5780. !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
  5781. tp->cp_cmd |= PCIDAC;
  5782. dev->features |= NETIF_F_HIGHDMA;
  5783. } else {
  5784. rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  5785. if (rc < 0) {
  5786. netif_err(tp, probe, dev, "DMA configuration failed\n");
  5787. goto err_out_free_res_3;
  5788. }
  5789. }
  5790. /* ioremap MMIO region */
  5791. ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
  5792. if (!ioaddr) {
  5793. netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
  5794. rc = -EIO;
  5795. goto err_out_free_res_3;
  5796. }
  5797. tp->mmio_addr = ioaddr;
  5798. if (!pci_is_pcie(pdev))
  5799. netif_info(tp, probe, dev, "not PCI Express\n");
  5800. /* Identify chip attached to board */
  5801. rtl8169_get_mac_version(tp, dev, cfg->default_ver);
  5802. rtl_init_rxcfg(tp);
  5803. rtl_irq_disable(tp);
  5804. rtl_hw_initialize(tp);
  5805. rtl_hw_reset(tp);
  5806. rtl_ack_events(tp, 0xffff);
  5807. pci_set_master(pdev);
  5808. /*
  5809. * Pretend we are using VLANs; This bypasses a nasty bug where
  5810. * Interrupts stop flowing on high load on 8110SCd controllers.
  5811. */
  5812. if (tp->mac_version == RTL_GIGA_MAC_VER_05)
  5813. tp->cp_cmd |= RxVlan;
  5814. rtl_init_mdio_ops(tp);
  5815. rtl_init_pll_power_ops(tp);
  5816. rtl_init_jumbo_ops(tp);
  5817. rtl_init_csi_ops(tp);
  5818. rtl8169_print_mac_version(tp);
  5819. chipset = tp->mac_version;
  5820. tp->txd_version = rtl_chip_infos[chipset].txd_version;
  5821. RTL_W8(Cfg9346, Cfg9346_Unlock);
  5822. RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
  5823. RTL_W8(Config5, RTL_R8(Config5) & (BWF | MWF | UWF | LanWake | PMEStatus));
  5824. if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
  5825. tp->features |= RTL_FEATURE_WOL;
  5826. if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
  5827. tp->features |= RTL_FEATURE_WOL;
  5828. tp->features |= rtl_try_msi(tp, cfg);
  5829. RTL_W8(Cfg9346, Cfg9346_Lock);
  5830. if (rtl_tbi_enabled(tp)) {
  5831. tp->set_speed = rtl8169_set_speed_tbi;
  5832. tp->get_settings = rtl8169_gset_tbi;
  5833. tp->phy_reset_enable = rtl8169_tbi_reset_enable;
  5834. tp->phy_reset_pending = rtl8169_tbi_reset_pending;
  5835. tp->link_ok = rtl8169_tbi_link_ok;
  5836. tp->do_ioctl = rtl_tbi_ioctl;
  5837. } else {
  5838. tp->set_speed = rtl8169_set_speed_xmii;
  5839. tp->get_settings = rtl8169_gset_xmii;
  5840. tp->phy_reset_enable = rtl8169_xmii_reset_enable;
  5841. tp->phy_reset_pending = rtl8169_xmii_reset_pending;
  5842. tp->link_ok = rtl8169_xmii_link_ok;
  5843. tp->do_ioctl = rtl_xmii_ioctl;
  5844. }
  5845. mutex_init(&tp->wk.mutex);
  5846. /* Get MAC address */
  5847. for (i = 0; i < ETH_ALEN; i++)
  5848. dev->dev_addr[i] = RTL_R8(MAC0 + i);
  5849. SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
  5850. dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
  5851. netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
  5852. /* don't enable SG, IP_CSUM and TSO by default - it might not work
  5853. * properly for all devices */
  5854. dev->features |= NETIF_F_RXCSUM |
  5855. NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
  5856. dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
  5857. NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
  5858. NETIF_F_HW_VLAN_CTAG_RX;
  5859. dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
  5860. NETIF_F_HIGHDMA;
  5861. if (tp->mac_version == RTL_GIGA_MAC_VER_05)
  5862. /* 8110SCd requires hardware Rx VLAN - disallow toggling */
  5863. dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
  5864. dev->hw_features |= NETIF_F_RXALL;
  5865. dev->hw_features |= NETIF_F_RXFCS;
  5866. tp->hw_start = cfg->hw_start;
  5867. tp->event_slow = cfg->event_slow;
  5868. tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ?
  5869. ~(RxBOVF | RxFOVF) : ~0;
  5870. init_timer(&tp->timer);
  5871. tp->timer.data = (unsigned long) dev;
  5872. tp->timer.function = rtl8169_phy_timer;
  5873. tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
  5874. rc = register_netdev(dev);
  5875. if (rc < 0)
  5876. goto err_out_msi_4;
  5877. pci_set_drvdata(pdev, dev);
  5878. netif_info(tp, probe, dev, "%s at 0x%p, %pM, XID %08x IRQ %d\n",
  5879. rtl_chip_infos[chipset].name, ioaddr, dev->dev_addr,
  5880. (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), pdev->irq);
  5881. if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
  5882. netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
  5883. "tx checksumming: %s]\n",
  5884. rtl_chip_infos[chipset].jumbo_max,
  5885. rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko");
  5886. }
  5887. if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
  5888. tp->mac_version == RTL_GIGA_MAC_VER_28 ||
  5889. tp->mac_version == RTL_GIGA_MAC_VER_31) {
  5890. rtl8168_driver_start(tp);
  5891. }
  5892. device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
  5893. if (pci_dev_run_wake(pdev))
  5894. pm_runtime_put_noidle(&pdev->dev);
  5895. netif_carrier_off(dev);
  5896. out:
  5897. return rc;
  5898. err_out_msi_4:
  5899. netif_napi_del(&tp->napi);
  5900. rtl_disable_msi(pdev, tp);
  5901. iounmap(ioaddr);
  5902. err_out_free_res_3:
  5903. pci_release_regions(pdev);
  5904. err_out_mwi_2:
  5905. pci_clear_mwi(pdev);
  5906. pci_disable_device(pdev);
  5907. err_out_free_dev_1:
  5908. free_netdev(dev);
  5909. goto out;
  5910. }
  5911. static struct pci_driver rtl8169_pci_driver = {
  5912. .name = MODULENAME,
  5913. .id_table = rtl8169_pci_tbl,
  5914. .probe = rtl_init_one,
  5915. .remove = rtl_remove_one,
  5916. .shutdown = rtl_shutdown,
  5917. .driver.pm = RTL8169_PM_OPS,
  5918. };
  5919. module_pci_driver(rtl8169_pci_driver);