i40e_lan_hmc.h 4.3 KB

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  1. /*******************************************************************************
  2. *
  3. * Intel Ethernet Controller XL710 Family Linux Driver
  4. * Copyright(c) 2013 Intel Corporation.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms and conditions of the GNU General Public License,
  8. * version 2, as published by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope it will be useful, but WITHOUT
  11. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  13. * more details.
  14. *
  15. * You should have received a copy of the GNU General Public License along with
  16. * this program; if not, write to the Free Software Foundation, Inc.,
  17. * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18. *
  19. * The full GNU General Public License is included in this distribution in
  20. * the file called "COPYING".
  21. *
  22. * Contact Information:
  23. * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25. *
  26. ******************************************************************************/
  27. #ifndef _I40E_LAN_HMC_H_
  28. #define _I40E_LAN_HMC_H_
  29. /* forward-declare the HW struct for the compiler */
  30. struct i40e_hw;
  31. /* HMC element context information */
  32. /* Rx queue context data */
  33. struct i40e_hmc_obj_rxq {
  34. u16 head;
  35. u8 cpuid;
  36. u64 base;
  37. u16 qlen;
  38. #define I40E_RXQ_CTX_DBUFF_SHIFT 7
  39. u8 dbuff;
  40. #define I40E_RXQ_CTX_HBUFF_SHIFT 6
  41. u8 hbuff;
  42. u8 dtype;
  43. u8 dsize;
  44. u8 crcstrip;
  45. u8 fc_ena;
  46. u8 l2tsel;
  47. u8 hsplit_0;
  48. u8 hsplit_1;
  49. u8 showiv;
  50. u16 rxmax;
  51. u8 tphrdesc_ena;
  52. u8 tphwdesc_ena;
  53. u8 tphdata_ena;
  54. u8 tphhead_ena;
  55. u8 lrxqthresh;
  56. };
  57. /* Tx queue context data */
  58. struct i40e_hmc_obj_txq {
  59. u16 head;
  60. u8 new_context;
  61. u64 base;
  62. u8 fc_ena;
  63. u8 timesync_ena;
  64. u8 fd_ena;
  65. u8 alt_vlan_ena;
  66. u16 thead_wb;
  67. u16 cpuid;
  68. u8 head_wb_ena;
  69. u16 qlen;
  70. u8 tphrdesc_ena;
  71. u8 tphrpacket_ena;
  72. u8 tphwdesc_ena;
  73. u64 head_wb_addr;
  74. u32 crc;
  75. u16 rdylist;
  76. u8 rdylist_act;
  77. };
  78. /* for hsplit_0 field of Rx HMC context */
  79. enum i40e_hmc_obj_rx_hsplit_0 {
  80. I40E_HMC_OBJ_RX_HSPLIT_0_NO_SPLIT = 0,
  81. I40E_HMC_OBJ_RX_HSPLIT_0_SPLIT_L2 = 1,
  82. I40E_HMC_OBJ_RX_HSPLIT_0_SPLIT_IP = 2,
  83. I40E_HMC_OBJ_RX_HSPLIT_0_SPLIT_TCP_UDP = 4,
  84. I40E_HMC_OBJ_RX_HSPLIT_0_SPLIT_SCTP = 8,
  85. };
  86. /* fcoe_cntx and fcoe_filt are for debugging purpose only */
  87. struct i40e_hmc_obj_fcoe_cntx {
  88. u32 rsv[32];
  89. };
  90. struct i40e_hmc_obj_fcoe_filt {
  91. u32 rsv[8];
  92. };
  93. /* Context sizes for LAN objects */
  94. enum i40e_hmc_lan_object_size {
  95. I40E_HMC_LAN_OBJ_SZ_8 = 0x3,
  96. I40E_HMC_LAN_OBJ_SZ_16 = 0x4,
  97. I40E_HMC_LAN_OBJ_SZ_32 = 0x5,
  98. I40E_HMC_LAN_OBJ_SZ_64 = 0x6,
  99. I40E_HMC_LAN_OBJ_SZ_128 = 0x7,
  100. I40E_HMC_LAN_OBJ_SZ_256 = 0x8,
  101. I40E_HMC_LAN_OBJ_SZ_512 = 0x9,
  102. };
  103. #define I40E_HMC_L2OBJ_BASE_ALIGNMENT 512
  104. #define I40E_HMC_OBJ_SIZE_TXQ 128
  105. #define I40E_HMC_OBJ_SIZE_RXQ 32
  106. #define I40E_HMC_OBJ_SIZE_FCOE_CNTX 128
  107. #define I40E_HMC_OBJ_SIZE_FCOE_FILT 32
  108. enum i40e_hmc_lan_rsrc_type {
  109. I40E_HMC_LAN_FULL = 0,
  110. I40E_HMC_LAN_TX = 1,
  111. I40E_HMC_LAN_RX = 2,
  112. I40E_HMC_FCOE_CTX = 3,
  113. I40E_HMC_FCOE_FILT = 4,
  114. I40E_HMC_LAN_MAX = 5
  115. };
  116. enum i40e_hmc_model {
  117. I40E_HMC_MODEL_DIRECT_PREFERRED = 0,
  118. I40E_HMC_MODEL_DIRECT_ONLY = 1,
  119. I40E_HMC_MODEL_PAGED_ONLY = 2,
  120. I40E_HMC_MODEL_UNKNOWN,
  121. };
  122. struct i40e_hmc_lan_create_obj_info {
  123. struct i40e_hmc_info *hmc_info;
  124. u32 rsrc_type;
  125. u32 start_idx;
  126. u32 count;
  127. enum i40e_sd_entry_type entry_type;
  128. u64 direct_mode_sz;
  129. };
  130. struct i40e_hmc_lan_delete_obj_info {
  131. struct i40e_hmc_info *hmc_info;
  132. u32 rsrc_type;
  133. u32 start_idx;
  134. u32 count;
  135. };
  136. i40e_status i40e_init_lan_hmc(struct i40e_hw *hw, u32 txq_num,
  137. u32 rxq_num, u32 fcoe_cntx_num,
  138. u32 fcoe_filt_num);
  139. i40e_status i40e_configure_lan_hmc(struct i40e_hw *hw,
  140. enum i40e_hmc_model model);
  141. i40e_status i40e_shutdown_lan_hmc(struct i40e_hw *hw);
  142. i40e_status i40e_clear_lan_tx_queue_context(struct i40e_hw *hw,
  143. u16 queue);
  144. i40e_status i40e_set_lan_tx_queue_context(struct i40e_hw *hw,
  145. u16 queue,
  146. struct i40e_hmc_obj_txq *s);
  147. i40e_status i40e_clear_lan_rx_queue_context(struct i40e_hw *hw,
  148. u16 queue);
  149. i40e_status i40e_set_lan_rx_queue_context(struct i40e_hw *hw,
  150. u16 queue,
  151. struct i40e_hmc_obj_rxq *s);
  152. #endif /* _I40E_LAN_HMC_H_ */