i40e_diag.c 4.3 KB

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  1. /*******************************************************************************
  2. *
  3. * Intel Ethernet Controller XL710 Family Linux Driver
  4. * Copyright(c) 2013 Intel Corporation.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms and conditions of the GNU General Public License,
  8. * version 2, as published by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope it will be useful, but WITHOUT
  11. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  13. * more details.
  14. *
  15. * You should have received a copy of the GNU General Public License along with
  16. * this program; if not, write to the Free Software Foundation, Inc.,
  17. * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18. *
  19. * The full GNU General Public License is included in this distribution in
  20. * the file called "COPYING".
  21. *
  22. * Contact Information:
  23. * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25. *
  26. ******************************************************************************/
  27. #include "i40e_diag.h"
  28. #include "i40e_prototype.h"
  29. /**
  30. * i40e_diag_reg_pattern_test
  31. * @hw: pointer to the hw struct
  32. * @reg: reg to be tested
  33. * @mask: bits to be touched
  34. **/
  35. static i40e_status i40e_diag_reg_pattern_test(struct i40e_hw *hw,
  36. u32 reg, u32 mask)
  37. {
  38. const u32 patterns[] = {0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF};
  39. u32 pat, val, orig_val;
  40. int i;
  41. orig_val = rd32(hw, reg);
  42. for (i = 0; i < ARRAY_SIZE(patterns); i++) {
  43. pat = patterns[i];
  44. wr32(hw, reg, (pat & mask));
  45. val = rd32(hw, reg);
  46. if ((val & mask) != (pat & mask)) {
  47. i40e_debug(hw, I40E_DEBUG_DIAG,
  48. "%s: reg pattern test failed - reg 0x%08x pat 0x%08x val 0x%08x\n",
  49. __func__, reg, pat, val);
  50. return I40E_ERR_DIAG_TEST_FAILED;
  51. }
  52. }
  53. wr32(hw, reg, orig_val);
  54. val = rd32(hw, reg);
  55. if (val != orig_val) {
  56. i40e_debug(hw, I40E_DEBUG_DIAG,
  57. "%s: reg restore test failed - reg 0x%08x orig_val 0x%08x val 0x%08x\n",
  58. __func__, reg, orig_val, val);
  59. return I40E_ERR_DIAG_TEST_FAILED;
  60. }
  61. return 0;
  62. }
  63. struct i40e_diag_reg_test_info i40e_reg_list[] = {
  64. /* offset mask elements stride */
  65. {I40E_QTX_CTL(0), 0x0000FFBF, 64, I40E_QTX_CTL(1) - I40E_QTX_CTL(0)},
  66. {I40E_PFINT_ITR0(0), 0x00000FFF, 3, I40E_PFINT_ITR0(1) - I40E_PFINT_ITR0(0)},
  67. {I40E_PFINT_ITRN(0, 0), 0x00000FFF, 64, I40E_PFINT_ITRN(0, 1) - I40E_PFINT_ITRN(0, 0)},
  68. {I40E_PFINT_ITRN(1, 0), 0x00000FFF, 64, I40E_PFINT_ITRN(1, 1) - I40E_PFINT_ITRN(1, 0)},
  69. {I40E_PFINT_ITRN(2, 0), 0x00000FFF, 64, I40E_PFINT_ITRN(2, 1) - I40E_PFINT_ITRN(2, 0)},
  70. {I40E_PFINT_STAT_CTL0, 0x0000000C, 1, 0},
  71. {I40E_PFINT_LNKLST0, 0x00001FFF, 1, 0},
  72. {I40E_PFINT_LNKLSTN(0), 0x000007FF, 511, I40E_PFINT_LNKLSTN(1) - I40E_PFINT_LNKLSTN(0)},
  73. {I40E_QINT_TQCTL(0), 0x000000FF, I40E_QINT_TQCTL_MAX_INDEX + 1, I40E_QINT_TQCTL(1) - I40E_QINT_TQCTL(0)},
  74. {I40E_QINT_RQCTL(0), 0x000000FF, I40E_QINT_RQCTL_MAX_INDEX + 1, I40E_QINT_RQCTL(1) - I40E_QINT_RQCTL(0)},
  75. {I40E_PFINT_ICR0_ENA, 0xF7F20000, 1, 0},
  76. { 0 }
  77. };
  78. /**
  79. * i40e_diag_reg_test
  80. * @hw: pointer to the hw struct
  81. *
  82. * Perform registers diagnostic test
  83. **/
  84. i40e_status i40e_diag_reg_test(struct i40e_hw *hw)
  85. {
  86. i40e_status ret_code = 0;
  87. u32 reg, mask;
  88. u32 i, j;
  89. for (i = 0; (i40e_reg_list[i].offset != 0) && !ret_code; i++) {
  90. mask = i40e_reg_list[i].mask;
  91. for (j = 0; (j < i40e_reg_list[i].elements) && !ret_code; j++) {
  92. reg = i40e_reg_list[i].offset +
  93. (j * i40e_reg_list[i].stride);
  94. ret_code = i40e_diag_reg_pattern_test(hw, reg, mask);
  95. }
  96. }
  97. return ret_code;
  98. }
  99. /**
  100. * i40e_diag_eeprom_test
  101. * @hw: pointer to the hw struct
  102. *
  103. * Perform EEPROM diagnostic test
  104. **/
  105. i40e_status i40e_diag_eeprom_test(struct i40e_hw *hw)
  106. {
  107. i40e_status ret_code;
  108. u16 reg_val;
  109. /* read NVM control word and if NVM valid, validate EEPROM checksum*/
  110. ret_code = i40e_read_nvm_word(hw, I40E_SR_NVM_CONTROL_WORD, &reg_val);
  111. if ((!ret_code) &&
  112. ((reg_val & I40E_SR_CONTROL_WORD_1_MASK) ==
  113. (0x01 << I40E_SR_CONTROL_WORD_1_SHIFT))) {
  114. ret_code = i40e_validate_nvm_checksum(hw, NULL);
  115. } else {
  116. ret_code = I40E_ERR_DIAG_TEST_FAILED;
  117. }
  118. return ret_code;
  119. }