emac.h 6.0 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214
  1. /*
  2. * Copyright (C) 2004-2013 Synopsys, Inc. (www.synopsys.com)
  3. *
  4. * Registers and bits definitions of ARC EMAC
  5. */
  6. #ifndef ARC_EMAC_H
  7. #define ARC_EMAC_H
  8. #include <linux/device.h>
  9. #include <linux/dma-mapping.h>
  10. #include <linux/netdevice.h>
  11. #include <linux/phy.h>
  12. /* STATUS and ENABLE Register bit masks */
  13. #define TXINT_MASK (1<<0) /* Transmit interrupt */
  14. #define RXINT_MASK (1<<1) /* Receive interrupt */
  15. #define ERR_MASK (1<<2) /* Error interrupt */
  16. #define TXCH_MASK (1<<3) /* Transmit chaining error interrupt */
  17. #define MSER_MASK (1<<4) /* Missed packet counter error */
  18. #define RXCR_MASK (1<<8) /* RXCRCERR counter rolled over */
  19. #define RXFR_MASK (1<<9) /* RXFRAMEERR counter rolled over */
  20. #define RXFL_MASK (1<<10) /* RXOFLOWERR counter rolled over */
  21. #define MDIO_MASK (1<<12) /* MDIO complete interrupt */
  22. #define TXPL_MASK (1<<31) /* Force polling of BD by EMAC */
  23. /* CONTROL Register bit masks */
  24. #define EN_MASK (1<<0) /* VMAC enable */
  25. #define TXRN_MASK (1<<3) /* TX enable */
  26. #define RXRN_MASK (1<<4) /* RX enable */
  27. #define DSBC_MASK (1<<8) /* Disable receive broadcast */
  28. #define ENFL_MASK (1<<10) /* Enable Full-duplex */
  29. #define PROM_MASK (1<<11) /* Promiscuous mode */
  30. /* Buffer descriptor INFO bit masks */
  31. #define OWN_MASK (1<<31) /* 0-CPU owns buffer, 1-EMAC owns buffer */
  32. #define FIRST_MASK (1<<16) /* First buffer in chain */
  33. #define LAST_MASK (1<<17) /* Last buffer in chain */
  34. #define LEN_MASK 0x000007FF /* last 11 bits */
  35. #define CRLS (1<<21)
  36. #define DEFR (1<<22)
  37. #define DROP (1<<23)
  38. #define RTRY (1<<24)
  39. #define LTCL (1<<28)
  40. #define UFLO (1<<29)
  41. #define FOR_EMAC OWN_MASK
  42. #define FOR_CPU 0
  43. /* ARC EMAC register set combines entries for MAC and MDIO */
  44. enum {
  45. R_ID = 0,
  46. R_STATUS,
  47. R_ENABLE,
  48. R_CTRL,
  49. R_POLLRATE,
  50. R_RXERR,
  51. R_MISS,
  52. R_TX_RING,
  53. R_RX_RING,
  54. R_ADDRL,
  55. R_ADDRH,
  56. R_LAFL,
  57. R_LAFH,
  58. R_MDIO,
  59. };
  60. #define TX_TIMEOUT (400*HZ/1000) /* Transmission timeout */
  61. #define ARC_EMAC_NAPI_WEIGHT 40 /* Workload for NAPI */
  62. #define EMAC_BUFFER_SIZE 1536 /* EMAC buffer size */
  63. /**
  64. * struct arc_emac_bd - EMAC buffer descriptor (BD).
  65. *
  66. * @info: Contains status information on the buffer itself.
  67. * @data: 32-bit byte addressable pointer to the packet data.
  68. */
  69. struct arc_emac_bd {
  70. __le32 info;
  71. dma_addr_t data;
  72. };
  73. /* Number of Rx/Tx BD's */
  74. #define RX_BD_NUM 128
  75. #define TX_BD_NUM 128
  76. #define RX_RING_SZ (RX_BD_NUM * sizeof(struct arc_emac_bd))
  77. #define TX_RING_SZ (TX_BD_NUM * sizeof(struct arc_emac_bd))
  78. /**
  79. * struct buffer_state - Stores Rx/Tx buffer state.
  80. * @sk_buff: Pointer to socket buffer.
  81. * @addr: Start address of DMA-mapped memory region.
  82. * @len: Length of DMA-mapped memory region.
  83. */
  84. struct buffer_state {
  85. struct sk_buff *skb;
  86. DEFINE_DMA_UNMAP_ADDR(addr);
  87. DEFINE_DMA_UNMAP_LEN(len);
  88. };
  89. /**
  90. * struct arc_emac_priv - Storage of EMAC's private information.
  91. * @dev: Pointer to the current device.
  92. * @ndev: Pointer to the current network device.
  93. * @phy_dev: Pointer to attached PHY device.
  94. * @bus: Pointer to the current MII bus.
  95. * @regs: Base address of EMAC memory-mapped control registers.
  96. * @napi: Structure for NAPI.
  97. * @stats: Network device statistics.
  98. * @rxbd: Pointer to Rx BD ring.
  99. * @txbd: Pointer to Tx BD ring.
  100. * @rxbd_dma: DMA handle for Rx BD ring.
  101. * @txbd_dma: DMA handle for Tx BD ring.
  102. * @rx_buff: Storage for Rx buffers states.
  103. * @tx_buff: Storage for Tx buffers states.
  104. * @txbd_curr: Index of Tx BD to use on the next "ndo_start_xmit".
  105. * @txbd_dirty: Index of Tx BD to free on the next Tx interrupt.
  106. * @last_rx_bd: Index of the last Rx BD we've got from EMAC.
  107. * @link: PHY's last seen link state.
  108. * @duplex: PHY's last set duplex mode.
  109. * @speed: PHY's last set speed.
  110. * @max_speed: Maximum supported by current system network data-rate.
  111. */
  112. struct arc_emac_priv {
  113. /* Devices */
  114. struct device *dev;
  115. struct net_device *ndev;
  116. struct phy_device *phy_dev;
  117. struct mii_bus *bus;
  118. void __iomem *regs;
  119. struct napi_struct napi;
  120. struct net_device_stats stats;
  121. struct arc_emac_bd *rxbd;
  122. struct arc_emac_bd *txbd;
  123. dma_addr_t rxbd_dma;
  124. dma_addr_t txbd_dma;
  125. struct buffer_state rx_buff[RX_BD_NUM];
  126. struct buffer_state tx_buff[TX_BD_NUM];
  127. unsigned int txbd_curr;
  128. unsigned int txbd_dirty;
  129. unsigned int last_rx_bd;
  130. unsigned int link;
  131. unsigned int duplex;
  132. unsigned int speed;
  133. unsigned int max_speed;
  134. };
  135. /**
  136. * arc_reg_set - Sets EMAC register with provided value.
  137. * @priv: Pointer to ARC EMAC private data structure.
  138. * @reg: Register offset from base address.
  139. * @value: Value to set in register.
  140. */
  141. static inline void arc_reg_set(struct arc_emac_priv *priv, int reg, int value)
  142. {
  143. iowrite32(value, priv->regs + reg * sizeof(int));
  144. }
  145. /**
  146. * arc_reg_get - Gets value of specified EMAC register.
  147. * @priv: Pointer to ARC EMAC private data structure.
  148. * @reg: Register offset from base address.
  149. *
  150. * returns: Value of requested register.
  151. */
  152. static inline unsigned int arc_reg_get(struct arc_emac_priv *priv, int reg)
  153. {
  154. return ioread32(priv->regs + reg * sizeof(int));
  155. }
  156. /**
  157. * arc_reg_or - Applies mask to specified EMAC register - ("reg" | "mask").
  158. * @priv: Pointer to ARC EMAC private data structure.
  159. * @reg: Register offset from base address.
  160. * @mask: Mask to apply to specified register.
  161. *
  162. * This function reads initial register value, then applies provided mask
  163. * to it and then writes register back.
  164. */
  165. static inline void arc_reg_or(struct arc_emac_priv *priv, int reg, int mask)
  166. {
  167. unsigned int value = arc_reg_get(priv, reg);
  168. arc_reg_set(priv, reg, value | mask);
  169. }
  170. /**
  171. * arc_reg_clr - Applies mask to specified EMAC register - ("reg" & ~"mask").
  172. * @priv: Pointer to ARC EMAC private data structure.
  173. * @reg: Register offset from base address.
  174. * @mask: Mask to apply to specified register.
  175. *
  176. * This function reads initial register value, then applies provided mask
  177. * to it and then writes register back.
  178. */
  179. static inline void arc_reg_clr(struct arc_emac_priv *priv, int reg, int mask)
  180. {
  181. unsigned int value = arc_reg_get(priv, reg);
  182. arc_reg_set(priv, reg, value & ~mask);
  183. }
  184. int arc_mdio_probe(struct platform_device *pdev, struct arc_emac_priv *priv);
  185. int arc_mdio_remove(struct arc_emac_priv *priv);
  186. #endif /* ARC_EMAC_H */