cs4231_lib.c 59 KB

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  1. /*
  2. * Copyright (c) by Jaroslav Kysela <perex@suse.cz>
  3. * Routines for control of CS4231(A)/CS4232/InterWave & compatible chips
  4. *
  5. * Bugs:
  6. * - sometimes record brokes playback with WSS portion of
  7. * Yamaha OPL3-SA3 chip
  8. * - CS4231 (GUS MAX) - still trouble with occasional noises
  9. * - broken initialization?
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of the GNU General Public License as published by
  13. * the Free Software Foundation; either version 2 of the License, or
  14. * (at your option) any later version.
  15. *
  16. * This program is distributed in the hope that it will be useful,
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19. * GNU General Public License for more details.
  20. *
  21. * You should have received a copy of the GNU General Public License
  22. * along with this program; if not, write to the Free Software
  23. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  24. *
  25. */
  26. #include <sound/driver.h>
  27. #include <linux/delay.h>
  28. #include <linux/pm.h>
  29. #include <linux/init.h>
  30. #include <linux/interrupt.h>
  31. #include <linux/slab.h>
  32. #include <linux/ioport.h>
  33. #include <sound/core.h>
  34. #include <sound/cs4231.h>
  35. #include <sound/pcm_params.h>
  36. #include <asm/io.h>
  37. #include <asm/dma.h>
  38. #include <asm/irq.h>
  39. MODULE_AUTHOR("Jaroslav Kysela <perex@suse.cz>");
  40. MODULE_DESCRIPTION("Routines for control of CS4231(A)/CS4232/InterWave & compatible chips");
  41. MODULE_LICENSE("GPL");
  42. #if 0
  43. #define SNDRV_DEBUG_MCE
  44. #endif
  45. /*
  46. * Some variables
  47. */
  48. static unsigned char freq_bits[14] = {
  49. /* 5510 */ 0x00 | CS4231_XTAL2,
  50. /* 6620 */ 0x0E | CS4231_XTAL2,
  51. /* 8000 */ 0x00 | CS4231_XTAL1,
  52. /* 9600 */ 0x0E | CS4231_XTAL1,
  53. /* 11025 */ 0x02 | CS4231_XTAL2,
  54. /* 16000 */ 0x02 | CS4231_XTAL1,
  55. /* 18900 */ 0x04 | CS4231_XTAL2,
  56. /* 22050 */ 0x06 | CS4231_XTAL2,
  57. /* 27042 */ 0x04 | CS4231_XTAL1,
  58. /* 32000 */ 0x06 | CS4231_XTAL1,
  59. /* 33075 */ 0x0C | CS4231_XTAL2,
  60. /* 37800 */ 0x08 | CS4231_XTAL2,
  61. /* 44100 */ 0x0A | CS4231_XTAL2,
  62. /* 48000 */ 0x0C | CS4231_XTAL1
  63. };
  64. static unsigned int rates[14] = {
  65. 5510, 6620, 8000, 9600, 11025, 16000, 18900, 22050,
  66. 27042, 32000, 33075, 37800, 44100, 48000
  67. };
  68. static snd_pcm_hw_constraint_list_t hw_constraints_rates = {
  69. .count = 14,
  70. .list = rates,
  71. .mask = 0,
  72. };
  73. static int snd_cs4231_xrate(snd_pcm_runtime_t *runtime)
  74. {
  75. return snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
  76. }
  77. static unsigned char snd_cs4231_original_image[32] =
  78. {
  79. 0x00, /* 00/00 - lic */
  80. 0x00, /* 01/01 - ric */
  81. 0x9f, /* 02/02 - la1ic */
  82. 0x9f, /* 03/03 - ra1ic */
  83. 0x9f, /* 04/04 - la2ic */
  84. 0x9f, /* 05/05 - ra2ic */
  85. 0xbf, /* 06/06 - loc */
  86. 0xbf, /* 07/07 - roc */
  87. 0x20, /* 08/08 - pdfr */
  88. CS4231_AUTOCALIB, /* 09/09 - ic */
  89. 0x00, /* 0a/10 - pc */
  90. 0x00, /* 0b/11 - ti */
  91. CS4231_MODE2, /* 0c/12 - mi */
  92. 0xfc, /* 0d/13 - lbc */
  93. 0x00, /* 0e/14 - pbru */
  94. 0x00, /* 0f/15 - pbrl */
  95. 0x80, /* 10/16 - afei */
  96. 0x01, /* 11/17 - afeii */
  97. 0x9f, /* 12/18 - llic */
  98. 0x9f, /* 13/19 - rlic */
  99. 0x00, /* 14/20 - tlb */
  100. 0x00, /* 15/21 - thb */
  101. 0x00, /* 16/22 - la3mic/reserved */
  102. 0x00, /* 17/23 - ra3mic/reserved */
  103. 0x00, /* 18/24 - afs */
  104. 0x00, /* 19/25 - lamoc/version */
  105. 0xcf, /* 1a/26 - mioc */
  106. 0x00, /* 1b/27 - ramoc/reserved */
  107. 0x20, /* 1c/28 - cdfr */
  108. 0x00, /* 1d/29 - res4 */
  109. 0x00, /* 1e/30 - cbru */
  110. 0x00, /* 1f/31 - cbrl */
  111. };
  112. /*
  113. * Basic I/O functions
  114. */
  115. #if !defined(EBUS_SUPPORT) && !defined(SBUS_SUPPORT)
  116. #define __CS4231_INLINE__ inline
  117. #else
  118. #define __CS4231_INLINE__ /* nothing */
  119. #endif
  120. static __CS4231_INLINE__ void cs4231_outb(cs4231_t *chip, u8 offset, u8 val)
  121. {
  122. #ifdef EBUS_SUPPORT
  123. if (chip->ebus->flag) {
  124. writeb(val, chip->port + (offset << 2));
  125. } else {
  126. #endif
  127. #ifdef SBUS_SUPPORT
  128. sbus_writeb(val, chip->port + (offset << 2));
  129. #endif
  130. #ifdef EBUS_SUPPORT
  131. }
  132. #endif
  133. #ifdef LEGACY_SUPPORT
  134. outb(val, chip->port + offset);
  135. #endif
  136. }
  137. static __CS4231_INLINE__ u8 cs4231_inb(cs4231_t *chip, u8 offset)
  138. {
  139. #ifdef EBUS_SUPPORT
  140. if (chip->ebus_flag) {
  141. return readb(chip->port + (offset << 2));
  142. } else {
  143. #endif
  144. #ifdef SBUS_SUPPORT
  145. return sbus_readb(chip->port + (offset << 2));
  146. #endif
  147. #ifdef EBUS_SUPPORT
  148. }
  149. #endif
  150. #ifdef LEGACY_SUPPORT
  151. return inb(chip->port + offset);
  152. #endif
  153. }
  154. static void snd_cs4231_outm(cs4231_t *chip, unsigned char reg,
  155. unsigned char mask, unsigned char value)
  156. {
  157. int timeout;
  158. unsigned char tmp;
  159. for (timeout = 250;
  160. timeout > 0 && (cs4231_inb(chip, CS4231P(REGSEL)) & CS4231_INIT);
  161. timeout--)
  162. udelay(100);
  163. #ifdef CONFIG_SND_DEBUG
  164. if (cs4231_inb(chip, CS4231P(REGSEL)) & CS4231_INIT)
  165. snd_printk("outm: auto calibration time out - reg = 0x%x, value = 0x%x\n", reg, value);
  166. #endif
  167. if (chip->calibrate_mute) {
  168. chip->image[reg] &= mask;
  169. chip->image[reg] |= value;
  170. } else {
  171. cs4231_outb(chip, CS4231P(REGSEL), chip->mce_bit | reg);
  172. mb();
  173. tmp = (chip->image[reg] & mask) | value;
  174. cs4231_outb(chip, CS4231P(REG), tmp);
  175. chip->image[reg] = tmp;
  176. mb();
  177. }
  178. }
  179. static void snd_cs4231_dout(cs4231_t *chip, unsigned char reg, unsigned char value)
  180. {
  181. int timeout;
  182. for (timeout = 250;
  183. timeout > 0 && (cs4231_inb(chip, CS4231P(REGSEL)) & CS4231_INIT);
  184. timeout--)
  185. udelay(10);
  186. cs4231_outb(chip, CS4231P(REGSEL), chip->mce_bit | reg);
  187. cs4231_outb(chip, CS4231P(REG), value);
  188. mb();
  189. }
  190. void snd_cs4231_out(cs4231_t *chip, unsigned char reg, unsigned char value)
  191. {
  192. int timeout;
  193. for (timeout = 250;
  194. timeout > 0 && (cs4231_inb(chip, CS4231P(REGSEL)) & CS4231_INIT);
  195. timeout--)
  196. udelay(100);
  197. #ifdef CONFIG_SND_DEBUG
  198. if (cs4231_inb(chip, CS4231P(REGSEL)) & CS4231_INIT)
  199. snd_printk("out: auto calibration time out - reg = 0x%x, value = 0x%x\n", reg, value);
  200. #endif
  201. cs4231_outb(chip, CS4231P(REGSEL), chip->mce_bit | reg);
  202. cs4231_outb(chip, CS4231P(REG), value);
  203. chip->image[reg] = value;
  204. mb();
  205. #if 0
  206. printk("codec out - reg 0x%x = 0x%x\n", chip->mce_bit | reg, value);
  207. #endif
  208. }
  209. unsigned char snd_cs4231_in(cs4231_t *chip, unsigned char reg)
  210. {
  211. int timeout;
  212. for (timeout = 250;
  213. timeout > 0 && (cs4231_inb(chip, CS4231P(REGSEL)) & CS4231_INIT);
  214. timeout--)
  215. udelay(100);
  216. #ifdef CONFIG_SND_DEBUG
  217. if (cs4231_inb(chip, CS4231P(REGSEL)) & CS4231_INIT)
  218. snd_printk("in: auto calibration time out - reg = 0x%x\n", reg);
  219. #endif
  220. cs4231_outb(chip, CS4231P(REGSEL), chip->mce_bit | reg);
  221. mb();
  222. return cs4231_inb(chip, CS4231P(REG));
  223. }
  224. void snd_cs4236_ext_out(cs4231_t *chip, unsigned char reg, unsigned char val)
  225. {
  226. cs4231_outb(chip, CS4231P(REGSEL), chip->mce_bit | 0x17);
  227. cs4231_outb(chip, CS4231P(REG), reg | (chip->image[CS4236_EXT_REG] & 0x01));
  228. cs4231_outb(chip, CS4231P(REG), val);
  229. chip->eimage[CS4236_REG(reg)] = val;
  230. #if 0
  231. printk("ext out : reg = 0x%x, val = 0x%x\n", reg, val);
  232. #endif
  233. }
  234. unsigned char snd_cs4236_ext_in(cs4231_t *chip, unsigned char reg)
  235. {
  236. cs4231_outb(chip, CS4231P(REGSEL), chip->mce_bit | 0x17);
  237. cs4231_outb(chip, CS4231P(REG), reg | (chip->image[CS4236_EXT_REG] & 0x01));
  238. #if 1
  239. return cs4231_inb(chip, CS4231P(REG));
  240. #else
  241. {
  242. unsigned char res;
  243. res = cs4231_inb(chip, CS4231P(REG));
  244. printk("ext in : reg = 0x%x, val = 0x%x\n", reg, res);
  245. return res;
  246. }
  247. #endif
  248. }
  249. #if 0
  250. static void snd_cs4231_debug(cs4231_t *chip)
  251. {
  252. printk("CS4231 REGS: INDEX = 0x%02x ", cs4231_inb(chip, CS4231P(REGSEL)));
  253. printk(" STATUS = 0x%02x\n", cs4231_inb(chip, CS4231P(STATUS)));
  254. printk(" 0x00: left input = 0x%02x ", snd_cs4231_in(chip, 0x00));
  255. printk(" 0x10: alt 1 (CFIG 2) = 0x%02x\n", snd_cs4231_in(chip, 0x10));
  256. printk(" 0x01: right input = 0x%02x ", snd_cs4231_in(chip, 0x01));
  257. printk(" 0x11: alt 2 (CFIG 3) = 0x%02x\n", snd_cs4231_in(chip, 0x11));
  258. printk(" 0x02: GF1 left input = 0x%02x ", snd_cs4231_in(chip, 0x02));
  259. printk(" 0x12: left line in = 0x%02x\n", snd_cs4231_in(chip, 0x12));
  260. printk(" 0x03: GF1 right input = 0x%02x ", snd_cs4231_in(chip, 0x03));
  261. printk(" 0x13: right line in = 0x%02x\n", snd_cs4231_in(chip, 0x13));
  262. printk(" 0x04: CD left input = 0x%02x ", snd_cs4231_in(chip, 0x04));
  263. printk(" 0x14: timer low = 0x%02x\n", snd_cs4231_in(chip, 0x14));
  264. printk(" 0x05: CD right input = 0x%02x ", snd_cs4231_in(chip, 0x05));
  265. printk(" 0x15: timer high = 0x%02x\n", snd_cs4231_in(chip, 0x15));
  266. printk(" 0x06: left output = 0x%02x ", snd_cs4231_in(chip, 0x06));
  267. printk(" 0x16: left MIC (PnP) = 0x%02x\n", snd_cs4231_in(chip, 0x16));
  268. printk(" 0x07: right output = 0x%02x ", snd_cs4231_in(chip, 0x07));
  269. printk(" 0x17: right MIC (PnP) = 0x%02x\n", snd_cs4231_in(chip, 0x17));
  270. printk(" 0x08: playback format = 0x%02x ", snd_cs4231_in(chip, 0x08));
  271. printk(" 0x18: IRQ status = 0x%02x\n", snd_cs4231_in(chip, 0x18));
  272. printk(" 0x09: iface (CFIG 1) = 0x%02x ", snd_cs4231_in(chip, 0x09));
  273. printk(" 0x19: left line out = 0x%02x\n", snd_cs4231_in(chip, 0x19));
  274. printk(" 0x0a: pin control = 0x%02x ", snd_cs4231_in(chip, 0x0a));
  275. printk(" 0x1a: mono control = 0x%02x\n", snd_cs4231_in(chip, 0x1a));
  276. printk(" 0x0b: init & status = 0x%02x ", snd_cs4231_in(chip, 0x0b));
  277. printk(" 0x1b: right line out = 0x%02x\n", snd_cs4231_in(chip, 0x1b));
  278. printk(" 0x0c: revision & mode = 0x%02x ", snd_cs4231_in(chip, 0x0c));
  279. printk(" 0x1c: record format = 0x%02x\n", snd_cs4231_in(chip, 0x1c));
  280. printk(" 0x0d: loopback = 0x%02x ", snd_cs4231_in(chip, 0x0d));
  281. printk(" 0x1d: var freq (PnP) = 0x%02x\n", snd_cs4231_in(chip, 0x1d));
  282. printk(" 0x0e: ply upr count = 0x%02x ", snd_cs4231_in(chip, 0x0e));
  283. printk(" 0x1e: ply lwr count = 0x%02x\n", snd_cs4231_in(chip, 0x1e));
  284. printk(" 0x0f: rec upr count = 0x%02x ", snd_cs4231_in(chip, 0x0f));
  285. printk(" 0x1f: rec lwr count = 0x%02x\n", snd_cs4231_in(chip, 0x1f));
  286. }
  287. #endif
  288. /*
  289. * CS4231 detection / MCE routines
  290. */
  291. static void snd_cs4231_busy_wait(cs4231_t *chip)
  292. {
  293. int timeout;
  294. /* huh.. looks like this sequence is proper for CS4231A chip (GUS MAX) */
  295. for (timeout = 5; timeout > 0; timeout--)
  296. cs4231_inb(chip, CS4231P(REGSEL));
  297. /* end of cleanup sequence */
  298. for (timeout = 250;
  299. timeout > 0 && (cs4231_inb(chip, CS4231P(REGSEL)) & CS4231_INIT);
  300. timeout--)
  301. udelay(10);
  302. }
  303. void snd_cs4231_mce_up(cs4231_t *chip)
  304. {
  305. unsigned long flags;
  306. int timeout;
  307. for (timeout = 250; timeout > 0 && (cs4231_inb(chip, CS4231P(REGSEL)) & CS4231_INIT); timeout--)
  308. udelay(100);
  309. #ifdef CONFIG_SND_DEBUG
  310. if (cs4231_inb(chip, CS4231P(REGSEL)) & CS4231_INIT)
  311. snd_printk("mce_up - auto calibration time out (0)\n");
  312. #endif
  313. spin_lock_irqsave(&chip->reg_lock, flags);
  314. chip->mce_bit |= CS4231_MCE;
  315. timeout = cs4231_inb(chip, CS4231P(REGSEL));
  316. if (timeout == 0x80)
  317. snd_printk("mce_up [0x%lx]: serious init problem - codec still busy\n", chip->port);
  318. if (!(timeout & CS4231_MCE))
  319. cs4231_outb(chip, CS4231P(REGSEL), chip->mce_bit | (timeout & 0x1f));
  320. spin_unlock_irqrestore(&chip->reg_lock, flags);
  321. }
  322. void snd_cs4231_mce_down(cs4231_t *chip)
  323. {
  324. unsigned long flags;
  325. int timeout;
  326. snd_cs4231_busy_wait(chip);
  327. #if 0
  328. printk("(1) timeout = %i\n", timeout);
  329. #endif
  330. #ifdef CONFIG_SND_DEBUG
  331. if (cs4231_inb(chip, CS4231P(REGSEL)) & CS4231_INIT)
  332. snd_printk("mce_down [0x%lx] - auto calibration time out (0)\n", (long)CS4231P(REGSEL));
  333. #endif
  334. spin_lock_irqsave(&chip->reg_lock, flags);
  335. chip->mce_bit &= ~CS4231_MCE;
  336. timeout = cs4231_inb(chip, CS4231P(REGSEL));
  337. cs4231_outb(chip, CS4231P(REGSEL), chip->mce_bit | (timeout & 0x1f));
  338. spin_unlock_irqrestore(&chip->reg_lock, flags);
  339. if (timeout == 0x80)
  340. snd_printk("mce_down [0x%lx]: serious init problem - codec still busy\n", chip->port);
  341. if ((timeout & CS4231_MCE) == 0 ||
  342. !(chip->hardware & (CS4231_HW_CS4231_MASK | CS4231_HW_CS4232_MASK))) {
  343. return;
  344. }
  345. snd_cs4231_busy_wait(chip);
  346. /* calibration process */
  347. for (timeout = 500; timeout > 0 && (snd_cs4231_in(chip, CS4231_TEST_INIT) & CS4231_CALIB_IN_PROGRESS) == 0; timeout--)
  348. udelay(10);
  349. if ((snd_cs4231_in(chip, CS4231_TEST_INIT) & CS4231_CALIB_IN_PROGRESS) == 0) {
  350. snd_printd("cs4231_mce_down - auto calibration time out (1)\n");
  351. return;
  352. }
  353. #if 0
  354. printk("(2) timeout = %i, jiffies = %li\n", timeout, jiffies);
  355. #endif
  356. /* in 10 ms increments, check condition, up to 250 ms */
  357. timeout = 25;
  358. while (snd_cs4231_in(chip, CS4231_TEST_INIT) & CS4231_CALIB_IN_PROGRESS) {
  359. if (--timeout < 0) {
  360. snd_printk("mce_down - auto calibration time out (2)\n");
  361. return;
  362. }
  363. msleep(10);
  364. }
  365. #if 0
  366. printk("(3) jiffies = %li\n", jiffies);
  367. #endif
  368. /* in 10 ms increments, check condition, up to 100 ms */
  369. timeout = 10;
  370. while (cs4231_inb(chip, CS4231P(REGSEL)) & CS4231_INIT) {
  371. if (--timeout < 0) {
  372. snd_printk(KERN_ERR "mce_down - auto calibration time out (3)\n");
  373. return;
  374. }
  375. msleep(10);
  376. }
  377. #if 0
  378. printk("(4) jiffies = %li\n", jiffies);
  379. snd_printk("mce_down - exit = 0x%x\n", cs4231_inb(chip, CS4231P(REGSEL)));
  380. #endif
  381. }
  382. static unsigned int snd_cs4231_get_count(unsigned char format, unsigned int size)
  383. {
  384. switch (format & 0xe0) {
  385. case CS4231_LINEAR_16:
  386. case CS4231_LINEAR_16_BIG:
  387. size >>= 1;
  388. break;
  389. case CS4231_ADPCM_16:
  390. return size >> 2;
  391. }
  392. if (format & CS4231_STEREO)
  393. size >>= 1;
  394. return size;
  395. }
  396. static int snd_cs4231_trigger(snd_pcm_substream_t *substream,
  397. int cmd)
  398. {
  399. cs4231_t *chip = snd_pcm_substream_chip(substream);
  400. int result = 0;
  401. unsigned int what;
  402. struct list_head *pos;
  403. snd_pcm_substream_t *s;
  404. int do_start;
  405. #if 0
  406. printk("codec trigger!!! - what = %i, enable = %i, status = 0x%x\n", what, enable, cs4231_inb(chip, CS4231P(STATUS)));
  407. #endif
  408. switch (cmd) {
  409. case SNDRV_PCM_TRIGGER_START:
  410. case SNDRV_PCM_TRIGGER_RESUME:
  411. do_start = 1; break;
  412. case SNDRV_PCM_TRIGGER_STOP:
  413. case SNDRV_PCM_TRIGGER_SUSPEND:
  414. do_start = 0; break;
  415. default:
  416. return -EINVAL;
  417. }
  418. what = 0;
  419. snd_pcm_group_for_each(pos, substream) {
  420. s = snd_pcm_group_substream_entry(pos);
  421. if (s == chip->playback_substream) {
  422. what |= CS4231_PLAYBACK_ENABLE;
  423. snd_pcm_trigger_done(s, substream);
  424. } else if (s == chip->capture_substream) {
  425. what |= CS4231_RECORD_ENABLE;
  426. snd_pcm_trigger_done(s, substream);
  427. }
  428. }
  429. spin_lock(&chip->reg_lock);
  430. if (do_start) {
  431. chip->image[CS4231_IFACE_CTRL] |= what;
  432. if (chip->trigger)
  433. chip->trigger(chip, what, 1);
  434. } else {
  435. chip->image[CS4231_IFACE_CTRL] &= ~what;
  436. if (chip->trigger)
  437. chip->trigger(chip, what, 0);
  438. }
  439. snd_cs4231_out(chip, CS4231_IFACE_CTRL, chip->image[CS4231_IFACE_CTRL]);
  440. spin_unlock(&chip->reg_lock);
  441. #if 0
  442. snd_cs4231_debug(chip);
  443. #endif
  444. return result;
  445. }
  446. /*
  447. * CODEC I/O
  448. */
  449. static unsigned char snd_cs4231_get_rate(unsigned int rate)
  450. {
  451. int i;
  452. for (i = 0; i < 14; i++)
  453. if (rate == rates[i])
  454. return freq_bits[i];
  455. // snd_BUG();
  456. return freq_bits[13];
  457. }
  458. static unsigned char snd_cs4231_get_format(cs4231_t *chip,
  459. int format,
  460. int channels)
  461. {
  462. unsigned char rformat;
  463. rformat = CS4231_LINEAR_8;
  464. switch (format) {
  465. case SNDRV_PCM_FORMAT_MU_LAW: rformat = CS4231_ULAW_8; break;
  466. case SNDRV_PCM_FORMAT_A_LAW: rformat = CS4231_ALAW_8; break;
  467. case SNDRV_PCM_FORMAT_S16_LE: rformat = CS4231_LINEAR_16; break;
  468. case SNDRV_PCM_FORMAT_S16_BE: rformat = CS4231_LINEAR_16_BIG; break;
  469. case SNDRV_PCM_FORMAT_IMA_ADPCM: rformat = CS4231_ADPCM_16; break;
  470. }
  471. if (channels > 1)
  472. rformat |= CS4231_STEREO;
  473. #if 0
  474. snd_printk("get_format: 0x%x (mode=0x%x)\n", format, mode);
  475. #endif
  476. return rformat;
  477. }
  478. static void snd_cs4231_calibrate_mute(cs4231_t *chip, int mute)
  479. {
  480. unsigned long flags;
  481. mute = mute ? 1 : 0;
  482. spin_lock_irqsave(&chip->reg_lock, flags);
  483. if (chip->calibrate_mute == mute) {
  484. spin_unlock_irqrestore(&chip->reg_lock, flags);
  485. return;
  486. }
  487. if (!mute) {
  488. snd_cs4231_dout(chip, CS4231_LEFT_INPUT, chip->image[CS4231_LEFT_INPUT]);
  489. snd_cs4231_dout(chip, CS4231_RIGHT_INPUT, chip->image[CS4231_RIGHT_INPUT]);
  490. snd_cs4231_dout(chip, CS4231_LOOPBACK, chip->image[CS4231_LOOPBACK]);
  491. }
  492. snd_cs4231_dout(chip, CS4231_AUX1_LEFT_INPUT, mute ? 0x80 : chip->image[CS4231_AUX1_LEFT_INPUT]);
  493. snd_cs4231_dout(chip, CS4231_AUX1_RIGHT_INPUT, mute ? 0x80 : chip->image[CS4231_AUX1_RIGHT_INPUT]);
  494. snd_cs4231_dout(chip, CS4231_AUX2_LEFT_INPUT, mute ? 0x80 : chip->image[CS4231_AUX2_LEFT_INPUT]);
  495. snd_cs4231_dout(chip, CS4231_AUX2_RIGHT_INPUT, mute ? 0x80 : chip->image[CS4231_AUX2_RIGHT_INPUT]);
  496. snd_cs4231_dout(chip, CS4231_LEFT_OUTPUT, mute ? 0x80 : chip->image[CS4231_LEFT_OUTPUT]);
  497. snd_cs4231_dout(chip, CS4231_RIGHT_OUTPUT, mute ? 0x80 : chip->image[CS4231_RIGHT_OUTPUT]);
  498. snd_cs4231_dout(chip, CS4231_LEFT_LINE_IN, mute ? 0x80 : chip->image[CS4231_LEFT_LINE_IN]);
  499. snd_cs4231_dout(chip, CS4231_RIGHT_LINE_IN, mute ? 0x80 : chip->image[CS4231_RIGHT_LINE_IN]);
  500. snd_cs4231_dout(chip, CS4231_MONO_CTRL, mute ? 0xc0 : chip->image[CS4231_MONO_CTRL]);
  501. if (chip->hardware == CS4231_HW_INTERWAVE) {
  502. snd_cs4231_dout(chip, CS4231_LEFT_MIC_INPUT, mute ? 0x80 : chip->image[CS4231_LEFT_MIC_INPUT]);
  503. snd_cs4231_dout(chip, CS4231_RIGHT_MIC_INPUT, mute ? 0x80 : chip->image[CS4231_RIGHT_MIC_INPUT]);
  504. snd_cs4231_dout(chip, CS4231_LINE_LEFT_OUTPUT, mute ? 0x80 : chip->image[CS4231_LINE_LEFT_OUTPUT]);
  505. snd_cs4231_dout(chip, CS4231_LINE_RIGHT_OUTPUT, mute ? 0x80 : chip->image[CS4231_LINE_RIGHT_OUTPUT]);
  506. }
  507. chip->calibrate_mute = mute;
  508. spin_unlock_irqrestore(&chip->reg_lock, flags);
  509. }
  510. static void snd_cs4231_playback_format(cs4231_t *chip,
  511. snd_pcm_hw_params_t *params,
  512. unsigned char pdfr)
  513. {
  514. unsigned long flags;
  515. int full_calib = 1;
  516. down(&chip->mce_mutex);
  517. snd_cs4231_calibrate_mute(chip, 1);
  518. if (chip->hardware == CS4231_HW_CS4231A ||
  519. (chip->hardware & CS4231_HW_CS4232_MASK)) {
  520. spin_lock_irqsave(&chip->reg_lock, flags);
  521. if ((chip->image[CS4231_PLAYBK_FORMAT] & 0x0f) == (pdfr & 0x0f)) { /* rate is same? */
  522. snd_cs4231_out(chip, CS4231_ALT_FEATURE_1, chip->image[CS4231_ALT_FEATURE_1] | 0x10);
  523. snd_cs4231_out(chip, CS4231_PLAYBK_FORMAT, chip->image[CS4231_PLAYBK_FORMAT] = pdfr);
  524. snd_cs4231_out(chip, CS4231_ALT_FEATURE_1, chip->image[CS4231_ALT_FEATURE_1] &= ~0x10);
  525. udelay(100); /* Fixes audible clicks at least on GUS MAX */
  526. full_calib = 0;
  527. }
  528. spin_unlock_irqrestore(&chip->reg_lock, flags);
  529. }
  530. if (full_calib) {
  531. snd_cs4231_mce_up(chip);
  532. spin_lock_irqsave(&chip->reg_lock, flags);
  533. if (chip->hardware != CS4231_HW_INTERWAVE && !chip->single_dma) {
  534. snd_cs4231_out(chip, CS4231_PLAYBK_FORMAT,
  535. (chip->image[CS4231_IFACE_CTRL] & CS4231_RECORD_ENABLE) ?
  536. (pdfr & 0xf0) | (chip->image[CS4231_REC_FORMAT] & 0x0f) :
  537. pdfr);
  538. } else {
  539. snd_cs4231_out(chip, CS4231_PLAYBK_FORMAT, chip->image[CS4231_PLAYBK_FORMAT] = pdfr);
  540. }
  541. spin_unlock_irqrestore(&chip->reg_lock, flags);
  542. snd_cs4231_mce_down(chip);
  543. }
  544. snd_cs4231_calibrate_mute(chip, 0);
  545. up(&chip->mce_mutex);
  546. }
  547. static void snd_cs4231_capture_format(cs4231_t *chip,
  548. snd_pcm_hw_params_t *params,
  549. unsigned char cdfr)
  550. {
  551. unsigned long flags;
  552. int full_calib = 1;
  553. down(&chip->mce_mutex);
  554. snd_cs4231_calibrate_mute(chip, 1);
  555. if (chip->hardware == CS4231_HW_CS4231A ||
  556. (chip->hardware & CS4231_HW_CS4232_MASK)) {
  557. spin_lock_irqsave(&chip->reg_lock, flags);
  558. if ((chip->image[CS4231_PLAYBK_FORMAT] & 0x0f) == (cdfr & 0x0f) || /* rate is same? */
  559. (chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE)) {
  560. snd_cs4231_out(chip, CS4231_ALT_FEATURE_1, chip->image[CS4231_ALT_FEATURE_1] | 0x20);
  561. snd_cs4231_out(chip, CS4231_REC_FORMAT, chip->image[CS4231_REC_FORMAT] = cdfr);
  562. snd_cs4231_out(chip, CS4231_ALT_FEATURE_1, chip->image[CS4231_ALT_FEATURE_1] &= ~0x20);
  563. full_calib = 0;
  564. }
  565. spin_unlock_irqrestore(&chip->reg_lock, flags);
  566. }
  567. if (full_calib) {
  568. snd_cs4231_mce_up(chip);
  569. spin_lock_irqsave(&chip->reg_lock, flags);
  570. if (chip->hardware != CS4231_HW_INTERWAVE) {
  571. if (!(chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE)) {
  572. snd_cs4231_out(chip, CS4231_PLAYBK_FORMAT,
  573. ((chip->single_dma ? cdfr : chip->image[CS4231_PLAYBK_FORMAT]) & 0xf0) |
  574. (cdfr & 0x0f));
  575. spin_unlock_irqrestore(&chip->reg_lock, flags);
  576. snd_cs4231_mce_down(chip);
  577. snd_cs4231_mce_up(chip);
  578. spin_lock_irqsave(&chip->reg_lock, flags);
  579. }
  580. }
  581. snd_cs4231_out(chip, CS4231_REC_FORMAT, cdfr);
  582. spin_unlock_irqrestore(&chip->reg_lock, flags);
  583. snd_cs4231_mce_down(chip);
  584. }
  585. snd_cs4231_calibrate_mute(chip, 0);
  586. up(&chip->mce_mutex);
  587. }
  588. /*
  589. * Timer interface
  590. */
  591. static unsigned long snd_cs4231_timer_resolution(snd_timer_t * timer)
  592. {
  593. cs4231_t *chip = snd_timer_chip(timer);
  594. if (chip->hardware & CS4231_HW_CS4236B_MASK)
  595. return 14467;
  596. else
  597. return chip->image[CS4231_PLAYBK_FORMAT] & 1 ? 9969 : 9920;
  598. }
  599. static int snd_cs4231_timer_start(snd_timer_t * timer)
  600. {
  601. unsigned long flags;
  602. unsigned int ticks;
  603. cs4231_t *chip = snd_timer_chip(timer);
  604. spin_lock_irqsave(&chip->reg_lock, flags);
  605. ticks = timer->sticks;
  606. if ((chip->image[CS4231_ALT_FEATURE_1] & CS4231_TIMER_ENABLE) == 0 ||
  607. (unsigned char)(ticks >> 8) != chip->image[CS4231_TIMER_HIGH] ||
  608. (unsigned char)ticks != chip->image[CS4231_TIMER_LOW]) {
  609. snd_cs4231_out(chip, CS4231_TIMER_HIGH, chip->image[CS4231_TIMER_HIGH] = (unsigned char) (ticks >> 8));
  610. snd_cs4231_out(chip, CS4231_TIMER_LOW, chip->image[CS4231_TIMER_LOW] = (unsigned char) ticks);
  611. snd_cs4231_out(chip, CS4231_ALT_FEATURE_1, chip->image[CS4231_ALT_FEATURE_1] | CS4231_TIMER_ENABLE);
  612. }
  613. spin_unlock_irqrestore(&chip->reg_lock, flags);
  614. return 0;
  615. }
  616. static int snd_cs4231_timer_stop(snd_timer_t * timer)
  617. {
  618. unsigned long flags;
  619. cs4231_t *chip = snd_timer_chip(timer);
  620. spin_lock_irqsave(&chip->reg_lock, flags);
  621. snd_cs4231_out(chip, CS4231_ALT_FEATURE_1, chip->image[CS4231_ALT_FEATURE_1] &= ~CS4231_TIMER_ENABLE);
  622. spin_unlock_irqrestore(&chip->reg_lock, flags);
  623. return 0;
  624. }
  625. static void snd_cs4231_init(cs4231_t *chip)
  626. {
  627. unsigned long flags;
  628. snd_cs4231_mce_down(chip);
  629. #ifdef SNDRV_DEBUG_MCE
  630. snd_printk("init: (1)\n");
  631. #endif
  632. snd_cs4231_mce_up(chip);
  633. spin_lock_irqsave(&chip->reg_lock, flags);
  634. chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_PLAYBACK_ENABLE | CS4231_PLAYBACK_PIO |
  635. CS4231_RECORD_ENABLE | CS4231_RECORD_PIO |
  636. CS4231_CALIB_MODE);
  637. chip->image[CS4231_IFACE_CTRL] |= CS4231_AUTOCALIB;
  638. snd_cs4231_out(chip, CS4231_IFACE_CTRL, chip->image[CS4231_IFACE_CTRL]);
  639. spin_unlock_irqrestore(&chip->reg_lock, flags);
  640. snd_cs4231_mce_down(chip);
  641. #ifdef SNDRV_DEBUG_MCE
  642. snd_printk("init: (2)\n");
  643. #endif
  644. snd_cs4231_mce_up(chip);
  645. spin_lock_irqsave(&chip->reg_lock, flags);
  646. snd_cs4231_out(chip, CS4231_ALT_FEATURE_1, chip->image[CS4231_ALT_FEATURE_1]);
  647. spin_unlock_irqrestore(&chip->reg_lock, flags);
  648. snd_cs4231_mce_down(chip);
  649. #ifdef SNDRV_DEBUG_MCE
  650. snd_printk("init: (3) - afei = 0x%x\n", chip->image[CS4231_ALT_FEATURE_1]);
  651. #endif
  652. spin_lock_irqsave(&chip->reg_lock, flags);
  653. snd_cs4231_out(chip, CS4231_ALT_FEATURE_2, chip->image[CS4231_ALT_FEATURE_2]);
  654. spin_unlock_irqrestore(&chip->reg_lock, flags);
  655. snd_cs4231_mce_up(chip);
  656. spin_lock_irqsave(&chip->reg_lock, flags);
  657. snd_cs4231_out(chip, CS4231_PLAYBK_FORMAT, chip->image[CS4231_PLAYBK_FORMAT]);
  658. spin_unlock_irqrestore(&chip->reg_lock, flags);
  659. snd_cs4231_mce_down(chip);
  660. #ifdef SNDRV_DEBUG_MCE
  661. snd_printk("init: (4)\n");
  662. #endif
  663. snd_cs4231_mce_up(chip);
  664. spin_lock_irqsave(&chip->reg_lock, flags);
  665. snd_cs4231_out(chip, CS4231_REC_FORMAT, chip->image[CS4231_REC_FORMAT]);
  666. spin_unlock_irqrestore(&chip->reg_lock, flags);
  667. snd_cs4231_mce_down(chip);
  668. #ifdef SNDRV_DEBUG_MCE
  669. snd_printk("init: (5)\n");
  670. #endif
  671. }
  672. static int snd_cs4231_open(cs4231_t *chip, unsigned int mode)
  673. {
  674. unsigned long flags;
  675. down(&chip->open_mutex);
  676. if ((chip->mode & mode) ||
  677. ((chip->mode & CS4231_MODE_OPEN) && chip->single_dma)) {
  678. up(&chip->open_mutex);
  679. return -EAGAIN;
  680. }
  681. if (chip->mode & CS4231_MODE_OPEN) {
  682. chip->mode |= mode;
  683. up(&chip->open_mutex);
  684. return 0;
  685. }
  686. /* ok. now enable and ack CODEC IRQ */
  687. spin_lock_irqsave(&chip->reg_lock, flags);
  688. snd_cs4231_out(chip, CS4231_IRQ_STATUS, CS4231_PLAYBACK_IRQ |
  689. CS4231_RECORD_IRQ |
  690. CS4231_TIMER_IRQ);
  691. snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0);
  692. cs4231_outb(chip, CS4231P(STATUS), 0); /* clear IRQ */
  693. cs4231_outb(chip, CS4231P(STATUS), 0); /* clear IRQ */
  694. chip->image[CS4231_PIN_CTRL] |= CS4231_IRQ_ENABLE;
  695. snd_cs4231_out(chip, CS4231_PIN_CTRL, chip->image[CS4231_PIN_CTRL]);
  696. snd_cs4231_out(chip, CS4231_IRQ_STATUS, CS4231_PLAYBACK_IRQ |
  697. CS4231_RECORD_IRQ |
  698. CS4231_TIMER_IRQ);
  699. snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0);
  700. spin_unlock_irqrestore(&chip->reg_lock, flags);
  701. chip->mode = mode;
  702. up(&chip->open_mutex);
  703. return 0;
  704. }
  705. static void snd_cs4231_close(cs4231_t *chip, unsigned int mode)
  706. {
  707. unsigned long flags;
  708. down(&chip->open_mutex);
  709. chip->mode &= ~mode;
  710. if (chip->mode & CS4231_MODE_OPEN) {
  711. up(&chip->open_mutex);
  712. return;
  713. }
  714. snd_cs4231_calibrate_mute(chip, 1);
  715. /* disable IRQ */
  716. spin_lock_irqsave(&chip->reg_lock, flags);
  717. snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0);
  718. cs4231_outb(chip, CS4231P(STATUS), 0); /* clear IRQ */
  719. cs4231_outb(chip, CS4231P(STATUS), 0); /* clear IRQ */
  720. chip->image[CS4231_PIN_CTRL] &= ~CS4231_IRQ_ENABLE;
  721. snd_cs4231_out(chip, CS4231_PIN_CTRL, chip->image[CS4231_PIN_CTRL]);
  722. /* now disable record & playback */
  723. if (chip->image[CS4231_IFACE_CTRL] & (CS4231_PLAYBACK_ENABLE | CS4231_PLAYBACK_PIO |
  724. CS4231_RECORD_ENABLE | CS4231_RECORD_PIO)) {
  725. spin_unlock_irqrestore(&chip->reg_lock, flags);
  726. snd_cs4231_mce_up(chip);
  727. spin_lock_irqsave(&chip->reg_lock, flags);
  728. chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_PLAYBACK_ENABLE | CS4231_PLAYBACK_PIO |
  729. CS4231_RECORD_ENABLE | CS4231_RECORD_PIO);
  730. snd_cs4231_out(chip, CS4231_IFACE_CTRL, chip->image[CS4231_IFACE_CTRL]);
  731. spin_unlock_irqrestore(&chip->reg_lock, flags);
  732. snd_cs4231_mce_down(chip);
  733. spin_lock_irqsave(&chip->reg_lock, flags);
  734. }
  735. /* clear IRQ again */
  736. snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0);
  737. cs4231_outb(chip, CS4231P(STATUS), 0); /* clear IRQ */
  738. cs4231_outb(chip, CS4231P(STATUS), 0); /* clear IRQ */
  739. spin_unlock_irqrestore(&chip->reg_lock, flags);
  740. snd_cs4231_calibrate_mute(chip, 0);
  741. chip->mode = 0;
  742. up(&chip->open_mutex);
  743. }
  744. /*
  745. * timer open/close
  746. */
  747. static int snd_cs4231_timer_open(snd_timer_t * timer)
  748. {
  749. cs4231_t *chip = snd_timer_chip(timer);
  750. snd_cs4231_open(chip, CS4231_MODE_TIMER);
  751. return 0;
  752. }
  753. static int snd_cs4231_timer_close(snd_timer_t * timer)
  754. {
  755. cs4231_t *chip = snd_timer_chip(timer);
  756. snd_cs4231_close(chip, CS4231_MODE_TIMER);
  757. return 0;
  758. }
  759. static struct _snd_timer_hardware snd_cs4231_timer_table =
  760. {
  761. .flags = SNDRV_TIMER_HW_AUTO,
  762. .resolution = 9945,
  763. .ticks = 65535,
  764. .open = snd_cs4231_timer_open,
  765. .close = snd_cs4231_timer_close,
  766. .c_resolution = snd_cs4231_timer_resolution,
  767. .start = snd_cs4231_timer_start,
  768. .stop = snd_cs4231_timer_stop,
  769. };
  770. /*
  771. * ok.. exported functions..
  772. */
  773. static int snd_cs4231_playback_hw_params(snd_pcm_substream_t * substream,
  774. snd_pcm_hw_params_t * hw_params)
  775. {
  776. cs4231_t *chip = snd_pcm_substream_chip(substream);
  777. unsigned char new_pdfr;
  778. int err;
  779. if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0)
  780. return err;
  781. new_pdfr = snd_cs4231_get_format(chip, params_format(hw_params), params_channels(hw_params)) |
  782. snd_cs4231_get_rate(params_rate(hw_params));
  783. chip->set_playback_format(chip, hw_params, new_pdfr);
  784. return 0;
  785. }
  786. static int snd_cs4231_playback_hw_free(snd_pcm_substream_t * substream)
  787. {
  788. return snd_pcm_lib_free_pages(substream);
  789. }
  790. #ifdef LEGACY_SUPPORT
  791. static int snd_cs4231_playback_prepare(snd_pcm_substream_t * substream)
  792. {
  793. cs4231_t *chip = snd_pcm_substream_chip(substream);
  794. snd_pcm_runtime_t *runtime = substream->runtime;
  795. unsigned long flags;
  796. unsigned int size = snd_pcm_lib_buffer_bytes(substream);
  797. unsigned int count = snd_pcm_lib_period_bytes(substream);
  798. spin_lock_irqsave(&chip->reg_lock, flags);
  799. chip->p_dma_size = size;
  800. chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_PLAYBACK_ENABLE | CS4231_PLAYBACK_PIO);
  801. snd_dma_program(chip->dma1, runtime->dma_addr, size, DMA_MODE_WRITE | DMA_AUTOINIT);
  802. count = snd_cs4231_get_count(chip->image[CS4231_PLAYBK_FORMAT], count) - 1;
  803. snd_cs4231_out(chip, CS4231_PLY_LWR_CNT, (unsigned char) count);
  804. snd_cs4231_out(chip, CS4231_PLY_UPR_CNT, (unsigned char) (count >> 8));
  805. spin_unlock_irqrestore(&chip->reg_lock, flags);
  806. #if 0
  807. snd_cs4231_debug(chip);
  808. #endif
  809. return 0;
  810. }
  811. #endif /* LEGACY_SUPPORT */
  812. static int snd_cs4231_capture_hw_params(snd_pcm_substream_t * substream,
  813. snd_pcm_hw_params_t * hw_params)
  814. {
  815. cs4231_t *chip = snd_pcm_substream_chip(substream);
  816. unsigned char new_cdfr;
  817. int err;
  818. if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0)
  819. return err;
  820. new_cdfr = snd_cs4231_get_format(chip, params_format(hw_params), params_channels(hw_params)) |
  821. snd_cs4231_get_rate(params_rate(hw_params));
  822. chip->set_capture_format(chip, hw_params, new_cdfr);
  823. return 0;
  824. }
  825. static int snd_cs4231_capture_hw_free(snd_pcm_substream_t * substream)
  826. {
  827. return snd_pcm_lib_free_pages(substream);
  828. }
  829. #ifdef LEGACY_SUPPORT
  830. static int snd_cs4231_capture_prepare(snd_pcm_substream_t * substream)
  831. {
  832. cs4231_t *chip = snd_pcm_substream_chip(substream);
  833. snd_pcm_runtime_t *runtime = substream->runtime;
  834. unsigned long flags;
  835. unsigned int size = snd_pcm_lib_buffer_bytes(substream);
  836. unsigned int count = snd_pcm_lib_period_bytes(substream);
  837. spin_lock_irqsave(&chip->reg_lock, flags);
  838. chip->c_dma_size = size;
  839. chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_RECORD_ENABLE | CS4231_RECORD_PIO);
  840. snd_dma_program(chip->dma2, runtime->dma_addr, size, DMA_MODE_READ | DMA_AUTOINIT);
  841. count = snd_cs4231_get_count(chip->image[CS4231_REC_FORMAT], count) - 1;
  842. if (chip->single_dma && chip->hardware != CS4231_HW_INTERWAVE) {
  843. snd_cs4231_out(chip, CS4231_PLY_LWR_CNT, (unsigned char) count);
  844. snd_cs4231_out(chip, CS4231_PLY_UPR_CNT, (unsigned char) (count >> 8));
  845. } else {
  846. snd_cs4231_out(chip, CS4231_REC_LWR_CNT, (unsigned char) count);
  847. snd_cs4231_out(chip, CS4231_REC_UPR_CNT, (unsigned char) (count >> 8));
  848. }
  849. spin_unlock_irqrestore(&chip->reg_lock, flags);
  850. return 0;
  851. }
  852. #endif
  853. static void snd_cs4231_overrange(cs4231_t *chip)
  854. {
  855. unsigned long flags;
  856. unsigned char res;
  857. spin_lock_irqsave(&chip->reg_lock, flags);
  858. res = snd_cs4231_in(chip, CS4231_TEST_INIT);
  859. spin_unlock_irqrestore(&chip->reg_lock, flags);
  860. if (res & (0x08 | 0x02)) /* detect overrange only above 0dB; may be user selectable? */
  861. chip->capture_substream->runtime->overrange++;
  862. }
  863. irqreturn_t snd_cs4231_interrupt(int irq, void *dev_id, struct pt_regs *regs)
  864. {
  865. cs4231_t *chip = dev_id;
  866. unsigned char status;
  867. status = snd_cs4231_in(chip, CS4231_IRQ_STATUS);
  868. if (status & CS4231_TIMER_IRQ) {
  869. if (chip->timer)
  870. snd_timer_interrupt(chip->timer, chip->timer->sticks);
  871. }
  872. if (chip->single_dma && chip->hardware != CS4231_HW_INTERWAVE) {
  873. if (status & CS4231_PLAYBACK_IRQ) {
  874. if (chip->mode & CS4231_MODE_PLAY) {
  875. if (chip->playback_substream)
  876. snd_pcm_period_elapsed(chip->playback_substream);
  877. }
  878. if (chip->mode & CS4231_MODE_RECORD) {
  879. if (chip->capture_substream) {
  880. snd_cs4231_overrange(chip);
  881. snd_pcm_period_elapsed(chip->capture_substream);
  882. }
  883. }
  884. }
  885. } else {
  886. if (status & CS4231_PLAYBACK_IRQ) {
  887. if (chip->playback_substream)
  888. snd_pcm_period_elapsed(chip->playback_substream);
  889. }
  890. if (status & CS4231_RECORD_IRQ) {
  891. if (chip->capture_substream) {
  892. snd_cs4231_overrange(chip);
  893. snd_pcm_period_elapsed(chip->capture_substream);
  894. }
  895. }
  896. }
  897. spin_lock(&chip->reg_lock);
  898. snd_cs4231_outm(chip, CS4231_IRQ_STATUS, ~CS4231_ALL_IRQS | ~status, 0);
  899. spin_unlock(&chip->reg_lock);
  900. return IRQ_HANDLED;
  901. }
  902. #ifdef LEGACY_SUPPORT
  903. static snd_pcm_uframes_t snd_cs4231_playback_pointer(snd_pcm_substream_t * substream)
  904. {
  905. cs4231_t *chip = snd_pcm_substream_chip(substream);
  906. size_t ptr;
  907. if (!(chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE))
  908. return 0;
  909. ptr = snd_dma_pointer(chip->dma1, chip->p_dma_size);
  910. return bytes_to_frames(substream->runtime, ptr);
  911. }
  912. static snd_pcm_uframes_t snd_cs4231_capture_pointer(snd_pcm_substream_t * substream)
  913. {
  914. cs4231_t *chip = snd_pcm_substream_chip(substream);
  915. size_t ptr;
  916. if (!(chip->image[CS4231_IFACE_CTRL] & CS4231_RECORD_ENABLE))
  917. return 0;
  918. ptr = snd_dma_pointer(chip->dma2, chip->c_dma_size);
  919. return bytes_to_frames(substream->runtime, ptr);
  920. }
  921. #endif /* LEGACY_SUPPORT */
  922. /*
  923. */
  924. static int snd_cs4231_probe(cs4231_t *chip)
  925. {
  926. unsigned long flags;
  927. int i, id, rev;
  928. unsigned char *ptr;
  929. unsigned int hw;
  930. #if 0
  931. snd_cs4231_debug(chip);
  932. #endif
  933. id = 0;
  934. for (i = 0; i < 50; i++) {
  935. mb();
  936. if (cs4231_inb(chip, CS4231P(REGSEL)) & CS4231_INIT)
  937. udelay(2000);
  938. else {
  939. spin_lock_irqsave(&chip->reg_lock, flags);
  940. snd_cs4231_out(chip, CS4231_MISC_INFO, CS4231_MODE2);
  941. id = snd_cs4231_in(chip, CS4231_MISC_INFO) & 0x0f;
  942. spin_unlock_irqrestore(&chip->reg_lock, flags);
  943. if (id == 0x0a)
  944. break; /* this is valid value */
  945. }
  946. }
  947. snd_printdd("cs4231: port = 0x%lx, id = 0x%x\n", chip->port, id);
  948. if (id != 0x0a)
  949. return -ENODEV; /* no valid device found */
  950. if (((hw = chip->hardware) & CS4231_HW_TYPE_MASK) == CS4231_HW_DETECT) {
  951. rev = snd_cs4231_in(chip, CS4231_VERSION) & 0xe7;
  952. snd_printdd("CS4231: VERSION (I25) = 0x%x\n", rev);
  953. if (rev == 0x80) {
  954. unsigned char tmp = snd_cs4231_in(chip, 23);
  955. snd_cs4231_out(chip, 23, ~tmp);
  956. if (snd_cs4231_in(chip, 23) != tmp)
  957. chip->hardware = CS4231_HW_AD1845;
  958. else
  959. chip->hardware = CS4231_HW_CS4231;
  960. } else if (rev == 0xa0) {
  961. chip->hardware = CS4231_HW_CS4231A;
  962. } else if (rev == 0xa2) {
  963. chip->hardware = CS4231_HW_CS4232;
  964. } else if (rev == 0xb2) {
  965. chip->hardware = CS4231_HW_CS4232A;
  966. } else if (rev == 0x83) {
  967. chip->hardware = CS4231_HW_CS4236;
  968. } else if (rev == 0x03) {
  969. chip->hardware = CS4231_HW_CS4236B;
  970. } else {
  971. snd_printk("unknown CS chip with version 0x%x\n", rev);
  972. return -ENODEV; /* unknown CS4231 chip? */
  973. }
  974. }
  975. spin_lock_irqsave(&chip->reg_lock, flags);
  976. cs4231_inb(chip, CS4231P(STATUS)); /* clear any pendings IRQ */
  977. cs4231_outb(chip, CS4231P(STATUS), 0);
  978. mb();
  979. spin_unlock_irqrestore(&chip->reg_lock, flags);
  980. chip->image[CS4231_MISC_INFO] = CS4231_MODE2;
  981. switch (chip->hardware) {
  982. case CS4231_HW_INTERWAVE:
  983. chip->image[CS4231_MISC_INFO] = CS4231_IW_MODE3;
  984. break;
  985. case CS4231_HW_CS4235:
  986. case CS4231_HW_CS4236B:
  987. case CS4231_HW_CS4237B:
  988. case CS4231_HW_CS4238B:
  989. case CS4231_HW_CS4239:
  990. if (hw == CS4231_HW_DETECT3)
  991. chip->image[CS4231_MISC_INFO] = CS4231_4236_MODE3;
  992. else
  993. chip->hardware = CS4231_HW_CS4236;
  994. break;
  995. }
  996. chip->image[CS4231_IFACE_CTRL] =
  997. (chip->image[CS4231_IFACE_CTRL] & ~CS4231_SINGLE_DMA) |
  998. (chip->single_dma ? CS4231_SINGLE_DMA : 0);
  999. chip->image[CS4231_ALT_FEATURE_1] = 0x80;
  1000. chip->image[CS4231_ALT_FEATURE_2] = chip->hardware == CS4231_HW_INTERWAVE ? 0xc2 : 0x01;
  1001. ptr = (unsigned char *) &chip->image;
  1002. snd_cs4231_mce_down(chip);
  1003. spin_lock_irqsave(&chip->reg_lock, flags);
  1004. for (i = 0; i < 32; i++) /* ok.. fill all CS4231 registers */
  1005. snd_cs4231_out(chip, i, *ptr++);
  1006. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1007. snd_cs4231_mce_up(chip);
  1008. snd_cs4231_mce_down(chip);
  1009. mdelay(2);
  1010. /* ok.. try check hardware version for CS4236+ chips */
  1011. if ((hw & CS4231_HW_TYPE_MASK) == CS4231_HW_DETECT) {
  1012. if (chip->hardware == CS4231_HW_CS4236B) {
  1013. rev = snd_cs4236_ext_in(chip, CS4236_VERSION);
  1014. snd_cs4236_ext_out(chip, CS4236_VERSION, 0xff);
  1015. id = snd_cs4236_ext_in(chip, CS4236_VERSION);
  1016. snd_cs4236_ext_out(chip, CS4236_VERSION, rev);
  1017. snd_printdd("CS4231: ext version; rev = 0x%x, id = 0x%x\n", rev, id);
  1018. if ((id & 0x1f) == 0x1d) { /* CS4235 */
  1019. chip->hardware = CS4231_HW_CS4235;
  1020. switch (id >> 5) {
  1021. case 4:
  1022. case 5:
  1023. case 6:
  1024. break;
  1025. default:
  1026. snd_printk("unknown CS4235 chip (enhanced version = 0x%x)\n", id);
  1027. }
  1028. } else if ((id & 0x1f) == 0x0b) { /* CS4236/B */
  1029. switch (id >> 5) {
  1030. case 4:
  1031. case 5:
  1032. case 6:
  1033. case 7:
  1034. chip->hardware = CS4231_HW_CS4236B;
  1035. break;
  1036. default:
  1037. snd_printk("unknown CS4236 chip (enhanced version = 0x%x)\n", id);
  1038. }
  1039. } else if ((id & 0x1f) == 0x08) { /* CS4237B */
  1040. chip->hardware = CS4231_HW_CS4237B;
  1041. switch (id >> 5) {
  1042. case 4:
  1043. case 5:
  1044. case 6:
  1045. case 7:
  1046. break;
  1047. default:
  1048. snd_printk("unknown CS4237B chip (enhanced version = 0x%x)\n", id);
  1049. }
  1050. } else if ((id & 0x1f) == 0x09) { /* CS4238B */
  1051. chip->hardware = CS4231_HW_CS4238B;
  1052. switch (id >> 5) {
  1053. case 5:
  1054. case 6:
  1055. case 7:
  1056. break;
  1057. default:
  1058. snd_printk("unknown CS4238B chip (enhanced version = 0x%x)\n", id);
  1059. }
  1060. } else if ((id & 0x1f) == 0x1e) { /* CS4239 */
  1061. chip->hardware = CS4231_HW_CS4239;
  1062. switch (id >> 5) {
  1063. case 4:
  1064. case 5:
  1065. case 6:
  1066. break;
  1067. default:
  1068. snd_printk("unknown CS4239 chip (enhanced version = 0x%x)\n", id);
  1069. }
  1070. } else {
  1071. snd_printk("unknown CS4236/CS423xB chip (enhanced version = 0x%x)\n", id);
  1072. }
  1073. }
  1074. }
  1075. return 0; /* all things are ok.. */
  1076. }
  1077. /*
  1078. */
  1079. static snd_pcm_hardware_t snd_cs4231_playback =
  1080. {
  1081. .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  1082. SNDRV_PCM_INFO_MMAP_VALID |
  1083. SNDRV_PCM_INFO_RESUME |
  1084. SNDRV_PCM_INFO_SYNC_START),
  1085. .formats = (SNDRV_PCM_FMTBIT_MU_LAW | SNDRV_PCM_FMTBIT_A_LAW | SNDRV_PCM_FMTBIT_IMA_ADPCM |
  1086. SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE),
  1087. .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_48000,
  1088. .rate_min = 5510,
  1089. .rate_max = 48000,
  1090. .channels_min = 1,
  1091. .channels_max = 2,
  1092. .buffer_bytes_max = (128*1024),
  1093. .period_bytes_min = 64,
  1094. .period_bytes_max = (128*1024),
  1095. .periods_min = 1,
  1096. .periods_max = 1024,
  1097. .fifo_size = 0,
  1098. };
  1099. static snd_pcm_hardware_t snd_cs4231_capture =
  1100. {
  1101. .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  1102. SNDRV_PCM_INFO_MMAP_VALID |
  1103. SNDRV_PCM_INFO_RESUME |
  1104. SNDRV_PCM_INFO_SYNC_START),
  1105. .formats = (SNDRV_PCM_FMTBIT_MU_LAW | SNDRV_PCM_FMTBIT_A_LAW | SNDRV_PCM_FMTBIT_IMA_ADPCM |
  1106. SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE),
  1107. .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_48000,
  1108. .rate_min = 5510,
  1109. .rate_max = 48000,
  1110. .channels_min = 1,
  1111. .channels_max = 2,
  1112. .buffer_bytes_max = (128*1024),
  1113. .period_bytes_min = 64,
  1114. .period_bytes_max = (128*1024),
  1115. .periods_min = 1,
  1116. .periods_max = 1024,
  1117. .fifo_size = 0,
  1118. };
  1119. /*
  1120. */
  1121. static int snd_cs4231_playback_open(snd_pcm_substream_t * substream)
  1122. {
  1123. cs4231_t *chip = snd_pcm_substream_chip(substream);
  1124. snd_pcm_runtime_t *runtime = substream->runtime;
  1125. int err;
  1126. runtime->hw = snd_cs4231_playback;
  1127. /* hardware bug in InterWave chipset */
  1128. if (chip->hardware == CS4231_HW_INTERWAVE && chip->dma1 > 3)
  1129. runtime->hw.formats &= ~SNDRV_PCM_FMTBIT_MU_LAW;
  1130. /* hardware limitation of cheap chips */
  1131. if (chip->hardware == CS4231_HW_CS4235 ||
  1132. chip->hardware == CS4231_HW_CS4239)
  1133. runtime->hw.formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE;
  1134. #ifdef LEGACY_SUPPORT
  1135. snd_pcm_limit_isa_dma_size(chip->dma1, &runtime->hw.buffer_bytes_max);
  1136. snd_pcm_limit_isa_dma_size(chip->dma1, &runtime->hw.period_bytes_max);
  1137. if (chip->claim_dma) {
  1138. if ((err = chip->claim_dma(chip, chip->dma_private_data, chip->dma1)) < 0)
  1139. return err;
  1140. }
  1141. #endif
  1142. if ((err = snd_cs4231_open(chip, CS4231_MODE_PLAY)) < 0) {
  1143. #ifdef LEGACY_SUPPORT
  1144. if (chip->release_dma)
  1145. chip->release_dma(chip, chip->dma_private_data, chip->dma1);
  1146. #endif
  1147. snd_free_pages(runtime->dma_area, runtime->dma_bytes);
  1148. return err;
  1149. }
  1150. chip->playback_substream = substream;
  1151. #if defined(SBUS_SUPPORT) || defined(EBUS_SUPPORT)
  1152. chip->p_periods_sent = 0;
  1153. #endif
  1154. snd_pcm_set_sync(substream);
  1155. chip->rate_constraint(runtime);
  1156. return 0;
  1157. }
  1158. static int snd_cs4231_capture_open(snd_pcm_substream_t * substream)
  1159. {
  1160. cs4231_t *chip = snd_pcm_substream_chip(substream);
  1161. snd_pcm_runtime_t *runtime = substream->runtime;
  1162. int err;
  1163. runtime->hw = snd_cs4231_capture;
  1164. /* hardware limitation of cheap chips */
  1165. if (chip->hardware == CS4231_HW_CS4235 ||
  1166. chip->hardware == CS4231_HW_CS4239)
  1167. runtime->hw.formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE;
  1168. #ifdef LEGACY_SUPPORT
  1169. snd_pcm_limit_isa_dma_size(chip->dma2, &runtime->hw.buffer_bytes_max);
  1170. snd_pcm_limit_isa_dma_size(chip->dma2, &runtime->hw.period_bytes_max);
  1171. if (chip->claim_dma) {
  1172. if ((err = chip->claim_dma(chip, chip->dma_private_data, chip->dma2)) < 0)
  1173. return err;
  1174. }
  1175. #endif
  1176. if ((err = snd_cs4231_open(chip, CS4231_MODE_RECORD)) < 0) {
  1177. #ifdef LEGACY_SUPPORT
  1178. if (chip->release_dma)
  1179. chip->release_dma(chip, chip->dma_private_data, chip->dma2);
  1180. #endif
  1181. snd_free_pages(runtime->dma_area, runtime->dma_bytes);
  1182. return err;
  1183. }
  1184. chip->capture_substream = substream;
  1185. #if defined(SBUS_SUPPORT) || defined(EBUS_SUPPORT)
  1186. chip->c_periods_sent = 0;
  1187. #endif
  1188. snd_pcm_set_sync(substream);
  1189. chip->rate_constraint(runtime);
  1190. return 0;
  1191. }
  1192. static int snd_cs4231_playback_close(snd_pcm_substream_t * substream)
  1193. {
  1194. cs4231_t *chip = snd_pcm_substream_chip(substream);
  1195. chip->playback_substream = NULL;
  1196. snd_cs4231_close(chip, CS4231_MODE_PLAY);
  1197. return 0;
  1198. }
  1199. static int snd_cs4231_capture_close(snd_pcm_substream_t * substream)
  1200. {
  1201. cs4231_t *chip = snd_pcm_substream_chip(substream);
  1202. chip->capture_substream = NULL;
  1203. snd_cs4231_close(chip, CS4231_MODE_RECORD);
  1204. return 0;
  1205. }
  1206. #ifdef CONFIG_PM
  1207. /* lowlevel suspend callback for CS4231 */
  1208. static void snd_cs4231_suspend(cs4231_t *chip)
  1209. {
  1210. int reg;
  1211. unsigned long flags;
  1212. spin_lock_irqsave(&chip->reg_lock, flags);
  1213. for (reg = 0; reg < 32; reg++)
  1214. chip->image[reg] = snd_cs4231_in(chip, reg);
  1215. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1216. }
  1217. /* lowlevel resume callback for CS4231 */
  1218. static void snd_cs4231_resume(cs4231_t *chip)
  1219. {
  1220. int reg;
  1221. unsigned long flags;
  1222. int timeout;
  1223. snd_cs4231_mce_up(chip);
  1224. spin_lock_irqsave(&chip->reg_lock, flags);
  1225. for (reg = 0; reg < 32; reg++) {
  1226. switch (reg) {
  1227. case CS4231_VERSION:
  1228. break;
  1229. default:
  1230. snd_cs4231_out(chip, reg, chip->image[reg]);
  1231. break;
  1232. }
  1233. }
  1234. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1235. #if 0
  1236. snd_cs4231_mce_down(chip);
  1237. #else
  1238. /* The following is a workaround to avoid freeze after resume on TP600E.
  1239. This is the first half of copy of snd_cs4231_mce_down(), but doesn't
  1240. include rescheduling. -- iwai
  1241. */
  1242. snd_cs4231_busy_wait(chip);
  1243. spin_lock_irqsave(&chip->reg_lock, flags);
  1244. chip->mce_bit &= ~CS4231_MCE;
  1245. timeout = cs4231_inb(chip, CS4231P(REGSEL));
  1246. cs4231_outb(chip, CS4231P(REGSEL), chip->mce_bit | (timeout & 0x1f));
  1247. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1248. if (timeout == 0x80)
  1249. snd_printk("down [0x%lx]: serious init problem - codec still busy\n", chip->port);
  1250. if ((timeout & CS4231_MCE) == 0 ||
  1251. !(chip->hardware & (CS4231_HW_CS4231_MASK | CS4231_HW_CS4232_MASK))) {
  1252. return;
  1253. }
  1254. snd_cs4231_busy_wait(chip);
  1255. #endif
  1256. }
  1257. static int snd_cs4231_pm_suspend(snd_card_t *card, pm_message_t state)
  1258. {
  1259. cs4231_t *chip = card->pm_private_data;
  1260. if (chip->suspend)
  1261. chip->suspend(chip);
  1262. return 0;
  1263. }
  1264. static int snd_cs4231_pm_resume(snd_card_t *card)
  1265. {
  1266. cs4231_t *chip = card->pm_private_data;
  1267. if (chip->resume)
  1268. chip->resume(chip);
  1269. return 0;
  1270. }
  1271. #endif /* CONFIG_PM */
  1272. #ifdef LEGACY_SUPPORT
  1273. static int snd_cs4231_free(cs4231_t *chip)
  1274. {
  1275. if (chip->res_port) {
  1276. release_resource(chip->res_port);
  1277. kfree_nocheck(chip->res_port);
  1278. }
  1279. if (chip->res_cport) {
  1280. release_resource(chip->res_cport);
  1281. kfree_nocheck(chip->res_cport);
  1282. }
  1283. if (chip->irq >= 0) {
  1284. disable_irq(chip->irq);
  1285. if (!(chip->hwshare & CS4231_HWSHARE_IRQ))
  1286. free_irq(chip->irq, (void *) chip);
  1287. }
  1288. if (!(chip->hwshare & CS4231_HWSHARE_DMA1) && chip->dma1 >= 0) {
  1289. snd_dma_disable(chip->dma1);
  1290. free_dma(chip->dma1);
  1291. }
  1292. if (!(chip->hwshare & CS4231_HWSHARE_DMA2) && chip->dma2 >= 0 && chip->dma2 != chip->dma1) {
  1293. snd_dma_disable(chip->dma2);
  1294. free_dma(chip->dma2);
  1295. }
  1296. if (chip->timer)
  1297. snd_device_free(chip->card, chip->timer);
  1298. kfree(chip);
  1299. return 0;
  1300. }
  1301. static int snd_cs4231_dev_free(snd_device_t *device)
  1302. {
  1303. cs4231_t *chip = device->device_data;
  1304. return snd_cs4231_free(chip);
  1305. }
  1306. #endif /* LEGACY_SUPPORT */
  1307. const char *snd_cs4231_chip_id(cs4231_t *chip)
  1308. {
  1309. switch (chip->hardware) {
  1310. case CS4231_HW_CS4231: return "CS4231";
  1311. case CS4231_HW_CS4231A: return "CS4231A";
  1312. case CS4231_HW_CS4232: return "CS4232";
  1313. case CS4231_HW_CS4232A: return "CS4232A";
  1314. case CS4231_HW_CS4235: return "CS4235";
  1315. case CS4231_HW_CS4236: return "CS4236";
  1316. case CS4231_HW_CS4236B: return "CS4236B";
  1317. case CS4231_HW_CS4237B: return "CS4237B";
  1318. case CS4231_HW_CS4238B: return "CS4238B";
  1319. case CS4231_HW_CS4239: return "CS4239";
  1320. case CS4231_HW_INTERWAVE: return "AMD InterWave";
  1321. case CS4231_HW_OPL3SA2: return chip->card->shortname;
  1322. case CS4231_HW_AD1845: return "AD1845";
  1323. default: return "???";
  1324. }
  1325. }
  1326. static int snd_cs4231_new(snd_card_t * card,
  1327. unsigned short hardware,
  1328. unsigned short hwshare,
  1329. cs4231_t ** rchip)
  1330. {
  1331. cs4231_t *chip;
  1332. *rchip = NULL;
  1333. chip = kcalloc(1, sizeof(*chip), GFP_KERNEL);
  1334. if (chip == NULL)
  1335. return -ENOMEM;
  1336. chip->hardware = hardware;
  1337. chip->hwshare = hwshare;
  1338. spin_lock_init(&chip->reg_lock);
  1339. init_MUTEX(&chip->mce_mutex);
  1340. init_MUTEX(&chip->open_mutex);
  1341. chip->card = card;
  1342. chip->rate_constraint = snd_cs4231_xrate;
  1343. chip->set_playback_format = snd_cs4231_playback_format;
  1344. chip->set_capture_format = snd_cs4231_capture_format;
  1345. memcpy(&chip->image, &snd_cs4231_original_image, sizeof(snd_cs4231_original_image));
  1346. *rchip = chip;
  1347. return 0;
  1348. }
  1349. #ifdef LEGACY_SUPPORT
  1350. int snd_cs4231_create(snd_card_t * card,
  1351. unsigned long port,
  1352. unsigned long cport,
  1353. int irq, int dma1, int dma2,
  1354. unsigned short hardware,
  1355. unsigned short hwshare,
  1356. cs4231_t ** rchip)
  1357. {
  1358. static snd_device_ops_t ops = {
  1359. .dev_free = snd_cs4231_dev_free,
  1360. };
  1361. cs4231_t *chip;
  1362. int err;
  1363. err = snd_cs4231_new(card, hardware, hwshare, &chip);
  1364. if (err < 0)
  1365. return err;
  1366. chip->irq = -1;
  1367. chip->dma1 = -1;
  1368. chip->dma2 = -1;
  1369. if ((chip->res_port = request_region(port, 4, "CS4231")) == NULL) {
  1370. snd_printk(KERN_ERR "cs4231: can't grab port 0x%lx\n", port);
  1371. snd_cs4231_free(chip);
  1372. return -EBUSY;
  1373. }
  1374. chip->port = port;
  1375. if ((long)cport >= 0 && (chip->res_cport = request_region(cport, 8, "CS4232 Control")) == NULL) {
  1376. snd_printk(KERN_ERR "cs4231: can't grab control port 0x%lx\n", cport);
  1377. snd_cs4231_free(chip);
  1378. return -ENODEV;
  1379. }
  1380. chip->cport = cport;
  1381. if (!(hwshare & CS4231_HWSHARE_IRQ) && request_irq(irq, snd_cs4231_interrupt, SA_INTERRUPT, "CS4231", (void *) chip)) {
  1382. snd_printk(KERN_ERR "cs4231: can't grab IRQ %d\n", irq);
  1383. snd_cs4231_free(chip);
  1384. return -EBUSY;
  1385. }
  1386. chip->irq = irq;
  1387. if (!(hwshare & CS4231_HWSHARE_DMA1) && request_dma(dma1, "CS4231 - 1")) {
  1388. snd_printk(KERN_ERR "cs4231: can't grab DMA1 %d\n", dma1);
  1389. snd_cs4231_free(chip);
  1390. return -EBUSY;
  1391. }
  1392. chip->dma1 = dma1;
  1393. if (!(hwshare & CS4231_HWSHARE_DMA2) && dma1 != dma2 && dma2 >= 0 && request_dma(dma2, "CS4231 - 2")) {
  1394. snd_printk(KERN_ERR "cs4231: can't grab DMA2 %d\n", dma2);
  1395. snd_cs4231_free(chip);
  1396. return -EBUSY;
  1397. }
  1398. if (dma1 == dma2 || dma2 < 0) {
  1399. chip->single_dma = 1;
  1400. chip->dma2 = chip->dma1;
  1401. } else
  1402. chip->dma2 = dma2;
  1403. /* global setup */
  1404. if (snd_cs4231_probe(chip) < 0) {
  1405. snd_cs4231_free(chip);
  1406. return -ENODEV;
  1407. }
  1408. snd_cs4231_init(chip);
  1409. if (chip->hardware & CS4231_HW_CS4232_MASK) {
  1410. if (chip->res_cport == NULL)
  1411. snd_printk("CS4232 control port features are not accessible\n");
  1412. }
  1413. /* Register device */
  1414. if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
  1415. snd_cs4231_free(chip);
  1416. return err;
  1417. }
  1418. #ifdef CONFIG_PM
  1419. /* Power Management */
  1420. chip->suspend = snd_cs4231_suspend;
  1421. chip->resume = snd_cs4231_resume;
  1422. snd_card_set_isa_pm_callback(card, snd_cs4231_pm_suspend, snd_cs4231_pm_resume, chip);
  1423. #endif
  1424. *rchip = chip;
  1425. return 0;
  1426. }
  1427. #endif /* LEGACY_SUPPORT */
  1428. static snd_pcm_ops_t snd_cs4231_playback_ops = {
  1429. .open = snd_cs4231_playback_open,
  1430. .close = snd_cs4231_playback_close,
  1431. .ioctl = snd_pcm_lib_ioctl,
  1432. .hw_params = snd_cs4231_playback_hw_params,
  1433. .hw_free = snd_cs4231_playback_hw_free,
  1434. .prepare = snd_cs4231_playback_prepare,
  1435. .trigger = snd_cs4231_trigger,
  1436. .pointer = snd_cs4231_playback_pointer,
  1437. };
  1438. static snd_pcm_ops_t snd_cs4231_capture_ops = {
  1439. .open = snd_cs4231_capture_open,
  1440. .close = snd_cs4231_capture_close,
  1441. .ioctl = snd_pcm_lib_ioctl,
  1442. .hw_params = snd_cs4231_capture_hw_params,
  1443. .hw_free = snd_cs4231_capture_hw_free,
  1444. .prepare = snd_cs4231_capture_prepare,
  1445. .trigger = snd_cs4231_trigger,
  1446. .pointer = snd_cs4231_capture_pointer,
  1447. };
  1448. static void snd_cs4231_pcm_free(snd_pcm_t *pcm)
  1449. {
  1450. cs4231_t *chip = pcm->private_data;
  1451. chip->pcm = NULL;
  1452. snd_pcm_lib_preallocate_free_for_all(pcm);
  1453. }
  1454. int snd_cs4231_pcm(cs4231_t *chip, int device, snd_pcm_t **rpcm)
  1455. {
  1456. snd_pcm_t *pcm;
  1457. int err;
  1458. if ((err = snd_pcm_new(chip->card, "CS4231", device, 1, 1, &pcm)) < 0)
  1459. return err;
  1460. spin_lock_init(&chip->reg_lock);
  1461. init_MUTEX(&chip->mce_mutex);
  1462. init_MUTEX(&chip->open_mutex);
  1463. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs4231_playback_ops);
  1464. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cs4231_capture_ops);
  1465. /* global setup */
  1466. pcm->private_data = chip;
  1467. pcm->private_free = snd_cs4231_pcm_free;
  1468. pcm->info_flags = 0;
  1469. if (chip->single_dma)
  1470. pcm->info_flags |= SNDRV_PCM_INFO_HALF_DUPLEX;
  1471. if (chip->hardware != CS4231_HW_INTERWAVE)
  1472. pcm->info_flags |= SNDRV_PCM_INFO_JOINT_DUPLEX;
  1473. strcpy(pcm->name, snd_cs4231_chip_id(chip));
  1474. #ifdef LEGACY_SUPPORT
  1475. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  1476. snd_dma_isa_data(),
  1477. 64*1024, chip->dma1 > 3 || chip->dma2 > 3 ? 128*1024 : 64*1024);
  1478. #else
  1479. # ifdef EBUS_SUPPORT
  1480. if (chip->ebus_flag) {
  1481. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  1482. chip->dev_u.pdev,
  1483. 64*1024, 128*1024);
  1484. } else {
  1485. # endif
  1486. # ifdef SBUS_SUPPORT
  1487. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_SBUS,
  1488. chip->dev_u.sdev,
  1489. 64*1024, 128*1024);
  1490. # endif
  1491. # ifdef EBUS_SUPPORT
  1492. }
  1493. # endif
  1494. #endif
  1495. chip->pcm = pcm;
  1496. if (rpcm)
  1497. *rpcm = pcm;
  1498. return 0;
  1499. }
  1500. static void snd_cs4231_timer_free(snd_timer_t *timer)
  1501. {
  1502. cs4231_t *chip = timer->private_data;
  1503. chip->timer = NULL;
  1504. }
  1505. int snd_cs4231_timer(cs4231_t *chip, int device, snd_timer_t **rtimer)
  1506. {
  1507. snd_timer_t *timer;
  1508. snd_timer_id_t tid;
  1509. int err;
  1510. /* Timer initialization */
  1511. tid.dev_class = SNDRV_TIMER_CLASS_CARD;
  1512. tid.dev_sclass = SNDRV_TIMER_SCLASS_NONE;
  1513. tid.card = chip->card->number;
  1514. tid.device = device;
  1515. tid.subdevice = 0;
  1516. if ((err = snd_timer_new(chip->card, "CS4231", &tid, &timer)) < 0)
  1517. return err;
  1518. strcpy(timer->name, snd_cs4231_chip_id(chip));
  1519. timer->private_data = chip;
  1520. timer->private_free = snd_cs4231_timer_free;
  1521. timer->hw = snd_cs4231_timer_table;
  1522. chip->timer = timer;
  1523. if (rtimer)
  1524. *rtimer = timer;
  1525. return 0;
  1526. }
  1527. /*
  1528. * MIXER part
  1529. */
  1530. static int snd_cs4231_info_mux(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
  1531. {
  1532. static char *texts[4] = {
  1533. "Line", "Aux", "Mic", "Mix"
  1534. };
  1535. static char *opl3sa_texts[4] = {
  1536. "Line", "CD", "Mic", "Mix"
  1537. };
  1538. static char *gusmax_texts[4] = {
  1539. "Line", "Synth", "Mic", "Mix"
  1540. };
  1541. char **ptexts = texts;
  1542. cs4231_t *chip = snd_kcontrol_chip(kcontrol);
  1543. snd_assert(chip->card != NULL, return -EINVAL);
  1544. uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
  1545. uinfo->count = 2;
  1546. uinfo->value.enumerated.items = 4;
  1547. if (uinfo->value.enumerated.item > 3)
  1548. uinfo->value.enumerated.item = 3;
  1549. if (!strcmp(chip->card->driver, "GUS MAX"))
  1550. ptexts = gusmax_texts;
  1551. switch (chip->hardware) {
  1552. case CS4231_HW_INTERWAVE: ptexts = gusmax_texts; break;
  1553. case CS4231_HW_OPL3SA2: ptexts = opl3sa_texts; break;
  1554. }
  1555. strcpy(uinfo->value.enumerated.name, ptexts[uinfo->value.enumerated.item]);
  1556. return 0;
  1557. }
  1558. static int snd_cs4231_get_mux(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
  1559. {
  1560. cs4231_t *chip = snd_kcontrol_chip(kcontrol);
  1561. unsigned long flags;
  1562. spin_lock_irqsave(&chip->reg_lock, flags);
  1563. ucontrol->value.enumerated.item[0] = (chip->image[CS4231_LEFT_INPUT] & CS4231_MIXS_ALL) >> 6;
  1564. ucontrol->value.enumerated.item[1] = (chip->image[CS4231_RIGHT_INPUT] & CS4231_MIXS_ALL) >> 6;
  1565. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1566. return 0;
  1567. }
  1568. static int snd_cs4231_put_mux(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
  1569. {
  1570. cs4231_t *chip = snd_kcontrol_chip(kcontrol);
  1571. unsigned long flags;
  1572. unsigned short left, right;
  1573. int change;
  1574. if (ucontrol->value.enumerated.item[0] > 3 ||
  1575. ucontrol->value.enumerated.item[1] > 3)
  1576. return -EINVAL;
  1577. left = ucontrol->value.enumerated.item[0] << 6;
  1578. right = ucontrol->value.enumerated.item[1] << 6;
  1579. spin_lock_irqsave(&chip->reg_lock, flags);
  1580. left = (chip->image[CS4231_LEFT_INPUT] & ~CS4231_MIXS_ALL) | left;
  1581. right = (chip->image[CS4231_RIGHT_INPUT] & ~CS4231_MIXS_ALL) | right;
  1582. change = left != chip->image[CS4231_LEFT_INPUT] ||
  1583. right != chip->image[CS4231_RIGHT_INPUT];
  1584. snd_cs4231_out(chip, CS4231_LEFT_INPUT, left);
  1585. snd_cs4231_out(chip, CS4231_RIGHT_INPUT, right);
  1586. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1587. return change;
  1588. }
  1589. int snd_cs4231_info_single(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
  1590. {
  1591. int mask = (kcontrol->private_value >> 16) & 0xff;
  1592. uinfo->type = mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
  1593. uinfo->count = 1;
  1594. uinfo->value.integer.min = 0;
  1595. uinfo->value.integer.max = mask;
  1596. return 0;
  1597. }
  1598. int snd_cs4231_get_single(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
  1599. {
  1600. cs4231_t *chip = snd_kcontrol_chip(kcontrol);
  1601. unsigned long flags;
  1602. int reg = kcontrol->private_value & 0xff;
  1603. int shift = (kcontrol->private_value >> 8) & 0xff;
  1604. int mask = (kcontrol->private_value >> 16) & 0xff;
  1605. int invert = (kcontrol->private_value >> 24) & 0xff;
  1606. spin_lock_irqsave(&chip->reg_lock, flags);
  1607. ucontrol->value.integer.value[0] = (chip->image[reg] >> shift) & mask;
  1608. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1609. if (invert)
  1610. ucontrol->value.integer.value[0] = mask - ucontrol->value.integer.value[0];
  1611. return 0;
  1612. }
  1613. int snd_cs4231_put_single(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
  1614. {
  1615. cs4231_t *chip = snd_kcontrol_chip(kcontrol);
  1616. unsigned long flags;
  1617. int reg = kcontrol->private_value & 0xff;
  1618. int shift = (kcontrol->private_value >> 8) & 0xff;
  1619. int mask = (kcontrol->private_value >> 16) & 0xff;
  1620. int invert = (kcontrol->private_value >> 24) & 0xff;
  1621. int change;
  1622. unsigned short val;
  1623. val = (ucontrol->value.integer.value[0] & mask);
  1624. if (invert)
  1625. val = mask - val;
  1626. val <<= shift;
  1627. spin_lock_irqsave(&chip->reg_lock, flags);
  1628. val = (chip->image[reg] & ~(mask << shift)) | val;
  1629. change = val != chip->image[reg];
  1630. snd_cs4231_out(chip, reg, val);
  1631. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1632. return change;
  1633. }
  1634. int snd_cs4231_info_double(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
  1635. {
  1636. int mask = (kcontrol->private_value >> 24) & 0xff;
  1637. uinfo->type = mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
  1638. uinfo->count = 2;
  1639. uinfo->value.integer.min = 0;
  1640. uinfo->value.integer.max = mask;
  1641. return 0;
  1642. }
  1643. int snd_cs4231_get_double(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
  1644. {
  1645. cs4231_t *chip = snd_kcontrol_chip(kcontrol);
  1646. unsigned long flags;
  1647. int left_reg = kcontrol->private_value & 0xff;
  1648. int right_reg = (kcontrol->private_value >> 8) & 0xff;
  1649. int shift_left = (kcontrol->private_value >> 16) & 0x07;
  1650. int shift_right = (kcontrol->private_value >> 19) & 0x07;
  1651. int mask = (kcontrol->private_value >> 24) & 0xff;
  1652. int invert = (kcontrol->private_value >> 22) & 1;
  1653. spin_lock_irqsave(&chip->reg_lock, flags);
  1654. ucontrol->value.integer.value[0] = (chip->image[left_reg] >> shift_left) & mask;
  1655. ucontrol->value.integer.value[1] = (chip->image[right_reg] >> shift_right) & mask;
  1656. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1657. if (invert) {
  1658. ucontrol->value.integer.value[0] = mask - ucontrol->value.integer.value[0];
  1659. ucontrol->value.integer.value[1] = mask - ucontrol->value.integer.value[1];
  1660. }
  1661. return 0;
  1662. }
  1663. int snd_cs4231_put_double(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
  1664. {
  1665. cs4231_t *chip = snd_kcontrol_chip(kcontrol);
  1666. unsigned long flags;
  1667. int left_reg = kcontrol->private_value & 0xff;
  1668. int right_reg = (kcontrol->private_value >> 8) & 0xff;
  1669. int shift_left = (kcontrol->private_value >> 16) & 0x07;
  1670. int shift_right = (kcontrol->private_value >> 19) & 0x07;
  1671. int mask = (kcontrol->private_value >> 24) & 0xff;
  1672. int invert = (kcontrol->private_value >> 22) & 1;
  1673. int change;
  1674. unsigned short val1, val2;
  1675. val1 = ucontrol->value.integer.value[0] & mask;
  1676. val2 = ucontrol->value.integer.value[1] & mask;
  1677. if (invert) {
  1678. val1 = mask - val1;
  1679. val2 = mask - val2;
  1680. }
  1681. val1 <<= shift_left;
  1682. val2 <<= shift_right;
  1683. spin_lock_irqsave(&chip->reg_lock, flags);
  1684. val1 = (chip->image[left_reg] & ~(mask << shift_left)) | val1;
  1685. val2 = (chip->image[right_reg] & ~(mask << shift_right)) | val2;
  1686. change = val1 != chip->image[left_reg] || val2 != chip->image[right_reg];
  1687. snd_cs4231_out(chip, left_reg, val1);
  1688. snd_cs4231_out(chip, right_reg, val2);
  1689. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1690. return change;
  1691. }
  1692. static snd_kcontrol_new_t snd_cs4231_controls[] = {
  1693. CS4231_DOUBLE("PCM Playback Switch", 0, CS4231_LEFT_OUTPUT, CS4231_RIGHT_OUTPUT, 7, 7, 1, 1),
  1694. CS4231_DOUBLE("PCM Playback Volume", 0, CS4231_LEFT_OUTPUT, CS4231_RIGHT_OUTPUT, 0, 0, 63, 1),
  1695. CS4231_DOUBLE("Line Playback Switch", 0, CS4231_LEFT_LINE_IN, CS4231_RIGHT_LINE_IN, 7, 7, 1, 1),
  1696. CS4231_DOUBLE("Line Playback Volume", 0, CS4231_LEFT_LINE_IN, CS4231_RIGHT_LINE_IN, 0, 0, 31, 1),
  1697. CS4231_DOUBLE("Aux Playback Switch", 0, CS4231_AUX1_LEFT_INPUT, CS4231_AUX1_RIGHT_INPUT, 7, 7, 1, 1),
  1698. CS4231_DOUBLE("Aux Playback Volume", 0, CS4231_AUX1_LEFT_INPUT, CS4231_AUX1_RIGHT_INPUT, 0, 0, 31, 1),
  1699. CS4231_DOUBLE("Aux Playback Switch", 1, CS4231_AUX2_LEFT_INPUT, CS4231_AUX2_RIGHT_INPUT, 7, 7, 1, 1),
  1700. CS4231_DOUBLE("Aux Playback Volume", 1, CS4231_AUX2_LEFT_INPUT, CS4231_AUX2_RIGHT_INPUT, 0, 0, 31, 1),
  1701. CS4231_SINGLE("Mono Playback Switch", 0, CS4231_MONO_CTRL, 7, 1, 1),
  1702. CS4231_SINGLE("Mono Playback Volume", 0, CS4231_MONO_CTRL, 0, 15, 1),
  1703. CS4231_SINGLE("Mono Output Playback Switch", 0, CS4231_MONO_CTRL, 6, 1, 1),
  1704. CS4231_SINGLE("Mono Output Playback Bypass", 0, CS4231_MONO_CTRL, 5, 1, 0),
  1705. CS4231_DOUBLE("Capture Volume", 0, CS4231_LEFT_INPUT, CS4231_RIGHT_INPUT, 0, 0, 15, 0),
  1706. {
  1707. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1708. .name = "Capture Source",
  1709. .info = snd_cs4231_info_mux,
  1710. .get = snd_cs4231_get_mux,
  1711. .put = snd_cs4231_put_mux,
  1712. },
  1713. CS4231_DOUBLE("Mic Boost", 0, CS4231_LEFT_INPUT, CS4231_RIGHT_INPUT, 5, 5, 1, 0),
  1714. CS4231_SINGLE("Loopback Capture Switch", 0, CS4231_LOOPBACK, 0, 1, 0),
  1715. CS4231_SINGLE("Loopback Capture Volume", 0, CS4231_LOOPBACK, 2, 63, 1)
  1716. };
  1717. int snd_cs4231_mixer(cs4231_t *chip)
  1718. {
  1719. snd_card_t *card;
  1720. unsigned int idx;
  1721. int err;
  1722. snd_assert(chip != NULL && chip->pcm != NULL, return -EINVAL);
  1723. card = chip->card;
  1724. strcpy(card->mixername, chip->pcm->name);
  1725. for (idx = 0; idx < ARRAY_SIZE(snd_cs4231_controls); idx++) {
  1726. if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_cs4231_controls[idx], chip))) < 0)
  1727. return err;
  1728. }
  1729. return 0;
  1730. }
  1731. EXPORT_SYMBOL(snd_cs4231_out);
  1732. EXPORT_SYMBOL(snd_cs4231_in);
  1733. EXPORT_SYMBOL(snd_cs4236_ext_out);
  1734. EXPORT_SYMBOL(snd_cs4236_ext_in);
  1735. EXPORT_SYMBOL(snd_cs4231_mce_up);
  1736. EXPORT_SYMBOL(snd_cs4231_mce_down);
  1737. EXPORT_SYMBOL(snd_cs4231_interrupt);
  1738. EXPORT_SYMBOL(snd_cs4231_chip_id);
  1739. EXPORT_SYMBOL(snd_cs4231_create);
  1740. EXPORT_SYMBOL(snd_cs4231_pcm);
  1741. EXPORT_SYMBOL(snd_cs4231_mixer);
  1742. EXPORT_SYMBOL(snd_cs4231_timer);
  1743. EXPORT_SYMBOL(snd_cs4231_info_single);
  1744. EXPORT_SYMBOL(snd_cs4231_get_single);
  1745. EXPORT_SYMBOL(snd_cs4231_put_single);
  1746. EXPORT_SYMBOL(snd_cs4231_info_double);
  1747. EXPORT_SYMBOL(snd_cs4231_get_double);
  1748. EXPORT_SYMBOL(snd_cs4231_put_double);
  1749. /*
  1750. * INIT part
  1751. */
  1752. static int __init alsa_cs4231_init(void)
  1753. {
  1754. return 0;
  1755. }
  1756. static void __exit alsa_cs4231_exit(void)
  1757. {
  1758. }
  1759. module_init(alsa_cs4231_init)
  1760. module_exit(alsa_cs4231_exit)