bnx2x_ethtool.c 72 KB

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  1. /* bnx2x_ethtool.c: Broadcom Everest network driver.
  2. *
  3. * Copyright (c) 2007-2012 Broadcom Corporation
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License as published by
  7. * the Free Software Foundation.
  8. *
  9. * Maintained by: Eilon Greenstein <eilong@broadcom.com>
  10. * Written by: Eliezer Tamir
  11. * Based on code from Michael Chan's bnx2 driver
  12. * UDP CSUM errata workaround by Arik Gendelman
  13. * Slowpath and fastpath rework by Vladislav Zolotarov
  14. * Statistics and Link management by Yitchak Gertner
  15. *
  16. */
  17. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  18. #include <linux/ethtool.h>
  19. #include <linux/netdevice.h>
  20. #include <linux/types.h>
  21. #include <linux/sched.h>
  22. #include <linux/crc32.h>
  23. #include "bnx2x.h"
  24. #include "bnx2x_cmn.h"
  25. #include "bnx2x_dump.h"
  26. #include "bnx2x_init.h"
  27. /* Note: in the format strings below %s is replaced by the queue-name which is
  28. * either its index or 'fcoe' for the fcoe queue. Make sure the format string
  29. * length does not exceed ETH_GSTRING_LEN - MAX_QUEUE_NAME_LEN + 2
  30. */
  31. #define MAX_QUEUE_NAME_LEN 4
  32. static const struct {
  33. long offset;
  34. int size;
  35. char string[ETH_GSTRING_LEN];
  36. } bnx2x_q_stats_arr[] = {
  37. /* 1 */ { Q_STATS_OFFSET32(total_bytes_received_hi), 8, "[%s]: rx_bytes" },
  38. { Q_STATS_OFFSET32(total_unicast_packets_received_hi),
  39. 8, "[%s]: rx_ucast_packets" },
  40. { Q_STATS_OFFSET32(total_multicast_packets_received_hi),
  41. 8, "[%s]: rx_mcast_packets" },
  42. { Q_STATS_OFFSET32(total_broadcast_packets_received_hi),
  43. 8, "[%s]: rx_bcast_packets" },
  44. { Q_STATS_OFFSET32(no_buff_discard_hi), 8, "[%s]: rx_discards" },
  45. { Q_STATS_OFFSET32(rx_err_discard_pkt),
  46. 4, "[%s]: rx_phy_ip_err_discards"},
  47. { Q_STATS_OFFSET32(rx_skb_alloc_failed),
  48. 4, "[%s]: rx_skb_alloc_discard" },
  49. { Q_STATS_OFFSET32(hw_csum_err), 4, "[%s]: rx_csum_offload_errors" },
  50. { Q_STATS_OFFSET32(total_bytes_transmitted_hi), 8, "[%s]: tx_bytes" },
  51. /* 10 */{ Q_STATS_OFFSET32(total_unicast_packets_transmitted_hi),
  52. 8, "[%s]: tx_ucast_packets" },
  53. { Q_STATS_OFFSET32(total_multicast_packets_transmitted_hi),
  54. 8, "[%s]: tx_mcast_packets" },
  55. { Q_STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
  56. 8, "[%s]: tx_bcast_packets" },
  57. { Q_STATS_OFFSET32(total_tpa_aggregations_hi),
  58. 8, "[%s]: tpa_aggregations" },
  59. { Q_STATS_OFFSET32(total_tpa_aggregated_frames_hi),
  60. 8, "[%s]: tpa_aggregated_frames"},
  61. { Q_STATS_OFFSET32(total_tpa_bytes_hi), 8, "[%s]: tpa_bytes"}
  62. };
  63. #define BNX2X_NUM_Q_STATS ARRAY_SIZE(bnx2x_q_stats_arr)
  64. static const struct {
  65. long offset;
  66. int size;
  67. u32 flags;
  68. #define STATS_FLAGS_PORT 1
  69. #define STATS_FLAGS_FUNC 2
  70. #define STATS_FLAGS_BOTH (STATS_FLAGS_FUNC | STATS_FLAGS_PORT)
  71. char string[ETH_GSTRING_LEN];
  72. } bnx2x_stats_arr[] = {
  73. /* 1 */ { STATS_OFFSET32(total_bytes_received_hi),
  74. 8, STATS_FLAGS_BOTH, "rx_bytes" },
  75. { STATS_OFFSET32(error_bytes_received_hi),
  76. 8, STATS_FLAGS_BOTH, "rx_error_bytes" },
  77. { STATS_OFFSET32(total_unicast_packets_received_hi),
  78. 8, STATS_FLAGS_BOTH, "rx_ucast_packets" },
  79. { STATS_OFFSET32(total_multicast_packets_received_hi),
  80. 8, STATS_FLAGS_BOTH, "rx_mcast_packets" },
  81. { STATS_OFFSET32(total_broadcast_packets_received_hi),
  82. 8, STATS_FLAGS_BOTH, "rx_bcast_packets" },
  83. { STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi),
  84. 8, STATS_FLAGS_PORT, "rx_crc_errors" },
  85. { STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi),
  86. 8, STATS_FLAGS_PORT, "rx_align_errors" },
  87. { STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi),
  88. 8, STATS_FLAGS_PORT, "rx_undersize_packets" },
  89. { STATS_OFFSET32(etherstatsoverrsizepkts_hi),
  90. 8, STATS_FLAGS_PORT, "rx_oversize_packets" },
  91. /* 10 */{ STATS_OFFSET32(rx_stat_etherstatsfragments_hi),
  92. 8, STATS_FLAGS_PORT, "rx_fragments" },
  93. { STATS_OFFSET32(rx_stat_etherstatsjabbers_hi),
  94. 8, STATS_FLAGS_PORT, "rx_jabbers" },
  95. { STATS_OFFSET32(no_buff_discard_hi),
  96. 8, STATS_FLAGS_BOTH, "rx_discards" },
  97. { STATS_OFFSET32(mac_filter_discard),
  98. 4, STATS_FLAGS_PORT, "rx_filtered_packets" },
  99. { STATS_OFFSET32(mf_tag_discard),
  100. 4, STATS_FLAGS_PORT, "rx_mf_tag_discard" },
  101. { STATS_OFFSET32(pfc_frames_received_hi),
  102. 8, STATS_FLAGS_PORT, "pfc_frames_received" },
  103. { STATS_OFFSET32(pfc_frames_sent_hi),
  104. 8, STATS_FLAGS_PORT, "pfc_frames_sent" },
  105. { STATS_OFFSET32(brb_drop_hi),
  106. 8, STATS_FLAGS_PORT, "rx_brb_discard" },
  107. { STATS_OFFSET32(brb_truncate_hi),
  108. 8, STATS_FLAGS_PORT, "rx_brb_truncate" },
  109. { STATS_OFFSET32(pause_frames_received_hi),
  110. 8, STATS_FLAGS_PORT, "rx_pause_frames" },
  111. { STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi),
  112. 8, STATS_FLAGS_PORT, "rx_mac_ctrl_frames" },
  113. { STATS_OFFSET32(nig_timer_max),
  114. 4, STATS_FLAGS_PORT, "rx_constant_pause_events" },
  115. /* 20 */{ STATS_OFFSET32(rx_err_discard_pkt),
  116. 4, STATS_FLAGS_BOTH, "rx_phy_ip_err_discards"},
  117. { STATS_OFFSET32(rx_skb_alloc_failed),
  118. 4, STATS_FLAGS_BOTH, "rx_skb_alloc_discard" },
  119. { STATS_OFFSET32(hw_csum_err),
  120. 4, STATS_FLAGS_BOTH, "rx_csum_offload_errors" },
  121. { STATS_OFFSET32(total_bytes_transmitted_hi),
  122. 8, STATS_FLAGS_BOTH, "tx_bytes" },
  123. { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi),
  124. 8, STATS_FLAGS_PORT, "tx_error_bytes" },
  125. { STATS_OFFSET32(total_unicast_packets_transmitted_hi),
  126. 8, STATS_FLAGS_BOTH, "tx_ucast_packets" },
  127. { STATS_OFFSET32(total_multicast_packets_transmitted_hi),
  128. 8, STATS_FLAGS_BOTH, "tx_mcast_packets" },
  129. { STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
  130. 8, STATS_FLAGS_BOTH, "tx_bcast_packets" },
  131. { STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi),
  132. 8, STATS_FLAGS_PORT, "tx_mac_errors" },
  133. { STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi),
  134. 8, STATS_FLAGS_PORT, "tx_carrier_errors" },
  135. /* 30 */{ STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi),
  136. 8, STATS_FLAGS_PORT, "tx_single_collisions" },
  137. { STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi),
  138. 8, STATS_FLAGS_PORT, "tx_multi_collisions" },
  139. { STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi),
  140. 8, STATS_FLAGS_PORT, "tx_deferred" },
  141. { STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi),
  142. 8, STATS_FLAGS_PORT, "tx_excess_collisions" },
  143. { STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi),
  144. 8, STATS_FLAGS_PORT, "tx_late_collisions" },
  145. { STATS_OFFSET32(tx_stat_etherstatscollisions_hi),
  146. 8, STATS_FLAGS_PORT, "tx_total_collisions" },
  147. { STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi),
  148. 8, STATS_FLAGS_PORT, "tx_64_byte_packets" },
  149. { STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi),
  150. 8, STATS_FLAGS_PORT, "tx_65_to_127_byte_packets" },
  151. { STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi),
  152. 8, STATS_FLAGS_PORT, "tx_128_to_255_byte_packets" },
  153. { STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi),
  154. 8, STATS_FLAGS_PORT, "tx_256_to_511_byte_packets" },
  155. /* 40 */{ STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi),
  156. 8, STATS_FLAGS_PORT, "tx_512_to_1023_byte_packets" },
  157. { STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi),
  158. 8, STATS_FLAGS_PORT, "tx_1024_to_1522_byte_packets" },
  159. { STATS_OFFSET32(etherstatspktsover1522octets_hi),
  160. 8, STATS_FLAGS_PORT, "tx_1523_to_9022_byte_packets" },
  161. { STATS_OFFSET32(pause_frames_sent_hi),
  162. 8, STATS_FLAGS_PORT, "tx_pause_frames" },
  163. { STATS_OFFSET32(total_tpa_aggregations_hi),
  164. 8, STATS_FLAGS_FUNC, "tpa_aggregations" },
  165. { STATS_OFFSET32(total_tpa_aggregated_frames_hi),
  166. 8, STATS_FLAGS_FUNC, "tpa_aggregated_frames"},
  167. { STATS_OFFSET32(total_tpa_bytes_hi),
  168. 8, STATS_FLAGS_FUNC, "tpa_bytes"},
  169. { STATS_OFFSET32(recoverable_error),
  170. 4, STATS_FLAGS_FUNC, "recoverable_errors" },
  171. { STATS_OFFSET32(unrecoverable_error),
  172. 4, STATS_FLAGS_FUNC, "unrecoverable_errors" },
  173. { STATS_OFFSET32(eee_tx_lpi),
  174. 4, STATS_FLAGS_PORT, "Tx LPI entry count"}
  175. };
  176. #define BNX2X_NUM_STATS ARRAY_SIZE(bnx2x_stats_arr)
  177. static int bnx2x_get_port_type(struct bnx2x *bp)
  178. {
  179. int port_type;
  180. u32 phy_idx = bnx2x_get_cur_phy_idx(bp);
  181. switch (bp->link_params.phy[phy_idx].media_type) {
  182. case ETH_PHY_SFP_FIBER:
  183. case ETH_PHY_XFP_FIBER:
  184. case ETH_PHY_KR:
  185. case ETH_PHY_CX4:
  186. port_type = PORT_FIBRE;
  187. break;
  188. case ETH_PHY_DA_TWINAX:
  189. port_type = PORT_DA;
  190. break;
  191. case ETH_PHY_BASE_T:
  192. port_type = PORT_TP;
  193. break;
  194. case ETH_PHY_NOT_PRESENT:
  195. port_type = PORT_NONE;
  196. break;
  197. case ETH_PHY_UNSPECIFIED:
  198. default:
  199. port_type = PORT_OTHER;
  200. break;
  201. }
  202. return port_type;
  203. }
  204. static int bnx2x_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  205. {
  206. struct bnx2x *bp = netdev_priv(dev);
  207. int cfg_idx = bnx2x_get_link_cfg_idx(bp);
  208. /* Dual Media boards present all available port types */
  209. cmd->supported = bp->port.supported[cfg_idx] |
  210. (bp->port.supported[cfg_idx ^ 1] &
  211. (SUPPORTED_TP | SUPPORTED_FIBRE));
  212. cmd->advertising = bp->port.advertising[cfg_idx];
  213. if ((bp->state == BNX2X_STATE_OPEN) && (bp->link_vars.link_up)) {
  214. if (!(bp->flags & MF_FUNC_DIS)) {
  215. ethtool_cmd_speed_set(cmd, bp->link_vars.line_speed);
  216. cmd->duplex = bp->link_vars.duplex;
  217. } else {
  218. ethtool_cmd_speed_set(
  219. cmd, bp->link_params.req_line_speed[cfg_idx]);
  220. cmd->duplex = bp->link_params.req_duplex[cfg_idx];
  221. }
  222. if (IS_MF(bp) && !BP_NOMCP(bp))
  223. ethtool_cmd_speed_set(cmd, bnx2x_get_mf_speed(bp));
  224. } else {
  225. cmd->duplex = DUPLEX_UNKNOWN;
  226. ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN);
  227. }
  228. cmd->port = bnx2x_get_port_type(bp);
  229. cmd->phy_address = bp->mdio.prtad;
  230. cmd->transceiver = XCVR_INTERNAL;
  231. if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG)
  232. cmd->autoneg = AUTONEG_ENABLE;
  233. else
  234. cmd->autoneg = AUTONEG_DISABLE;
  235. /* Publish LP advertised speeds and FC */
  236. if (bp->link_vars.link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
  237. u32 status = bp->link_vars.link_status;
  238. cmd->lp_advertising |= ADVERTISED_Autoneg;
  239. if (status & LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE)
  240. cmd->lp_advertising |= ADVERTISED_Pause;
  241. if (status & LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE)
  242. cmd->lp_advertising |= ADVERTISED_Asym_Pause;
  243. if (status & LINK_STATUS_LINK_PARTNER_10THD_CAPABLE)
  244. cmd->lp_advertising |= ADVERTISED_10baseT_Half;
  245. if (status & LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE)
  246. cmd->lp_advertising |= ADVERTISED_10baseT_Full;
  247. if (status & LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE)
  248. cmd->lp_advertising |= ADVERTISED_100baseT_Half;
  249. if (status & LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE)
  250. cmd->lp_advertising |= ADVERTISED_100baseT_Full;
  251. if (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE)
  252. cmd->lp_advertising |= ADVERTISED_1000baseT_Half;
  253. if (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE)
  254. cmd->lp_advertising |= ADVERTISED_1000baseT_Full;
  255. if (status & LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE)
  256. cmd->lp_advertising |= ADVERTISED_2500baseX_Full;
  257. if (status & LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE)
  258. cmd->lp_advertising |= ADVERTISED_10000baseT_Full;
  259. }
  260. cmd->maxtxpkt = 0;
  261. cmd->maxrxpkt = 0;
  262. DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n"
  263. " supported 0x%x advertising 0x%x speed %u\n"
  264. " duplex %d port %d phy_address %d transceiver %d\n"
  265. " autoneg %d maxtxpkt %d maxrxpkt %d\n",
  266. cmd->cmd, cmd->supported, cmd->advertising,
  267. ethtool_cmd_speed(cmd),
  268. cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
  269. cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
  270. return 0;
  271. }
  272. static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  273. {
  274. struct bnx2x *bp = netdev_priv(dev);
  275. u32 advertising, cfg_idx, old_multi_phy_config, new_multi_phy_config;
  276. u32 speed;
  277. if (IS_MF_SD(bp))
  278. return 0;
  279. DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n"
  280. " supported 0x%x advertising 0x%x speed %u\n"
  281. " duplex %d port %d phy_address %d transceiver %d\n"
  282. " autoneg %d maxtxpkt %d maxrxpkt %d\n",
  283. cmd->cmd, cmd->supported, cmd->advertising,
  284. ethtool_cmd_speed(cmd),
  285. cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
  286. cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
  287. speed = ethtool_cmd_speed(cmd);
  288. /* If recieved a request for an unknown duplex, assume full*/
  289. if (cmd->duplex == DUPLEX_UNKNOWN)
  290. cmd->duplex = DUPLEX_FULL;
  291. if (IS_MF_SI(bp)) {
  292. u32 part;
  293. u32 line_speed = bp->link_vars.line_speed;
  294. /* use 10G if no link detected */
  295. if (!line_speed)
  296. line_speed = 10000;
  297. if (bp->common.bc_ver < REQ_BC_VER_4_SET_MF_BW) {
  298. DP(BNX2X_MSG_ETHTOOL,
  299. "To set speed BC %X or higher is required, please upgrade BC\n",
  300. REQ_BC_VER_4_SET_MF_BW);
  301. return -EINVAL;
  302. }
  303. part = (speed * 100) / line_speed;
  304. if (line_speed < speed || !part) {
  305. DP(BNX2X_MSG_ETHTOOL,
  306. "Speed setting should be in a range from 1%% to 100%% of actual line speed\n");
  307. return -EINVAL;
  308. }
  309. if (bp->state != BNX2X_STATE_OPEN)
  310. /* store value for following "load" */
  311. bp->pending_max = part;
  312. else
  313. bnx2x_update_max_mf_config(bp, part);
  314. return 0;
  315. }
  316. cfg_idx = bnx2x_get_link_cfg_idx(bp);
  317. old_multi_phy_config = bp->link_params.multi_phy_config;
  318. switch (cmd->port) {
  319. case PORT_TP:
  320. if (bp->port.supported[cfg_idx] & SUPPORTED_TP)
  321. break; /* no port change */
  322. if (!(bp->port.supported[0] & SUPPORTED_TP ||
  323. bp->port.supported[1] & SUPPORTED_TP)) {
  324. DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n");
  325. return -EINVAL;
  326. }
  327. bp->link_params.multi_phy_config &=
  328. ~PORT_HW_CFG_PHY_SELECTION_MASK;
  329. if (bp->link_params.multi_phy_config &
  330. PORT_HW_CFG_PHY_SWAPPED_ENABLED)
  331. bp->link_params.multi_phy_config |=
  332. PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
  333. else
  334. bp->link_params.multi_phy_config |=
  335. PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
  336. break;
  337. case PORT_FIBRE:
  338. case PORT_DA:
  339. if (bp->port.supported[cfg_idx] & SUPPORTED_FIBRE)
  340. break; /* no port change */
  341. if (!(bp->port.supported[0] & SUPPORTED_FIBRE ||
  342. bp->port.supported[1] & SUPPORTED_FIBRE)) {
  343. DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n");
  344. return -EINVAL;
  345. }
  346. bp->link_params.multi_phy_config &=
  347. ~PORT_HW_CFG_PHY_SELECTION_MASK;
  348. if (bp->link_params.multi_phy_config &
  349. PORT_HW_CFG_PHY_SWAPPED_ENABLED)
  350. bp->link_params.multi_phy_config |=
  351. PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
  352. else
  353. bp->link_params.multi_phy_config |=
  354. PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
  355. break;
  356. default:
  357. DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n");
  358. return -EINVAL;
  359. }
  360. /* Save new config in case command complete successully */
  361. new_multi_phy_config = bp->link_params.multi_phy_config;
  362. /* Get the new cfg_idx */
  363. cfg_idx = bnx2x_get_link_cfg_idx(bp);
  364. /* Restore old config in case command failed */
  365. bp->link_params.multi_phy_config = old_multi_phy_config;
  366. DP(BNX2X_MSG_ETHTOOL, "cfg_idx = %x\n", cfg_idx);
  367. if (cmd->autoneg == AUTONEG_ENABLE) {
  368. u32 an_supported_speed = bp->port.supported[cfg_idx];
  369. if (bp->link_params.phy[EXT_PHY1].type ==
  370. PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
  371. an_supported_speed |= (SUPPORTED_100baseT_Half |
  372. SUPPORTED_100baseT_Full);
  373. if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
  374. DP(BNX2X_MSG_ETHTOOL, "Autoneg not supported\n");
  375. return -EINVAL;
  376. }
  377. /* advertise the requested speed and duplex if supported */
  378. if (cmd->advertising & ~an_supported_speed) {
  379. DP(BNX2X_MSG_ETHTOOL,
  380. "Advertisement parameters are not supported\n");
  381. return -EINVAL;
  382. }
  383. bp->link_params.req_line_speed[cfg_idx] = SPEED_AUTO_NEG;
  384. bp->link_params.req_duplex[cfg_idx] = cmd->duplex;
  385. bp->port.advertising[cfg_idx] = (ADVERTISED_Autoneg |
  386. cmd->advertising);
  387. if (cmd->advertising) {
  388. bp->link_params.speed_cap_mask[cfg_idx] = 0;
  389. if (cmd->advertising & ADVERTISED_10baseT_Half) {
  390. bp->link_params.speed_cap_mask[cfg_idx] |=
  391. PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF;
  392. }
  393. if (cmd->advertising & ADVERTISED_10baseT_Full)
  394. bp->link_params.speed_cap_mask[cfg_idx] |=
  395. PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL;
  396. if (cmd->advertising & ADVERTISED_100baseT_Full)
  397. bp->link_params.speed_cap_mask[cfg_idx] |=
  398. PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL;
  399. if (cmd->advertising & ADVERTISED_100baseT_Half) {
  400. bp->link_params.speed_cap_mask[cfg_idx] |=
  401. PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF;
  402. }
  403. if (cmd->advertising & ADVERTISED_1000baseT_Half) {
  404. bp->link_params.speed_cap_mask[cfg_idx] |=
  405. PORT_HW_CFG_SPEED_CAPABILITY_D0_1G;
  406. }
  407. if (cmd->advertising & (ADVERTISED_1000baseT_Full |
  408. ADVERTISED_1000baseKX_Full))
  409. bp->link_params.speed_cap_mask[cfg_idx] |=
  410. PORT_HW_CFG_SPEED_CAPABILITY_D0_1G;
  411. if (cmd->advertising & (ADVERTISED_10000baseT_Full |
  412. ADVERTISED_10000baseKX4_Full |
  413. ADVERTISED_10000baseKR_Full))
  414. bp->link_params.speed_cap_mask[cfg_idx] |=
  415. PORT_HW_CFG_SPEED_CAPABILITY_D0_10G;
  416. }
  417. } else { /* forced speed */
  418. /* advertise the requested speed and duplex if supported */
  419. switch (speed) {
  420. case SPEED_10:
  421. if (cmd->duplex == DUPLEX_FULL) {
  422. if (!(bp->port.supported[cfg_idx] &
  423. SUPPORTED_10baseT_Full)) {
  424. DP(BNX2X_MSG_ETHTOOL,
  425. "10M full not supported\n");
  426. return -EINVAL;
  427. }
  428. advertising = (ADVERTISED_10baseT_Full |
  429. ADVERTISED_TP);
  430. } else {
  431. if (!(bp->port.supported[cfg_idx] &
  432. SUPPORTED_10baseT_Half)) {
  433. DP(BNX2X_MSG_ETHTOOL,
  434. "10M half not supported\n");
  435. return -EINVAL;
  436. }
  437. advertising = (ADVERTISED_10baseT_Half |
  438. ADVERTISED_TP);
  439. }
  440. break;
  441. case SPEED_100:
  442. if (cmd->duplex == DUPLEX_FULL) {
  443. if (!(bp->port.supported[cfg_idx] &
  444. SUPPORTED_100baseT_Full)) {
  445. DP(BNX2X_MSG_ETHTOOL,
  446. "100M full not supported\n");
  447. return -EINVAL;
  448. }
  449. advertising = (ADVERTISED_100baseT_Full |
  450. ADVERTISED_TP);
  451. } else {
  452. if (!(bp->port.supported[cfg_idx] &
  453. SUPPORTED_100baseT_Half)) {
  454. DP(BNX2X_MSG_ETHTOOL,
  455. "100M half not supported\n");
  456. return -EINVAL;
  457. }
  458. advertising = (ADVERTISED_100baseT_Half |
  459. ADVERTISED_TP);
  460. }
  461. break;
  462. case SPEED_1000:
  463. if (cmd->duplex != DUPLEX_FULL) {
  464. DP(BNX2X_MSG_ETHTOOL,
  465. "1G half not supported\n");
  466. return -EINVAL;
  467. }
  468. if (!(bp->port.supported[cfg_idx] &
  469. SUPPORTED_1000baseT_Full)) {
  470. DP(BNX2X_MSG_ETHTOOL,
  471. "1G full not supported\n");
  472. return -EINVAL;
  473. }
  474. advertising = (ADVERTISED_1000baseT_Full |
  475. ADVERTISED_TP);
  476. break;
  477. case SPEED_2500:
  478. if (cmd->duplex != DUPLEX_FULL) {
  479. DP(BNX2X_MSG_ETHTOOL,
  480. "2.5G half not supported\n");
  481. return -EINVAL;
  482. }
  483. if (!(bp->port.supported[cfg_idx]
  484. & SUPPORTED_2500baseX_Full)) {
  485. DP(BNX2X_MSG_ETHTOOL,
  486. "2.5G full not supported\n");
  487. return -EINVAL;
  488. }
  489. advertising = (ADVERTISED_2500baseX_Full |
  490. ADVERTISED_TP);
  491. break;
  492. case SPEED_10000:
  493. if (cmd->duplex != DUPLEX_FULL) {
  494. DP(BNX2X_MSG_ETHTOOL,
  495. "10G half not supported\n");
  496. return -EINVAL;
  497. }
  498. if (!(bp->port.supported[cfg_idx]
  499. & SUPPORTED_10000baseT_Full)) {
  500. DP(BNX2X_MSG_ETHTOOL,
  501. "10G full not supported\n");
  502. return -EINVAL;
  503. }
  504. advertising = (ADVERTISED_10000baseT_Full |
  505. ADVERTISED_FIBRE);
  506. break;
  507. default:
  508. DP(BNX2X_MSG_ETHTOOL, "Unsupported speed %u\n", speed);
  509. return -EINVAL;
  510. }
  511. bp->link_params.req_line_speed[cfg_idx] = speed;
  512. bp->link_params.req_duplex[cfg_idx] = cmd->duplex;
  513. bp->port.advertising[cfg_idx] = advertising;
  514. }
  515. DP(BNX2X_MSG_ETHTOOL, "req_line_speed %d\n"
  516. " req_duplex %d advertising 0x%x\n",
  517. bp->link_params.req_line_speed[cfg_idx],
  518. bp->link_params.req_duplex[cfg_idx],
  519. bp->port.advertising[cfg_idx]);
  520. /* Set new config */
  521. bp->link_params.multi_phy_config = new_multi_phy_config;
  522. if (netif_running(dev)) {
  523. bnx2x_stats_handle(bp, STATS_EVENT_STOP);
  524. bnx2x_link_set(bp);
  525. }
  526. return 0;
  527. }
  528. #define IS_E1_ONLINE(info) (((info) & RI_E1_ONLINE) == RI_E1_ONLINE)
  529. #define IS_E1H_ONLINE(info) (((info) & RI_E1H_ONLINE) == RI_E1H_ONLINE)
  530. #define IS_E2_ONLINE(info) (((info) & RI_E2_ONLINE) == RI_E2_ONLINE)
  531. #define IS_E3_ONLINE(info) (((info) & RI_E3_ONLINE) == RI_E3_ONLINE)
  532. #define IS_E3B0_ONLINE(info) (((info) & RI_E3B0_ONLINE) == RI_E3B0_ONLINE)
  533. static bool bnx2x_is_reg_online(struct bnx2x *bp,
  534. const struct reg_addr *reg_info)
  535. {
  536. if (CHIP_IS_E1(bp))
  537. return IS_E1_ONLINE(reg_info->info);
  538. else if (CHIP_IS_E1H(bp))
  539. return IS_E1H_ONLINE(reg_info->info);
  540. else if (CHIP_IS_E2(bp))
  541. return IS_E2_ONLINE(reg_info->info);
  542. else if (CHIP_IS_E3A0(bp))
  543. return IS_E3_ONLINE(reg_info->info);
  544. else if (CHIP_IS_E3B0(bp))
  545. return IS_E3B0_ONLINE(reg_info->info);
  546. else
  547. return false;
  548. }
  549. /******* Paged registers info selectors ********/
  550. static const u32 *__bnx2x_get_page_addr_ar(struct bnx2x *bp)
  551. {
  552. if (CHIP_IS_E2(bp))
  553. return page_vals_e2;
  554. else if (CHIP_IS_E3(bp))
  555. return page_vals_e3;
  556. else
  557. return NULL;
  558. }
  559. static u32 __bnx2x_get_page_reg_num(struct bnx2x *bp)
  560. {
  561. if (CHIP_IS_E2(bp))
  562. return PAGE_MODE_VALUES_E2;
  563. else if (CHIP_IS_E3(bp))
  564. return PAGE_MODE_VALUES_E3;
  565. else
  566. return 0;
  567. }
  568. static const u32 *__bnx2x_get_page_write_ar(struct bnx2x *bp)
  569. {
  570. if (CHIP_IS_E2(bp))
  571. return page_write_regs_e2;
  572. else if (CHIP_IS_E3(bp))
  573. return page_write_regs_e3;
  574. else
  575. return NULL;
  576. }
  577. static u32 __bnx2x_get_page_write_num(struct bnx2x *bp)
  578. {
  579. if (CHIP_IS_E2(bp))
  580. return PAGE_WRITE_REGS_E2;
  581. else if (CHIP_IS_E3(bp))
  582. return PAGE_WRITE_REGS_E3;
  583. else
  584. return 0;
  585. }
  586. static const struct reg_addr *__bnx2x_get_page_read_ar(struct bnx2x *bp)
  587. {
  588. if (CHIP_IS_E2(bp))
  589. return page_read_regs_e2;
  590. else if (CHIP_IS_E3(bp))
  591. return page_read_regs_e3;
  592. else
  593. return NULL;
  594. }
  595. static u32 __bnx2x_get_page_read_num(struct bnx2x *bp)
  596. {
  597. if (CHIP_IS_E2(bp))
  598. return PAGE_READ_REGS_E2;
  599. else if (CHIP_IS_E3(bp))
  600. return PAGE_READ_REGS_E3;
  601. else
  602. return 0;
  603. }
  604. static int __bnx2x_get_regs_len(struct bnx2x *bp)
  605. {
  606. int num_pages = __bnx2x_get_page_reg_num(bp);
  607. int page_write_num = __bnx2x_get_page_write_num(bp);
  608. const struct reg_addr *page_read_addr = __bnx2x_get_page_read_ar(bp);
  609. int page_read_num = __bnx2x_get_page_read_num(bp);
  610. int regdump_len = 0;
  611. int i, j, k;
  612. for (i = 0; i < REGS_COUNT; i++)
  613. if (bnx2x_is_reg_online(bp, &reg_addrs[i]))
  614. regdump_len += reg_addrs[i].size;
  615. for (i = 0; i < num_pages; i++)
  616. for (j = 0; j < page_write_num; j++)
  617. for (k = 0; k < page_read_num; k++)
  618. if (bnx2x_is_reg_online(bp, &page_read_addr[k]))
  619. regdump_len += page_read_addr[k].size;
  620. return regdump_len;
  621. }
  622. static int bnx2x_get_regs_len(struct net_device *dev)
  623. {
  624. struct bnx2x *bp = netdev_priv(dev);
  625. int regdump_len = 0;
  626. regdump_len = __bnx2x_get_regs_len(bp);
  627. regdump_len *= 4;
  628. regdump_len += sizeof(struct dump_hdr);
  629. return regdump_len;
  630. }
  631. /**
  632. * bnx2x_read_pages_regs - read "paged" registers
  633. *
  634. * @bp device handle
  635. * @p output buffer
  636. *
  637. * Reads "paged" memories: memories that may only be read by first writing to a
  638. * specific address ("write address") and then reading from a specific address
  639. * ("read address"). There may be more than one write address per "page" and
  640. * more than one read address per write address.
  641. */
  642. static void bnx2x_read_pages_regs(struct bnx2x *bp, u32 *p)
  643. {
  644. u32 i, j, k, n;
  645. /* addresses of the paged registers */
  646. const u32 *page_addr = __bnx2x_get_page_addr_ar(bp);
  647. /* number of paged registers */
  648. int num_pages = __bnx2x_get_page_reg_num(bp);
  649. /* write addresses */
  650. const u32 *write_addr = __bnx2x_get_page_write_ar(bp);
  651. /* number of write addresses */
  652. int write_num = __bnx2x_get_page_write_num(bp);
  653. /* read addresses info */
  654. const struct reg_addr *read_addr = __bnx2x_get_page_read_ar(bp);
  655. /* number of read addresses */
  656. int read_num = __bnx2x_get_page_read_num(bp);
  657. for (i = 0; i < num_pages; i++) {
  658. for (j = 0; j < write_num; j++) {
  659. REG_WR(bp, write_addr[j], page_addr[i]);
  660. for (k = 0; k < read_num; k++)
  661. if (bnx2x_is_reg_online(bp, &read_addr[k]))
  662. for (n = 0; n <
  663. read_addr[k].size; n++)
  664. *p++ = REG_RD(bp,
  665. read_addr[k].addr + n*4);
  666. }
  667. }
  668. }
  669. static void __bnx2x_get_regs(struct bnx2x *bp, u32 *p)
  670. {
  671. u32 i, j;
  672. /* Read the regular registers */
  673. for (i = 0; i < REGS_COUNT; i++)
  674. if (bnx2x_is_reg_online(bp, &reg_addrs[i]))
  675. for (j = 0; j < reg_addrs[i].size; j++)
  676. *p++ = REG_RD(bp, reg_addrs[i].addr + j*4);
  677. /* Read "paged" registes */
  678. bnx2x_read_pages_regs(bp, p);
  679. }
  680. static void bnx2x_get_regs(struct net_device *dev,
  681. struct ethtool_regs *regs, void *_p)
  682. {
  683. u32 *p = _p;
  684. struct bnx2x *bp = netdev_priv(dev);
  685. struct dump_hdr dump_hdr = {0};
  686. regs->version = 0;
  687. memset(p, 0, regs->len);
  688. if (!netif_running(bp->dev))
  689. return;
  690. /* Disable parity attentions as long as following dump may
  691. * cause false alarms by reading never written registers. We
  692. * will re-enable parity attentions right after the dump.
  693. */
  694. bnx2x_disable_blocks_parity(bp);
  695. dump_hdr.hdr_size = (sizeof(struct dump_hdr) / 4) - 1;
  696. dump_hdr.dump_sign = dump_sign_all;
  697. dump_hdr.xstorm_waitp = REG_RD(bp, XSTORM_WAITP_ADDR);
  698. dump_hdr.tstorm_waitp = REG_RD(bp, TSTORM_WAITP_ADDR);
  699. dump_hdr.ustorm_waitp = REG_RD(bp, USTORM_WAITP_ADDR);
  700. dump_hdr.cstorm_waitp = REG_RD(bp, CSTORM_WAITP_ADDR);
  701. if (CHIP_IS_E1(bp))
  702. dump_hdr.info = RI_E1_ONLINE;
  703. else if (CHIP_IS_E1H(bp))
  704. dump_hdr.info = RI_E1H_ONLINE;
  705. else if (!CHIP_IS_E1x(bp))
  706. dump_hdr.info = RI_E2_ONLINE |
  707. (BP_PATH(bp) ? RI_PATH1_DUMP : RI_PATH0_DUMP);
  708. memcpy(p, &dump_hdr, sizeof(struct dump_hdr));
  709. p += dump_hdr.hdr_size + 1;
  710. /* Actually read the registers */
  711. __bnx2x_get_regs(bp, p);
  712. /* Re-enable parity attentions */
  713. bnx2x_clear_blocks_parity(bp);
  714. bnx2x_enable_blocks_parity(bp);
  715. }
  716. static void bnx2x_get_drvinfo(struct net_device *dev,
  717. struct ethtool_drvinfo *info)
  718. {
  719. struct bnx2x *bp = netdev_priv(dev);
  720. u8 phy_fw_ver[PHY_FW_VER_LEN];
  721. strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
  722. strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
  723. phy_fw_ver[0] = '\0';
  724. bnx2x_get_ext_phy_fw_version(&bp->link_params,
  725. phy_fw_ver, PHY_FW_VER_LEN);
  726. strlcpy(info->fw_version, bp->fw_ver, sizeof(info->fw_version));
  727. snprintf(info->fw_version + strlen(bp->fw_ver), 32 - strlen(bp->fw_ver),
  728. "bc %d.%d.%d%s%s",
  729. (bp->common.bc_ver & 0xff0000) >> 16,
  730. (bp->common.bc_ver & 0xff00) >> 8,
  731. (bp->common.bc_ver & 0xff),
  732. ((phy_fw_ver[0] != '\0') ? " phy " : ""), phy_fw_ver);
  733. strlcpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info));
  734. info->n_stats = BNX2X_NUM_STATS;
  735. info->testinfo_len = BNX2X_NUM_TESTS;
  736. info->eedump_len = bp->common.flash_size;
  737. info->regdump_len = bnx2x_get_regs_len(dev);
  738. }
  739. static void bnx2x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
  740. {
  741. struct bnx2x *bp = netdev_priv(dev);
  742. if (bp->flags & NO_WOL_FLAG) {
  743. wol->supported = 0;
  744. wol->wolopts = 0;
  745. } else {
  746. wol->supported = WAKE_MAGIC;
  747. if (bp->wol)
  748. wol->wolopts = WAKE_MAGIC;
  749. else
  750. wol->wolopts = 0;
  751. }
  752. memset(&wol->sopass, 0, sizeof(wol->sopass));
  753. }
  754. static int bnx2x_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
  755. {
  756. struct bnx2x *bp = netdev_priv(dev);
  757. if (wol->wolopts & ~WAKE_MAGIC) {
  758. DP(BNX2X_MSG_ETHTOOL, "WOL not supproted\n");
  759. return -EINVAL;
  760. }
  761. if (wol->wolopts & WAKE_MAGIC) {
  762. if (bp->flags & NO_WOL_FLAG) {
  763. DP(BNX2X_MSG_ETHTOOL, "WOL not supproted\n");
  764. return -EINVAL;
  765. }
  766. bp->wol = 1;
  767. } else
  768. bp->wol = 0;
  769. return 0;
  770. }
  771. static u32 bnx2x_get_msglevel(struct net_device *dev)
  772. {
  773. struct bnx2x *bp = netdev_priv(dev);
  774. return bp->msg_enable;
  775. }
  776. static void bnx2x_set_msglevel(struct net_device *dev, u32 level)
  777. {
  778. struct bnx2x *bp = netdev_priv(dev);
  779. if (capable(CAP_NET_ADMIN)) {
  780. /* dump MCP trace */
  781. if (level & BNX2X_MSG_MCP)
  782. bnx2x_fw_dump_lvl(bp, KERN_INFO);
  783. bp->msg_enable = level;
  784. }
  785. }
  786. static int bnx2x_nway_reset(struct net_device *dev)
  787. {
  788. struct bnx2x *bp = netdev_priv(dev);
  789. if (!bp->port.pmf)
  790. return 0;
  791. if (netif_running(dev)) {
  792. bnx2x_stats_handle(bp, STATS_EVENT_STOP);
  793. bnx2x_link_set(bp);
  794. }
  795. return 0;
  796. }
  797. static u32 bnx2x_get_link(struct net_device *dev)
  798. {
  799. struct bnx2x *bp = netdev_priv(dev);
  800. if (bp->flags & MF_FUNC_DIS || (bp->state != BNX2X_STATE_OPEN))
  801. return 0;
  802. return bp->link_vars.link_up;
  803. }
  804. static int bnx2x_get_eeprom_len(struct net_device *dev)
  805. {
  806. struct bnx2x *bp = netdev_priv(dev);
  807. return bp->common.flash_size;
  808. }
  809. /* Per pf misc lock must be aquired before the per port mcp lock. Otherwise, had
  810. * we done things the other way around, if two pfs from the same port would
  811. * attempt to access nvram at the same time, we could run into a scenario such
  812. * as:
  813. * pf A takes the port lock.
  814. * pf B succeeds in taking the same lock since they are from the same port.
  815. * pf A takes the per pf misc lock. Performs eeprom access.
  816. * pf A finishes. Unlocks the per pf misc lock.
  817. * Pf B takes the lock and proceeds to perform it's own access.
  818. * pf A unlocks the per port lock, while pf B is still working (!).
  819. * mcp takes the per port lock and corrupts pf B's access (and/or has it's own
  820. * acess corrupted by pf B).*
  821. */
  822. static int bnx2x_acquire_nvram_lock(struct bnx2x *bp)
  823. {
  824. int port = BP_PORT(bp);
  825. int count, i;
  826. u32 val;
  827. /* acquire HW lock: protect against other PFs in PF Direct Assignment */
  828. bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM);
  829. /* adjust timeout for emulation/FPGA */
  830. count = BNX2X_NVRAM_TIMEOUT_COUNT;
  831. if (CHIP_REV_IS_SLOW(bp))
  832. count *= 100;
  833. /* request access to nvram interface */
  834. REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
  835. (MCPR_NVM_SW_ARB_ARB_REQ_SET1 << port));
  836. for (i = 0; i < count*10; i++) {
  837. val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
  838. if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))
  839. break;
  840. udelay(5);
  841. }
  842. if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) {
  843. DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
  844. "cannot get access to nvram interface\n");
  845. return -EBUSY;
  846. }
  847. return 0;
  848. }
  849. static int bnx2x_release_nvram_lock(struct bnx2x *bp)
  850. {
  851. int port = BP_PORT(bp);
  852. int count, i;
  853. u32 val;
  854. /* adjust timeout for emulation/FPGA */
  855. count = BNX2X_NVRAM_TIMEOUT_COUNT;
  856. if (CHIP_REV_IS_SLOW(bp))
  857. count *= 100;
  858. /* relinquish nvram interface */
  859. REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
  860. (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << port));
  861. for (i = 0; i < count*10; i++) {
  862. val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
  863. if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)))
  864. break;
  865. udelay(5);
  866. }
  867. if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) {
  868. DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
  869. "cannot free access to nvram interface\n");
  870. return -EBUSY;
  871. }
  872. /* release HW lock: protect against other PFs in PF Direct Assignment */
  873. bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM);
  874. return 0;
  875. }
  876. static void bnx2x_enable_nvram_access(struct bnx2x *bp)
  877. {
  878. u32 val;
  879. val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
  880. /* enable both bits, even on read */
  881. REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
  882. (val | MCPR_NVM_ACCESS_ENABLE_EN |
  883. MCPR_NVM_ACCESS_ENABLE_WR_EN));
  884. }
  885. static void bnx2x_disable_nvram_access(struct bnx2x *bp)
  886. {
  887. u32 val;
  888. val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
  889. /* disable both bits, even after read */
  890. REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
  891. (val & ~(MCPR_NVM_ACCESS_ENABLE_EN |
  892. MCPR_NVM_ACCESS_ENABLE_WR_EN)));
  893. }
  894. static int bnx2x_nvram_read_dword(struct bnx2x *bp, u32 offset, __be32 *ret_val,
  895. u32 cmd_flags)
  896. {
  897. int count, i, rc;
  898. u32 val;
  899. /* build the command word */
  900. cmd_flags |= MCPR_NVM_COMMAND_DOIT;
  901. /* need to clear DONE bit separately */
  902. REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
  903. /* address of the NVRAM to read from */
  904. REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
  905. (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
  906. /* issue a read command */
  907. REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
  908. /* adjust timeout for emulation/FPGA */
  909. count = BNX2X_NVRAM_TIMEOUT_COUNT;
  910. if (CHIP_REV_IS_SLOW(bp))
  911. count *= 100;
  912. /* wait for completion */
  913. *ret_val = 0;
  914. rc = -EBUSY;
  915. for (i = 0; i < count; i++) {
  916. udelay(5);
  917. val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
  918. if (val & MCPR_NVM_COMMAND_DONE) {
  919. val = REG_RD(bp, MCP_REG_MCPR_NVM_READ);
  920. /* we read nvram data in cpu order
  921. * but ethtool sees it as an array of bytes
  922. * converting to big-endian will do the work */
  923. *ret_val = cpu_to_be32(val);
  924. rc = 0;
  925. break;
  926. }
  927. }
  928. if (rc == -EBUSY)
  929. DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
  930. "nvram read timeout expired\n");
  931. return rc;
  932. }
  933. static int bnx2x_nvram_read(struct bnx2x *bp, u32 offset, u8 *ret_buf,
  934. int buf_size)
  935. {
  936. int rc;
  937. u32 cmd_flags;
  938. __be32 val;
  939. if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
  940. DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
  941. "Invalid parameter: offset 0x%x buf_size 0x%x\n",
  942. offset, buf_size);
  943. return -EINVAL;
  944. }
  945. if (offset + buf_size > bp->common.flash_size) {
  946. DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
  947. "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
  948. offset, buf_size, bp->common.flash_size);
  949. return -EINVAL;
  950. }
  951. /* request access to nvram interface */
  952. rc = bnx2x_acquire_nvram_lock(bp);
  953. if (rc)
  954. return rc;
  955. /* enable access to nvram interface */
  956. bnx2x_enable_nvram_access(bp);
  957. /* read the first word(s) */
  958. cmd_flags = MCPR_NVM_COMMAND_FIRST;
  959. while ((buf_size > sizeof(u32)) && (rc == 0)) {
  960. rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
  961. memcpy(ret_buf, &val, 4);
  962. /* advance to the next dword */
  963. offset += sizeof(u32);
  964. ret_buf += sizeof(u32);
  965. buf_size -= sizeof(u32);
  966. cmd_flags = 0;
  967. }
  968. if (rc == 0) {
  969. cmd_flags |= MCPR_NVM_COMMAND_LAST;
  970. rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
  971. memcpy(ret_buf, &val, 4);
  972. }
  973. /* disable access to nvram interface */
  974. bnx2x_disable_nvram_access(bp);
  975. bnx2x_release_nvram_lock(bp);
  976. return rc;
  977. }
  978. static int bnx2x_get_eeprom(struct net_device *dev,
  979. struct ethtool_eeprom *eeprom, u8 *eebuf)
  980. {
  981. struct bnx2x *bp = netdev_priv(dev);
  982. int rc;
  983. if (!netif_running(dev)) {
  984. DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
  985. "cannot access eeprom when the interface is down\n");
  986. return -EAGAIN;
  987. }
  988. DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
  989. " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n",
  990. eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
  991. eeprom->len, eeprom->len);
  992. /* parameters already validated in ethtool_get_eeprom */
  993. rc = bnx2x_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
  994. return rc;
  995. }
  996. static int bnx2x_nvram_write_dword(struct bnx2x *bp, u32 offset, u32 val,
  997. u32 cmd_flags)
  998. {
  999. int count, i, rc;
  1000. /* build the command word */
  1001. cmd_flags |= MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WR;
  1002. /* need to clear DONE bit separately */
  1003. REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
  1004. /* write the data */
  1005. REG_WR(bp, MCP_REG_MCPR_NVM_WRITE, val);
  1006. /* address of the NVRAM to write to */
  1007. REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
  1008. (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
  1009. /* issue the write command */
  1010. REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
  1011. /* adjust timeout for emulation/FPGA */
  1012. count = BNX2X_NVRAM_TIMEOUT_COUNT;
  1013. if (CHIP_REV_IS_SLOW(bp))
  1014. count *= 100;
  1015. /* wait for completion */
  1016. rc = -EBUSY;
  1017. for (i = 0; i < count; i++) {
  1018. udelay(5);
  1019. val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
  1020. if (val & MCPR_NVM_COMMAND_DONE) {
  1021. rc = 0;
  1022. break;
  1023. }
  1024. }
  1025. if (rc == -EBUSY)
  1026. DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
  1027. "nvram write timeout expired\n");
  1028. return rc;
  1029. }
  1030. #define BYTE_OFFSET(offset) (8 * (offset & 0x03))
  1031. static int bnx2x_nvram_write1(struct bnx2x *bp, u32 offset, u8 *data_buf,
  1032. int buf_size)
  1033. {
  1034. int rc;
  1035. u32 cmd_flags;
  1036. u32 align_offset;
  1037. __be32 val;
  1038. if (offset + buf_size > bp->common.flash_size) {
  1039. DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
  1040. "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
  1041. offset, buf_size, bp->common.flash_size);
  1042. return -EINVAL;
  1043. }
  1044. /* request access to nvram interface */
  1045. rc = bnx2x_acquire_nvram_lock(bp);
  1046. if (rc)
  1047. return rc;
  1048. /* enable access to nvram interface */
  1049. bnx2x_enable_nvram_access(bp);
  1050. cmd_flags = (MCPR_NVM_COMMAND_FIRST | MCPR_NVM_COMMAND_LAST);
  1051. align_offset = (offset & ~0x03);
  1052. rc = bnx2x_nvram_read_dword(bp, align_offset, &val, cmd_flags);
  1053. if (rc == 0) {
  1054. val &= ~(0xff << BYTE_OFFSET(offset));
  1055. val |= (*data_buf << BYTE_OFFSET(offset));
  1056. /* nvram data is returned as an array of bytes
  1057. * convert it back to cpu order */
  1058. val = be32_to_cpu(val);
  1059. rc = bnx2x_nvram_write_dword(bp, align_offset, val,
  1060. cmd_flags);
  1061. }
  1062. /* disable access to nvram interface */
  1063. bnx2x_disable_nvram_access(bp);
  1064. bnx2x_release_nvram_lock(bp);
  1065. return rc;
  1066. }
  1067. static int bnx2x_nvram_write(struct bnx2x *bp, u32 offset, u8 *data_buf,
  1068. int buf_size)
  1069. {
  1070. int rc;
  1071. u32 cmd_flags;
  1072. u32 val;
  1073. u32 written_so_far;
  1074. if (buf_size == 1) /* ethtool */
  1075. return bnx2x_nvram_write1(bp, offset, data_buf, buf_size);
  1076. if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
  1077. DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
  1078. "Invalid parameter: offset 0x%x buf_size 0x%x\n",
  1079. offset, buf_size);
  1080. return -EINVAL;
  1081. }
  1082. if (offset + buf_size > bp->common.flash_size) {
  1083. DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
  1084. "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
  1085. offset, buf_size, bp->common.flash_size);
  1086. return -EINVAL;
  1087. }
  1088. /* request access to nvram interface */
  1089. rc = bnx2x_acquire_nvram_lock(bp);
  1090. if (rc)
  1091. return rc;
  1092. /* enable access to nvram interface */
  1093. bnx2x_enable_nvram_access(bp);
  1094. written_so_far = 0;
  1095. cmd_flags = MCPR_NVM_COMMAND_FIRST;
  1096. while ((written_so_far < buf_size) && (rc == 0)) {
  1097. if (written_so_far == (buf_size - sizeof(u32)))
  1098. cmd_flags |= MCPR_NVM_COMMAND_LAST;
  1099. else if (((offset + 4) % BNX2X_NVRAM_PAGE_SIZE) == 0)
  1100. cmd_flags |= MCPR_NVM_COMMAND_LAST;
  1101. else if ((offset % BNX2X_NVRAM_PAGE_SIZE) == 0)
  1102. cmd_flags |= MCPR_NVM_COMMAND_FIRST;
  1103. memcpy(&val, data_buf, 4);
  1104. rc = bnx2x_nvram_write_dword(bp, offset, val, cmd_flags);
  1105. /* advance to the next dword */
  1106. offset += sizeof(u32);
  1107. data_buf += sizeof(u32);
  1108. written_so_far += sizeof(u32);
  1109. cmd_flags = 0;
  1110. }
  1111. /* disable access to nvram interface */
  1112. bnx2x_disable_nvram_access(bp);
  1113. bnx2x_release_nvram_lock(bp);
  1114. return rc;
  1115. }
  1116. static int bnx2x_set_eeprom(struct net_device *dev,
  1117. struct ethtool_eeprom *eeprom, u8 *eebuf)
  1118. {
  1119. struct bnx2x *bp = netdev_priv(dev);
  1120. int port = BP_PORT(bp);
  1121. int rc = 0;
  1122. u32 ext_phy_config;
  1123. if (!netif_running(dev)) {
  1124. DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
  1125. "cannot access eeprom when the interface is down\n");
  1126. return -EAGAIN;
  1127. }
  1128. DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
  1129. " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n",
  1130. eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
  1131. eeprom->len, eeprom->len);
  1132. /* parameters already validated in ethtool_set_eeprom */
  1133. /* PHY eeprom can be accessed only by the PMF */
  1134. if ((eeprom->magic >= 0x50485900) && (eeprom->magic <= 0x504859FF) &&
  1135. !bp->port.pmf) {
  1136. DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
  1137. "wrong magic or interface is not pmf\n");
  1138. return -EINVAL;
  1139. }
  1140. ext_phy_config =
  1141. SHMEM_RD(bp,
  1142. dev_info.port_hw_config[port].external_phy_config);
  1143. if (eeprom->magic == 0x50485950) {
  1144. /* 'PHYP' (0x50485950): prepare phy for FW upgrade */
  1145. bnx2x_stats_handle(bp, STATS_EVENT_STOP);
  1146. bnx2x_acquire_phy_lock(bp);
  1147. rc |= bnx2x_link_reset(&bp->link_params,
  1148. &bp->link_vars, 0);
  1149. if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
  1150. PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101)
  1151. bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
  1152. MISC_REGISTERS_GPIO_HIGH, port);
  1153. bnx2x_release_phy_lock(bp);
  1154. bnx2x_link_report(bp);
  1155. } else if (eeprom->magic == 0x50485952) {
  1156. /* 'PHYR' (0x50485952): re-init link after FW upgrade */
  1157. if (bp->state == BNX2X_STATE_OPEN) {
  1158. bnx2x_acquire_phy_lock(bp);
  1159. rc |= bnx2x_link_reset(&bp->link_params,
  1160. &bp->link_vars, 1);
  1161. rc |= bnx2x_phy_init(&bp->link_params,
  1162. &bp->link_vars);
  1163. bnx2x_release_phy_lock(bp);
  1164. bnx2x_calc_fc_adv(bp);
  1165. }
  1166. } else if (eeprom->magic == 0x53985943) {
  1167. /* 'PHYC' (0x53985943): PHY FW upgrade completed */
  1168. if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
  1169. PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) {
  1170. /* DSP Remove Download Mode */
  1171. bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
  1172. MISC_REGISTERS_GPIO_LOW, port);
  1173. bnx2x_acquire_phy_lock(bp);
  1174. bnx2x_sfx7101_sp_sw_reset(bp,
  1175. &bp->link_params.phy[EXT_PHY1]);
  1176. /* wait 0.5 sec to allow it to run */
  1177. msleep(500);
  1178. bnx2x_ext_phy_hw_reset(bp, port);
  1179. msleep(500);
  1180. bnx2x_release_phy_lock(bp);
  1181. }
  1182. } else
  1183. rc = bnx2x_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
  1184. return rc;
  1185. }
  1186. static int bnx2x_get_coalesce(struct net_device *dev,
  1187. struct ethtool_coalesce *coal)
  1188. {
  1189. struct bnx2x *bp = netdev_priv(dev);
  1190. memset(coal, 0, sizeof(struct ethtool_coalesce));
  1191. coal->rx_coalesce_usecs = bp->rx_ticks;
  1192. coal->tx_coalesce_usecs = bp->tx_ticks;
  1193. return 0;
  1194. }
  1195. static int bnx2x_set_coalesce(struct net_device *dev,
  1196. struct ethtool_coalesce *coal)
  1197. {
  1198. struct bnx2x *bp = netdev_priv(dev);
  1199. bp->rx_ticks = (u16)coal->rx_coalesce_usecs;
  1200. if (bp->rx_ticks > BNX2X_MAX_COALESCE_TOUT)
  1201. bp->rx_ticks = BNX2X_MAX_COALESCE_TOUT;
  1202. bp->tx_ticks = (u16)coal->tx_coalesce_usecs;
  1203. if (bp->tx_ticks > BNX2X_MAX_COALESCE_TOUT)
  1204. bp->tx_ticks = BNX2X_MAX_COALESCE_TOUT;
  1205. if (netif_running(dev))
  1206. bnx2x_update_coalesce(bp);
  1207. return 0;
  1208. }
  1209. static void bnx2x_get_ringparam(struct net_device *dev,
  1210. struct ethtool_ringparam *ering)
  1211. {
  1212. struct bnx2x *bp = netdev_priv(dev);
  1213. ering->rx_max_pending = MAX_RX_AVAIL;
  1214. if (bp->rx_ring_size)
  1215. ering->rx_pending = bp->rx_ring_size;
  1216. else
  1217. ering->rx_pending = MAX_RX_AVAIL;
  1218. ering->tx_max_pending = IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL;
  1219. ering->tx_pending = bp->tx_ring_size;
  1220. }
  1221. static int bnx2x_set_ringparam(struct net_device *dev,
  1222. struct ethtool_ringparam *ering)
  1223. {
  1224. struct bnx2x *bp = netdev_priv(dev);
  1225. if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
  1226. DP(BNX2X_MSG_ETHTOOL,
  1227. "Handling parity error recovery. Try again later\n");
  1228. return -EAGAIN;
  1229. }
  1230. if ((ering->rx_pending > MAX_RX_AVAIL) ||
  1231. (ering->rx_pending < (bp->disable_tpa ? MIN_RX_SIZE_NONTPA :
  1232. MIN_RX_SIZE_TPA)) ||
  1233. (ering->tx_pending > (IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL)) ||
  1234. (ering->tx_pending <= MAX_SKB_FRAGS + 4)) {
  1235. DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
  1236. return -EINVAL;
  1237. }
  1238. bp->rx_ring_size = ering->rx_pending;
  1239. bp->tx_ring_size = ering->tx_pending;
  1240. return bnx2x_reload_if_running(dev);
  1241. }
  1242. static void bnx2x_get_pauseparam(struct net_device *dev,
  1243. struct ethtool_pauseparam *epause)
  1244. {
  1245. struct bnx2x *bp = netdev_priv(dev);
  1246. int cfg_idx = bnx2x_get_link_cfg_idx(bp);
  1247. int cfg_reg;
  1248. epause->autoneg = (bp->link_params.req_flow_ctrl[cfg_idx] ==
  1249. BNX2X_FLOW_CTRL_AUTO);
  1250. if (!epause->autoneg)
  1251. cfg_reg = bp->link_params.req_flow_ctrl[cfg_idx];
  1252. else
  1253. cfg_reg = bp->link_params.req_fc_auto_adv;
  1254. epause->rx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_RX) ==
  1255. BNX2X_FLOW_CTRL_RX);
  1256. epause->tx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_TX) ==
  1257. BNX2X_FLOW_CTRL_TX);
  1258. DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n"
  1259. " autoneg %d rx_pause %d tx_pause %d\n",
  1260. epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
  1261. }
  1262. static int bnx2x_set_pauseparam(struct net_device *dev,
  1263. struct ethtool_pauseparam *epause)
  1264. {
  1265. struct bnx2x *bp = netdev_priv(dev);
  1266. u32 cfg_idx = bnx2x_get_link_cfg_idx(bp);
  1267. if (IS_MF(bp))
  1268. return 0;
  1269. DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n"
  1270. " autoneg %d rx_pause %d tx_pause %d\n",
  1271. epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
  1272. bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_AUTO;
  1273. if (epause->rx_pause)
  1274. bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_RX;
  1275. if (epause->tx_pause)
  1276. bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_TX;
  1277. if (bp->link_params.req_flow_ctrl[cfg_idx] == BNX2X_FLOW_CTRL_AUTO)
  1278. bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_NONE;
  1279. if (epause->autoneg) {
  1280. if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
  1281. DP(BNX2X_MSG_ETHTOOL, "autoneg not supported\n");
  1282. return -EINVAL;
  1283. }
  1284. if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG) {
  1285. bp->link_params.req_flow_ctrl[cfg_idx] =
  1286. BNX2X_FLOW_CTRL_AUTO;
  1287. }
  1288. }
  1289. DP(BNX2X_MSG_ETHTOOL,
  1290. "req_flow_ctrl 0x%x\n", bp->link_params.req_flow_ctrl[cfg_idx]);
  1291. if (netif_running(dev)) {
  1292. bnx2x_stats_handle(bp, STATS_EVENT_STOP);
  1293. bnx2x_link_set(bp);
  1294. }
  1295. return 0;
  1296. }
  1297. static const struct {
  1298. char string[ETH_GSTRING_LEN];
  1299. } bnx2x_tests_str_arr[BNX2X_NUM_TESTS] = {
  1300. { "register_test (offline)" },
  1301. { "memory_test (offline)" },
  1302. { "loopback_test (offline)" },
  1303. { "nvram_test (online)" },
  1304. { "interrupt_test (online)" },
  1305. { "link_test (online)" },
  1306. { "idle check (online)" }
  1307. };
  1308. static u32 bnx2x_eee_to_adv(u32 eee_adv)
  1309. {
  1310. u32 modes = 0;
  1311. if (eee_adv & SHMEM_EEE_100M_ADV)
  1312. modes |= ADVERTISED_100baseT_Full;
  1313. if (eee_adv & SHMEM_EEE_1G_ADV)
  1314. modes |= ADVERTISED_1000baseT_Full;
  1315. if (eee_adv & SHMEM_EEE_10G_ADV)
  1316. modes |= ADVERTISED_10000baseT_Full;
  1317. return modes;
  1318. }
  1319. static u32 bnx2x_adv_to_eee(u32 modes, u32 shift)
  1320. {
  1321. u32 eee_adv = 0;
  1322. if (modes & ADVERTISED_100baseT_Full)
  1323. eee_adv |= SHMEM_EEE_100M_ADV;
  1324. if (modes & ADVERTISED_1000baseT_Full)
  1325. eee_adv |= SHMEM_EEE_1G_ADV;
  1326. if (modes & ADVERTISED_10000baseT_Full)
  1327. eee_adv |= SHMEM_EEE_10G_ADV;
  1328. return eee_adv << shift;
  1329. }
  1330. static int bnx2x_get_eee(struct net_device *dev, struct ethtool_eee *edata)
  1331. {
  1332. struct bnx2x *bp = netdev_priv(dev);
  1333. u32 eee_cfg;
  1334. if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) {
  1335. DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n");
  1336. return -EOPNOTSUPP;
  1337. }
  1338. eee_cfg = SHMEM2_RD(bp, eee_status[BP_PORT(bp)]);
  1339. edata->supported =
  1340. bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_SUPPORTED_MASK) >>
  1341. SHMEM_EEE_SUPPORTED_SHIFT);
  1342. edata->advertised =
  1343. bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_ADV_STATUS_MASK) >>
  1344. SHMEM_EEE_ADV_STATUS_SHIFT);
  1345. edata->lp_advertised =
  1346. bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_LP_ADV_STATUS_MASK) >>
  1347. SHMEM_EEE_LP_ADV_STATUS_SHIFT);
  1348. /* SHMEM value is in 16u units --> Convert to 1u units. */
  1349. edata->tx_lpi_timer = (eee_cfg & SHMEM_EEE_TIMER_MASK) << 4;
  1350. edata->eee_enabled = (eee_cfg & SHMEM_EEE_REQUESTED_BIT) ? 1 : 0;
  1351. edata->eee_active = (eee_cfg & SHMEM_EEE_ACTIVE_BIT) ? 1 : 0;
  1352. edata->tx_lpi_enabled = (eee_cfg & SHMEM_EEE_LPI_REQUESTED_BIT) ? 1 : 0;
  1353. return 0;
  1354. }
  1355. static int bnx2x_set_eee(struct net_device *dev, struct ethtool_eee *edata)
  1356. {
  1357. struct bnx2x *bp = netdev_priv(dev);
  1358. u32 eee_cfg;
  1359. u32 advertised;
  1360. if (IS_MF(bp))
  1361. return 0;
  1362. if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) {
  1363. DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n");
  1364. return -EOPNOTSUPP;
  1365. }
  1366. eee_cfg = SHMEM2_RD(bp, eee_status[BP_PORT(bp)]);
  1367. if (!(eee_cfg & SHMEM_EEE_SUPPORTED_MASK)) {
  1368. DP(BNX2X_MSG_ETHTOOL, "Board does not support EEE!\n");
  1369. return -EOPNOTSUPP;
  1370. }
  1371. advertised = bnx2x_adv_to_eee(edata->advertised,
  1372. SHMEM_EEE_ADV_STATUS_SHIFT);
  1373. if ((advertised != (eee_cfg & SHMEM_EEE_ADV_STATUS_MASK))) {
  1374. DP(BNX2X_MSG_ETHTOOL,
  1375. "Direct manipulation of EEE advertisment is not supported\n");
  1376. return -EINVAL;
  1377. }
  1378. if (edata->tx_lpi_timer > EEE_MODE_TIMER_MASK) {
  1379. DP(BNX2X_MSG_ETHTOOL,
  1380. "Maximal Tx Lpi timer supported is %x(u)\n",
  1381. EEE_MODE_TIMER_MASK);
  1382. return -EINVAL;
  1383. }
  1384. if (edata->tx_lpi_enabled &&
  1385. (edata->tx_lpi_timer < EEE_MODE_NVRAM_AGGRESSIVE_TIME)) {
  1386. DP(BNX2X_MSG_ETHTOOL,
  1387. "Minimal Tx Lpi timer supported is %d(u)\n",
  1388. EEE_MODE_NVRAM_AGGRESSIVE_TIME);
  1389. return -EINVAL;
  1390. }
  1391. /* All is well; Apply changes*/
  1392. if (edata->eee_enabled)
  1393. bp->link_params.eee_mode |= EEE_MODE_ADV_LPI;
  1394. else
  1395. bp->link_params.eee_mode &= ~EEE_MODE_ADV_LPI;
  1396. if (edata->tx_lpi_enabled)
  1397. bp->link_params.eee_mode |= EEE_MODE_ENABLE_LPI;
  1398. else
  1399. bp->link_params.eee_mode &= ~EEE_MODE_ENABLE_LPI;
  1400. bp->link_params.eee_mode &= ~EEE_MODE_TIMER_MASK;
  1401. bp->link_params.eee_mode |= (edata->tx_lpi_timer &
  1402. EEE_MODE_TIMER_MASK) |
  1403. EEE_MODE_OVERRIDE_NVRAM |
  1404. EEE_MODE_OUTPUT_TIME;
  1405. /* Restart link to propogate changes */
  1406. if (netif_running(dev)) {
  1407. bnx2x_stats_handle(bp, STATS_EVENT_STOP);
  1408. bnx2x_link_set(bp);
  1409. }
  1410. return 0;
  1411. }
  1412. enum {
  1413. BNX2X_CHIP_E1_OFST = 0,
  1414. BNX2X_CHIP_E1H_OFST,
  1415. BNX2X_CHIP_E2_OFST,
  1416. BNX2X_CHIP_E3_OFST,
  1417. BNX2X_CHIP_E3B0_OFST,
  1418. BNX2X_CHIP_MAX_OFST
  1419. };
  1420. #define BNX2X_CHIP_MASK_E1 (1 << BNX2X_CHIP_E1_OFST)
  1421. #define BNX2X_CHIP_MASK_E1H (1 << BNX2X_CHIP_E1H_OFST)
  1422. #define BNX2X_CHIP_MASK_E2 (1 << BNX2X_CHIP_E2_OFST)
  1423. #define BNX2X_CHIP_MASK_E3 (1 << BNX2X_CHIP_E3_OFST)
  1424. #define BNX2X_CHIP_MASK_E3B0 (1 << BNX2X_CHIP_E3B0_OFST)
  1425. #define BNX2X_CHIP_MASK_ALL ((1 << BNX2X_CHIP_MAX_OFST) - 1)
  1426. #define BNX2X_CHIP_MASK_E1X (BNX2X_CHIP_MASK_E1 | BNX2X_CHIP_MASK_E1H)
  1427. static int bnx2x_test_registers(struct bnx2x *bp)
  1428. {
  1429. int idx, i, rc = -ENODEV;
  1430. u32 wr_val = 0, hw;
  1431. int port = BP_PORT(bp);
  1432. static const struct {
  1433. u32 hw;
  1434. u32 offset0;
  1435. u32 offset1;
  1436. u32 mask;
  1437. } reg_tbl[] = {
  1438. /* 0 */ { BNX2X_CHIP_MASK_ALL,
  1439. BRB1_REG_PAUSE_LOW_THRESHOLD_0, 4, 0x000003ff },
  1440. { BNX2X_CHIP_MASK_ALL,
  1441. DORQ_REG_DB_ADDR0, 4, 0xffffffff },
  1442. { BNX2X_CHIP_MASK_E1X,
  1443. HC_REG_AGG_INT_0, 4, 0x000003ff },
  1444. { BNX2X_CHIP_MASK_ALL,
  1445. PBF_REG_MAC_IF0_ENABLE, 4, 0x00000001 },
  1446. { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2 | BNX2X_CHIP_MASK_E3,
  1447. PBF_REG_P0_INIT_CRD, 4, 0x000007ff },
  1448. { BNX2X_CHIP_MASK_E3B0,
  1449. PBF_REG_INIT_CRD_Q0, 4, 0x000007ff },
  1450. { BNX2X_CHIP_MASK_ALL,
  1451. PRS_REG_CID_PORT_0, 4, 0x00ffffff },
  1452. { BNX2X_CHIP_MASK_ALL,
  1453. PXP2_REG_PSWRQ_CDU0_L2P, 4, 0x000fffff },
  1454. { BNX2X_CHIP_MASK_ALL,
  1455. PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
  1456. { BNX2X_CHIP_MASK_ALL,
  1457. PXP2_REG_PSWRQ_TM0_L2P, 4, 0x000fffff },
  1458. /* 10 */ { BNX2X_CHIP_MASK_ALL,
  1459. PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
  1460. { BNX2X_CHIP_MASK_ALL,
  1461. PXP2_REG_PSWRQ_TSDM0_L2P, 4, 0x000fffff },
  1462. { BNX2X_CHIP_MASK_ALL,
  1463. QM_REG_CONNNUM_0, 4, 0x000fffff },
  1464. { BNX2X_CHIP_MASK_ALL,
  1465. TM_REG_LIN0_MAX_ACTIVE_CID, 4, 0x0003ffff },
  1466. { BNX2X_CHIP_MASK_ALL,
  1467. SRC_REG_KEYRSS0_0, 40, 0xffffffff },
  1468. { BNX2X_CHIP_MASK_ALL,
  1469. SRC_REG_KEYRSS0_7, 40, 0xffffffff },
  1470. { BNX2X_CHIP_MASK_ALL,
  1471. XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 4, 0x00000001 },
  1472. { BNX2X_CHIP_MASK_ALL,
  1473. XCM_REG_WU_DA_CNT_CMD00, 4, 0x00000003 },
  1474. { BNX2X_CHIP_MASK_ALL,
  1475. XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 4, 0x000000ff },
  1476. { BNX2X_CHIP_MASK_ALL,
  1477. NIG_REG_LLH0_T_BIT, 4, 0x00000001 },
  1478. /* 20 */ { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
  1479. NIG_REG_EMAC0_IN_EN, 4, 0x00000001 },
  1480. { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
  1481. NIG_REG_BMAC0_IN_EN, 4, 0x00000001 },
  1482. { BNX2X_CHIP_MASK_ALL,
  1483. NIG_REG_XCM0_OUT_EN, 4, 0x00000001 },
  1484. { BNX2X_CHIP_MASK_ALL,
  1485. NIG_REG_BRB0_OUT_EN, 4, 0x00000001 },
  1486. { BNX2X_CHIP_MASK_ALL,
  1487. NIG_REG_LLH0_XCM_MASK, 4, 0x00000007 },
  1488. { BNX2X_CHIP_MASK_ALL,
  1489. NIG_REG_LLH0_ACPI_PAT_6_LEN, 68, 0x000000ff },
  1490. { BNX2X_CHIP_MASK_ALL,
  1491. NIG_REG_LLH0_ACPI_PAT_0_CRC, 68, 0xffffffff },
  1492. { BNX2X_CHIP_MASK_ALL,
  1493. NIG_REG_LLH0_DEST_MAC_0_0, 160, 0xffffffff },
  1494. { BNX2X_CHIP_MASK_ALL,
  1495. NIG_REG_LLH0_DEST_IP_0_1, 160, 0xffffffff },
  1496. { BNX2X_CHIP_MASK_ALL,
  1497. NIG_REG_LLH0_IPV4_IPV6_0, 160, 0x00000001 },
  1498. /* 30 */ { BNX2X_CHIP_MASK_ALL,
  1499. NIG_REG_LLH0_DEST_UDP_0, 160, 0x0000ffff },
  1500. { BNX2X_CHIP_MASK_ALL,
  1501. NIG_REG_LLH0_DEST_TCP_0, 160, 0x0000ffff },
  1502. { BNX2X_CHIP_MASK_ALL,
  1503. NIG_REG_LLH0_VLAN_ID_0, 160, 0x00000fff },
  1504. { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
  1505. NIG_REG_XGXS_SERDES0_MODE_SEL, 4, 0x00000001 },
  1506. { BNX2X_CHIP_MASK_ALL,
  1507. NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0, 4, 0x00000001},
  1508. { BNX2X_CHIP_MASK_ALL,
  1509. NIG_REG_STATUS_INTERRUPT_PORT0, 4, 0x07ffffff },
  1510. { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
  1511. NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST, 24, 0x00000001 },
  1512. { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
  1513. NIG_REG_SERDES0_CTRL_PHY_ADDR, 16, 0x0000001f },
  1514. { BNX2X_CHIP_MASK_ALL, 0xffffffff, 0, 0x00000000 }
  1515. };
  1516. if (!netif_running(bp->dev)) {
  1517. DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
  1518. "cannot access eeprom when the interface is down\n");
  1519. return rc;
  1520. }
  1521. if (CHIP_IS_E1(bp))
  1522. hw = BNX2X_CHIP_MASK_E1;
  1523. else if (CHIP_IS_E1H(bp))
  1524. hw = BNX2X_CHIP_MASK_E1H;
  1525. else if (CHIP_IS_E2(bp))
  1526. hw = BNX2X_CHIP_MASK_E2;
  1527. else if (CHIP_IS_E3B0(bp))
  1528. hw = BNX2X_CHIP_MASK_E3B0;
  1529. else /* e3 A0 */
  1530. hw = BNX2X_CHIP_MASK_E3;
  1531. /* Repeat the test twice:
  1532. First by writing 0x00000000, second by writing 0xffffffff */
  1533. for (idx = 0; idx < 2; idx++) {
  1534. switch (idx) {
  1535. case 0:
  1536. wr_val = 0;
  1537. break;
  1538. case 1:
  1539. wr_val = 0xffffffff;
  1540. break;
  1541. }
  1542. for (i = 0; reg_tbl[i].offset0 != 0xffffffff; i++) {
  1543. u32 offset, mask, save_val, val;
  1544. if (!(hw & reg_tbl[i].hw))
  1545. continue;
  1546. offset = reg_tbl[i].offset0 + port*reg_tbl[i].offset1;
  1547. mask = reg_tbl[i].mask;
  1548. save_val = REG_RD(bp, offset);
  1549. REG_WR(bp, offset, wr_val & mask);
  1550. val = REG_RD(bp, offset);
  1551. /* Restore the original register's value */
  1552. REG_WR(bp, offset, save_val);
  1553. /* verify value is as expected */
  1554. if ((val & mask) != (wr_val & mask)) {
  1555. DP(BNX2X_MSG_ETHTOOL,
  1556. "offset 0x%x: val 0x%x != 0x%x mask 0x%x\n",
  1557. offset, val, wr_val, mask);
  1558. goto test_reg_exit;
  1559. }
  1560. }
  1561. }
  1562. rc = 0;
  1563. test_reg_exit:
  1564. return rc;
  1565. }
  1566. static int bnx2x_test_memory(struct bnx2x *bp)
  1567. {
  1568. int i, j, rc = -ENODEV;
  1569. u32 val, index;
  1570. static const struct {
  1571. u32 offset;
  1572. int size;
  1573. } mem_tbl[] = {
  1574. { CCM_REG_XX_DESCR_TABLE, CCM_REG_XX_DESCR_TABLE_SIZE },
  1575. { CFC_REG_ACTIVITY_COUNTER, CFC_REG_ACTIVITY_COUNTER_SIZE },
  1576. { CFC_REG_LINK_LIST, CFC_REG_LINK_LIST_SIZE },
  1577. { DMAE_REG_CMD_MEM, DMAE_REG_CMD_MEM_SIZE },
  1578. { TCM_REG_XX_DESCR_TABLE, TCM_REG_XX_DESCR_TABLE_SIZE },
  1579. { UCM_REG_XX_DESCR_TABLE, UCM_REG_XX_DESCR_TABLE_SIZE },
  1580. { XCM_REG_XX_DESCR_TABLE, XCM_REG_XX_DESCR_TABLE_SIZE },
  1581. { 0xffffffff, 0 }
  1582. };
  1583. static const struct {
  1584. char *name;
  1585. u32 offset;
  1586. u32 hw_mask[BNX2X_CHIP_MAX_OFST];
  1587. } prty_tbl[] = {
  1588. { "CCM_PRTY_STS", CCM_REG_CCM_PRTY_STS,
  1589. {0x3ffc0, 0, 0, 0} },
  1590. { "CFC_PRTY_STS", CFC_REG_CFC_PRTY_STS,
  1591. {0x2, 0x2, 0, 0} },
  1592. { "DMAE_PRTY_STS", DMAE_REG_DMAE_PRTY_STS,
  1593. {0, 0, 0, 0} },
  1594. { "TCM_PRTY_STS", TCM_REG_TCM_PRTY_STS,
  1595. {0x3ffc0, 0, 0, 0} },
  1596. { "UCM_PRTY_STS", UCM_REG_UCM_PRTY_STS,
  1597. {0x3ffc0, 0, 0, 0} },
  1598. { "XCM_PRTY_STS", XCM_REG_XCM_PRTY_STS,
  1599. {0x3ffc1, 0, 0, 0} },
  1600. { NULL, 0xffffffff, {0, 0, 0, 0} }
  1601. };
  1602. if (!netif_running(bp->dev)) {
  1603. DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
  1604. "cannot access eeprom when the interface is down\n");
  1605. return rc;
  1606. }
  1607. if (CHIP_IS_E1(bp))
  1608. index = BNX2X_CHIP_E1_OFST;
  1609. else if (CHIP_IS_E1H(bp))
  1610. index = BNX2X_CHIP_E1H_OFST;
  1611. else if (CHIP_IS_E2(bp))
  1612. index = BNX2X_CHIP_E2_OFST;
  1613. else /* e3 */
  1614. index = BNX2X_CHIP_E3_OFST;
  1615. /* pre-Check the parity status */
  1616. for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
  1617. val = REG_RD(bp, prty_tbl[i].offset);
  1618. if (val & ~(prty_tbl[i].hw_mask[index])) {
  1619. DP(BNX2X_MSG_ETHTOOL,
  1620. "%s is 0x%x\n", prty_tbl[i].name, val);
  1621. goto test_mem_exit;
  1622. }
  1623. }
  1624. /* Go through all the memories */
  1625. for (i = 0; mem_tbl[i].offset != 0xffffffff; i++)
  1626. for (j = 0; j < mem_tbl[i].size; j++)
  1627. REG_RD(bp, mem_tbl[i].offset + j*4);
  1628. /* Check the parity status */
  1629. for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
  1630. val = REG_RD(bp, prty_tbl[i].offset);
  1631. if (val & ~(prty_tbl[i].hw_mask[index])) {
  1632. DP(BNX2X_MSG_ETHTOOL,
  1633. "%s is 0x%x\n", prty_tbl[i].name, val);
  1634. goto test_mem_exit;
  1635. }
  1636. }
  1637. rc = 0;
  1638. test_mem_exit:
  1639. return rc;
  1640. }
  1641. static void bnx2x_wait_for_link(struct bnx2x *bp, u8 link_up, u8 is_serdes)
  1642. {
  1643. int cnt = 1400;
  1644. if (link_up) {
  1645. while (bnx2x_link_test(bp, is_serdes) && cnt--)
  1646. msleep(20);
  1647. if (cnt <= 0 && bnx2x_link_test(bp, is_serdes))
  1648. DP(BNX2X_MSG_ETHTOOL, "Timeout waiting for link up\n");
  1649. }
  1650. }
  1651. static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode)
  1652. {
  1653. unsigned int pkt_size, num_pkts, i;
  1654. struct sk_buff *skb;
  1655. unsigned char *packet;
  1656. struct bnx2x_fastpath *fp_rx = &bp->fp[0];
  1657. struct bnx2x_fastpath *fp_tx = &bp->fp[0];
  1658. struct bnx2x_fp_txdata *txdata = &fp_tx->txdata[0];
  1659. u16 tx_start_idx, tx_idx;
  1660. u16 rx_start_idx, rx_idx;
  1661. u16 pkt_prod, bd_prod;
  1662. struct sw_tx_bd *tx_buf;
  1663. struct eth_tx_start_bd *tx_start_bd;
  1664. struct eth_tx_parse_bd_e1x *pbd_e1x = NULL;
  1665. struct eth_tx_parse_bd_e2 *pbd_e2 = NULL;
  1666. dma_addr_t mapping;
  1667. union eth_rx_cqe *cqe;
  1668. u8 cqe_fp_flags, cqe_fp_type;
  1669. struct sw_rx_bd *rx_buf;
  1670. u16 len;
  1671. int rc = -ENODEV;
  1672. u8 *data;
  1673. struct netdev_queue *txq = netdev_get_tx_queue(bp->dev, txdata->txq_index);
  1674. /* check the loopback mode */
  1675. switch (loopback_mode) {
  1676. case BNX2X_PHY_LOOPBACK:
  1677. if (bp->link_params.loopback_mode != LOOPBACK_XGXS)
  1678. return -EINVAL;
  1679. break;
  1680. case BNX2X_MAC_LOOPBACK:
  1681. if (CHIP_IS_E3(bp)) {
  1682. int cfg_idx = bnx2x_get_link_cfg_idx(bp);
  1683. if (bp->port.supported[cfg_idx] &
  1684. (SUPPORTED_10000baseT_Full |
  1685. SUPPORTED_20000baseMLD2_Full |
  1686. SUPPORTED_20000baseKR2_Full))
  1687. bp->link_params.loopback_mode = LOOPBACK_XMAC;
  1688. else
  1689. bp->link_params.loopback_mode = LOOPBACK_UMAC;
  1690. } else
  1691. bp->link_params.loopback_mode = LOOPBACK_BMAC;
  1692. bnx2x_phy_init(&bp->link_params, &bp->link_vars);
  1693. break;
  1694. default:
  1695. DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
  1696. return -EINVAL;
  1697. }
  1698. /* prepare the loopback packet */
  1699. pkt_size = (((bp->dev->mtu < ETH_MAX_PACKET_SIZE) ?
  1700. bp->dev->mtu : ETH_MAX_PACKET_SIZE) + ETH_HLEN);
  1701. skb = netdev_alloc_skb(bp->dev, fp_rx->rx_buf_size);
  1702. if (!skb) {
  1703. DP(BNX2X_MSG_ETHTOOL, "Can't allocate skb\n");
  1704. rc = -ENOMEM;
  1705. goto test_loopback_exit;
  1706. }
  1707. packet = skb_put(skb, pkt_size);
  1708. memcpy(packet, bp->dev->dev_addr, ETH_ALEN);
  1709. memset(packet + ETH_ALEN, 0, ETH_ALEN);
  1710. memset(packet + 2*ETH_ALEN, 0x77, (ETH_HLEN - 2*ETH_ALEN));
  1711. for (i = ETH_HLEN; i < pkt_size; i++)
  1712. packet[i] = (unsigned char) (i & 0xff);
  1713. mapping = dma_map_single(&bp->pdev->dev, skb->data,
  1714. skb_headlen(skb), DMA_TO_DEVICE);
  1715. if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
  1716. rc = -ENOMEM;
  1717. dev_kfree_skb(skb);
  1718. DP(BNX2X_MSG_ETHTOOL, "Unable to map SKB\n");
  1719. goto test_loopback_exit;
  1720. }
  1721. /* send the loopback packet */
  1722. num_pkts = 0;
  1723. tx_start_idx = le16_to_cpu(*txdata->tx_cons_sb);
  1724. rx_start_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
  1725. netdev_tx_sent_queue(txq, skb->len);
  1726. pkt_prod = txdata->tx_pkt_prod++;
  1727. tx_buf = &txdata->tx_buf_ring[TX_BD(pkt_prod)];
  1728. tx_buf->first_bd = txdata->tx_bd_prod;
  1729. tx_buf->skb = skb;
  1730. tx_buf->flags = 0;
  1731. bd_prod = TX_BD(txdata->tx_bd_prod);
  1732. tx_start_bd = &txdata->tx_desc_ring[bd_prod].start_bd;
  1733. tx_start_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
  1734. tx_start_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
  1735. tx_start_bd->nbd = cpu_to_le16(2); /* start + pbd */
  1736. tx_start_bd->nbytes = cpu_to_le16(skb_headlen(skb));
  1737. tx_start_bd->vlan_or_ethertype = cpu_to_le16(pkt_prod);
  1738. tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
  1739. SET_FLAG(tx_start_bd->general_data,
  1740. ETH_TX_START_BD_ETH_ADDR_TYPE,
  1741. UNICAST_ADDRESS);
  1742. SET_FLAG(tx_start_bd->general_data,
  1743. ETH_TX_START_BD_HDR_NBDS,
  1744. 1);
  1745. /* turn on parsing and get a BD */
  1746. bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
  1747. pbd_e1x = &txdata->tx_desc_ring[bd_prod].parse_bd_e1x;
  1748. pbd_e2 = &txdata->tx_desc_ring[bd_prod].parse_bd_e2;
  1749. memset(pbd_e2, 0, sizeof(struct eth_tx_parse_bd_e2));
  1750. memset(pbd_e1x, 0, sizeof(struct eth_tx_parse_bd_e1x));
  1751. wmb();
  1752. txdata->tx_db.data.prod += 2;
  1753. barrier();
  1754. DOORBELL(bp, txdata->cid, txdata->tx_db.raw);
  1755. mmiowb();
  1756. barrier();
  1757. num_pkts++;
  1758. txdata->tx_bd_prod += 2; /* start + pbd */
  1759. udelay(100);
  1760. tx_idx = le16_to_cpu(*txdata->tx_cons_sb);
  1761. if (tx_idx != tx_start_idx + num_pkts)
  1762. goto test_loopback_exit;
  1763. /* Unlike HC IGU won't generate an interrupt for status block
  1764. * updates that have been performed while interrupts were
  1765. * disabled.
  1766. */
  1767. if (bp->common.int_block == INT_BLOCK_IGU) {
  1768. /* Disable local BHes to prevent a dead-lock situation between
  1769. * sch_direct_xmit() and bnx2x_run_loopback() (calling
  1770. * bnx2x_tx_int()), as both are taking netif_tx_lock().
  1771. */
  1772. local_bh_disable();
  1773. bnx2x_tx_int(bp, txdata);
  1774. local_bh_enable();
  1775. }
  1776. rx_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
  1777. if (rx_idx != rx_start_idx + num_pkts)
  1778. goto test_loopback_exit;
  1779. cqe = &fp_rx->rx_comp_ring[RCQ_BD(fp_rx->rx_comp_cons)];
  1780. cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
  1781. cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE;
  1782. if (!CQE_TYPE_FAST(cqe_fp_type) || (cqe_fp_flags & ETH_RX_ERROR_FALGS))
  1783. goto test_loopback_rx_exit;
  1784. len = le16_to_cpu(cqe->fast_path_cqe.pkt_len_or_gro_seg_len);
  1785. if (len != pkt_size)
  1786. goto test_loopback_rx_exit;
  1787. rx_buf = &fp_rx->rx_buf_ring[RX_BD(fp_rx->rx_bd_cons)];
  1788. dma_sync_single_for_cpu(&bp->pdev->dev,
  1789. dma_unmap_addr(rx_buf, mapping),
  1790. fp_rx->rx_buf_size, DMA_FROM_DEVICE);
  1791. data = rx_buf->data + NET_SKB_PAD + cqe->fast_path_cqe.placement_offset;
  1792. for (i = ETH_HLEN; i < pkt_size; i++)
  1793. if (*(data + i) != (unsigned char) (i & 0xff))
  1794. goto test_loopback_rx_exit;
  1795. rc = 0;
  1796. test_loopback_rx_exit:
  1797. fp_rx->rx_bd_cons = NEXT_RX_IDX(fp_rx->rx_bd_cons);
  1798. fp_rx->rx_bd_prod = NEXT_RX_IDX(fp_rx->rx_bd_prod);
  1799. fp_rx->rx_comp_cons = NEXT_RCQ_IDX(fp_rx->rx_comp_cons);
  1800. fp_rx->rx_comp_prod = NEXT_RCQ_IDX(fp_rx->rx_comp_prod);
  1801. /* Update producers */
  1802. bnx2x_update_rx_prod(bp, fp_rx, fp_rx->rx_bd_prod, fp_rx->rx_comp_prod,
  1803. fp_rx->rx_sge_prod);
  1804. test_loopback_exit:
  1805. bp->link_params.loopback_mode = LOOPBACK_NONE;
  1806. return rc;
  1807. }
  1808. static int bnx2x_test_loopback(struct bnx2x *bp)
  1809. {
  1810. int rc = 0, res;
  1811. if (BP_NOMCP(bp))
  1812. return rc;
  1813. if (!netif_running(bp->dev))
  1814. return BNX2X_LOOPBACK_FAILED;
  1815. bnx2x_netif_stop(bp, 1);
  1816. bnx2x_acquire_phy_lock(bp);
  1817. res = bnx2x_run_loopback(bp, BNX2X_PHY_LOOPBACK);
  1818. if (res) {
  1819. DP(BNX2X_MSG_ETHTOOL, " PHY loopback failed (res %d)\n", res);
  1820. rc |= BNX2X_PHY_LOOPBACK_FAILED;
  1821. }
  1822. res = bnx2x_run_loopback(bp, BNX2X_MAC_LOOPBACK);
  1823. if (res) {
  1824. DP(BNX2X_MSG_ETHTOOL, " MAC loopback failed (res %d)\n", res);
  1825. rc |= BNX2X_MAC_LOOPBACK_FAILED;
  1826. }
  1827. bnx2x_release_phy_lock(bp);
  1828. bnx2x_netif_start(bp);
  1829. return rc;
  1830. }
  1831. #define CRC32_RESIDUAL 0xdebb20e3
  1832. static int bnx2x_test_nvram(struct bnx2x *bp)
  1833. {
  1834. static const struct {
  1835. int offset;
  1836. int size;
  1837. } nvram_tbl[] = {
  1838. { 0, 0x14 }, /* bootstrap */
  1839. { 0x14, 0xec }, /* dir */
  1840. { 0x100, 0x350 }, /* manuf_info */
  1841. { 0x450, 0xf0 }, /* feature_info */
  1842. { 0x640, 0x64 }, /* upgrade_key_info */
  1843. { 0x708, 0x70 }, /* manuf_key_info */
  1844. { 0, 0 }
  1845. };
  1846. __be32 *buf;
  1847. u8 *data;
  1848. int i, rc;
  1849. u32 magic, crc;
  1850. if (BP_NOMCP(bp))
  1851. return 0;
  1852. buf = kmalloc(0x350, GFP_KERNEL);
  1853. if (!buf) {
  1854. DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "kmalloc failed\n");
  1855. rc = -ENOMEM;
  1856. goto test_nvram_exit;
  1857. }
  1858. data = (u8 *)buf;
  1859. rc = bnx2x_nvram_read(bp, 0, data, 4);
  1860. if (rc) {
  1861. DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
  1862. "magic value read (rc %d)\n", rc);
  1863. goto test_nvram_exit;
  1864. }
  1865. magic = be32_to_cpu(buf[0]);
  1866. if (magic != 0x669955aa) {
  1867. DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
  1868. "wrong magic value (0x%08x)\n", magic);
  1869. rc = -ENODEV;
  1870. goto test_nvram_exit;
  1871. }
  1872. for (i = 0; nvram_tbl[i].size; i++) {
  1873. rc = bnx2x_nvram_read(bp, nvram_tbl[i].offset, data,
  1874. nvram_tbl[i].size);
  1875. if (rc) {
  1876. DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
  1877. "nvram_tbl[%d] read data (rc %d)\n", i, rc);
  1878. goto test_nvram_exit;
  1879. }
  1880. crc = ether_crc_le(nvram_tbl[i].size, data);
  1881. if (crc != CRC32_RESIDUAL) {
  1882. DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
  1883. "nvram_tbl[%d] wrong crc value (0x%08x)\n", i, crc);
  1884. rc = -ENODEV;
  1885. goto test_nvram_exit;
  1886. }
  1887. }
  1888. test_nvram_exit:
  1889. kfree(buf);
  1890. return rc;
  1891. }
  1892. /* Send an EMPTY ramrod on the first queue */
  1893. static int bnx2x_test_intr(struct bnx2x *bp)
  1894. {
  1895. struct bnx2x_queue_state_params params = {NULL};
  1896. if (!netif_running(bp->dev)) {
  1897. DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
  1898. "cannot access eeprom when the interface is down\n");
  1899. return -ENODEV;
  1900. }
  1901. params.q_obj = &bp->fp->q_obj;
  1902. params.cmd = BNX2X_Q_CMD_EMPTY;
  1903. __set_bit(RAMROD_COMP_WAIT, &params.ramrod_flags);
  1904. return bnx2x_queue_state_change(bp, &params);
  1905. }
  1906. static void bnx2x_self_test(struct net_device *dev,
  1907. struct ethtool_test *etest, u64 *buf)
  1908. {
  1909. struct bnx2x *bp = netdev_priv(dev);
  1910. u8 is_serdes;
  1911. if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
  1912. netdev_err(bp->dev,
  1913. "Handling parity error recovery. Try again later\n");
  1914. etest->flags |= ETH_TEST_FL_FAILED;
  1915. return;
  1916. }
  1917. memset(buf, 0, sizeof(u64) * BNX2X_NUM_TESTS);
  1918. if (!netif_running(dev))
  1919. return;
  1920. /* offline tests are not supported in MF mode */
  1921. if (IS_MF(bp))
  1922. etest->flags &= ~ETH_TEST_FL_OFFLINE;
  1923. is_serdes = (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0;
  1924. if (etest->flags & ETH_TEST_FL_OFFLINE) {
  1925. int port = BP_PORT(bp);
  1926. u32 val;
  1927. u8 link_up;
  1928. /* save current value of input enable for TX port IF */
  1929. val = REG_RD(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4);
  1930. /* disable input for TX port IF */
  1931. REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, 0);
  1932. link_up = bp->link_vars.link_up;
  1933. bnx2x_nic_unload(bp, UNLOAD_NORMAL);
  1934. bnx2x_nic_load(bp, LOAD_DIAG);
  1935. /* wait until link state is restored */
  1936. bnx2x_wait_for_link(bp, 1, is_serdes);
  1937. if (bnx2x_test_registers(bp) != 0) {
  1938. buf[0] = 1;
  1939. etest->flags |= ETH_TEST_FL_FAILED;
  1940. }
  1941. if (bnx2x_test_memory(bp) != 0) {
  1942. buf[1] = 1;
  1943. etest->flags |= ETH_TEST_FL_FAILED;
  1944. }
  1945. buf[2] = bnx2x_test_loopback(bp);
  1946. if (buf[2] != 0)
  1947. etest->flags |= ETH_TEST_FL_FAILED;
  1948. bnx2x_nic_unload(bp, UNLOAD_NORMAL);
  1949. /* restore input for TX port IF */
  1950. REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, val);
  1951. bnx2x_nic_load(bp, LOAD_NORMAL);
  1952. /* wait until link state is restored */
  1953. bnx2x_wait_for_link(bp, link_up, is_serdes);
  1954. }
  1955. if (bnx2x_test_nvram(bp) != 0) {
  1956. buf[3] = 1;
  1957. etest->flags |= ETH_TEST_FL_FAILED;
  1958. }
  1959. if (bnx2x_test_intr(bp) != 0) {
  1960. buf[4] = 1;
  1961. etest->flags |= ETH_TEST_FL_FAILED;
  1962. }
  1963. if (bnx2x_link_test(bp, is_serdes) != 0) {
  1964. buf[5] = 1;
  1965. etest->flags |= ETH_TEST_FL_FAILED;
  1966. }
  1967. #ifdef BNX2X_EXTRA_DEBUG
  1968. bnx2x_panic_dump(bp);
  1969. #endif
  1970. }
  1971. #define IS_PORT_STAT(i) \
  1972. ((bnx2x_stats_arr[i].flags & STATS_FLAGS_BOTH) == STATS_FLAGS_PORT)
  1973. #define IS_FUNC_STAT(i) (bnx2x_stats_arr[i].flags & STATS_FLAGS_FUNC)
  1974. #define IS_MF_MODE_STAT(bp) \
  1975. (IS_MF(bp) && !(bp->msg_enable & BNX2X_MSG_STATS))
  1976. /* ethtool statistics are displayed for all regular ethernet queues and the
  1977. * fcoe L2 queue if not disabled
  1978. */
  1979. static int bnx2x_num_stat_queues(struct bnx2x *bp)
  1980. {
  1981. return BNX2X_NUM_ETH_QUEUES(bp);
  1982. }
  1983. static int bnx2x_get_sset_count(struct net_device *dev, int stringset)
  1984. {
  1985. struct bnx2x *bp = netdev_priv(dev);
  1986. int i, num_stats;
  1987. switch (stringset) {
  1988. case ETH_SS_STATS:
  1989. if (is_multi(bp)) {
  1990. num_stats = bnx2x_num_stat_queues(bp) *
  1991. BNX2X_NUM_Q_STATS;
  1992. } else
  1993. num_stats = 0;
  1994. if (IS_MF_MODE_STAT(bp)) {
  1995. for (i = 0; i < BNX2X_NUM_STATS; i++)
  1996. if (IS_FUNC_STAT(i))
  1997. num_stats++;
  1998. } else
  1999. num_stats += BNX2X_NUM_STATS;
  2000. return num_stats;
  2001. case ETH_SS_TEST:
  2002. return BNX2X_NUM_TESTS;
  2003. default:
  2004. return -EINVAL;
  2005. }
  2006. }
  2007. static void bnx2x_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
  2008. {
  2009. struct bnx2x *bp = netdev_priv(dev);
  2010. int i, j, k;
  2011. char queue_name[MAX_QUEUE_NAME_LEN+1];
  2012. switch (stringset) {
  2013. case ETH_SS_STATS:
  2014. k = 0;
  2015. if (is_multi(bp)) {
  2016. for_each_eth_queue(bp, i) {
  2017. memset(queue_name, 0, sizeof(queue_name));
  2018. sprintf(queue_name, "%d", i);
  2019. for (j = 0; j < BNX2X_NUM_Q_STATS; j++)
  2020. snprintf(buf + (k + j)*ETH_GSTRING_LEN,
  2021. ETH_GSTRING_LEN,
  2022. bnx2x_q_stats_arr[j].string,
  2023. queue_name);
  2024. k += BNX2X_NUM_Q_STATS;
  2025. }
  2026. }
  2027. for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
  2028. if (IS_MF_MODE_STAT(bp) && IS_PORT_STAT(i))
  2029. continue;
  2030. strcpy(buf + (k + j)*ETH_GSTRING_LEN,
  2031. bnx2x_stats_arr[i].string);
  2032. j++;
  2033. }
  2034. break;
  2035. case ETH_SS_TEST:
  2036. memcpy(buf, bnx2x_tests_str_arr, sizeof(bnx2x_tests_str_arr));
  2037. break;
  2038. }
  2039. }
  2040. static void bnx2x_get_ethtool_stats(struct net_device *dev,
  2041. struct ethtool_stats *stats, u64 *buf)
  2042. {
  2043. struct bnx2x *bp = netdev_priv(dev);
  2044. u32 *hw_stats, *offset;
  2045. int i, j, k = 0;
  2046. if (is_multi(bp)) {
  2047. for_each_eth_queue(bp, i) {
  2048. hw_stats = (u32 *)&bp->fp[i].eth_q_stats;
  2049. for (j = 0; j < BNX2X_NUM_Q_STATS; j++) {
  2050. if (bnx2x_q_stats_arr[j].size == 0) {
  2051. /* skip this counter */
  2052. buf[k + j] = 0;
  2053. continue;
  2054. }
  2055. offset = (hw_stats +
  2056. bnx2x_q_stats_arr[j].offset);
  2057. if (bnx2x_q_stats_arr[j].size == 4) {
  2058. /* 4-byte counter */
  2059. buf[k + j] = (u64) *offset;
  2060. continue;
  2061. }
  2062. /* 8-byte counter */
  2063. buf[k + j] = HILO_U64(*offset, *(offset + 1));
  2064. }
  2065. k += BNX2X_NUM_Q_STATS;
  2066. }
  2067. }
  2068. hw_stats = (u32 *)&bp->eth_stats;
  2069. for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
  2070. if (IS_MF_MODE_STAT(bp) && IS_PORT_STAT(i))
  2071. continue;
  2072. if (bnx2x_stats_arr[i].size == 0) {
  2073. /* skip this counter */
  2074. buf[k + j] = 0;
  2075. j++;
  2076. continue;
  2077. }
  2078. offset = (hw_stats + bnx2x_stats_arr[i].offset);
  2079. if (bnx2x_stats_arr[i].size == 4) {
  2080. /* 4-byte counter */
  2081. buf[k + j] = (u64) *offset;
  2082. j++;
  2083. continue;
  2084. }
  2085. /* 8-byte counter */
  2086. buf[k + j] = HILO_U64(*offset, *(offset + 1));
  2087. j++;
  2088. }
  2089. }
  2090. static int bnx2x_set_phys_id(struct net_device *dev,
  2091. enum ethtool_phys_id_state state)
  2092. {
  2093. struct bnx2x *bp = netdev_priv(dev);
  2094. if (!netif_running(dev)) {
  2095. DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
  2096. "cannot access eeprom when the interface is down\n");
  2097. return -EAGAIN;
  2098. }
  2099. if (!bp->port.pmf) {
  2100. DP(BNX2X_MSG_ETHTOOL, "Interface is not pmf\n");
  2101. return -EOPNOTSUPP;
  2102. }
  2103. switch (state) {
  2104. case ETHTOOL_ID_ACTIVE:
  2105. return 1; /* cycle on/off once per second */
  2106. case ETHTOOL_ID_ON:
  2107. bnx2x_set_led(&bp->link_params, &bp->link_vars,
  2108. LED_MODE_ON, SPEED_1000);
  2109. break;
  2110. case ETHTOOL_ID_OFF:
  2111. bnx2x_set_led(&bp->link_params, &bp->link_vars,
  2112. LED_MODE_FRONT_PANEL_OFF, 0);
  2113. break;
  2114. case ETHTOOL_ID_INACTIVE:
  2115. bnx2x_set_led(&bp->link_params, &bp->link_vars,
  2116. LED_MODE_OPER,
  2117. bp->link_vars.line_speed);
  2118. }
  2119. return 0;
  2120. }
  2121. static int bnx2x_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
  2122. u32 *rules __always_unused)
  2123. {
  2124. struct bnx2x *bp = netdev_priv(dev);
  2125. switch (info->cmd) {
  2126. case ETHTOOL_GRXRINGS:
  2127. info->data = BNX2X_NUM_ETH_QUEUES(bp);
  2128. return 0;
  2129. default:
  2130. DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
  2131. return -EOPNOTSUPP;
  2132. }
  2133. }
  2134. static u32 bnx2x_get_rxfh_indir_size(struct net_device *dev)
  2135. {
  2136. return T_ETH_INDIRECTION_TABLE_SIZE;
  2137. }
  2138. static int bnx2x_get_rxfh_indir(struct net_device *dev, u32 *indir)
  2139. {
  2140. struct bnx2x *bp = netdev_priv(dev);
  2141. u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE] = {0};
  2142. size_t i;
  2143. /* Get the current configuration of the RSS indirection table */
  2144. bnx2x_get_rss_ind_table(&bp->rss_conf_obj, ind_table);
  2145. /*
  2146. * We can't use a memcpy() as an internal storage of an
  2147. * indirection table is a u8 array while indir->ring_index
  2148. * points to an array of u32.
  2149. *
  2150. * Indirection table contains the FW Client IDs, so we need to
  2151. * align the returned table to the Client ID of the leading RSS
  2152. * queue.
  2153. */
  2154. for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++)
  2155. indir[i] = ind_table[i] - bp->fp->cl_id;
  2156. return 0;
  2157. }
  2158. static int bnx2x_set_rxfh_indir(struct net_device *dev, const u32 *indir)
  2159. {
  2160. struct bnx2x *bp = netdev_priv(dev);
  2161. size_t i;
  2162. u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE] = {0};
  2163. for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++) {
  2164. /*
  2165. * The same as in bnx2x_get_rxfh_indir: we can't use a memcpy()
  2166. * as an internal storage of an indirection table is a u8 array
  2167. * while indir->ring_index points to an array of u32.
  2168. *
  2169. * Indirection table contains the FW Client IDs, so we need to
  2170. * align the received table to the Client ID of the leading RSS
  2171. * queue
  2172. */
  2173. ind_table[i] = indir[i] + bp->fp->cl_id;
  2174. }
  2175. return bnx2x_config_rss_eth(bp, ind_table, false);
  2176. }
  2177. static const struct ethtool_ops bnx2x_ethtool_ops = {
  2178. .get_settings = bnx2x_get_settings,
  2179. .set_settings = bnx2x_set_settings,
  2180. .get_drvinfo = bnx2x_get_drvinfo,
  2181. .get_regs_len = bnx2x_get_regs_len,
  2182. .get_regs = bnx2x_get_regs,
  2183. .get_wol = bnx2x_get_wol,
  2184. .set_wol = bnx2x_set_wol,
  2185. .get_msglevel = bnx2x_get_msglevel,
  2186. .set_msglevel = bnx2x_set_msglevel,
  2187. .nway_reset = bnx2x_nway_reset,
  2188. .get_link = bnx2x_get_link,
  2189. .get_eeprom_len = bnx2x_get_eeprom_len,
  2190. .get_eeprom = bnx2x_get_eeprom,
  2191. .set_eeprom = bnx2x_set_eeprom,
  2192. .get_coalesce = bnx2x_get_coalesce,
  2193. .set_coalesce = bnx2x_set_coalesce,
  2194. .get_ringparam = bnx2x_get_ringparam,
  2195. .set_ringparam = bnx2x_set_ringparam,
  2196. .get_pauseparam = bnx2x_get_pauseparam,
  2197. .set_pauseparam = bnx2x_set_pauseparam,
  2198. .self_test = bnx2x_self_test,
  2199. .get_sset_count = bnx2x_get_sset_count,
  2200. .get_strings = bnx2x_get_strings,
  2201. .set_phys_id = bnx2x_set_phys_id,
  2202. .get_ethtool_stats = bnx2x_get_ethtool_stats,
  2203. .get_rxnfc = bnx2x_get_rxnfc,
  2204. .get_rxfh_indir_size = bnx2x_get_rxfh_indir_size,
  2205. .get_rxfh_indir = bnx2x_get_rxfh_indir,
  2206. .set_rxfh_indir = bnx2x_set_rxfh_indir,
  2207. .get_eee = bnx2x_get_eee,
  2208. .set_eee = bnx2x_set_eee,
  2209. };
  2210. void bnx2x_set_ethtool_ops(struct net_device *netdev)
  2211. {
  2212. SET_ETHTOOL_OPS(netdev, &bnx2x_ethtool_ops);
  2213. }