xhci-pci.c 10 KB

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  1. /*
  2. * xHCI host controller driver PCI Bus Glue.
  3. *
  4. * Copyright (C) 2008 Intel Corp.
  5. *
  6. * Author: Sarah Sharp
  7. * Some code borrowed from the Linux EHCI driver.
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License version 2 as
  11. * published by the Free Software Foundation.
  12. *
  13. * This program is distributed in the hope that it will be useful, but
  14. * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15. * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  16. * for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software Foundation,
  20. * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21. */
  22. #include <linux/pci.h>
  23. #include <linux/slab.h>
  24. #include <linux/module.h>
  25. #include "xhci.h"
  26. /* Device for a quirk */
  27. #define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73
  28. #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK 0x1000
  29. #define PCI_VENDOR_ID_ETRON 0x1b6f
  30. #define PCI_DEVICE_ID_ASROCK_P67 0x7023
  31. static const char hcd_name[] = "xhci_hcd";
  32. /* called after powerup, by probe or system-pm "wakeup" */
  33. static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev)
  34. {
  35. /*
  36. * TODO: Implement finding debug ports later.
  37. * TODO: see if there are any quirks that need to be added to handle
  38. * new extended capabilities.
  39. */
  40. /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
  41. if (!pci_set_mwi(pdev))
  42. xhci_dbg(xhci, "MWI active\n");
  43. xhci_dbg(xhci, "Finished xhci_pci_reinit\n");
  44. return 0;
  45. }
  46. static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci)
  47. {
  48. struct pci_dev *pdev = to_pci_dev(dev);
  49. /* Look for vendor-specific quirks */
  50. if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
  51. pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK) {
  52. if (pdev->revision == 0x0) {
  53. xhci->quirks |= XHCI_RESET_EP_QUIRK;
  54. xhci_dbg(xhci, "QUIRK: Fresco Logic xHC needs configure"
  55. " endpoint cmd after reset endpoint\n");
  56. }
  57. /* Fresco Logic confirms: all revisions of this chip do not
  58. * support MSI, even though some of them claim to in their PCI
  59. * capabilities.
  60. */
  61. xhci->quirks |= XHCI_BROKEN_MSI;
  62. xhci_dbg(xhci, "QUIRK: Fresco Logic revision %u "
  63. "has broken MSI implementation\n",
  64. pdev->revision);
  65. xhci->quirks |= XHCI_TRUST_TX_LENGTH;
  66. }
  67. if (pdev->vendor == PCI_VENDOR_ID_NEC)
  68. xhci->quirks |= XHCI_NEC_HOST;
  69. if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96)
  70. xhci->quirks |= XHCI_AMD_0x96_HOST;
  71. /* AMD PLL quirk */
  72. if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_find_chipset_info())
  73. xhci->quirks |= XHCI_AMD_PLL_FIX;
  74. if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
  75. xhci->quirks |= XHCI_LPM_SUPPORT;
  76. xhci->quirks |= XHCI_INTEL_HOST;
  77. }
  78. if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
  79. pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) {
  80. xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
  81. xhci->quirks |= XHCI_EP_LIMIT_QUIRK;
  82. xhci->limit_active_eps = 64;
  83. xhci->quirks |= XHCI_SW_BW_CHECKING;
  84. /*
  85. * PPT desktop boards DH77EB and DH77DF will power back on after
  86. * a few seconds of being shutdown. The fix for this is to
  87. * switch the ports from xHCI to EHCI on shutdown. We can't use
  88. * DMI information to find those particular boards (since each
  89. * vendor will change the board name), so we have to key off all
  90. * PPT chipsets.
  91. */
  92. xhci->quirks |= XHCI_SPURIOUS_REBOOT;
  93. }
  94. if (pdev->vendor == PCI_VENDOR_ID_ETRON &&
  95. pdev->device == PCI_DEVICE_ID_ASROCK_P67) {
  96. xhci->quirks |= XHCI_RESET_ON_RESUME;
  97. xhci_dbg(xhci, "QUIRK: Resetting on resume\n");
  98. xhci->quirks |= XHCI_TRUST_TX_LENGTH;
  99. }
  100. if (pdev->vendor == PCI_VENDOR_ID_VIA)
  101. xhci->quirks |= XHCI_RESET_ON_RESUME;
  102. }
  103. /* called during probe() after chip reset completes */
  104. static int xhci_pci_setup(struct usb_hcd *hcd)
  105. {
  106. struct xhci_hcd *xhci;
  107. struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
  108. int retval;
  109. retval = xhci_gen_setup(hcd, xhci_pci_quirks);
  110. if (retval)
  111. return retval;
  112. xhci = hcd_to_xhci(hcd);
  113. if (!usb_hcd_is_primary_hcd(hcd))
  114. return 0;
  115. pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn);
  116. xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn);
  117. /* Find any debug ports */
  118. retval = xhci_pci_reinit(xhci, pdev);
  119. if (!retval)
  120. return retval;
  121. kfree(xhci);
  122. return retval;
  123. }
  124. /*
  125. * We need to register our own PCI probe function (instead of the USB core's
  126. * function) in order to create a second roothub under xHCI.
  127. */
  128. static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
  129. {
  130. int retval;
  131. struct xhci_hcd *xhci;
  132. struct hc_driver *driver;
  133. struct usb_hcd *hcd;
  134. driver = (struct hc_driver *)id->driver_data;
  135. /* Register the USB 2.0 roothub.
  136. * FIXME: USB core must know to register the USB 2.0 roothub first.
  137. * This is sort of silly, because we could just set the HCD driver flags
  138. * to say USB 2.0, but I'm not sure what the implications would be in
  139. * the other parts of the HCD code.
  140. */
  141. retval = usb_hcd_pci_probe(dev, id);
  142. if (retval)
  143. return retval;
  144. /* USB 2.0 roothub is stored in the PCI device now. */
  145. hcd = dev_get_drvdata(&dev->dev);
  146. xhci = hcd_to_xhci(hcd);
  147. xhci->shared_hcd = usb_create_shared_hcd(driver, &dev->dev,
  148. pci_name(dev), hcd);
  149. if (!xhci->shared_hcd) {
  150. retval = -ENOMEM;
  151. goto dealloc_usb2_hcd;
  152. }
  153. /* Set the xHCI pointer before xhci_pci_setup() (aka hcd_driver.reset)
  154. * is called by usb_add_hcd().
  155. */
  156. *((struct xhci_hcd **) xhci->shared_hcd->hcd_priv) = xhci;
  157. retval = usb_add_hcd(xhci->shared_hcd, dev->irq,
  158. IRQF_SHARED);
  159. if (retval)
  160. goto put_usb3_hcd;
  161. /* Roothub already marked as USB 3.0 speed */
  162. /* We know the LPM timeout algorithms for this host, let the USB core
  163. * enable and disable LPM for devices under the USB 3.0 roothub.
  164. */
  165. if (xhci->quirks & XHCI_LPM_SUPPORT)
  166. hcd_to_bus(xhci->shared_hcd)->root_hub->lpm_capable = 1;
  167. return 0;
  168. put_usb3_hcd:
  169. usb_put_hcd(xhci->shared_hcd);
  170. dealloc_usb2_hcd:
  171. usb_hcd_pci_remove(dev);
  172. return retval;
  173. }
  174. static void xhci_pci_remove(struct pci_dev *dev)
  175. {
  176. struct xhci_hcd *xhci;
  177. xhci = hcd_to_xhci(pci_get_drvdata(dev));
  178. if (xhci->shared_hcd) {
  179. usb_remove_hcd(xhci->shared_hcd);
  180. usb_put_hcd(xhci->shared_hcd);
  181. }
  182. usb_hcd_pci_remove(dev);
  183. kfree(xhci);
  184. }
  185. #ifdef CONFIG_PM
  186. static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
  187. {
  188. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  189. int retval = 0;
  190. if (hcd->state != HC_STATE_SUSPENDED ||
  191. xhci->shared_hcd->state != HC_STATE_SUSPENDED)
  192. return -EINVAL;
  193. retval = xhci_suspend(xhci);
  194. return retval;
  195. }
  196. static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated)
  197. {
  198. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  199. struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
  200. int retval = 0;
  201. /* The BIOS on systems with the Intel Panther Point chipset may or may
  202. * not support xHCI natively. That means that during system resume, it
  203. * may switch the ports back to EHCI so that users can use their
  204. * keyboard to select a kernel from GRUB after resume from hibernate.
  205. *
  206. * The BIOS is supposed to remember whether the OS had xHCI ports
  207. * enabled before resume, and switch the ports back to xHCI when the
  208. * BIOS/OS semaphore is written, but we all know we can't trust BIOS
  209. * writers.
  210. *
  211. * Unconditionally switch the ports back to xHCI after a system resume.
  212. * We can't tell whether the EHCI or xHCI controller will be resumed
  213. * first, so we have to do the port switchover in both drivers. Writing
  214. * a '1' to the port switchover registers should have no effect if the
  215. * port was already switched over.
  216. */
  217. if (usb_is_intel_switchable_xhci(pdev))
  218. usb_enable_xhci_ports(pdev);
  219. retval = xhci_resume(xhci, hibernated);
  220. return retval;
  221. }
  222. #endif /* CONFIG_PM */
  223. static const struct hc_driver xhci_pci_hc_driver = {
  224. .description = hcd_name,
  225. .product_desc = "xHCI Host Controller",
  226. .hcd_priv_size = sizeof(struct xhci_hcd *),
  227. /*
  228. * generic hardware linkage
  229. */
  230. .irq = xhci_irq,
  231. .flags = HCD_MEMORY | HCD_USB3 | HCD_SHARED,
  232. /*
  233. * basic lifecycle operations
  234. */
  235. .reset = xhci_pci_setup,
  236. .start = xhci_run,
  237. #ifdef CONFIG_PM
  238. .pci_suspend = xhci_pci_suspend,
  239. .pci_resume = xhci_pci_resume,
  240. #endif
  241. .stop = xhci_stop,
  242. .shutdown = xhci_shutdown,
  243. /*
  244. * managing i/o requests and associated device resources
  245. */
  246. .urb_enqueue = xhci_urb_enqueue,
  247. .urb_dequeue = xhci_urb_dequeue,
  248. .alloc_dev = xhci_alloc_dev,
  249. .free_dev = xhci_free_dev,
  250. .alloc_streams = xhci_alloc_streams,
  251. .free_streams = xhci_free_streams,
  252. .add_endpoint = xhci_add_endpoint,
  253. .drop_endpoint = xhci_drop_endpoint,
  254. .endpoint_reset = xhci_endpoint_reset,
  255. .check_bandwidth = xhci_check_bandwidth,
  256. .reset_bandwidth = xhci_reset_bandwidth,
  257. .address_device = xhci_address_device,
  258. .update_hub_device = xhci_update_hub_device,
  259. .reset_device = xhci_discover_or_reset_device,
  260. /*
  261. * scheduling support
  262. */
  263. .get_frame_number = xhci_get_frame,
  264. /* Root hub support */
  265. .hub_control = xhci_hub_control,
  266. .hub_status_data = xhci_hub_status_data,
  267. .bus_suspend = xhci_bus_suspend,
  268. .bus_resume = xhci_bus_resume,
  269. /*
  270. * call back when device connected and addressed
  271. */
  272. .update_device = xhci_update_device,
  273. .set_usb2_hw_lpm = xhci_set_usb2_hardware_lpm,
  274. .enable_usb3_lpm_timeout = xhci_enable_usb3_lpm_timeout,
  275. .disable_usb3_lpm_timeout = xhci_disable_usb3_lpm_timeout,
  276. };
  277. /*-------------------------------------------------------------------------*/
  278. /* PCI driver selection metadata; PCI hotplugging uses this */
  279. static const struct pci_device_id pci_ids[] = { {
  280. /* handle any USB 3.0 xHCI controller */
  281. PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0),
  282. .driver_data = (unsigned long) &xhci_pci_hc_driver,
  283. },
  284. { /* end: all zeroes */ }
  285. };
  286. MODULE_DEVICE_TABLE(pci, pci_ids);
  287. /* pci driver glue; this is a "new style" PCI driver module */
  288. static struct pci_driver xhci_pci_driver = {
  289. .name = (char *) hcd_name,
  290. .id_table = pci_ids,
  291. .probe = xhci_pci_probe,
  292. .remove = xhci_pci_remove,
  293. /* suspend and resume implemented later */
  294. .shutdown = usb_hcd_pci_shutdown,
  295. #ifdef CONFIG_PM_SLEEP
  296. .driver = {
  297. .pm = &usb_hcd_pci_pm_ops
  298. },
  299. #endif
  300. };
  301. int __init xhci_register_pci(void)
  302. {
  303. return pci_register_driver(&xhci_pci_driver);
  304. }
  305. void xhci_unregister_pci(void)
  306. {
  307. pci_unregister_driver(&xhci_pci_driver);
  308. }