am335x-evm.dts 8.6 KB

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  1. /*
  2. * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License version 2 as
  6. * published by the Free Software Foundation.
  7. */
  8. /dts-v1/;
  9. #include "am33xx.dtsi"
  10. / {
  11. model = "TI AM335x EVM";
  12. compatible = "ti,am335x-evm", "ti,am33xx";
  13. cpus {
  14. cpu@0 {
  15. cpu0-supply = <&vdd1_reg>;
  16. };
  17. };
  18. memory {
  19. device_type = "memory";
  20. reg = <0x80000000 0x10000000>; /* 256 MB */
  21. };
  22. am33xx_pinmux: pinmux@44e10800 {
  23. pinctrl-names = "default";
  24. pinctrl-0 = <&matrix_keypad_s0 &volume_keys_s0 &clkout2_pin>;
  25. matrix_keypad_s0: matrix_keypad_s0 {
  26. pinctrl-single,pins = <
  27. 0x54 0x7 /* gpmc_a5.gpio1_21, OUTPUT | MODE7 */
  28. 0x58 0x7 /* gpmc_a6.gpio1_22, OUTPUT | MODE7 */
  29. 0x64 0x27 /* gpmc_a9.gpio1_25, INPUT | MODE7 */
  30. 0x68 0x27 /* gpmc_a10.gpio1_26, INPUT | MODE7 */
  31. 0x6c 0x27 /* gpmc_a11.gpio1_27, INPUT | MODE7 */
  32. >;
  33. };
  34. volume_keys_s0: volume_keys_s0 {
  35. pinctrl-single,pins = <
  36. 0x150 0x27 /* spi0_sclk.gpio0_2, INPUT | MODE7 */
  37. 0x154 0x27 /* spi0_d0.gpio0_3, INPUT | MODE7 */
  38. >;
  39. };
  40. i2c0_pins: pinmux_i2c0_pins {
  41. pinctrl-single,pins = <
  42. 0x188 0x30 /* i2c0_sda.i2c0_sda PULLUP | INPUTENABLE | MODE0 */
  43. 0x18c 0x30 /* i2c0_scl.i2c0_scl PULLUP | INPUTENABLE | MODE0 */
  44. >;
  45. };
  46. i2c1_pins: pinmux_i2c1_pins {
  47. pinctrl-single,pins = <
  48. 0x158 0x32 /* spi0_d1.i2c1_sda PULLUP | INPUTENABLE | MODE2 */
  49. 0x15c 0x32 /* spi0_cs0.i2c1_scl PULLUP | INPUTENABLE | MODE2 */
  50. >;
  51. };
  52. uart0_pins: pinmux_uart0_pins {
  53. pinctrl-single,pins = <
  54. 0x170 0x30 /* uart0_rxd.uart0_rxd PULLUP | INPUTENABLE | MODE0 */
  55. 0x174 0x00 /* uart0_txd.uart0_txd PULLDOWN | MODE0 */
  56. >;
  57. };
  58. clkout2_pin: pinmux_clkout2_pin {
  59. pinctrl-single,pins = <
  60. 0x1b4 0x03 /* xdma_event_intr1.clkout2 OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT */
  61. >;
  62. };
  63. nandflash_pins_s0: nandflash_pins_s0 {
  64. pinctrl-single,pins = <
  65. 0x0 0x30 /* gpmc_ad0.gpmc_ad0, INPUT | PULLUP | MODE0 */
  66. 0x4 0x30 /* gpmc_ad1.gpmc_ad1, INPUT | PULLUP | MODE0 */
  67. 0x8 0x30 /* gpmc_ad2.gpmc_ad2, INPUT | PULLUP | MODE0 */
  68. 0xc 0x30 /* gpmc_ad3.gpmc_ad3, INPUT | PULLUP | MODE0 */
  69. 0x10 0x30 /* gpmc_ad4.gpmc_ad4, INPUT | PULLUP | MODE0 */
  70. 0x14 0x30 /* gpmc_ad5.gpmc_ad5, INPUT | PULLUP | MODE0 */
  71. 0x18 0x30 /* gpmc_ad6.gpmc_ad6, INPUT | PULLUP | MODE0 */
  72. 0x1c 0x30 /* gpmc_ad7.gpmc_ad7, INPUT | PULLUP | MODE0 */
  73. 0x70 0x30 /* gpmc_wait0.gpmc_wait0, INPUT | PULLUP | MODE0 */
  74. 0x74 0x37 /* gpmc_wpn.gpio0_30, INPUT | PULLUP | MODE7 */
  75. 0x7c 0x8 /* gpmc_csn0.gpmc_csn0, PULL DISA */
  76. 0x90 0x8 /* gpmc_advn_ale.gpmc_advn_ale, PULL DISA */
  77. 0x94 0x8 /* gpmc_oen_ren.gpmc_oen_ren, PULL DISA */
  78. 0x98 0x8 /* gpmc_wen.gpmc_wen, PULL DISA */
  79. 0x9c 0x8 /* gpmc_be0n_cle.gpmc_be0n_cle, PULL DISA */
  80. >;
  81. };
  82. };
  83. ocp {
  84. uart0: serial@44e09000 {
  85. pinctrl-names = "default";
  86. pinctrl-0 = <&uart0_pins>;
  87. status = "okay";
  88. };
  89. i2c0: i2c@44e0b000 {
  90. pinctrl-names = "default";
  91. pinctrl-0 = <&i2c0_pins>;
  92. status = "okay";
  93. clock-frequency = <400000>;
  94. tps: tps@2d {
  95. reg = <0x2d>;
  96. };
  97. };
  98. i2c1: i2c@4802a000 {
  99. pinctrl-names = "default";
  100. pinctrl-0 = <&i2c1_pins>;
  101. status = "okay";
  102. clock-frequency = <100000>;
  103. lis331dlh: lis331dlh@18 {
  104. compatible = "st,lis331dlh", "st,lis3lv02d";
  105. reg = <0x18>;
  106. Vdd-supply = <&lis3_reg>;
  107. Vdd_IO-supply = <&lis3_reg>;
  108. st,click-single-x;
  109. st,click-single-y;
  110. st,click-single-z;
  111. st,click-thresh-x = <10>;
  112. st,click-thresh-y = <10>;
  113. st,click-thresh-z = <10>;
  114. st,irq1-click;
  115. st,irq2-click;
  116. st,wakeup-x-lo;
  117. st,wakeup-x-hi;
  118. st,wakeup-y-lo;
  119. st,wakeup-y-hi;
  120. st,wakeup-z-lo;
  121. st,wakeup-z-hi;
  122. st,min-limit-x = <120>;
  123. st,min-limit-y = <120>;
  124. st,min-limit-z = <140>;
  125. st,max-limit-x = <550>;
  126. st,max-limit-y = <550>;
  127. st,max-limit-z = <750>;
  128. };
  129. tsl2550: tsl2550@39 {
  130. compatible = "taos,tsl2550";
  131. reg = <0x39>;
  132. };
  133. tmp275: tmp275@48 {
  134. compatible = "ti,tmp275";
  135. reg = <0x48>;
  136. };
  137. };
  138. elm: elm@48080000 {
  139. status = "okay";
  140. };
  141. gpmc: gpmc@50000000 {
  142. status = "okay";
  143. pinctrl-names = "default";
  144. pinctrl-0 = <&nandflash_pins_s0>;
  145. ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */
  146. nand@0,0 {
  147. reg = <0 0 0>; /* CS0, offset 0 */
  148. nand-bus-width = <8>;
  149. ti,nand-ecc-opt = "bch8";
  150. gpmc,device-nand = "true";
  151. gpmc,device-width = <1>;
  152. gpmc,sync-clk-ps = <0>;
  153. gpmc,cs-on-ns = <0>;
  154. gpmc,cs-rd-off-ns = <44>;
  155. gpmc,cs-wr-off-ns = <44>;
  156. gpmc,adv-on-ns = <6>;
  157. gpmc,adv-rd-off-ns = <34>;
  158. gpmc,adv-wr-off-ns = <44>;
  159. gpmc,we-on-ns = <0>;
  160. gpmc,we-off-ns = <40>;
  161. gpmc,oe-on-ns = <0>;
  162. gpmc,oe-off-ns = <54>;
  163. gpmc,access-ns = <64>;
  164. gpmc,rd-cycle-ns = <82>;
  165. gpmc,wr-cycle-ns = <82>;
  166. gpmc,wait-on-read = "true";
  167. gpmc,wait-on-write = "true";
  168. gpmc,bus-turnaround-ns = <0>;
  169. gpmc,cycle2cycle-delay-ns = <0>;
  170. gpmc,clk-activation-ns = <0>;
  171. gpmc,wait-monitoring-ns = <0>;
  172. gpmc,wr-access-ns = <40>;
  173. gpmc,wr-data-mux-bus-ns = <0>;
  174. #address-cells = <1>;
  175. #size-cells = <1>;
  176. elm_id = <&elm>;
  177. /* MTD partition table */
  178. partition@0 {
  179. label = "SPL1";
  180. reg = <0x00000000 0x000020000>;
  181. };
  182. partition@1 {
  183. label = "SPL2";
  184. reg = <0x00020000 0x00020000>;
  185. };
  186. partition@2 {
  187. label = "SPL3";
  188. reg = <0x00040000 0x00020000>;
  189. };
  190. partition@3 {
  191. label = "SPL4";
  192. reg = <0x00060000 0x00020000>;
  193. };
  194. partition@4 {
  195. label = "U-boot";
  196. reg = <0x00080000 0x001e0000>;
  197. };
  198. partition@5 {
  199. label = "environment";
  200. reg = <0x00260000 0x00020000>;
  201. };
  202. partition@6 {
  203. label = "Kernel";
  204. reg = <0x00280000 0x00500000>;
  205. };
  206. partition@7 {
  207. label = "File-System";
  208. reg = <0x00780000 0x0F880000>;
  209. };
  210. };
  211. };
  212. };
  213. vbat: fixedregulator@0 {
  214. compatible = "regulator-fixed";
  215. regulator-name = "vbat";
  216. regulator-min-microvolt = <5000000>;
  217. regulator-max-microvolt = <5000000>;
  218. regulator-boot-on;
  219. };
  220. lis3_reg: fixedregulator@1 {
  221. compatible = "regulator-fixed";
  222. regulator-name = "lis3_reg";
  223. regulator-boot-on;
  224. };
  225. matrix_keypad: matrix_keypad@0 {
  226. compatible = "gpio-matrix-keypad";
  227. debounce-delay-ms = <5>;
  228. col-scan-delay-us = <2>;
  229. row-gpios = <&gpio1 25 GPIO_ACTIVE_HIGH /* Bank1, pin25 */
  230. &gpio1 26 GPIO_ACTIVE_HIGH /* Bank1, pin26 */
  231. &gpio1 27 GPIO_ACTIVE_HIGH>; /* Bank1, pin27 */
  232. col-gpios = <&gpio1 21 GPIO_ACTIVE_HIGH /* Bank1, pin21 */
  233. &gpio1 22 GPIO_ACTIVE_HIGH>; /* Bank1, pin22 */
  234. linux,keymap = <0x0000008b /* MENU */
  235. 0x0100009e /* BACK */
  236. 0x02000069 /* LEFT */
  237. 0x0001006a /* RIGHT */
  238. 0x0101001c /* ENTER */
  239. 0x0201006c>; /* DOWN */
  240. };
  241. gpio_keys: volume_keys@0 {
  242. compatible = "gpio-keys";
  243. #address-cells = <1>;
  244. #size-cells = <0>;
  245. autorepeat;
  246. switch@9 {
  247. label = "volume-up";
  248. linux,code = <115>;
  249. gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
  250. gpio-key,wakeup;
  251. };
  252. switch@10 {
  253. label = "volume-down";
  254. linux,code = <114>;
  255. gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
  256. gpio-key,wakeup;
  257. };
  258. };
  259. };
  260. #include "tps65910.dtsi"
  261. &tps {
  262. vcc1-supply = <&vbat>;
  263. vcc2-supply = <&vbat>;
  264. vcc3-supply = <&vbat>;
  265. vcc4-supply = <&vbat>;
  266. vcc5-supply = <&vbat>;
  267. vcc6-supply = <&vbat>;
  268. vcc7-supply = <&vbat>;
  269. vccio-supply = <&vbat>;
  270. regulators {
  271. vrtc_reg: regulator@0 {
  272. regulator-always-on;
  273. };
  274. vio_reg: regulator@1 {
  275. regulator-always-on;
  276. };
  277. vdd1_reg: regulator@2 {
  278. /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
  279. regulator-name = "vdd_mpu";
  280. regulator-min-microvolt = <912500>;
  281. regulator-max-microvolt = <1312500>;
  282. regulator-boot-on;
  283. regulator-always-on;
  284. };
  285. vdd2_reg: regulator@3 {
  286. /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
  287. regulator-name = "vdd_core";
  288. regulator-min-microvolt = <912500>;
  289. regulator-max-microvolt = <1150000>;
  290. regulator-boot-on;
  291. regulator-always-on;
  292. };
  293. vdd3_reg: regulator@4 {
  294. regulator-always-on;
  295. };
  296. vdig1_reg: regulator@5 {
  297. regulator-always-on;
  298. };
  299. vdig2_reg: regulator@6 {
  300. regulator-always-on;
  301. };
  302. vpll_reg: regulator@7 {
  303. regulator-always-on;
  304. };
  305. vdac_reg: regulator@8 {
  306. regulator-always-on;
  307. };
  308. vaux1_reg: regulator@9 {
  309. regulator-always-on;
  310. };
  311. vaux2_reg: regulator@10 {
  312. regulator-always-on;
  313. };
  314. vaux33_reg: regulator@11 {
  315. regulator-always-on;
  316. };
  317. vmmc_reg: regulator@12 {
  318. regulator-always-on;
  319. };
  320. };
  321. };
  322. &cpsw_emac0 {
  323. phy_id = <&davinci_mdio>, <0>;
  324. };
  325. &cpsw_emac1 {
  326. phy_id = <&davinci_mdio>, <1>;
  327. };