mach-qt2410.c 8.2 KB

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  1. /* linux/arch/arm/mach-s3c2410/mach-qt2410.c
  2. *
  3. * Copyright (C) 2006 by OpenMoko, Inc.
  4. * Author: Harald Welte <laforge@openmoko.org>
  5. * All rights reserved.
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License as
  9. * published by the Free Software Foundation; either version 2 of
  10. * the License, or (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20. * MA 02111-1307 USA
  21. *
  22. */
  23. #include <linux/kernel.h>
  24. #include <linux/types.h>
  25. #include <linux/interrupt.h>
  26. #include <linux/list.h>
  27. #include <linux/timer.h>
  28. #include <linux/init.h>
  29. #include <linux/sysdev.h>
  30. #include <linux/platform_device.h>
  31. #include <linux/serial_core.h>
  32. #include <linux/spi/spi.h>
  33. #include <linux/spi/spi_bitbang.h>
  34. #include <linux/mtd/mtd.h>
  35. #include <linux/mtd/nand.h>
  36. #include <linux/mtd/nand_ecc.h>
  37. #include <linux/mtd/partitions.h>
  38. #include <asm/mach/arch.h>
  39. #include <asm/mach/map.h>
  40. #include <asm/mach/irq.h>
  41. #include <asm/hardware.h>
  42. #include <asm/io.h>
  43. #include <asm/irq.h>
  44. #include <asm/mach-types.h>
  45. #include <asm/arch/regs-gpio.h>
  46. #include <asm/arch/leds-gpio.h>
  47. #include <asm/plat-s3c/regs-serial.h>
  48. #include <asm/arch/fb.h>
  49. #include <asm/plat-s3c/nand.h>
  50. #include <asm/plat-s3c24xx/udc.h>
  51. #include <asm/arch/spi.h>
  52. #include <asm/arch/spi-gpio.h>
  53. #include <asm/plat-s3c24xx/common-smdk.h>
  54. #include <asm/plat-s3c24xx/devs.h>
  55. #include <asm/plat-s3c24xx/cpu.h>
  56. #include <asm/plat-s3c24xx/pm.h>
  57. static struct map_desc qt2410_iodesc[] __initdata = {
  58. { 0xe0000000, __phys_to_pfn(S3C2410_CS3+0x01000000), SZ_1M, MT_DEVICE }
  59. };
  60. #define UCON S3C2410_UCON_DEFAULT
  61. #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
  62. #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
  63. static struct s3c2410_uartcfg smdk2410_uartcfgs[] = {
  64. [0] = {
  65. .hwport = 0,
  66. .flags = 0,
  67. .ucon = UCON,
  68. .ulcon = ULCON,
  69. .ufcon = UFCON,
  70. },
  71. [1] = {
  72. .hwport = 1,
  73. .flags = 0,
  74. .ucon = UCON,
  75. .ulcon = ULCON,
  76. .ufcon = UFCON,
  77. },
  78. [2] = {
  79. .hwport = 2,
  80. .flags = 0,
  81. .ucon = UCON,
  82. .ulcon = ULCON,
  83. .ufcon = UFCON,
  84. }
  85. };
  86. /* LCD driver info */
  87. static struct s3c2410fb_display qt2410_lcd_cfg[] __initdata = {
  88. {
  89. /* Configuration for 640x480 SHARP LQ080V3DG01 */
  90. .lcdcon1 = S3C2410_LCDCON1_TFT16BPP |
  91. S3C2410_LCDCON1_TFT |
  92. S3C2410_LCDCON1_CLKVAL(0x01), /* HCLK/4 */
  93. .lcdcon5 = S3C2410_LCDCON5_FRM565 |
  94. S3C2410_LCDCON5_INVVLINE |
  95. S3C2410_LCDCON5_INVVFRAME |
  96. S3C2410_LCDCON5_PWREN |
  97. S3C2410_LCDCON5_HWSWP,
  98. .type = S3C2410_LCDCON1_TFT,
  99. .width = 640,
  100. .height = 480,
  101. .xres = 640,
  102. .yres = 480,
  103. .bpp = 16,
  104. .left_margin = 44,
  105. .right_margin = 116,
  106. .hsync_len = 96,
  107. .upper_margin = 19,
  108. .lower_margin = 11,
  109. .vsync_len = 15,
  110. },
  111. {
  112. /* Configuration for 480x640 toppoly TD028TTEC1 */
  113. .lcdcon1 = S3C2410_LCDCON1_TFT16BPP |
  114. S3C2410_LCDCON1_TFT |
  115. S3C2410_LCDCON1_CLKVAL(0x01), /* HCLK/4 */
  116. .lcdcon5 = S3C2410_LCDCON5_FRM565 |
  117. S3C2410_LCDCON5_INVVLINE |
  118. S3C2410_LCDCON5_INVVFRAME |
  119. S3C2410_LCDCON5_PWREN |
  120. S3C2410_LCDCON5_HWSWP,
  121. .type = S3C2410_LCDCON1_TFT,
  122. .width = 480,
  123. .height = 640,
  124. .xres = 480,
  125. .yres = 640,
  126. .bpp = 16,
  127. .left_margin = 8,
  128. .right_margin = 24,
  129. .hsync_len = 8,
  130. .upper_margin = 2,
  131. .lower_margin = 4,
  132. .vsync_len = 2,
  133. },
  134. {
  135. /* Config for 240x320 LCD */
  136. .lcdcon1 = S3C2410_LCDCON1_TFT16BPP |
  137. S3C2410_LCDCON1_TFT |
  138. S3C2410_LCDCON1_CLKVAL(0x04),
  139. .lcdcon5 = S3C2410_LCDCON5_FRM565 |
  140. S3C2410_LCDCON5_INVVLINE |
  141. S3C2410_LCDCON5_INVVFRAME |
  142. S3C2410_LCDCON5_PWREN |
  143. S3C2410_LCDCON5_HWSWP,
  144. .type = S3C2410_LCDCON1_TFT,
  145. .width = 240,
  146. .height = 320,
  147. .xres = 240,
  148. .yres = 320,
  149. .bpp = 16,
  150. .left_margin = 13,
  151. .right_margin = 8,
  152. .hsync_len = 4,
  153. .upper_margin = 2,
  154. .lower_margin = 7,
  155. .vsync_len = 4,
  156. },
  157. };
  158. static struct s3c2410fb_mach_info qt2410_fb_info __initdata = {
  159. .displays = qt2410_lcd_cfg,
  160. .num_displays = ARRAY_SIZE(qt2410_lcd_cfg),
  161. .default_display = 0,
  162. .lpcsel = ((0xCE6) & ~7) | 1<<4,
  163. };
  164. /* CS8900 */
  165. static struct resource qt2410_cs89x0_resources[] = {
  166. [0] = {
  167. .start = 0x19000000,
  168. .end = 0x19000000 + 16,
  169. .flags = IORESOURCE_MEM,
  170. },
  171. [1] = {
  172. .start = IRQ_EINT9,
  173. .end = IRQ_EINT9,
  174. .flags = IORESOURCE_IRQ,
  175. },
  176. };
  177. static struct platform_device qt2410_cs89x0 = {
  178. .name = "cirrus-cs89x0",
  179. .num_resources = ARRAY_SIZE(qt2410_cs89x0_resources),
  180. .resource = qt2410_cs89x0_resources,
  181. };
  182. /* LED */
  183. static struct s3c24xx_led_platdata qt2410_pdata_led = {
  184. .gpio = S3C2410_GPB0,
  185. .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE,
  186. .name = "led",
  187. .def_trigger = "timer",
  188. };
  189. static struct platform_device qt2410_led = {
  190. .name = "s3c24xx_led",
  191. .id = 0,
  192. .dev = {
  193. .platform_data = &qt2410_pdata_led,
  194. },
  195. };
  196. /* SPI */
  197. static void spi_gpio_cs(struct s3c2410_spigpio_info *spi, int cs)
  198. {
  199. switch (cs) {
  200. case BITBANG_CS_ACTIVE:
  201. s3c2410_gpio_setpin(S3C2410_GPB5, 0);
  202. break;
  203. case BITBANG_CS_INACTIVE:
  204. s3c2410_gpio_setpin(S3C2410_GPB5, 1);
  205. break;
  206. }
  207. }
  208. static struct s3c2410_spigpio_info spi_gpio_cfg = {
  209. .pin_clk = S3C2410_GPG7,
  210. .pin_mosi = S3C2410_GPG6,
  211. .pin_miso = S3C2410_GPG5,
  212. .chip_select = &spi_gpio_cs,
  213. };
  214. static struct platform_device qt2410_spi = {
  215. .name = "s3c24xx-spi-gpio",
  216. .id = 1,
  217. .dev = {
  218. .platform_data = &spi_gpio_cfg,
  219. },
  220. };
  221. /* Board devices */
  222. static struct platform_device *qt2410_devices[] __initdata = {
  223. &s3c_device_usb,
  224. &s3c_device_lcd,
  225. &s3c_device_wdt,
  226. &s3c_device_i2c,
  227. &s3c_device_iis,
  228. &s3c_device_sdi,
  229. &s3c_device_usbgadget,
  230. &qt2410_spi,
  231. &qt2410_cs89x0,
  232. &qt2410_led,
  233. };
  234. static struct mtd_partition qt2410_nand_part[] = {
  235. [0] = {
  236. .name = "U-Boot",
  237. .size = 0x30000,
  238. .offset = 0,
  239. },
  240. [1] = {
  241. .name = "U-Boot environment",
  242. .offset = 0x30000,
  243. .size = 0x4000,
  244. },
  245. [2] = {
  246. .name = "kernel",
  247. .offset = 0x34000,
  248. .size = SZ_2M,
  249. },
  250. [3] = {
  251. .name = "initrd",
  252. .offset = 0x234000,
  253. .size = SZ_4M,
  254. },
  255. [4] = {
  256. .name = "jffs2",
  257. .offset = 0x634000,
  258. .size = 0x39cc000,
  259. },
  260. };
  261. static struct s3c2410_nand_set qt2410_nand_sets[] = {
  262. [0] = {
  263. .name = "NAND",
  264. .nr_chips = 1,
  265. .nr_partitions = ARRAY_SIZE(qt2410_nand_part),
  266. .partitions = qt2410_nand_part,
  267. },
  268. };
  269. /* choose a set of timings which should suit most 512Mbit
  270. * chips and beyond.
  271. */
  272. static struct s3c2410_platform_nand qt2410_nand_info = {
  273. .tacls = 20,
  274. .twrph0 = 60,
  275. .twrph1 = 20,
  276. .nr_sets = ARRAY_SIZE(qt2410_nand_sets),
  277. .sets = qt2410_nand_sets,
  278. };
  279. /* UDC */
  280. static struct s3c2410_udc_mach_info qt2410_udc_cfg = {
  281. };
  282. static char tft_type = 's';
  283. static int __init qt2410_tft_setup(char *str)
  284. {
  285. tft_type = str[0];
  286. return 1;
  287. }
  288. __setup("tft=", qt2410_tft_setup);
  289. static void __init qt2410_map_io(void)
  290. {
  291. s3c24xx_init_io(qt2410_iodesc, ARRAY_SIZE(qt2410_iodesc));
  292. s3c24xx_init_clocks(12*1000*1000);
  293. s3c24xx_init_uarts(smdk2410_uartcfgs, ARRAY_SIZE(smdk2410_uartcfgs));
  294. }
  295. static void __init qt2410_machine_init(void)
  296. {
  297. s3c_device_nand.dev.platform_data = &qt2410_nand_info;
  298. switch (tft_type) {
  299. case 'p': /* production */
  300. qt2410_fb_info.default_display = 1;
  301. break;
  302. case 'b': /* big */
  303. qt2410_fb_info.default_display = 0;
  304. break;
  305. case 's': /* small */
  306. default:
  307. qt2410_fb_info.default_display = 2;
  308. break;
  309. }
  310. s3c24xx_fb_set_platdata(&qt2410_fb_info);
  311. s3c2410_gpio_cfgpin(S3C2410_GPB0, S3C2410_GPIO_OUTPUT);
  312. s3c2410_gpio_setpin(S3C2410_GPB0, 1);
  313. s3c24xx_udc_set_platdata(&qt2410_udc_cfg);
  314. s3c2410_gpio_cfgpin(S3C2410_GPB5, S3C2410_GPIO_OUTPUT);
  315. platform_add_devices(qt2410_devices, ARRAY_SIZE(qt2410_devices));
  316. s3c2410_pm_init();
  317. }
  318. MACHINE_START(QT2410, "QT2410")
  319. .phys_io = S3C2410_PA_UART,
  320. .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
  321. .boot_params = S3C2410_SDRAM_PA + 0x100,
  322. .map_io = qt2410_map_io,
  323. .init_irq = s3c24xx_init_irq,
  324. .init_machine = qt2410_machine_init,
  325. .timer = &s3c24xx_timer,
  326. MACHINE_END