sdhci.c 36 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512
  1. /*
  2. * linux/drivers/mmc/sdhci.c - Secure Digital Host Controller Interface driver
  3. *
  4. * Copyright (C) 2005-2006 Pierre Ossman, All Rights Reserved.
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or (at
  9. * your option) any later version.
  10. */
  11. #include <linux/delay.h>
  12. #include <linux/highmem.h>
  13. #include <linux/pci.h>
  14. #include <linux/dma-mapping.h>
  15. #include <linux/mmc/host.h>
  16. #include <linux/mmc/protocol.h>
  17. #include <asm/scatterlist.h>
  18. #include "sdhci.h"
  19. #define DRIVER_NAME "sdhci"
  20. #define DRIVER_VERSION "0.12"
  21. #define BUGMAIL "<sdhci-devel@list.drzeus.cx>"
  22. #define DBG(f, x...) \
  23. pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
  24. static unsigned int debug_nodma = 0;
  25. static unsigned int debug_forcedma = 0;
  26. static unsigned int debug_quirks = 0;
  27. #define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1<<0)
  28. #define SDHCI_QUIRK_FORCE_DMA (1<<1)
  29. static const struct pci_device_id pci_ids[] __devinitdata = {
  30. {
  31. .vendor = PCI_VENDOR_ID_RICOH,
  32. .device = PCI_DEVICE_ID_RICOH_R5C822,
  33. .subvendor = PCI_VENDOR_ID_IBM,
  34. .subdevice = PCI_ANY_ID,
  35. .driver_data = SDHCI_QUIRK_CLOCK_BEFORE_RESET |
  36. SDHCI_QUIRK_FORCE_DMA,
  37. },
  38. {
  39. .vendor = PCI_VENDOR_ID_RICOH,
  40. .device = PCI_DEVICE_ID_RICOH_R5C822,
  41. .subvendor = PCI_ANY_ID,
  42. .subdevice = PCI_ANY_ID,
  43. .driver_data = SDHCI_QUIRK_FORCE_DMA,
  44. },
  45. {
  46. .vendor = PCI_VENDOR_ID_TI,
  47. .device = PCI_DEVICE_ID_TI_XX21_XX11_SD,
  48. .subvendor = PCI_ANY_ID,
  49. .subdevice = PCI_ANY_ID,
  50. .driver_data = SDHCI_QUIRK_FORCE_DMA,
  51. },
  52. { /* Generic SD host controller */
  53. PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00)
  54. },
  55. { /* end: all zeroes */ },
  56. };
  57. MODULE_DEVICE_TABLE(pci, pci_ids);
  58. static void sdhci_prepare_data(struct sdhci_host *, struct mmc_data *);
  59. static void sdhci_finish_data(struct sdhci_host *);
  60. static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
  61. static void sdhci_finish_command(struct sdhci_host *);
  62. static void sdhci_dumpregs(struct sdhci_host *host)
  63. {
  64. printk(KERN_DEBUG DRIVER_NAME ": ============== REGISTER DUMP ==============\n");
  65. printk(KERN_DEBUG DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
  66. readl(host->ioaddr + SDHCI_DMA_ADDRESS),
  67. readw(host->ioaddr + SDHCI_HOST_VERSION));
  68. printk(KERN_DEBUG DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
  69. readw(host->ioaddr + SDHCI_BLOCK_SIZE),
  70. readw(host->ioaddr + SDHCI_BLOCK_COUNT));
  71. printk(KERN_DEBUG DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
  72. readl(host->ioaddr + SDHCI_ARGUMENT),
  73. readw(host->ioaddr + SDHCI_TRANSFER_MODE));
  74. printk(KERN_DEBUG DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
  75. readl(host->ioaddr + SDHCI_PRESENT_STATE),
  76. readb(host->ioaddr + SDHCI_HOST_CONTROL));
  77. printk(KERN_DEBUG DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
  78. readb(host->ioaddr + SDHCI_POWER_CONTROL),
  79. readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL));
  80. printk(KERN_DEBUG DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
  81. readb(host->ioaddr + SDHCI_WALK_UP_CONTROL),
  82. readw(host->ioaddr + SDHCI_CLOCK_CONTROL));
  83. printk(KERN_DEBUG DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
  84. readb(host->ioaddr + SDHCI_TIMEOUT_CONTROL),
  85. readl(host->ioaddr + SDHCI_INT_STATUS));
  86. printk(KERN_DEBUG DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
  87. readl(host->ioaddr + SDHCI_INT_ENABLE),
  88. readl(host->ioaddr + SDHCI_SIGNAL_ENABLE));
  89. printk(KERN_DEBUG DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
  90. readw(host->ioaddr + SDHCI_ACMD12_ERR),
  91. readw(host->ioaddr + SDHCI_SLOT_INT_STATUS));
  92. printk(KERN_DEBUG DRIVER_NAME ": Caps: 0x%08x | Max curr: 0x%08x\n",
  93. readl(host->ioaddr + SDHCI_CAPABILITIES),
  94. readl(host->ioaddr + SDHCI_MAX_CURRENT));
  95. printk(KERN_DEBUG DRIVER_NAME ": ===========================================\n");
  96. }
  97. /*****************************************************************************\
  98. * *
  99. * Low level functions *
  100. * *
  101. \*****************************************************************************/
  102. static void sdhci_reset(struct sdhci_host *host, u8 mask)
  103. {
  104. unsigned long timeout;
  105. writeb(mask, host->ioaddr + SDHCI_SOFTWARE_RESET);
  106. if (mask & SDHCI_RESET_ALL)
  107. host->clock = 0;
  108. /* Wait max 100 ms */
  109. timeout = 100;
  110. /* hw clears the bit when it's done */
  111. while (readb(host->ioaddr + SDHCI_SOFTWARE_RESET) & mask) {
  112. if (timeout == 0) {
  113. printk(KERN_ERR "%s: Reset 0x%x never completed. "
  114. "Please report this to " BUGMAIL ".\n",
  115. mmc_hostname(host->mmc), (int)mask);
  116. sdhci_dumpregs(host);
  117. return;
  118. }
  119. timeout--;
  120. mdelay(1);
  121. }
  122. }
  123. static void sdhci_init(struct sdhci_host *host)
  124. {
  125. u32 intmask;
  126. sdhci_reset(host, SDHCI_RESET_ALL);
  127. intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
  128. SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
  129. SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
  130. SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT |
  131. SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL |
  132. SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE;
  133. writel(intmask, host->ioaddr + SDHCI_INT_ENABLE);
  134. writel(intmask, host->ioaddr + SDHCI_SIGNAL_ENABLE);
  135. }
  136. static void sdhci_activate_led(struct sdhci_host *host)
  137. {
  138. u8 ctrl;
  139. ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
  140. ctrl |= SDHCI_CTRL_LED;
  141. writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
  142. }
  143. static void sdhci_deactivate_led(struct sdhci_host *host)
  144. {
  145. u8 ctrl;
  146. ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
  147. ctrl &= ~SDHCI_CTRL_LED;
  148. writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
  149. }
  150. /*****************************************************************************\
  151. * *
  152. * Core functions *
  153. * *
  154. \*****************************************************************************/
  155. static inline char* sdhci_kmap_sg(struct sdhci_host* host)
  156. {
  157. host->mapped_sg = kmap_atomic(host->cur_sg->page, KM_BIO_SRC_IRQ);
  158. return host->mapped_sg + host->cur_sg->offset;
  159. }
  160. static inline void sdhci_kunmap_sg(struct sdhci_host* host)
  161. {
  162. kunmap_atomic(host->mapped_sg, KM_BIO_SRC_IRQ);
  163. }
  164. static inline int sdhci_next_sg(struct sdhci_host* host)
  165. {
  166. /*
  167. * Skip to next SG entry.
  168. */
  169. host->cur_sg++;
  170. host->num_sg--;
  171. /*
  172. * Any entries left?
  173. */
  174. if (host->num_sg > 0) {
  175. host->offset = 0;
  176. host->remain = host->cur_sg->length;
  177. }
  178. return host->num_sg;
  179. }
  180. static void sdhci_read_block_pio(struct sdhci_host *host)
  181. {
  182. int blksize, chunk_remain;
  183. u32 data;
  184. char *buffer;
  185. int size;
  186. DBG("PIO reading\n");
  187. blksize = host->data->blksz;
  188. chunk_remain = 0;
  189. data = 0;
  190. buffer = sdhci_kmap_sg(host) + host->offset;
  191. while (blksize) {
  192. if (chunk_remain == 0) {
  193. data = readl(host->ioaddr + SDHCI_BUFFER);
  194. chunk_remain = min(blksize, 4);
  195. }
  196. size = min(host->size, host->remain);
  197. size = min(size, chunk_remain);
  198. chunk_remain -= size;
  199. blksize -= size;
  200. host->offset += size;
  201. host->remain -= size;
  202. host->size -= size;
  203. while (size) {
  204. *buffer = data & 0xFF;
  205. buffer++;
  206. data >>= 8;
  207. size--;
  208. }
  209. if (host->remain == 0) {
  210. sdhci_kunmap_sg(host);
  211. if (sdhci_next_sg(host) == 0) {
  212. BUG_ON(blksize != 0);
  213. return;
  214. }
  215. buffer = sdhci_kmap_sg(host);
  216. }
  217. }
  218. sdhci_kunmap_sg(host);
  219. }
  220. static void sdhci_write_block_pio(struct sdhci_host *host)
  221. {
  222. int blksize, chunk_remain;
  223. u32 data;
  224. char *buffer;
  225. int bytes, size;
  226. DBG("PIO writing\n");
  227. blksize = host->data->blksz;
  228. chunk_remain = 4;
  229. data = 0;
  230. bytes = 0;
  231. buffer = sdhci_kmap_sg(host) + host->offset;
  232. while (blksize) {
  233. size = min(host->size, host->remain);
  234. size = min(size, chunk_remain);
  235. chunk_remain -= size;
  236. blksize -= size;
  237. host->offset += size;
  238. host->remain -= size;
  239. host->size -= size;
  240. while (size) {
  241. data >>= 8;
  242. data |= (u32)*buffer << 24;
  243. buffer++;
  244. size--;
  245. }
  246. if (chunk_remain == 0) {
  247. writel(data, host->ioaddr + SDHCI_BUFFER);
  248. chunk_remain = min(blksize, 4);
  249. }
  250. if (host->remain == 0) {
  251. sdhci_kunmap_sg(host);
  252. if (sdhci_next_sg(host) == 0) {
  253. BUG_ON(blksize != 0);
  254. return;
  255. }
  256. buffer = sdhci_kmap_sg(host);
  257. }
  258. }
  259. sdhci_kunmap_sg(host);
  260. }
  261. static void sdhci_transfer_pio(struct sdhci_host *host)
  262. {
  263. u32 mask;
  264. BUG_ON(!host->data);
  265. if (host->size == 0)
  266. return;
  267. if (host->data->flags & MMC_DATA_READ)
  268. mask = SDHCI_DATA_AVAILABLE;
  269. else
  270. mask = SDHCI_SPACE_AVAILABLE;
  271. while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) {
  272. if (host->data->flags & MMC_DATA_READ)
  273. sdhci_read_block_pio(host);
  274. else
  275. sdhci_write_block_pio(host);
  276. if (host->size == 0)
  277. break;
  278. BUG_ON(host->num_sg == 0);
  279. }
  280. DBG("PIO transfer complete.\n");
  281. }
  282. static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data)
  283. {
  284. u8 count;
  285. unsigned target_timeout, current_timeout;
  286. WARN_ON(host->data);
  287. if (data == NULL)
  288. return;
  289. DBG("blksz %04x blks %04x flags %08x\n",
  290. data->blksz, data->blocks, data->flags);
  291. DBG("tsac %d ms nsac %d clk\n",
  292. data->timeout_ns / 1000000, data->timeout_clks);
  293. /* Sanity checks */
  294. BUG_ON(data->blksz * data->blocks > 524288);
  295. BUG_ON(data->blksz > host->max_block);
  296. BUG_ON(data->blocks > 65535);
  297. /* timeout in us */
  298. target_timeout = data->timeout_ns / 1000 +
  299. data->timeout_clks / host->clock;
  300. /*
  301. * Figure out needed cycles.
  302. * We do this in steps in order to fit inside a 32 bit int.
  303. * The first step is the minimum timeout, which will have a
  304. * minimum resolution of 6 bits:
  305. * (1) 2^13*1000 > 2^22,
  306. * (2) host->timeout_clk < 2^16
  307. * =>
  308. * (1) / (2) > 2^6
  309. */
  310. count = 0;
  311. current_timeout = (1 << 13) * 1000 / host->timeout_clk;
  312. while (current_timeout < target_timeout) {
  313. count++;
  314. current_timeout <<= 1;
  315. if (count >= 0xF)
  316. break;
  317. }
  318. if (count >= 0xF) {
  319. printk(KERN_WARNING "%s: Too large timeout requested!\n",
  320. mmc_hostname(host->mmc));
  321. count = 0xE;
  322. }
  323. writeb(count, host->ioaddr + SDHCI_TIMEOUT_CONTROL);
  324. if (host->flags & SDHCI_USE_DMA) {
  325. int count;
  326. count = pci_map_sg(host->chip->pdev, data->sg, data->sg_len,
  327. (data->flags & MMC_DATA_READ)?PCI_DMA_FROMDEVICE:PCI_DMA_TODEVICE);
  328. BUG_ON(count != 1);
  329. writel(sg_dma_address(data->sg), host->ioaddr + SDHCI_DMA_ADDRESS);
  330. } else {
  331. host->size = data->blksz * data->blocks;
  332. host->cur_sg = data->sg;
  333. host->num_sg = data->sg_len;
  334. host->offset = 0;
  335. host->remain = host->cur_sg->length;
  336. }
  337. /* We do not handle DMA boundaries, so set it to max (512 KiB) */
  338. writew(SDHCI_MAKE_BLKSZ(7, data->blksz),
  339. host->ioaddr + SDHCI_BLOCK_SIZE);
  340. writew(data->blocks, host->ioaddr + SDHCI_BLOCK_COUNT);
  341. }
  342. static void sdhci_set_transfer_mode(struct sdhci_host *host,
  343. struct mmc_data *data)
  344. {
  345. u16 mode;
  346. WARN_ON(host->data);
  347. if (data == NULL)
  348. return;
  349. mode = SDHCI_TRNS_BLK_CNT_EN;
  350. if (data->blocks > 1)
  351. mode |= SDHCI_TRNS_MULTI;
  352. if (data->flags & MMC_DATA_READ)
  353. mode |= SDHCI_TRNS_READ;
  354. if (host->flags & SDHCI_USE_DMA)
  355. mode |= SDHCI_TRNS_DMA;
  356. writew(mode, host->ioaddr + SDHCI_TRANSFER_MODE);
  357. }
  358. static void sdhci_finish_data(struct sdhci_host *host)
  359. {
  360. struct mmc_data *data;
  361. u16 blocks;
  362. BUG_ON(!host->data);
  363. data = host->data;
  364. host->data = NULL;
  365. if (host->flags & SDHCI_USE_DMA) {
  366. pci_unmap_sg(host->chip->pdev, data->sg, data->sg_len,
  367. (data->flags & MMC_DATA_READ)?PCI_DMA_FROMDEVICE:PCI_DMA_TODEVICE);
  368. }
  369. /*
  370. * Controller doesn't count down when in single block mode.
  371. */
  372. if ((data->blocks == 1) && (data->error == MMC_ERR_NONE))
  373. blocks = 0;
  374. else
  375. blocks = readw(host->ioaddr + SDHCI_BLOCK_COUNT);
  376. data->bytes_xfered = data->blksz * (data->blocks - blocks);
  377. if ((data->error == MMC_ERR_NONE) && blocks) {
  378. printk(KERN_ERR "%s: Controller signalled completion even "
  379. "though there were blocks left. Please report this "
  380. "to " BUGMAIL ".\n", mmc_hostname(host->mmc));
  381. data->error = MMC_ERR_FAILED;
  382. } else if (host->size != 0) {
  383. printk(KERN_ERR "%s: %d bytes were left untransferred. "
  384. "Please report this to " BUGMAIL ".\n",
  385. mmc_hostname(host->mmc), host->size);
  386. data->error = MMC_ERR_FAILED;
  387. }
  388. DBG("Ending data transfer (%d bytes)\n", data->bytes_xfered);
  389. if (data->stop) {
  390. /*
  391. * The controller needs a reset of internal state machines
  392. * upon error conditions.
  393. */
  394. if (data->error != MMC_ERR_NONE) {
  395. sdhci_reset(host, SDHCI_RESET_CMD);
  396. sdhci_reset(host, SDHCI_RESET_DATA);
  397. }
  398. sdhci_send_command(host, data->stop);
  399. } else
  400. tasklet_schedule(&host->finish_tasklet);
  401. }
  402. static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
  403. {
  404. int flags;
  405. u32 mask;
  406. unsigned long timeout;
  407. WARN_ON(host->cmd);
  408. DBG("Sending cmd (%x)\n", cmd->opcode);
  409. /* Wait max 10 ms */
  410. timeout = 10;
  411. mask = SDHCI_CMD_INHIBIT;
  412. if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
  413. mask |= SDHCI_DATA_INHIBIT;
  414. /* We shouldn't wait for data inihibit for stop commands, even
  415. though they might use busy signaling */
  416. if (host->mrq->data && (cmd == host->mrq->data->stop))
  417. mask &= ~SDHCI_DATA_INHIBIT;
  418. while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) {
  419. if (timeout == 0) {
  420. printk(KERN_ERR "%s: Controller never released "
  421. "inhibit bit(s). Please report this to "
  422. BUGMAIL ".\n", mmc_hostname(host->mmc));
  423. sdhci_dumpregs(host);
  424. cmd->error = MMC_ERR_FAILED;
  425. tasklet_schedule(&host->finish_tasklet);
  426. return;
  427. }
  428. timeout--;
  429. mdelay(1);
  430. }
  431. mod_timer(&host->timer, jiffies + 10 * HZ);
  432. host->cmd = cmd;
  433. sdhci_prepare_data(host, cmd->data);
  434. writel(cmd->arg, host->ioaddr + SDHCI_ARGUMENT);
  435. sdhci_set_transfer_mode(host, cmd->data);
  436. if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
  437. printk(KERN_ERR "%s: Unsupported response type! "
  438. "Please report this to " BUGMAIL ".\n",
  439. mmc_hostname(host->mmc));
  440. cmd->error = MMC_ERR_INVALID;
  441. tasklet_schedule(&host->finish_tasklet);
  442. return;
  443. }
  444. if (!(cmd->flags & MMC_RSP_PRESENT))
  445. flags = SDHCI_CMD_RESP_NONE;
  446. else if (cmd->flags & MMC_RSP_136)
  447. flags = SDHCI_CMD_RESP_LONG;
  448. else if (cmd->flags & MMC_RSP_BUSY)
  449. flags = SDHCI_CMD_RESP_SHORT_BUSY;
  450. else
  451. flags = SDHCI_CMD_RESP_SHORT;
  452. if (cmd->flags & MMC_RSP_CRC)
  453. flags |= SDHCI_CMD_CRC;
  454. if (cmd->flags & MMC_RSP_OPCODE)
  455. flags |= SDHCI_CMD_INDEX;
  456. if (cmd->data)
  457. flags |= SDHCI_CMD_DATA;
  458. writew(SDHCI_MAKE_CMD(cmd->opcode, flags),
  459. host->ioaddr + SDHCI_COMMAND);
  460. }
  461. static void sdhci_finish_command(struct sdhci_host *host)
  462. {
  463. int i;
  464. BUG_ON(host->cmd == NULL);
  465. if (host->cmd->flags & MMC_RSP_PRESENT) {
  466. if (host->cmd->flags & MMC_RSP_136) {
  467. /* CRC is stripped so we need to do some shifting. */
  468. for (i = 0;i < 4;i++) {
  469. host->cmd->resp[i] = readl(host->ioaddr +
  470. SDHCI_RESPONSE + (3-i)*4) << 8;
  471. if (i != 3)
  472. host->cmd->resp[i] |=
  473. readb(host->ioaddr +
  474. SDHCI_RESPONSE + (3-i)*4-1);
  475. }
  476. } else {
  477. host->cmd->resp[0] = readl(host->ioaddr + SDHCI_RESPONSE);
  478. }
  479. }
  480. host->cmd->error = MMC_ERR_NONE;
  481. DBG("Ending cmd (%x)\n", host->cmd->opcode);
  482. if (host->cmd->data)
  483. host->data = host->cmd->data;
  484. else
  485. tasklet_schedule(&host->finish_tasklet);
  486. host->cmd = NULL;
  487. }
  488. static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
  489. {
  490. int div;
  491. u16 clk;
  492. unsigned long timeout;
  493. if (clock == host->clock)
  494. return;
  495. writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL);
  496. if (clock == 0)
  497. goto out;
  498. for (div = 1;div < 256;div *= 2) {
  499. if ((host->max_clk / div) <= clock)
  500. break;
  501. }
  502. div >>= 1;
  503. clk = div << SDHCI_DIVIDER_SHIFT;
  504. clk |= SDHCI_CLOCK_INT_EN;
  505. writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
  506. /* Wait max 10 ms */
  507. timeout = 10;
  508. while (!((clk = readw(host->ioaddr + SDHCI_CLOCK_CONTROL))
  509. & SDHCI_CLOCK_INT_STABLE)) {
  510. if (timeout == 0) {
  511. printk(KERN_ERR "%s: Internal clock never stabilised. "
  512. "Please report this to " BUGMAIL ".\n",
  513. mmc_hostname(host->mmc));
  514. sdhci_dumpregs(host);
  515. return;
  516. }
  517. timeout--;
  518. mdelay(1);
  519. }
  520. clk |= SDHCI_CLOCK_CARD_EN;
  521. writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
  522. out:
  523. host->clock = clock;
  524. }
  525. static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
  526. {
  527. u8 pwr;
  528. if (host->power == power)
  529. return;
  530. writeb(0, host->ioaddr + SDHCI_POWER_CONTROL);
  531. if (power == (unsigned short)-1)
  532. goto out;
  533. pwr = SDHCI_POWER_ON;
  534. switch (power) {
  535. case MMC_VDD_170:
  536. case MMC_VDD_180:
  537. case MMC_VDD_190:
  538. pwr |= SDHCI_POWER_180;
  539. break;
  540. case MMC_VDD_290:
  541. case MMC_VDD_300:
  542. case MMC_VDD_310:
  543. pwr |= SDHCI_POWER_300;
  544. break;
  545. case MMC_VDD_320:
  546. case MMC_VDD_330:
  547. case MMC_VDD_340:
  548. pwr |= SDHCI_POWER_330;
  549. break;
  550. default:
  551. BUG();
  552. }
  553. writeb(pwr, host->ioaddr + SDHCI_POWER_CONTROL);
  554. out:
  555. host->power = power;
  556. }
  557. /*****************************************************************************\
  558. * *
  559. * MMC callbacks *
  560. * *
  561. \*****************************************************************************/
  562. static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
  563. {
  564. struct sdhci_host *host;
  565. unsigned long flags;
  566. host = mmc_priv(mmc);
  567. spin_lock_irqsave(&host->lock, flags);
  568. WARN_ON(host->mrq != NULL);
  569. sdhci_activate_led(host);
  570. host->mrq = mrq;
  571. if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
  572. host->mrq->cmd->error = MMC_ERR_TIMEOUT;
  573. tasklet_schedule(&host->finish_tasklet);
  574. } else
  575. sdhci_send_command(host, mrq->cmd);
  576. spin_unlock_irqrestore(&host->lock, flags);
  577. }
  578. static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
  579. {
  580. struct sdhci_host *host;
  581. unsigned long flags;
  582. u8 ctrl;
  583. host = mmc_priv(mmc);
  584. spin_lock_irqsave(&host->lock, flags);
  585. /*
  586. * Reset the chip on each power off.
  587. * Should clear out any weird states.
  588. */
  589. if (ios->power_mode == MMC_POWER_OFF) {
  590. writel(0, host->ioaddr + SDHCI_SIGNAL_ENABLE);
  591. sdhci_init(host);
  592. }
  593. sdhci_set_clock(host, ios->clock);
  594. if (ios->power_mode == MMC_POWER_OFF)
  595. sdhci_set_power(host, -1);
  596. else
  597. sdhci_set_power(host, ios->vdd);
  598. ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
  599. if (ios->bus_width == MMC_BUS_WIDTH_4)
  600. ctrl |= SDHCI_CTRL_4BITBUS;
  601. else
  602. ctrl &= ~SDHCI_CTRL_4BITBUS;
  603. writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
  604. spin_unlock_irqrestore(&host->lock, flags);
  605. }
  606. static int sdhci_get_ro(struct mmc_host *mmc)
  607. {
  608. struct sdhci_host *host;
  609. unsigned long flags;
  610. int present;
  611. host = mmc_priv(mmc);
  612. spin_lock_irqsave(&host->lock, flags);
  613. present = readl(host->ioaddr + SDHCI_PRESENT_STATE);
  614. spin_unlock_irqrestore(&host->lock, flags);
  615. return !(present & SDHCI_WRITE_PROTECT);
  616. }
  617. static struct mmc_host_ops sdhci_ops = {
  618. .request = sdhci_request,
  619. .set_ios = sdhci_set_ios,
  620. .get_ro = sdhci_get_ro,
  621. };
  622. /*****************************************************************************\
  623. * *
  624. * Tasklets *
  625. * *
  626. \*****************************************************************************/
  627. static void sdhci_tasklet_card(unsigned long param)
  628. {
  629. struct sdhci_host *host;
  630. unsigned long flags;
  631. host = (struct sdhci_host*)param;
  632. spin_lock_irqsave(&host->lock, flags);
  633. if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
  634. if (host->mrq) {
  635. printk(KERN_ERR "%s: Card removed during transfer!\n",
  636. mmc_hostname(host->mmc));
  637. printk(KERN_ERR "%s: Resetting controller.\n",
  638. mmc_hostname(host->mmc));
  639. sdhci_reset(host, SDHCI_RESET_CMD);
  640. sdhci_reset(host, SDHCI_RESET_DATA);
  641. host->mrq->cmd->error = MMC_ERR_FAILED;
  642. tasklet_schedule(&host->finish_tasklet);
  643. }
  644. }
  645. spin_unlock_irqrestore(&host->lock, flags);
  646. mmc_detect_change(host->mmc, msecs_to_jiffies(500));
  647. }
  648. static void sdhci_tasklet_finish(unsigned long param)
  649. {
  650. struct sdhci_host *host;
  651. unsigned long flags;
  652. struct mmc_request *mrq;
  653. host = (struct sdhci_host*)param;
  654. spin_lock_irqsave(&host->lock, flags);
  655. del_timer(&host->timer);
  656. mrq = host->mrq;
  657. DBG("Ending request, cmd (%x)\n", mrq->cmd->opcode);
  658. /*
  659. * The controller needs a reset of internal state machines
  660. * upon error conditions.
  661. */
  662. if ((mrq->cmd->error != MMC_ERR_NONE) ||
  663. (mrq->data && ((mrq->data->error != MMC_ERR_NONE) ||
  664. (mrq->data->stop && (mrq->data->stop->error != MMC_ERR_NONE))))) {
  665. /* Some controllers need this kick or reset won't work here */
  666. if (host->chip->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) {
  667. unsigned int clock;
  668. /* This is to force an update */
  669. clock = host->clock;
  670. host->clock = 0;
  671. sdhci_set_clock(host, clock);
  672. }
  673. /* Spec says we should do both at the same time, but Ricoh
  674. controllers do not like that. */
  675. sdhci_reset(host, SDHCI_RESET_CMD);
  676. sdhci_reset(host, SDHCI_RESET_DATA);
  677. }
  678. host->mrq = NULL;
  679. host->cmd = NULL;
  680. host->data = NULL;
  681. sdhci_deactivate_led(host);
  682. spin_unlock_irqrestore(&host->lock, flags);
  683. mmc_request_done(host->mmc, mrq);
  684. }
  685. static void sdhci_timeout_timer(unsigned long data)
  686. {
  687. struct sdhci_host *host;
  688. unsigned long flags;
  689. host = (struct sdhci_host*)data;
  690. spin_lock_irqsave(&host->lock, flags);
  691. if (host->mrq) {
  692. printk(KERN_ERR "%s: Timeout waiting for hardware interrupt. "
  693. "Please report this to " BUGMAIL ".\n",
  694. mmc_hostname(host->mmc));
  695. sdhci_dumpregs(host);
  696. if (host->data) {
  697. host->data->error = MMC_ERR_TIMEOUT;
  698. sdhci_finish_data(host);
  699. } else {
  700. if (host->cmd)
  701. host->cmd->error = MMC_ERR_TIMEOUT;
  702. else
  703. host->mrq->cmd->error = MMC_ERR_TIMEOUT;
  704. tasklet_schedule(&host->finish_tasklet);
  705. }
  706. }
  707. spin_unlock_irqrestore(&host->lock, flags);
  708. }
  709. /*****************************************************************************\
  710. * *
  711. * Interrupt handling *
  712. * *
  713. \*****************************************************************************/
  714. static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
  715. {
  716. BUG_ON(intmask == 0);
  717. if (!host->cmd) {
  718. printk(KERN_ERR "%s: Got command interrupt even though no "
  719. "command operation was in progress.\n",
  720. mmc_hostname(host->mmc));
  721. printk(KERN_ERR "%s: Please report this to " BUGMAIL ".\n",
  722. mmc_hostname(host->mmc));
  723. sdhci_dumpregs(host);
  724. return;
  725. }
  726. if (intmask & SDHCI_INT_RESPONSE)
  727. sdhci_finish_command(host);
  728. else {
  729. if (intmask & SDHCI_INT_TIMEOUT)
  730. host->cmd->error = MMC_ERR_TIMEOUT;
  731. else if (intmask & SDHCI_INT_CRC)
  732. host->cmd->error = MMC_ERR_BADCRC;
  733. else if (intmask & (SDHCI_INT_END_BIT | SDHCI_INT_INDEX))
  734. host->cmd->error = MMC_ERR_FAILED;
  735. else
  736. host->cmd->error = MMC_ERR_INVALID;
  737. tasklet_schedule(&host->finish_tasklet);
  738. }
  739. }
  740. static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
  741. {
  742. BUG_ON(intmask == 0);
  743. if (!host->data) {
  744. /*
  745. * A data end interrupt is sent together with the response
  746. * for the stop command.
  747. */
  748. if (intmask & SDHCI_INT_DATA_END)
  749. return;
  750. printk(KERN_ERR "%s: Got data interrupt even though no "
  751. "data operation was in progress.\n",
  752. mmc_hostname(host->mmc));
  753. printk(KERN_ERR "%s: Please report this to " BUGMAIL ".\n",
  754. mmc_hostname(host->mmc));
  755. sdhci_dumpregs(host);
  756. return;
  757. }
  758. if (intmask & SDHCI_INT_DATA_TIMEOUT)
  759. host->data->error = MMC_ERR_TIMEOUT;
  760. else if (intmask & SDHCI_INT_DATA_CRC)
  761. host->data->error = MMC_ERR_BADCRC;
  762. else if (intmask & SDHCI_INT_DATA_END_BIT)
  763. host->data->error = MMC_ERR_FAILED;
  764. if (host->data->error != MMC_ERR_NONE)
  765. sdhci_finish_data(host);
  766. else {
  767. if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
  768. sdhci_transfer_pio(host);
  769. if (intmask & SDHCI_INT_DATA_END)
  770. sdhci_finish_data(host);
  771. }
  772. }
  773. static irqreturn_t sdhci_irq(int irq, void *dev_id, struct pt_regs *regs)
  774. {
  775. irqreturn_t result;
  776. struct sdhci_host* host = dev_id;
  777. u32 intmask;
  778. spin_lock(&host->lock);
  779. intmask = readl(host->ioaddr + SDHCI_INT_STATUS);
  780. if (!intmask) {
  781. result = IRQ_NONE;
  782. goto out;
  783. }
  784. DBG("*** %s got interrupt: 0x%08x\n", host->slot_descr, intmask);
  785. if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
  786. writel(intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE),
  787. host->ioaddr + SDHCI_INT_STATUS);
  788. tasklet_schedule(&host->card_tasklet);
  789. }
  790. intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
  791. if (intmask & SDHCI_INT_CMD_MASK) {
  792. writel(intmask & SDHCI_INT_CMD_MASK,
  793. host->ioaddr + SDHCI_INT_STATUS);
  794. sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
  795. }
  796. if (intmask & SDHCI_INT_DATA_MASK) {
  797. writel(intmask & SDHCI_INT_DATA_MASK,
  798. host->ioaddr + SDHCI_INT_STATUS);
  799. sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
  800. }
  801. intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
  802. if (intmask & SDHCI_INT_BUS_POWER) {
  803. printk(KERN_ERR "%s: Card is consuming too much power!\n",
  804. mmc_hostname(host->mmc));
  805. writel(SDHCI_INT_BUS_POWER, host->ioaddr + SDHCI_INT_STATUS);
  806. }
  807. intmask &= SDHCI_INT_BUS_POWER;
  808. if (intmask) {
  809. printk(KERN_ERR "%s: Unexpected interrupt 0x%08x. Please "
  810. "report this to " BUGMAIL ".\n",
  811. mmc_hostname(host->mmc), intmask);
  812. sdhci_dumpregs(host);
  813. writel(intmask, host->ioaddr + SDHCI_INT_STATUS);
  814. }
  815. result = IRQ_HANDLED;
  816. out:
  817. spin_unlock(&host->lock);
  818. return result;
  819. }
  820. /*****************************************************************************\
  821. * *
  822. * Suspend/resume *
  823. * *
  824. \*****************************************************************************/
  825. #ifdef CONFIG_PM
  826. static int sdhci_suspend (struct pci_dev *pdev, pm_message_t state)
  827. {
  828. struct sdhci_chip *chip;
  829. int i, ret;
  830. chip = pci_get_drvdata(pdev);
  831. if (!chip)
  832. return 0;
  833. DBG("Suspending...\n");
  834. for (i = 0;i < chip->num_slots;i++) {
  835. if (!chip->hosts[i])
  836. continue;
  837. ret = mmc_suspend_host(chip->hosts[i]->mmc, state);
  838. if (ret) {
  839. for (i--;i >= 0;i--)
  840. mmc_resume_host(chip->hosts[i]->mmc);
  841. return ret;
  842. }
  843. }
  844. pci_save_state(pdev);
  845. pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
  846. pci_disable_device(pdev);
  847. pci_set_power_state(pdev, pci_choose_state(pdev, state));
  848. return 0;
  849. }
  850. static int sdhci_resume (struct pci_dev *pdev)
  851. {
  852. struct sdhci_chip *chip;
  853. int i, ret;
  854. chip = pci_get_drvdata(pdev);
  855. if (!chip)
  856. return 0;
  857. DBG("Resuming...\n");
  858. pci_set_power_state(pdev, PCI_D0);
  859. pci_restore_state(pdev);
  860. pci_enable_device(pdev);
  861. for (i = 0;i < chip->num_slots;i++) {
  862. if (!chip->hosts[i])
  863. continue;
  864. if (chip->hosts[i]->flags & SDHCI_USE_DMA)
  865. pci_set_master(pdev);
  866. sdhci_init(chip->hosts[i]);
  867. ret = mmc_resume_host(chip->hosts[i]->mmc);
  868. if (ret)
  869. return ret;
  870. }
  871. return 0;
  872. }
  873. #else /* CONFIG_PM */
  874. #define sdhci_suspend NULL
  875. #define sdhci_resume NULL
  876. #endif /* CONFIG_PM */
  877. /*****************************************************************************\
  878. * *
  879. * Device probing/removal *
  880. * *
  881. \*****************************************************************************/
  882. static int __devinit sdhci_probe_slot(struct pci_dev *pdev, int slot)
  883. {
  884. int ret;
  885. unsigned int version;
  886. struct sdhci_chip *chip;
  887. struct mmc_host *mmc;
  888. struct sdhci_host *host;
  889. u8 first_bar;
  890. unsigned int caps;
  891. chip = pci_get_drvdata(pdev);
  892. BUG_ON(!chip);
  893. ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar);
  894. if (ret)
  895. return ret;
  896. first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK;
  897. if (first_bar > 5) {
  898. printk(KERN_ERR DRIVER_NAME ": Invalid first BAR. Aborting.\n");
  899. return -ENODEV;
  900. }
  901. if (!(pci_resource_flags(pdev, first_bar + slot) & IORESOURCE_MEM)) {
  902. printk(KERN_ERR DRIVER_NAME ": BAR is not iomem. Aborting.\n");
  903. return -ENODEV;
  904. }
  905. if (pci_resource_len(pdev, first_bar + slot) != 0x100) {
  906. printk(KERN_ERR DRIVER_NAME ": Invalid iomem size. Aborting.\n");
  907. return -ENODEV;
  908. }
  909. if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
  910. printk(KERN_ERR DRIVER_NAME ": Vendor specific interface. Aborting.\n");
  911. return -ENODEV;
  912. }
  913. if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) {
  914. printk(KERN_ERR DRIVER_NAME ": Unknown interface. Aborting.\n");
  915. return -ENODEV;
  916. }
  917. mmc = mmc_alloc_host(sizeof(struct sdhci_host), &pdev->dev);
  918. if (!mmc)
  919. return -ENOMEM;
  920. host = mmc_priv(mmc);
  921. host->mmc = mmc;
  922. host->bar = first_bar + slot;
  923. host->addr = pci_resource_start(pdev, host->bar);
  924. host->irq = pdev->irq;
  925. DBG("slot %d at 0x%08lx, irq %d\n", slot, host->addr, host->irq);
  926. snprintf(host->slot_descr, 20, "sdhci:slot%d", slot);
  927. ret = pci_request_region(pdev, host->bar, host->slot_descr);
  928. if (ret)
  929. goto free;
  930. host->ioaddr = ioremap_nocache(host->addr,
  931. pci_resource_len(pdev, host->bar));
  932. if (!host->ioaddr) {
  933. ret = -ENOMEM;
  934. goto release;
  935. }
  936. sdhci_reset(host, SDHCI_RESET_ALL);
  937. version = readw(host->ioaddr + SDHCI_HOST_VERSION);
  938. version = (version & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT;
  939. if (version != 0) {
  940. printk(KERN_ERR "%s: Unknown controller version (%d). "
  941. "You may experience problems.\n", host->slot_descr,
  942. version);
  943. }
  944. caps = readl(host->ioaddr + SDHCI_CAPABILITIES);
  945. if (debug_nodma)
  946. DBG("DMA forced off\n");
  947. else if (debug_forcedma) {
  948. DBG("DMA forced on\n");
  949. host->flags |= SDHCI_USE_DMA;
  950. } else if (chip->quirks & SDHCI_QUIRK_FORCE_DMA)
  951. host->flags |= SDHCI_USE_DMA;
  952. else if ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA)
  953. DBG("Controller doesn't have DMA interface\n");
  954. else if (!(caps & SDHCI_CAN_DO_DMA))
  955. DBG("Controller doesn't have DMA capability\n");
  956. else
  957. host->flags |= SDHCI_USE_DMA;
  958. if (host->flags & SDHCI_USE_DMA) {
  959. if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
  960. printk(KERN_WARNING "%s: No suitable DMA available. "
  961. "Falling back to PIO.\n", host->slot_descr);
  962. host->flags &= ~SDHCI_USE_DMA;
  963. }
  964. }
  965. if (host->flags & SDHCI_USE_DMA)
  966. pci_set_master(pdev);
  967. else /* XXX: Hack to get MMC layer to avoid highmem */
  968. pdev->dma_mask = 0;
  969. host->max_clk =
  970. (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
  971. if (host->max_clk == 0) {
  972. printk(KERN_ERR "%s: Hardware doesn't specify base clock "
  973. "frequency.\n", host->slot_descr);
  974. ret = -ENODEV;
  975. goto unmap;
  976. }
  977. host->max_clk *= 1000000;
  978. host->timeout_clk =
  979. (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
  980. if (host->timeout_clk == 0) {
  981. printk(KERN_ERR "%s: Hardware doesn't specify timeout clock "
  982. "frequency.\n", host->slot_descr);
  983. ret = -ENODEV;
  984. goto unmap;
  985. }
  986. if (caps & SDHCI_TIMEOUT_CLK_UNIT)
  987. host->timeout_clk *= 1000;
  988. host->max_block = (caps & SDHCI_MAX_BLOCK_MASK) >> SDHCI_MAX_BLOCK_SHIFT;
  989. if (host->max_block >= 3) {
  990. printk(KERN_ERR "%s: Invalid maximum block size.\n",
  991. host->slot_descr);
  992. ret = -ENODEV;
  993. goto unmap;
  994. }
  995. host->max_block = 512 << host->max_block;
  996. /*
  997. * Set host parameters.
  998. */
  999. mmc->ops = &sdhci_ops;
  1000. mmc->f_min = host->max_clk / 256;
  1001. mmc->f_max = host->max_clk;
  1002. mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_MULTIWRITE | MMC_CAP_BYTEBLOCK;
  1003. mmc->ocr_avail = 0;
  1004. if (caps & SDHCI_CAN_VDD_330)
  1005. mmc->ocr_avail |= MMC_VDD_32_33|MMC_VDD_33_34;
  1006. else if (caps & SDHCI_CAN_VDD_300)
  1007. mmc->ocr_avail |= MMC_VDD_29_30|MMC_VDD_30_31;
  1008. else if (caps & SDHCI_CAN_VDD_180)
  1009. mmc->ocr_avail |= MMC_VDD_17_18|MMC_VDD_18_19;
  1010. if (mmc->ocr_avail == 0) {
  1011. printk(KERN_ERR "%s: Hardware doesn't report any "
  1012. "support voltages.\n", host->slot_descr);
  1013. ret = -ENODEV;
  1014. goto unmap;
  1015. }
  1016. spin_lock_init(&host->lock);
  1017. /*
  1018. * Maximum number of segments. Hardware cannot do scatter lists.
  1019. */
  1020. if (host->flags & SDHCI_USE_DMA)
  1021. mmc->max_hw_segs = 1;
  1022. else
  1023. mmc->max_hw_segs = 16;
  1024. mmc->max_phys_segs = 16;
  1025. /*
  1026. * Maximum number of sectors in one transfer. Limited by DMA boundary
  1027. * size (512KiB), which means (512 KiB/512=) 1024 entries.
  1028. */
  1029. mmc->max_sectors = 1024;
  1030. /*
  1031. * Maximum segment size. Could be one segment with the maximum number
  1032. * of sectors.
  1033. */
  1034. mmc->max_seg_size = mmc->max_sectors * 512;
  1035. /*
  1036. * Init tasklets.
  1037. */
  1038. tasklet_init(&host->card_tasklet,
  1039. sdhci_tasklet_card, (unsigned long)host);
  1040. tasklet_init(&host->finish_tasklet,
  1041. sdhci_tasklet_finish, (unsigned long)host);
  1042. setup_timer(&host->timer, sdhci_timeout_timer, (long)host);
  1043. ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
  1044. host->slot_descr, host);
  1045. if (ret)
  1046. goto untasklet;
  1047. sdhci_init(host);
  1048. #ifdef CONFIG_MMC_DEBUG
  1049. sdhci_dumpregs(host);
  1050. #endif
  1051. host->chip = chip;
  1052. chip->hosts[slot] = host;
  1053. mmc_add_host(mmc);
  1054. printk(KERN_INFO "%s: SDHCI at 0x%08lx irq %d %s\n", mmc_hostname(mmc),
  1055. host->addr, host->irq,
  1056. (host->flags & SDHCI_USE_DMA)?"DMA":"PIO");
  1057. return 0;
  1058. untasklet:
  1059. tasklet_kill(&host->card_tasklet);
  1060. tasklet_kill(&host->finish_tasklet);
  1061. unmap:
  1062. iounmap(host->ioaddr);
  1063. release:
  1064. pci_release_region(pdev, host->bar);
  1065. free:
  1066. mmc_free_host(mmc);
  1067. return ret;
  1068. }
  1069. static void sdhci_remove_slot(struct pci_dev *pdev, int slot)
  1070. {
  1071. struct sdhci_chip *chip;
  1072. struct mmc_host *mmc;
  1073. struct sdhci_host *host;
  1074. chip = pci_get_drvdata(pdev);
  1075. host = chip->hosts[slot];
  1076. mmc = host->mmc;
  1077. chip->hosts[slot] = NULL;
  1078. mmc_remove_host(mmc);
  1079. sdhci_reset(host, SDHCI_RESET_ALL);
  1080. free_irq(host->irq, host);
  1081. del_timer_sync(&host->timer);
  1082. tasklet_kill(&host->card_tasklet);
  1083. tasklet_kill(&host->finish_tasklet);
  1084. iounmap(host->ioaddr);
  1085. pci_release_region(pdev, host->bar);
  1086. mmc_free_host(mmc);
  1087. }
  1088. static int __devinit sdhci_probe(struct pci_dev *pdev,
  1089. const struct pci_device_id *ent)
  1090. {
  1091. int ret, i;
  1092. u8 slots, rev;
  1093. struct sdhci_chip *chip;
  1094. BUG_ON(pdev == NULL);
  1095. BUG_ON(ent == NULL);
  1096. pci_read_config_byte(pdev, PCI_CLASS_REVISION, &rev);
  1097. printk(KERN_INFO DRIVER_NAME
  1098. ": SDHCI controller found at %s [%04x:%04x] (rev %x)\n",
  1099. pci_name(pdev), (int)pdev->vendor, (int)pdev->device,
  1100. (int)rev);
  1101. ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots);
  1102. if (ret)
  1103. return ret;
  1104. slots = PCI_SLOT_INFO_SLOTS(slots) + 1;
  1105. DBG("found %d slot(s)\n", slots);
  1106. if (slots == 0)
  1107. return -ENODEV;
  1108. ret = pci_enable_device(pdev);
  1109. if (ret)
  1110. return ret;
  1111. chip = kzalloc(sizeof(struct sdhci_chip) +
  1112. sizeof(struct sdhci_host*) * slots, GFP_KERNEL);
  1113. if (!chip) {
  1114. ret = -ENOMEM;
  1115. goto err;
  1116. }
  1117. chip->pdev = pdev;
  1118. chip->quirks = ent->driver_data;
  1119. if (debug_quirks)
  1120. chip->quirks = debug_quirks;
  1121. chip->num_slots = slots;
  1122. pci_set_drvdata(pdev, chip);
  1123. for (i = 0;i < slots;i++) {
  1124. ret = sdhci_probe_slot(pdev, i);
  1125. if (ret) {
  1126. for (i--;i >= 0;i--)
  1127. sdhci_remove_slot(pdev, i);
  1128. goto free;
  1129. }
  1130. }
  1131. return 0;
  1132. free:
  1133. pci_set_drvdata(pdev, NULL);
  1134. kfree(chip);
  1135. err:
  1136. pci_disable_device(pdev);
  1137. return ret;
  1138. }
  1139. static void __devexit sdhci_remove(struct pci_dev *pdev)
  1140. {
  1141. int i;
  1142. struct sdhci_chip *chip;
  1143. chip = pci_get_drvdata(pdev);
  1144. if (chip) {
  1145. for (i = 0;i < chip->num_slots;i++)
  1146. sdhci_remove_slot(pdev, i);
  1147. pci_set_drvdata(pdev, NULL);
  1148. kfree(chip);
  1149. }
  1150. pci_disable_device(pdev);
  1151. }
  1152. static struct pci_driver sdhci_driver = {
  1153. .name = DRIVER_NAME,
  1154. .id_table = pci_ids,
  1155. .probe = sdhci_probe,
  1156. .remove = __devexit_p(sdhci_remove),
  1157. .suspend = sdhci_suspend,
  1158. .resume = sdhci_resume,
  1159. };
  1160. /*****************************************************************************\
  1161. * *
  1162. * Driver init/exit *
  1163. * *
  1164. \*****************************************************************************/
  1165. static int __init sdhci_drv_init(void)
  1166. {
  1167. printk(KERN_INFO DRIVER_NAME
  1168. ": Secure Digital Host Controller Interface driver, "
  1169. DRIVER_VERSION "\n");
  1170. printk(KERN_INFO DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
  1171. return pci_register_driver(&sdhci_driver);
  1172. }
  1173. static void __exit sdhci_drv_exit(void)
  1174. {
  1175. DBG("Exiting\n");
  1176. pci_unregister_driver(&sdhci_driver);
  1177. }
  1178. module_init(sdhci_drv_init);
  1179. module_exit(sdhci_drv_exit);
  1180. module_param(debug_nodma, uint, 0444);
  1181. module_param(debug_forcedma, uint, 0444);
  1182. module_param(debug_quirks, uint, 0444);
  1183. MODULE_AUTHOR("Pierre Ossman <drzeus@drzeus.cx>");
  1184. MODULE_DESCRIPTION("Secure Digital Host Controller Interface driver");
  1185. MODULE_VERSION(DRIVER_VERSION);
  1186. MODULE_LICENSE("GPL");
  1187. MODULE_PARM_DESC(debug_nodma, "Forcefully disable DMA transfers. (default 0)");
  1188. MODULE_PARM_DESC(debug_forcedma, "Forcefully enable DMA transfers. (default 0)");
  1189. MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");