atmel_usba_udc.c 49 KB

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  1. /*
  2. * Driver for the Atmel USBA high speed USB device controller
  3. *
  4. * Copyright (C) 2005-2007 Atmel Corporation
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. */
  10. #include <linux/clk.h>
  11. #include <linux/module.h>
  12. #include <linux/init.h>
  13. #include <linux/interrupt.h>
  14. #include <linux/io.h>
  15. #include <linux/slab.h>
  16. #include <linux/device.h>
  17. #include <linux/dma-mapping.h>
  18. #include <linux/list.h>
  19. #include <linux/platform_device.h>
  20. #include <linux/usb/ch9.h>
  21. #include <linux/usb/gadget.h>
  22. #include <linux/usb/atmel_usba_udc.h>
  23. #include <linux/delay.h>
  24. #include <linux/platform_data/atmel.h>
  25. #include <asm/gpio.h>
  26. #include "atmel_usba_udc.h"
  27. #ifdef CONFIG_USB_GADGET_DEBUG_FS
  28. #include <linux/debugfs.h>
  29. #include <linux/uaccess.h>
  30. static int queue_dbg_open(struct inode *inode, struct file *file)
  31. {
  32. struct usba_ep *ep = inode->i_private;
  33. struct usba_request *req, *req_copy;
  34. struct list_head *queue_data;
  35. queue_data = kmalloc(sizeof(*queue_data), GFP_KERNEL);
  36. if (!queue_data)
  37. return -ENOMEM;
  38. INIT_LIST_HEAD(queue_data);
  39. spin_lock_irq(&ep->udc->lock);
  40. list_for_each_entry(req, &ep->queue, queue) {
  41. req_copy = kmemdup(req, sizeof(*req_copy), GFP_ATOMIC);
  42. if (!req_copy)
  43. goto fail;
  44. list_add_tail(&req_copy->queue, queue_data);
  45. }
  46. spin_unlock_irq(&ep->udc->lock);
  47. file->private_data = queue_data;
  48. return 0;
  49. fail:
  50. spin_unlock_irq(&ep->udc->lock);
  51. list_for_each_entry_safe(req, req_copy, queue_data, queue) {
  52. list_del(&req->queue);
  53. kfree(req);
  54. }
  55. kfree(queue_data);
  56. return -ENOMEM;
  57. }
  58. /*
  59. * bbbbbbbb llllllll IZS sssss nnnn FDL\n\0
  60. *
  61. * b: buffer address
  62. * l: buffer length
  63. * I/i: interrupt/no interrupt
  64. * Z/z: zero/no zero
  65. * S/s: short ok/short not ok
  66. * s: status
  67. * n: nr_packets
  68. * F/f: submitted/not submitted to FIFO
  69. * D/d: using/not using DMA
  70. * L/l: last transaction/not last transaction
  71. */
  72. static ssize_t queue_dbg_read(struct file *file, char __user *buf,
  73. size_t nbytes, loff_t *ppos)
  74. {
  75. struct list_head *queue = file->private_data;
  76. struct usba_request *req, *tmp_req;
  77. size_t len, remaining, actual = 0;
  78. char tmpbuf[38];
  79. if (!access_ok(VERIFY_WRITE, buf, nbytes))
  80. return -EFAULT;
  81. mutex_lock(&file_inode(file)->i_mutex);
  82. list_for_each_entry_safe(req, tmp_req, queue, queue) {
  83. len = snprintf(tmpbuf, sizeof(tmpbuf),
  84. "%8p %08x %c%c%c %5d %c%c%c\n",
  85. req->req.buf, req->req.length,
  86. req->req.no_interrupt ? 'i' : 'I',
  87. req->req.zero ? 'Z' : 'z',
  88. req->req.short_not_ok ? 's' : 'S',
  89. req->req.status,
  90. req->submitted ? 'F' : 'f',
  91. req->using_dma ? 'D' : 'd',
  92. req->last_transaction ? 'L' : 'l');
  93. len = min(len, sizeof(tmpbuf));
  94. if (len > nbytes)
  95. break;
  96. list_del(&req->queue);
  97. kfree(req);
  98. remaining = __copy_to_user(buf, tmpbuf, len);
  99. actual += len - remaining;
  100. if (remaining)
  101. break;
  102. nbytes -= len;
  103. buf += len;
  104. }
  105. mutex_unlock(&file_inode(file)->i_mutex);
  106. return actual;
  107. }
  108. static int queue_dbg_release(struct inode *inode, struct file *file)
  109. {
  110. struct list_head *queue_data = file->private_data;
  111. struct usba_request *req, *tmp_req;
  112. list_for_each_entry_safe(req, tmp_req, queue_data, queue) {
  113. list_del(&req->queue);
  114. kfree(req);
  115. }
  116. kfree(queue_data);
  117. return 0;
  118. }
  119. static int regs_dbg_open(struct inode *inode, struct file *file)
  120. {
  121. struct usba_udc *udc;
  122. unsigned int i;
  123. u32 *data;
  124. int ret = -ENOMEM;
  125. mutex_lock(&inode->i_mutex);
  126. udc = inode->i_private;
  127. data = kmalloc(inode->i_size, GFP_KERNEL);
  128. if (!data)
  129. goto out;
  130. spin_lock_irq(&udc->lock);
  131. for (i = 0; i < inode->i_size / 4; i++)
  132. data[i] = __raw_readl(udc->regs + i * 4);
  133. spin_unlock_irq(&udc->lock);
  134. file->private_data = data;
  135. ret = 0;
  136. out:
  137. mutex_unlock(&inode->i_mutex);
  138. return ret;
  139. }
  140. static ssize_t regs_dbg_read(struct file *file, char __user *buf,
  141. size_t nbytes, loff_t *ppos)
  142. {
  143. struct inode *inode = file_inode(file);
  144. int ret;
  145. mutex_lock(&inode->i_mutex);
  146. ret = simple_read_from_buffer(buf, nbytes, ppos,
  147. file->private_data,
  148. file_inode(file)->i_size);
  149. mutex_unlock(&inode->i_mutex);
  150. return ret;
  151. }
  152. static int regs_dbg_release(struct inode *inode, struct file *file)
  153. {
  154. kfree(file->private_data);
  155. return 0;
  156. }
  157. const struct file_operations queue_dbg_fops = {
  158. .owner = THIS_MODULE,
  159. .open = queue_dbg_open,
  160. .llseek = no_llseek,
  161. .read = queue_dbg_read,
  162. .release = queue_dbg_release,
  163. };
  164. const struct file_operations regs_dbg_fops = {
  165. .owner = THIS_MODULE,
  166. .open = regs_dbg_open,
  167. .llseek = generic_file_llseek,
  168. .read = regs_dbg_read,
  169. .release = regs_dbg_release,
  170. };
  171. static void usba_ep_init_debugfs(struct usba_udc *udc,
  172. struct usba_ep *ep)
  173. {
  174. struct dentry *ep_root;
  175. ep_root = debugfs_create_dir(ep->ep.name, udc->debugfs_root);
  176. if (!ep_root)
  177. goto err_root;
  178. ep->debugfs_dir = ep_root;
  179. ep->debugfs_queue = debugfs_create_file("queue", 0400, ep_root,
  180. ep, &queue_dbg_fops);
  181. if (!ep->debugfs_queue)
  182. goto err_queue;
  183. if (ep->can_dma) {
  184. ep->debugfs_dma_status
  185. = debugfs_create_u32("dma_status", 0400, ep_root,
  186. &ep->last_dma_status);
  187. if (!ep->debugfs_dma_status)
  188. goto err_dma_status;
  189. }
  190. if (ep_is_control(ep)) {
  191. ep->debugfs_state
  192. = debugfs_create_u32("state", 0400, ep_root,
  193. &ep->state);
  194. if (!ep->debugfs_state)
  195. goto err_state;
  196. }
  197. return;
  198. err_state:
  199. if (ep->can_dma)
  200. debugfs_remove(ep->debugfs_dma_status);
  201. err_dma_status:
  202. debugfs_remove(ep->debugfs_queue);
  203. err_queue:
  204. debugfs_remove(ep_root);
  205. err_root:
  206. dev_err(&ep->udc->pdev->dev,
  207. "failed to create debugfs directory for %s\n", ep->ep.name);
  208. }
  209. static void usba_ep_cleanup_debugfs(struct usba_ep *ep)
  210. {
  211. debugfs_remove(ep->debugfs_queue);
  212. debugfs_remove(ep->debugfs_dma_status);
  213. debugfs_remove(ep->debugfs_state);
  214. debugfs_remove(ep->debugfs_dir);
  215. ep->debugfs_dma_status = NULL;
  216. ep->debugfs_dir = NULL;
  217. }
  218. static void usba_init_debugfs(struct usba_udc *udc)
  219. {
  220. struct dentry *root, *regs;
  221. struct resource *regs_resource;
  222. root = debugfs_create_dir(udc->gadget.name, NULL);
  223. if (IS_ERR(root) || !root)
  224. goto err_root;
  225. udc->debugfs_root = root;
  226. regs = debugfs_create_file("regs", 0400, root, udc, &regs_dbg_fops);
  227. if (!regs)
  228. goto err_regs;
  229. regs_resource = platform_get_resource(udc->pdev, IORESOURCE_MEM,
  230. CTRL_IOMEM_ID);
  231. regs->d_inode->i_size = resource_size(regs_resource);
  232. udc->debugfs_regs = regs;
  233. usba_ep_init_debugfs(udc, to_usba_ep(udc->gadget.ep0));
  234. return;
  235. err_regs:
  236. debugfs_remove(root);
  237. err_root:
  238. udc->debugfs_root = NULL;
  239. dev_err(&udc->pdev->dev, "debugfs is not available\n");
  240. }
  241. static void usba_cleanup_debugfs(struct usba_udc *udc)
  242. {
  243. usba_ep_cleanup_debugfs(to_usba_ep(udc->gadget.ep0));
  244. debugfs_remove(udc->debugfs_regs);
  245. debugfs_remove(udc->debugfs_root);
  246. udc->debugfs_regs = NULL;
  247. udc->debugfs_root = NULL;
  248. }
  249. #else
  250. static inline void usba_ep_init_debugfs(struct usba_udc *udc,
  251. struct usba_ep *ep)
  252. {
  253. }
  254. static inline void usba_ep_cleanup_debugfs(struct usba_ep *ep)
  255. {
  256. }
  257. static inline void usba_init_debugfs(struct usba_udc *udc)
  258. {
  259. }
  260. static inline void usba_cleanup_debugfs(struct usba_udc *udc)
  261. {
  262. }
  263. #endif
  264. static int vbus_is_present(struct usba_udc *udc)
  265. {
  266. if (gpio_is_valid(udc->vbus_pin))
  267. return gpio_get_value(udc->vbus_pin) ^ udc->vbus_pin_inverted;
  268. /* No Vbus detection: Assume always present */
  269. return 1;
  270. }
  271. #if defined(CONFIG_ARCH_AT91SAM9RL)
  272. #include <mach/at91_pmc.h>
  273. static void toggle_bias(int is_on)
  274. {
  275. unsigned int uckr = at91_pmc_read(AT91_CKGR_UCKR);
  276. if (is_on)
  277. at91_pmc_write(AT91_CKGR_UCKR, uckr | AT91_PMC_BIASEN);
  278. else
  279. at91_pmc_write(AT91_CKGR_UCKR, uckr & ~(AT91_PMC_BIASEN));
  280. }
  281. #else
  282. static void toggle_bias(int is_on)
  283. {
  284. }
  285. #endif /* CONFIG_ARCH_AT91SAM9RL */
  286. static void next_fifo_transaction(struct usba_ep *ep, struct usba_request *req)
  287. {
  288. unsigned int transaction_len;
  289. transaction_len = req->req.length - req->req.actual;
  290. req->last_transaction = 1;
  291. if (transaction_len > ep->ep.maxpacket) {
  292. transaction_len = ep->ep.maxpacket;
  293. req->last_transaction = 0;
  294. } else if (transaction_len == ep->ep.maxpacket && req->req.zero)
  295. req->last_transaction = 0;
  296. DBG(DBG_QUEUE, "%s: submit_transaction, req %p (length %d)%s\n",
  297. ep->ep.name, req, transaction_len,
  298. req->last_transaction ? ", done" : "");
  299. memcpy_toio(ep->fifo, req->req.buf + req->req.actual, transaction_len);
  300. usba_ep_writel(ep, SET_STA, USBA_TX_PK_RDY);
  301. req->req.actual += transaction_len;
  302. }
  303. static void submit_request(struct usba_ep *ep, struct usba_request *req)
  304. {
  305. DBG(DBG_QUEUE, "%s: submit_request: req %p (length %d)\n",
  306. ep->ep.name, req, req->req.length);
  307. req->req.actual = 0;
  308. req->submitted = 1;
  309. if (req->using_dma) {
  310. if (req->req.length == 0) {
  311. usba_ep_writel(ep, CTL_ENB, USBA_TX_PK_RDY);
  312. return;
  313. }
  314. if (req->req.zero)
  315. usba_ep_writel(ep, CTL_ENB, USBA_SHORT_PACKET);
  316. else
  317. usba_ep_writel(ep, CTL_DIS, USBA_SHORT_PACKET);
  318. usba_dma_writel(ep, ADDRESS, req->req.dma);
  319. usba_dma_writel(ep, CONTROL, req->ctrl);
  320. } else {
  321. next_fifo_transaction(ep, req);
  322. if (req->last_transaction) {
  323. usba_ep_writel(ep, CTL_DIS, USBA_TX_PK_RDY);
  324. usba_ep_writel(ep, CTL_ENB, USBA_TX_COMPLETE);
  325. } else {
  326. usba_ep_writel(ep, CTL_DIS, USBA_TX_COMPLETE);
  327. usba_ep_writel(ep, CTL_ENB, USBA_TX_PK_RDY);
  328. }
  329. }
  330. }
  331. static void submit_next_request(struct usba_ep *ep)
  332. {
  333. struct usba_request *req;
  334. if (list_empty(&ep->queue)) {
  335. usba_ep_writel(ep, CTL_DIS, USBA_TX_PK_RDY | USBA_RX_BK_RDY);
  336. return;
  337. }
  338. req = list_entry(ep->queue.next, struct usba_request, queue);
  339. if (!req->submitted)
  340. submit_request(ep, req);
  341. }
  342. static void send_status(struct usba_udc *udc, struct usba_ep *ep)
  343. {
  344. ep->state = STATUS_STAGE_IN;
  345. usba_ep_writel(ep, SET_STA, USBA_TX_PK_RDY);
  346. usba_ep_writel(ep, CTL_ENB, USBA_TX_COMPLETE);
  347. }
  348. static void receive_data(struct usba_ep *ep)
  349. {
  350. struct usba_udc *udc = ep->udc;
  351. struct usba_request *req;
  352. unsigned long status;
  353. unsigned int bytecount, nr_busy;
  354. int is_complete = 0;
  355. status = usba_ep_readl(ep, STA);
  356. nr_busy = USBA_BFEXT(BUSY_BANKS, status);
  357. DBG(DBG_QUEUE, "receive data: nr_busy=%u\n", nr_busy);
  358. while (nr_busy > 0) {
  359. if (list_empty(&ep->queue)) {
  360. usba_ep_writel(ep, CTL_DIS, USBA_RX_BK_RDY);
  361. break;
  362. }
  363. req = list_entry(ep->queue.next,
  364. struct usba_request, queue);
  365. bytecount = USBA_BFEXT(BYTE_COUNT, status);
  366. if (status & (1 << 31))
  367. is_complete = 1;
  368. if (req->req.actual + bytecount >= req->req.length) {
  369. is_complete = 1;
  370. bytecount = req->req.length - req->req.actual;
  371. }
  372. memcpy_fromio(req->req.buf + req->req.actual,
  373. ep->fifo, bytecount);
  374. req->req.actual += bytecount;
  375. usba_ep_writel(ep, CLR_STA, USBA_RX_BK_RDY);
  376. if (is_complete) {
  377. DBG(DBG_QUEUE, "%s: request done\n", ep->ep.name);
  378. req->req.status = 0;
  379. list_del_init(&req->queue);
  380. usba_ep_writel(ep, CTL_DIS, USBA_RX_BK_RDY);
  381. spin_unlock(&udc->lock);
  382. req->req.complete(&ep->ep, &req->req);
  383. spin_lock(&udc->lock);
  384. }
  385. status = usba_ep_readl(ep, STA);
  386. nr_busy = USBA_BFEXT(BUSY_BANKS, status);
  387. if (is_complete && ep_is_control(ep)) {
  388. send_status(udc, ep);
  389. break;
  390. }
  391. }
  392. }
  393. static void
  394. request_complete(struct usba_ep *ep, struct usba_request *req, int status)
  395. {
  396. struct usba_udc *udc = ep->udc;
  397. WARN_ON(!list_empty(&req->queue));
  398. if (req->req.status == -EINPROGRESS)
  399. req->req.status = status;
  400. if (req->using_dma)
  401. usb_gadget_unmap_request(&udc->gadget, &req->req, ep->is_in);
  402. DBG(DBG_GADGET | DBG_REQ,
  403. "%s: req %p complete: status %d, actual %u\n",
  404. ep->ep.name, req, req->req.status, req->req.actual);
  405. spin_unlock(&udc->lock);
  406. req->req.complete(&ep->ep, &req->req);
  407. spin_lock(&udc->lock);
  408. }
  409. static void
  410. request_complete_list(struct usba_ep *ep, struct list_head *list, int status)
  411. {
  412. struct usba_request *req, *tmp_req;
  413. list_for_each_entry_safe(req, tmp_req, list, queue) {
  414. list_del_init(&req->queue);
  415. request_complete(ep, req, status);
  416. }
  417. }
  418. static int
  419. usba_ep_enable(struct usb_ep *_ep, const struct usb_endpoint_descriptor *desc)
  420. {
  421. struct usba_ep *ep = to_usba_ep(_ep);
  422. struct usba_udc *udc = ep->udc;
  423. unsigned long flags, ept_cfg, maxpacket;
  424. unsigned int nr_trans;
  425. DBG(DBG_GADGET, "%s: ep_enable: desc=%p\n", ep->ep.name, desc);
  426. maxpacket = usb_endpoint_maxp(desc) & 0x7ff;
  427. if (((desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK) != ep->index)
  428. || ep->index == 0
  429. || desc->bDescriptorType != USB_DT_ENDPOINT
  430. || maxpacket == 0
  431. || maxpacket > ep->fifo_size) {
  432. DBG(DBG_ERR, "ep_enable: Invalid argument");
  433. return -EINVAL;
  434. }
  435. ep->is_isoc = 0;
  436. ep->is_in = 0;
  437. if (maxpacket <= 8)
  438. ept_cfg = USBA_BF(EPT_SIZE, USBA_EPT_SIZE_8);
  439. else
  440. /* LSB is bit 1, not 0 */
  441. ept_cfg = USBA_BF(EPT_SIZE, fls(maxpacket - 1) - 3);
  442. DBG(DBG_HW, "%s: EPT_SIZE = %lu (maxpacket = %lu)\n",
  443. ep->ep.name, ept_cfg, maxpacket);
  444. if (usb_endpoint_dir_in(desc)) {
  445. ep->is_in = 1;
  446. ept_cfg |= USBA_EPT_DIR_IN;
  447. }
  448. switch (usb_endpoint_type(desc)) {
  449. case USB_ENDPOINT_XFER_CONTROL:
  450. ept_cfg |= USBA_BF(EPT_TYPE, USBA_EPT_TYPE_CONTROL);
  451. ept_cfg |= USBA_BF(BK_NUMBER, USBA_BK_NUMBER_ONE);
  452. break;
  453. case USB_ENDPOINT_XFER_ISOC:
  454. if (!ep->can_isoc) {
  455. DBG(DBG_ERR, "ep_enable: %s is not isoc capable\n",
  456. ep->ep.name);
  457. return -EINVAL;
  458. }
  459. /*
  460. * Bits 11:12 specify number of _additional_
  461. * transactions per microframe.
  462. */
  463. nr_trans = ((usb_endpoint_maxp(desc) >> 11) & 3) + 1;
  464. if (nr_trans > 3)
  465. return -EINVAL;
  466. ep->is_isoc = 1;
  467. ept_cfg |= USBA_BF(EPT_TYPE, USBA_EPT_TYPE_ISO);
  468. /*
  469. * Do triple-buffering on high-bandwidth iso endpoints.
  470. */
  471. if (nr_trans > 1 && ep->nr_banks == 3)
  472. ept_cfg |= USBA_BF(BK_NUMBER, USBA_BK_NUMBER_TRIPLE);
  473. else
  474. ept_cfg |= USBA_BF(BK_NUMBER, USBA_BK_NUMBER_DOUBLE);
  475. ept_cfg |= USBA_BF(NB_TRANS, nr_trans);
  476. break;
  477. case USB_ENDPOINT_XFER_BULK:
  478. ept_cfg |= USBA_BF(EPT_TYPE, USBA_EPT_TYPE_BULK);
  479. ept_cfg |= USBA_BF(BK_NUMBER, USBA_BK_NUMBER_DOUBLE);
  480. break;
  481. case USB_ENDPOINT_XFER_INT:
  482. ept_cfg |= USBA_BF(EPT_TYPE, USBA_EPT_TYPE_INT);
  483. ept_cfg |= USBA_BF(BK_NUMBER, USBA_BK_NUMBER_DOUBLE);
  484. break;
  485. }
  486. spin_lock_irqsave(&ep->udc->lock, flags);
  487. ep->ep.desc = desc;
  488. ep->ep.maxpacket = maxpacket;
  489. usba_ep_writel(ep, CFG, ept_cfg);
  490. usba_ep_writel(ep, CTL_ENB, USBA_EPT_ENABLE);
  491. if (ep->can_dma) {
  492. u32 ctrl;
  493. usba_writel(udc, INT_ENB,
  494. (usba_readl(udc, INT_ENB)
  495. | USBA_BF(EPT_INT, 1 << ep->index)
  496. | USBA_BF(DMA_INT, 1 << ep->index)));
  497. ctrl = USBA_AUTO_VALID | USBA_INTDIS_DMA;
  498. usba_ep_writel(ep, CTL_ENB, ctrl);
  499. } else {
  500. usba_writel(udc, INT_ENB,
  501. (usba_readl(udc, INT_ENB)
  502. | USBA_BF(EPT_INT, 1 << ep->index)));
  503. }
  504. spin_unlock_irqrestore(&udc->lock, flags);
  505. DBG(DBG_HW, "EPT_CFG%d after init: %#08lx\n", ep->index,
  506. (unsigned long)usba_ep_readl(ep, CFG));
  507. DBG(DBG_HW, "INT_ENB after init: %#08lx\n",
  508. (unsigned long)usba_readl(udc, INT_ENB));
  509. return 0;
  510. }
  511. static int usba_ep_disable(struct usb_ep *_ep)
  512. {
  513. struct usba_ep *ep = to_usba_ep(_ep);
  514. struct usba_udc *udc = ep->udc;
  515. LIST_HEAD(req_list);
  516. unsigned long flags;
  517. DBG(DBG_GADGET, "ep_disable: %s\n", ep->ep.name);
  518. spin_lock_irqsave(&udc->lock, flags);
  519. if (!ep->ep.desc) {
  520. spin_unlock_irqrestore(&udc->lock, flags);
  521. /* REVISIT because this driver disables endpoints in
  522. * reset_all_endpoints() before calling disconnect(),
  523. * most gadget drivers would trigger this non-error ...
  524. */
  525. if (udc->gadget.speed != USB_SPEED_UNKNOWN)
  526. DBG(DBG_ERR, "ep_disable: %s not enabled\n",
  527. ep->ep.name);
  528. return -EINVAL;
  529. }
  530. ep->ep.desc = NULL;
  531. list_splice_init(&ep->queue, &req_list);
  532. if (ep->can_dma) {
  533. usba_dma_writel(ep, CONTROL, 0);
  534. usba_dma_writel(ep, ADDRESS, 0);
  535. usba_dma_readl(ep, STATUS);
  536. }
  537. usba_ep_writel(ep, CTL_DIS, USBA_EPT_ENABLE);
  538. usba_writel(udc, INT_ENB,
  539. usba_readl(udc, INT_ENB)
  540. & ~USBA_BF(EPT_INT, 1 << ep->index));
  541. request_complete_list(ep, &req_list, -ESHUTDOWN);
  542. spin_unlock_irqrestore(&udc->lock, flags);
  543. return 0;
  544. }
  545. static struct usb_request *
  546. usba_ep_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags)
  547. {
  548. struct usba_request *req;
  549. DBG(DBG_GADGET, "ep_alloc_request: %p, 0x%x\n", _ep, gfp_flags);
  550. req = kzalloc(sizeof(*req), gfp_flags);
  551. if (!req)
  552. return NULL;
  553. INIT_LIST_HEAD(&req->queue);
  554. return &req->req;
  555. }
  556. static void
  557. usba_ep_free_request(struct usb_ep *_ep, struct usb_request *_req)
  558. {
  559. struct usba_request *req = to_usba_req(_req);
  560. DBG(DBG_GADGET, "ep_free_request: %p, %p\n", _ep, _req);
  561. kfree(req);
  562. }
  563. static int queue_dma(struct usba_udc *udc, struct usba_ep *ep,
  564. struct usba_request *req, gfp_t gfp_flags)
  565. {
  566. unsigned long flags;
  567. int ret;
  568. DBG(DBG_DMA, "%s: req l/%u d/%08x %c%c%c\n",
  569. ep->ep.name, req->req.length, req->req.dma,
  570. req->req.zero ? 'Z' : 'z',
  571. req->req.short_not_ok ? 'S' : 's',
  572. req->req.no_interrupt ? 'I' : 'i');
  573. if (req->req.length > 0x10000) {
  574. /* Lengths from 0 to 65536 (inclusive) are supported */
  575. DBG(DBG_ERR, "invalid request length %u\n", req->req.length);
  576. return -EINVAL;
  577. }
  578. ret = usb_gadget_map_request(&udc->gadget, &req->req, ep->is_in);
  579. if (ret)
  580. return ret;
  581. req->using_dma = 1;
  582. req->ctrl = USBA_BF(DMA_BUF_LEN, req->req.length)
  583. | USBA_DMA_CH_EN | USBA_DMA_END_BUF_IE
  584. | USBA_DMA_END_TR_EN | USBA_DMA_END_TR_IE;
  585. if (ep->is_in)
  586. req->ctrl |= USBA_DMA_END_BUF_EN;
  587. /*
  588. * Add this request to the queue and submit for DMA if
  589. * possible. Check if we're still alive first -- we may have
  590. * received a reset since last time we checked.
  591. */
  592. ret = -ESHUTDOWN;
  593. spin_lock_irqsave(&udc->lock, flags);
  594. if (ep->ep.desc) {
  595. if (list_empty(&ep->queue))
  596. submit_request(ep, req);
  597. list_add_tail(&req->queue, &ep->queue);
  598. ret = 0;
  599. }
  600. spin_unlock_irqrestore(&udc->lock, flags);
  601. return ret;
  602. }
  603. static int
  604. usba_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
  605. {
  606. struct usba_request *req = to_usba_req(_req);
  607. struct usba_ep *ep = to_usba_ep(_ep);
  608. struct usba_udc *udc = ep->udc;
  609. unsigned long flags;
  610. int ret;
  611. DBG(DBG_GADGET | DBG_QUEUE | DBG_REQ, "%s: queue req %p, len %u\n",
  612. ep->ep.name, req, _req->length);
  613. if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN ||
  614. !ep->ep.desc)
  615. return -ESHUTDOWN;
  616. req->submitted = 0;
  617. req->using_dma = 0;
  618. req->last_transaction = 0;
  619. _req->status = -EINPROGRESS;
  620. _req->actual = 0;
  621. if (ep->can_dma)
  622. return queue_dma(udc, ep, req, gfp_flags);
  623. /* May have received a reset since last time we checked */
  624. ret = -ESHUTDOWN;
  625. spin_lock_irqsave(&udc->lock, flags);
  626. if (ep->ep.desc) {
  627. list_add_tail(&req->queue, &ep->queue);
  628. if ((!ep_is_control(ep) && ep->is_in) ||
  629. (ep_is_control(ep)
  630. && (ep->state == DATA_STAGE_IN
  631. || ep->state == STATUS_STAGE_IN)))
  632. usba_ep_writel(ep, CTL_ENB, USBA_TX_PK_RDY);
  633. else
  634. usba_ep_writel(ep, CTL_ENB, USBA_RX_BK_RDY);
  635. ret = 0;
  636. }
  637. spin_unlock_irqrestore(&udc->lock, flags);
  638. return ret;
  639. }
  640. static void
  641. usba_update_req(struct usba_ep *ep, struct usba_request *req, u32 status)
  642. {
  643. req->req.actual = req->req.length - USBA_BFEXT(DMA_BUF_LEN, status);
  644. }
  645. static int stop_dma(struct usba_ep *ep, u32 *pstatus)
  646. {
  647. unsigned int timeout;
  648. u32 status;
  649. /*
  650. * Stop the DMA controller. When writing both CH_EN
  651. * and LINK to 0, the other bits are not affected.
  652. */
  653. usba_dma_writel(ep, CONTROL, 0);
  654. /* Wait for the FIFO to empty */
  655. for (timeout = 40; timeout; --timeout) {
  656. status = usba_dma_readl(ep, STATUS);
  657. if (!(status & USBA_DMA_CH_EN))
  658. break;
  659. udelay(1);
  660. }
  661. if (pstatus)
  662. *pstatus = status;
  663. if (timeout == 0) {
  664. dev_err(&ep->udc->pdev->dev,
  665. "%s: timed out waiting for DMA FIFO to empty\n",
  666. ep->ep.name);
  667. return -ETIMEDOUT;
  668. }
  669. return 0;
  670. }
  671. static int usba_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
  672. {
  673. struct usba_ep *ep = to_usba_ep(_ep);
  674. struct usba_udc *udc = ep->udc;
  675. struct usba_request *req = to_usba_req(_req);
  676. unsigned long flags;
  677. u32 status;
  678. DBG(DBG_GADGET | DBG_QUEUE, "ep_dequeue: %s, req %p\n",
  679. ep->ep.name, req);
  680. spin_lock_irqsave(&udc->lock, flags);
  681. if (req->using_dma) {
  682. /*
  683. * If this request is currently being transferred,
  684. * stop the DMA controller and reset the FIFO.
  685. */
  686. if (ep->queue.next == &req->queue) {
  687. status = usba_dma_readl(ep, STATUS);
  688. if (status & USBA_DMA_CH_EN)
  689. stop_dma(ep, &status);
  690. #ifdef CONFIG_USB_GADGET_DEBUG_FS
  691. ep->last_dma_status = status;
  692. #endif
  693. usba_writel(udc, EPT_RST, 1 << ep->index);
  694. usba_update_req(ep, req, status);
  695. }
  696. }
  697. /*
  698. * Errors should stop the queue from advancing until the
  699. * completion function returns.
  700. */
  701. list_del_init(&req->queue);
  702. request_complete(ep, req, -ECONNRESET);
  703. /* Process the next request if any */
  704. submit_next_request(ep);
  705. spin_unlock_irqrestore(&udc->lock, flags);
  706. return 0;
  707. }
  708. static int usba_ep_set_halt(struct usb_ep *_ep, int value)
  709. {
  710. struct usba_ep *ep = to_usba_ep(_ep);
  711. struct usba_udc *udc = ep->udc;
  712. unsigned long flags;
  713. int ret = 0;
  714. DBG(DBG_GADGET, "endpoint %s: %s HALT\n", ep->ep.name,
  715. value ? "set" : "clear");
  716. if (!ep->ep.desc) {
  717. DBG(DBG_ERR, "Attempted to halt uninitialized ep %s\n",
  718. ep->ep.name);
  719. return -ENODEV;
  720. }
  721. if (ep->is_isoc) {
  722. DBG(DBG_ERR, "Attempted to halt isochronous ep %s\n",
  723. ep->ep.name);
  724. return -ENOTTY;
  725. }
  726. spin_lock_irqsave(&udc->lock, flags);
  727. /*
  728. * We can't halt IN endpoints while there are still data to be
  729. * transferred
  730. */
  731. if (!list_empty(&ep->queue)
  732. || ((value && ep->is_in && (usba_ep_readl(ep, STA)
  733. & USBA_BF(BUSY_BANKS, -1L))))) {
  734. ret = -EAGAIN;
  735. } else {
  736. if (value)
  737. usba_ep_writel(ep, SET_STA, USBA_FORCE_STALL);
  738. else
  739. usba_ep_writel(ep, CLR_STA,
  740. USBA_FORCE_STALL | USBA_TOGGLE_CLR);
  741. usba_ep_readl(ep, STA);
  742. }
  743. spin_unlock_irqrestore(&udc->lock, flags);
  744. return ret;
  745. }
  746. static int usba_ep_fifo_status(struct usb_ep *_ep)
  747. {
  748. struct usba_ep *ep = to_usba_ep(_ep);
  749. return USBA_BFEXT(BYTE_COUNT, usba_ep_readl(ep, STA));
  750. }
  751. static void usba_ep_fifo_flush(struct usb_ep *_ep)
  752. {
  753. struct usba_ep *ep = to_usba_ep(_ep);
  754. struct usba_udc *udc = ep->udc;
  755. usba_writel(udc, EPT_RST, 1 << ep->index);
  756. }
  757. static const struct usb_ep_ops usba_ep_ops = {
  758. .enable = usba_ep_enable,
  759. .disable = usba_ep_disable,
  760. .alloc_request = usba_ep_alloc_request,
  761. .free_request = usba_ep_free_request,
  762. .queue = usba_ep_queue,
  763. .dequeue = usba_ep_dequeue,
  764. .set_halt = usba_ep_set_halt,
  765. .fifo_status = usba_ep_fifo_status,
  766. .fifo_flush = usba_ep_fifo_flush,
  767. };
  768. static int usba_udc_get_frame(struct usb_gadget *gadget)
  769. {
  770. struct usba_udc *udc = to_usba_udc(gadget);
  771. return USBA_BFEXT(FRAME_NUMBER, usba_readl(udc, FNUM));
  772. }
  773. static int usba_udc_wakeup(struct usb_gadget *gadget)
  774. {
  775. struct usba_udc *udc = to_usba_udc(gadget);
  776. unsigned long flags;
  777. u32 ctrl;
  778. int ret = -EINVAL;
  779. spin_lock_irqsave(&udc->lock, flags);
  780. if (udc->devstatus & (1 << USB_DEVICE_REMOTE_WAKEUP)) {
  781. ctrl = usba_readl(udc, CTRL);
  782. usba_writel(udc, CTRL, ctrl | USBA_REMOTE_WAKE_UP);
  783. ret = 0;
  784. }
  785. spin_unlock_irqrestore(&udc->lock, flags);
  786. return ret;
  787. }
  788. static int
  789. usba_udc_set_selfpowered(struct usb_gadget *gadget, int is_selfpowered)
  790. {
  791. struct usba_udc *udc = to_usba_udc(gadget);
  792. unsigned long flags;
  793. spin_lock_irqsave(&udc->lock, flags);
  794. if (is_selfpowered)
  795. udc->devstatus |= 1 << USB_DEVICE_SELF_POWERED;
  796. else
  797. udc->devstatus &= ~(1 << USB_DEVICE_SELF_POWERED);
  798. spin_unlock_irqrestore(&udc->lock, flags);
  799. return 0;
  800. }
  801. static int atmel_usba_start(struct usb_gadget *gadget,
  802. struct usb_gadget_driver *driver);
  803. static int atmel_usba_stop(struct usb_gadget *gadget,
  804. struct usb_gadget_driver *driver);
  805. static const struct usb_gadget_ops usba_udc_ops = {
  806. .get_frame = usba_udc_get_frame,
  807. .wakeup = usba_udc_wakeup,
  808. .set_selfpowered = usba_udc_set_selfpowered,
  809. .udc_start = atmel_usba_start,
  810. .udc_stop = atmel_usba_stop,
  811. };
  812. static struct usb_endpoint_descriptor usba_ep0_desc = {
  813. .bLength = USB_DT_ENDPOINT_SIZE,
  814. .bDescriptorType = USB_DT_ENDPOINT,
  815. .bEndpointAddress = 0,
  816. .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
  817. .wMaxPacketSize = cpu_to_le16(64),
  818. /* FIXME: I have no idea what to put here */
  819. .bInterval = 1,
  820. };
  821. static void nop_release(struct device *dev)
  822. {
  823. }
  824. struct usb_gadget usba_gadget_template = {
  825. .ops = &usba_udc_ops,
  826. .max_speed = USB_SPEED_HIGH,
  827. .name = "atmel_usba_udc",
  828. .dev = {
  829. .init_name = "gadget",
  830. .release = nop_release,
  831. },
  832. };
  833. /*
  834. * Called with interrupts disabled and udc->lock held.
  835. */
  836. static void reset_all_endpoints(struct usba_udc *udc)
  837. {
  838. struct usba_ep *ep;
  839. struct usba_request *req, *tmp_req;
  840. usba_writel(udc, EPT_RST, ~0UL);
  841. ep = to_usba_ep(udc->gadget.ep0);
  842. list_for_each_entry_safe(req, tmp_req, &ep->queue, queue) {
  843. list_del_init(&req->queue);
  844. request_complete(ep, req, -ECONNRESET);
  845. }
  846. /* NOTE: normally, the next call to the gadget driver is in
  847. * charge of disabling endpoints... usually disconnect().
  848. * The exception would be entering a high speed test mode.
  849. *
  850. * FIXME remove this code ... and retest thoroughly.
  851. */
  852. list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) {
  853. if (ep->ep.desc) {
  854. spin_unlock(&udc->lock);
  855. usba_ep_disable(&ep->ep);
  856. spin_lock(&udc->lock);
  857. }
  858. }
  859. }
  860. static struct usba_ep *get_ep_by_addr(struct usba_udc *udc, u16 wIndex)
  861. {
  862. struct usba_ep *ep;
  863. if ((wIndex & USB_ENDPOINT_NUMBER_MASK) == 0)
  864. return to_usba_ep(udc->gadget.ep0);
  865. list_for_each_entry (ep, &udc->gadget.ep_list, ep.ep_list) {
  866. u8 bEndpointAddress;
  867. if (!ep->ep.desc)
  868. continue;
  869. bEndpointAddress = ep->ep.desc->bEndpointAddress;
  870. if ((wIndex ^ bEndpointAddress) & USB_DIR_IN)
  871. continue;
  872. if ((bEndpointAddress & USB_ENDPOINT_NUMBER_MASK)
  873. == (wIndex & USB_ENDPOINT_NUMBER_MASK))
  874. return ep;
  875. }
  876. return NULL;
  877. }
  878. /* Called with interrupts disabled and udc->lock held */
  879. static inline void set_protocol_stall(struct usba_udc *udc, struct usba_ep *ep)
  880. {
  881. usba_ep_writel(ep, SET_STA, USBA_FORCE_STALL);
  882. ep->state = WAIT_FOR_SETUP;
  883. }
  884. static inline int is_stalled(struct usba_udc *udc, struct usba_ep *ep)
  885. {
  886. if (usba_ep_readl(ep, STA) & USBA_FORCE_STALL)
  887. return 1;
  888. return 0;
  889. }
  890. static inline void set_address(struct usba_udc *udc, unsigned int addr)
  891. {
  892. u32 regval;
  893. DBG(DBG_BUS, "setting address %u...\n", addr);
  894. regval = usba_readl(udc, CTRL);
  895. regval = USBA_BFINS(DEV_ADDR, addr, regval);
  896. usba_writel(udc, CTRL, regval);
  897. }
  898. static int do_test_mode(struct usba_udc *udc)
  899. {
  900. static const char test_packet_buffer[] = {
  901. /* JKJKJKJK * 9 */
  902. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  903. /* JJKKJJKK * 8 */
  904. 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA,
  905. /* JJKKJJKK * 8 */
  906. 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE,
  907. /* JJJJJJJKKKKKKK * 8 */
  908. 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
  909. 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
  910. /* JJJJJJJK * 8 */
  911. 0x7F, 0xBF, 0xDF, 0xEF, 0xF7, 0xFB, 0xFD,
  912. /* {JKKKKKKK * 10}, JK */
  913. 0xFC, 0x7E, 0xBF, 0xDF, 0xEF, 0xF7, 0xFB, 0xFD, 0x7E
  914. };
  915. struct usba_ep *ep;
  916. struct device *dev = &udc->pdev->dev;
  917. int test_mode;
  918. test_mode = udc->test_mode;
  919. /* Start from a clean slate */
  920. reset_all_endpoints(udc);
  921. switch (test_mode) {
  922. case 0x0100:
  923. /* Test_J */
  924. usba_writel(udc, TST, USBA_TST_J_MODE);
  925. dev_info(dev, "Entering Test_J mode...\n");
  926. break;
  927. case 0x0200:
  928. /* Test_K */
  929. usba_writel(udc, TST, USBA_TST_K_MODE);
  930. dev_info(dev, "Entering Test_K mode...\n");
  931. break;
  932. case 0x0300:
  933. /*
  934. * Test_SE0_NAK: Force high-speed mode and set up ep0
  935. * for Bulk IN transfers
  936. */
  937. ep = &udc->usba_ep[0];
  938. usba_writel(udc, TST,
  939. USBA_BF(SPEED_CFG, USBA_SPEED_CFG_FORCE_HIGH));
  940. usba_ep_writel(ep, CFG,
  941. USBA_BF(EPT_SIZE, USBA_EPT_SIZE_64)
  942. | USBA_EPT_DIR_IN
  943. | USBA_BF(EPT_TYPE, USBA_EPT_TYPE_BULK)
  944. | USBA_BF(BK_NUMBER, 1));
  945. if (!(usba_ep_readl(ep, CFG) & USBA_EPT_MAPPED)) {
  946. set_protocol_stall(udc, ep);
  947. dev_err(dev, "Test_SE0_NAK: ep0 not mapped\n");
  948. } else {
  949. usba_ep_writel(ep, CTL_ENB, USBA_EPT_ENABLE);
  950. dev_info(dev, "Entering Test_SE0_NAK mode...\n");
  951. }
  952. break;
  953. case 0x0400:
  954. /* Test_Packet */
  955. ep = &udc->usba_ep[0];
  956. usba_ep_writel(ep, CFG,
  957. USBA_BF(EPT_SIZE, USBA_EPT_SIZE_64)
  958. | USBA_EPT_DIR_IN
  959. | USBA_BF(EPT_TYPE, USBA_EPT_TYPE_BULK)
  960. | USBA_BF(BK_NUMBER, 1));
  961. if (!(usba_ep_readl(ep, CFG) & USBA_EPT_MAPPED)) {
  962. set_protocol_stall(udc, ep);
  963. dev_err(dev, "Test_Packet: ep0 not mapped\n");
  964. } else {
  965. usba_ep_writel(ep, CTL_ENB, USBA_EPT_ENABLE);
  966. usba_writel(udc, TST, USBA_TST_PKT_MODE);
  967. memcpy_toio(ep->fifo, test_packet_buffer,
  968. sizeof(test_packet_buffer));
  969. usba_ep_writel(ep, SET_STA, USBA_TX_PK_RDY);
  970. dev_info(dev, "Entering Test_Packet mode...\n");
  971. }
  972. break;
  973. default:
  974. dev_err(dev, "Invalid test mode: 0x%04x\n", test_mode);
  975. return -EINVAL;
  976. }
  977. return 0;
  978. }
  979. /* Avoid overly long expressions */
  980. static inline bool feature_is_dev_remote_wakeup(struct usb_ctrlrequest *crq)
  981. {
  982. if (crq->wValue == cpu_to_le16(USB_DEVICE_REMOTE_WAKEUP))
  983. return true;
  984. return false;
  985. }
  986. static inline bool feature_is_dev_test_mode(struct usb_ctrlrequest *crq)
  987. {
  988. if (crq->wValue == cpu_to_le16(USB_DEVICE_TEST_MODE))
  989. return true;
  990. return false;
  991. }
  992. static inline bool feature_is_ep_halt(struct usb_ctrlrequest *crq)
  993. {
  994. if (crq->wValue == cpu_to_le16(USB_ENDPOINT_HALT))
  995. return true;
  996. return false;
  997. }
  998. static int handle_ep0_setup(struct usba_udc *udc, struct usba_ep *ep,
  999. struct usb_ctrlrequest *crq)
  1000. {
  1001. int retval = 0;
  1002. switch (crq->bRequest) {
  1003. case USB_REQ_GET_STATUS: {
  1004. u16 status;
  1005. if (crq->bRequestType == (USB_DIR_IN | USB_RECIP_DEVICE)) {
  1006. status = cpu_to_le16(udc->devstatus);
  1007. } else if (crq->bRequestType
  1008. == (USB_DIR_IN | USB_RECIP_INTERFACE)) {
  1009. status = cpu_to_le16(0);
  1010. } else if (crq->bRequestType
  1011. == (USB_DIR_IN | USB_RECIP_ENDPOINT)) {
  1012. struct usba_ep *target;
  1013. target = get_ep_by_addr(udc, le16_to_cpu(crq->wIndex));
  1014. if (!target)
  1015. goto stall;
  1016. status = 0;
  1017. if (is_stalled(udc, target))
  1018. status |= cpu_to_le16(1);
  1019. } else
  1020. goto delegate;
  1021. /* Write directly to the FIFO. No queueing is done. */
  1022. if (crq->wLength != cpu_to_le16(sizeof(status)))
  1023. goto stall;
  1024. ep->state = DATA_STAGE_IN;
  1025. __raw_writew(status, ep->fifo);
  1026. usba_ep_writel(ep, SET_STA, USBA_TX_PK_RDY);
  1027. break;
  1028. }
  1029. case USB_REQ_CLEAR_FEATURE: {
  1030. if (crq->bRequestType == USB_RECIP_DEVICE) {
  1031. if (feature_is_dev_remote_wakeup(crq))
  1032. udc->devstatus
  1033. &= ~(1 << USB_DEVICE_REMOTE_WAKEUP);
  1034. else
  1035. /* Can't CLEAR_FEATURE TEST_MODE */
  1036. goto stall;
  1037. } else if (crq->bRequestType == USB_RECIP_ENDPOINT) {
  1038. struct usba_ep *target;
  1039. if (crq->wLength != cpu_to_le16(0)
  1040. || !feature_is_ep_halt(crq))
  1041. goto stall;
  1042. target = get_ep_by_addr(udc, le16_to_cpu(crq->wIndex));
  1043. if (!target)
  1044. goto stall;
  1045. usba_ep_writel(target, CLR_STA, USBA_FORCE_STALL);
  1046. if (target->index != 0)
  1047. usba_ep_writel(target, CLR_STA,
  1048. USBA_TOGGLE_CLR);
  1049. } else {
  1050. goto delegate;
  1051. }
  1052. send_status(udc, ep);
  1053. break;
  1054. }
  1055. case USB_REQ_SET_FEATURE: {
  1056. if (crq->bRequestType == USB_RECIP_DEVICE) {
  1057. if (feature_is_dev_test_mode(crq)) {
  1058. send_status(udc, ep);
  1059. ep->state = STATUS_STAGE_TEST;
  1060. udc->test_mode = le16_to_cpu(crq->wIndex);
  1061. return 0;
  1062. } else if (feature_is_dev_remote_wakeup(crq)) {
  1063. udc->devstatus |= 1 << USB_DEVICE_REMOTE_WAKEUP;
  1064. } else {
  1065. goto stall;
  1066. }
  1067. } else if (crq->bRequestType == USB_RECIP_ENDPOINT) {
  1068. struct usba_ep *target;
  1069. if (crq->wLength != cpu_to_le16(0)
  1070. || !feature_is_ep_halt(crq))
  1071. goto stall;
  1072. target = get_ep_by_addr(udc, le16_to_cpu(crq->wIndex));
  1073. if (!target)
  1074. goto stall;
  1075. usba_ep_writel(target, SET_STA, USBA_FORCE_STALL);
  1076. } else
  1077. goto delegate;
  1078. send_status(udc, ep);
  1079. break;
  1080. }
  1081. case USB_REQ_SET_ADDRESS:
  1082. if (crq->bRequestType != (USB_DIR_OUT | USB_RECIP_DEVICE))
  1083. goto delegate;
  1084. set_address(udc, le16_to_cpu(crq->wValue));
  1085. send_status(udc, ep);
  1086. ep->state = STATUS_STAGE_ADDR;
  1087. break;
  1088. default:
  1089. delegate:
  1090. spin_unlock(&udc->lock);
  1091. retval = udc->driver->setup(&udc->gadget, crq);
  1092. spin_lock(&udc->lock);
  1093. }
  1094. return retval;
  1095. stall:
  1096. pr_err("udc: %s: Invalid setup request: %02x.%02x v%04x i%04x l%d, "
  1097. "halting endpoint...\n",
  1098. ep->ep.name, crq->bRequestType, crq->bRequest,
  1099. le16_to_cpu(crq->wValue), le16_to_cpu(crq->wIndex),
  1100. le16_to_cpu(crq->wLength));
  1101. set_protocol_stall(udc, ep);
  1102. return -1;
  1103. }
  1104. static void usba_control_irq(struct usba_udc *udc, struct usba_ep *ep)
  1105. {
  1106. struct usba_request *req;
  1107. u32 epstatus;
  1108. u32 epctrl;
  1109. restart:
  1110. epstatus = usba_ep_readl(ep, STA);
  1111. epctrl = usba_ep_readl(ep, CTL);
  1112. DBG(DBG_INT, "%s [%d]: s/%08x c/%08x\n",
  1113. ep->ep.name, ep->state, epstatus, epctrl);
  1114. req = NULL;
  1115. if (!list_empty(&ep->queue))
  1116. req = list_entry(ep->queue.next,
  1117. struct usba_request, queue);
  1118. if ((epctrl & USBA_TX_PK_RDY) && !(epstatus & USBA_TX_PK_RDY)) {
  1119. if (req->submitted)
  1120. next_fifo_transaction(ep, req);
  1121. else
  1122. submit_request(ep, req);
  1123. if (req->last_transaction) {
  1124. usba_ep_writel(ep, CTL_DIS, USBA_TX_PK_RDY);
  1125. usba_ep_writel(ep, CTL_ENB, USBA_TX_COMPLETE);
  1126. }
  1127. goto restart;
  1128. }
  1129. if ((epstatus & epctrl) & USBA_TX_COMPLETE) {
  1130. usba_ep_writel(ep, CLR_STA, USBA_TX_COMPLETE);
  1131. switch (ep->state) {
  1132. case DATA_STAGE_IN:
  1133. usba_ep_writel(ep, CTL_ENB, USBA_RX_BK_RDY);
  1134. usba_ep_writel(ep, CTL_DIS, USBA_TX_COMPLETE);
  1135. ep->state = STATUS_STAGE_OUT;
  1136. break;
  1137. case STATUS_STAGE_ADDR:
  1138. /* Activate our new address */
  1139. usba_writel(udc, CTRL, (usba_readl(udc, CTRL)
  1140. | USBA_FADDR_EN));
  1141. usba_ep_writel(ep, CTL_DIS, USBA_TX_COMPLETE);
  1142. ep->state = WAIT_FOR_SETUP;
  1143. break;
  1144. case STATUS_STAGE_IN:
  1145. if (req) {
  1146. list_del_init(&req->queue);
  1147. request_complete(ep, req, 0);
  1148. submit_next_request(ep);
  1149. }
  1150. usba_ep_writel(ep, CTL_DIS, USBA_TX_COMPLETE);
  1151. ep->state = WAIT_FOR_SETUP;
  1152. break;
  1153. case STATUS_STAGE_TEST:
  1154. usba_ep_writel(ep, CTL_DIS, USBA_TX_COMPLETE);
  1155. ep->state = WAIT_FOR_SETUP;
  1156. if (do_test_mode(udc))
  1157. set_protocol_stall(udc, ep);
  1158. break;
  1159. default:
  1160. pr_err("udc: %s: TXCOMP: Invalid endpoint state %d, "
  1161. "halting endpoint...\n",
  1162. ep->ep.name, ep->state);
  1163. set_protocol_stall(udc, ep);
  1164. break;
  1165. }
  1166. goto restart;
  1167. }
  1168. if ((epstatus & epctrl) & USBA_RX_BK_RDY) {
  1169. switch (ep->state) {
  1170. case STATUS_STAGE_OUT:
  1171. usba_ep_writel(ep, CLR_STA, USBA_RX_BK_RDY);
  1172. usba_ep_writel(ep, CTL_DIS, USBA_RX_BK_RDY);
  1173. if (req) {
  1174. list_del_init(&req->queue);
  1175. request_complete(ep, req, 0);
  1176. }
  1177. ep->state = WAIT_FOR_SETUP;
  1178. break;
  1179. case DATA_STAGE_OUT:
  1180. receive_data(ep);
  1181. break;
  1182. default:
  1183. usba_ep_writel(ep, CLR_STA, USBA_RX_BK_RDY);
  1184. usba_ep_writel(ep, CTL_DIS, USBA_RX_BK_RDY);
  1185. pr_err("udc: %s: RXRDY: Invalid endpoint state %d, "
  1186. "halting endpoint...\n",
  1187. ep->ep.name, ep->state);
  1188. set_protocol_stall(udc, ep);
  1189. break;
  1190. }
  1191. goto restart;
  1192. }
  1193. if (epstatus & USBA_RX_SETUP) {
  1194. union {
  1195. struct usb_ctrlrequest crq;
  1196. unsigned long data[2];
  1197. } crq;
  1198. unsigned int pkt_len;
  1199. int ret;
  1200. if (ep->state != WAIT_FOR_SETUP) {
  1201. /*
  1202. * Didn't expect a SETUP packet at this
  1203. * point. Clean up any pending requests (which
  1204. * may be successful).
  1205. */
  1206. int status = -EPROTO;
  1207. /*
  1208. * RXRDY and TXCOMP are dropped when SETUP
  1209. * packets arrive. Just pretend we received
  1210. * the status packet.
  1211. */
  1212. if (ep->state == STATUS_STAGE_OUT
  1213. || ep->state == STATUS_STAGE_IN) {
  1214. usba_ep_writel(ep, CTL_DIS, USBA_RX_BK_RDY);
  1215. status = 0;
  1216. }
  1217. if (req) {
  1218. list_del_init(&req->queue);
  1219. request_complete(ep, req, status);
  1220. }
  1221. }
  1222. pkt_len = USBA_BFEXT(BYTE_COUNT, usba_ep_readl(ep, STA));
  1223. DBG(DBG_HW, "Packet length: %u\n", pkt_len);
  1224. if (pkt_len != sizeof(crq)) {
  1225. pr_warning("udc: Invalid packet length %u "
  1226. "(expected %zu)\n", pkt_len, sizeof(crq));
  1227. set_protocol_stall(udc, ep);
  1228. return;
  1229. }
  1230. DBG(DBG_FIFO, "Copying ctrl request from 0x%p:\n", ep->fifo);
  1231. memcpy_fromio(crq.data, ep->fifo, sizeof(crq));
  1232. /* Free up one bank in the FIFO so that we can
  1233. * generate or receive a reply right away. */
  1234. usba_ep_writel(ep, CLR_STA, USBA_RX_SETUP);
  1235. /* printk(KERN_DEBUG "setup: %d: %02x.%02x\n",
  1236. ep->state, crq.crq.bRequestType,
  1237. crq.crq.bRequest); */
  1238. if (crq.crq.bRequestType & USB_DIR_IN) {
  1239. /*
  1240. * The USB 2.0 spec states that "if wLength is
  1241. * zero, there is no data transfer phase."
  1242. * However, testusb #14 seems to actually
  1243. * expect a data phase even if wLength = 0...
  1244. */
  1245. ep->state = DATA_STAGE_IN;
  1246. } else {
  1247. if (crq.crq.wLength != cpu_to_le16(0))
  1248. ep->state = DATA_STAGE_OUT;
  1249. else
  1250. ep->state = STATUS_STAGE_IN;
  1251. }
  1252. ret = -1;
  1253. if (ep->index == 0)
  1254. ret = handle_ep0_setup(udc, ep, &crq.crq);
  1255. else {
  1256. spin_unlock(&udc->lock);
  1257. ret = udc->driver->setup(&udc->gadget, &crq.crq);
  1258. spin_lock(&udc->lock);
  1259. }
  1260. DBG(DBG_BUS, "req %02x.%02x, length %d, state %d, ret %d\n",
  1261. crq.crq.bRequestType, crq.crq.bRequest,
  1262. le16_to_cpu(crq.crq.wLength), ep->state, ret);
  1263. if (ret < 0) {
  1264. /* Let the host know that we failed */
  1265. set_protocol_stall(udc, ep);
  1266. }
  1267. }
  1268. }
  1269. static void usba_ep_irq(struct usba_udc *udc, struct usba_ep *ep)
  1270. {
  1271. struct usba_request *req;
  1272. u32 epstatus;
  1273. u32 epctrl;
  1274. epstatus = usba_ep_readl(ep, STA);
  1275. epctrl = usba_ep_readl(ep, CTL);
  1276. DBG(DBG_INT, "%s: interrupt, status: 0x%08x\n", ep->ep.name, epstatus);
  1277. while ((epctrl & USBA_TX_PK_RDY) && !(epstatus & USBA_TX_PK_RDY)) {
  1278. DBG(DBG_BUS, "%s: TX PK ready\n", ep->ep.name);
  1279. if (list_empty(&ep->queue)) {
  1280. dev_warn(&udc->pdev->dev, "ep_irq: queue empty\n");
  1281. usba_ep_writel(ep, CTL_DIS, USBA_TX_PK_RDY);
  1282. return;
  1283. }
  1284. req = list_entry(ep->queue.next, struct usba_request, queue);
  1285. if (req->using_dma) {
  1286. /* Send a zero-length packet */
  1287. usba_ep_writel(ep, SET_STA,
  1288. USBA_TX_PK_RDY);
  1289. usba_ep_writel(ep, CTL_DIS,
  1290. USBA_TX_PK_RDY);
  1291. list_del_init(&req->queue);
  1292. submit_next_request(ep);
  1293. request_complete(ep, req, 0);
  1294. } else {
  1295. if (req->submitted)
  1296. next_fifo_transaction(ep, req);
  1297. else
  1298. submit_request(ep, req);
  1299. if (req->last_transaction) {
  1300. list_del_init(&req->queue);
  1301. submit_next_request(ep);
  1302. request_complete(ep, req, 0);
  1303. }
  1304. }
  1305. epstatus = usba_ep_readl(ep, STA);
  1306. epctrl = usba_ep_readl(ep, CTL);
  1307. }
  1308. if ((epstatus & epctrl) & USBA_RX_BK_RDY) {
  1309. DBG(DBG_BUS, "%s: RX data ready\n", ep->ep.name);
  1310. receive_data(ep);
  1311. usba_ep_writel(ep, CLR_STA, USBA_RX_BK_RDY);
  1312. }
  1313. }
  1314. static void usba_dma_irq(struct usba_udc *udc, struct usba_ep *ep)
  1315. {
  1316. struct usba_request *req;
  1317. u32 status, control, pending;
  1318. status = usba_dma_readl(ep, STATUS);
  1319. control = usba_dma_readl(ep, CONTROL);
  1320. #ifdef CONFIG_USB_GADGET_DEBUG_FS
  1321. ep->last_dma_status = status;
  1322. #endif
  1323. pending = status & control;
  1324. DBG(DBG_INT | DBG_DMA, "dma irq, s/%#08x, c/%#08x\n", status, control);
  1325. if (status & USBA_DMA_CH_EN) {
  1326. dev_err(&udc->pdev->dev,
  1327. "DMA_CH_EN is set after transfer is finished!\n");
  1328. dev_err(&udc->pdev->dev,
  1329. "status=%#08x, pending=%#08x, control=%#08x\n",
  1330. status, pending, control);
  1331. /*
  1332. * try to pretend nothing happened. We might have to
  1333. * do something here...
  1334. */
  1335. }
  1336. if (list_empty(&ep->queue))
  1337. /* Might happen if a reset comes along at the right moment */
  1338. return;
  1339. if (pending & (USBA_DMA_END_TR_ST | USBA_DMA_END_BUF_ST)) {
  1340. req = list_entry(ep->queue.next, struct usba_request, queue);
  1341. usba_update_req(ep, req, status);
  1342. list_del_init(&req->queue);
  1343. submit_next_request(ep);
  1344. request_complete(ep, req, 0);
  1345. }
  1346. }
  1347. static irqreturn_t usba_udc_irq(int irq, void *devid)
  1348. {
  1349. struct usba_udc *udc = devid;
  1350. u32 status;
  1351. u32 dma_status;
  1352. u32 ep_status;
  1353. spin_lock(&udc->lock);
  1354. status = usba_readl(udc, INT_STA);
  1355. DBG(DBG_INT, "irq, status=%#08x\n", status);
  1356. if (status & USBA_DET_SUSPEND) {
  1357. toggle_bias(0);
  1358. usba_writel(udc, INT_CLR, USBA_DET_SUSPEND);
  1359. DBG(DBG_BUS, "Suspend detected\n");
  1360. if (udc->gadget.speed != USB_SPEED_UNKNOWN
  1361. && udc->driver && udc->driver->suspend) {
  1362. spin_unlock(&udc->lock);
  1363. udc->driver->suspend(&udc->gadget);
  1364. spin_lock(&udc->lock);
  1365. }
  1366. }
  1367. if (status & USBA_WAKE_UP) {
  1368. toggle_bias(1);
  1369. usba_writel(udc, INT_CLR, USBA_WAKE_UP);
  1370. DBG(DBG_BUS, "Wake Up CPU detected\n");
  1371. }
  1372. if (status & USBA_END_OF_RESUME) {
  1373. usba_writel(udc, INT_CLR, USBA_END_OF_RESUME);
  1374. DBG(DBG_BUS, "Resume detected\n");
  1375. if (udc->gadget.speed != USB_SPEED_UNKNOWN
  1376. && udc->driver && udc->driver->resume) {
  1377. spin_unlock(&udc->lock);
  1378. udc->driver->resume(&udc->gadget);
  1379. spin_lock(&udc->lock);
  1380. }
  1381. }
  1382. dma_status = USBA_BFEXT(DMA_INT, status);
  1383. if (dma_status) {
  1384. int i;
  1385. for (i = 1; i < USBA_NR_ENDPOINTS; i++)
  1386. if (dma_status & (1 << i))
  1387. usba_dma_irq(udc, &udc->usba_ep[i]);
  1388. }
  1389. ep_status = USBA_BFEXT(EPT_INT, status);
  1390. if (ep_status) {
  1391. int i;
  1392. for (i = 0; i < USBA_NR_ENDPOINTS; i++)
  1393. if (ep_status & (1 << i)) {
  1394. if (ep_is_control(&udc->usba_ep[i]))
  1395. usba_control_irq(udc, &udc->usba_ep[i]);
  1396. else
  1397. usba_ep_irq(udc, &udc->usba_ep[i]);
  1398. }
  1399. }
  1400. if (status & USBA_END_OF_RESET) {
  1401. struct usba_ep *ep0;
  1402. usba_writel(udc, INT_CLR, USBA_END_OF_RESET);
  1403. reset_all_endpoints(udc);
  1404. if (udc->gadget.speed != USB_SPEED_UNKNOWN
  1405. && udc->driver->disconnect) {
  1406. udc->gadget.speed = USB_SPEED_UNKNOWN;
  1407. spin_unlock(&udc->lock);
  1408. udc->driver->disconnect(&udc->gadget);
  1409. spin_lock(&udc->lock);
  1410. }
  1411. if (status & USBA_HIGH_SPEED)
  1412. udc->gadget.speed = USB_SPEED_HIGH;
  1413. else
  1414. udc->gadget.speed = USB_SPEED_FULL;
  1415. DBG(DBG_BUS, "%s bus reset detected\n",
  1416. usb_speed_string(udc->gadget.speed));
  1417. ep0 = &udc->usba_ep[0];
  1418. ep0->ep.desc = &usba_ep0_desc;
  1419. ep0->state = WAIT_FOR_SETUP;
  1420. usba_ep_writel(ep0, CFG,
  1421. (USBA_BF(EPT_SIZE, EP0_EPT_SIZE)
  1422. | USBA_BF(EPT_TYPE, USBA_EPT_TYPE_CONTROL)
  1423. | USBA_BF(BK_NUMBER, USBA_BK_NUMBER_ONE)));
  1424. usba_ep_writel(ep0, CTL_ENB,
  1425. USBA_EPT_ENABLE | USBA_RX_SETUP);
  1426. usba_writel(udc, INT_ENB,
  1427. (usba_readl(udc, INT_ENB)
  1428. | USBA_BF(EPT_INT, 1)
  1429. | USBA_DET_SUSPEND
  1430. | USBA_END_OF_RESUME));
  1431. /*
  1432. * Unclear why we hit this irregularly, e.g. in usbtest,
  1433. * but it's clearly harmless...
  1434. */
  1435. if (!(usba_ep_readl(ep0, CFG) & USBA_EPT_MAPPED))
  1436. dev_dbg(&udc->pdev->dev,
  1437. "ODD: EP0 configuration is invalid!\n");
  1438. }
  1439. spin_unlock(&udc->lock);
  1440. return IRQ_HANDLED;
  1441. }
  1442. static irqreturn_t usba_vbus_irq(int irq, void *devid)
  1443. {
  1444. struct usba_udc *udc = devid;
  1445. int vbus;
  1446. /* debounce */
  1447. udelay(10);
  1448. spin_lock(&udc->lock);
  1449. /* May happen if Vbus pin toggles during probe() */
  1450. if (!udc->driver)
  1451. goto out;
  1452. vbus = vbus_is_present(udc);
  1453. if (vbus != udc->vbus_prev) {
  1454. if (vbus) {
  1455. toggle_bias(1);
  1456. usba_writel(udc, CTRL, USBA_ENABLE_MASK);
  1457. usba_writel(udc, INT_ENB, USBA_END_OF_RESET);
  1458. } else {
  1459. udc->gadget.speed = USB_SPEED_UNKNOWN;
  1460. reset_all_endpoints(udc);
  1461. toggle_bias(0);
  1462. usba_writel(udc, CTRL, USBA_DISABLE_MASK);
  1463. if (udc->driver->disconnect) {
  1464. spin_unlock(&udc->lock);
  1465. udc->driver->disconnect(&udc->gadget);
  1466. spin_lock(&udc->lock);
  1467. }
  1468. }
  1469. udc->vbus_prev = vbus;
  1470. }
  1471. out:
  1472. spin_unlock(&udc->lock);
  1473. return IRQ_HANDLED;
  1474. }
  1475. static int atmel_usba_start(struct usb_gadget *gadget,
  1476. struct usb_gadget_driver *driver)
  1477. {
  1478. struct usba_udc *udc = container_of(gadget, struct usba_udc, gadget);
  1479. unsigned long flags;
  1480. spin_lock_irqsave(&udc->lock, flags);
  1481. udc->devstatus = 1 << USB_DEVICE_SELF_POWERED;
  1482. udc->driver = driver;
  1483. spin_unlock_irqrestore(&udc->lock, flags);
  1484. clk_enable(udc->pclk);
  1485. clk_enable(udc->hclk);
  1486. DBG(DBG_GADGET, "registered driver `%s'\n", driver->driver.name);
  1487. udc->vbus_prev = 0;
  1488. if (gpio_is_valid(udc->vbus_pin))
  1489. enable_irq(gpio_to_irq(udc->vbus_pin));
  1490. /* If Vbus is present, enable the controller and wait for reset */
  1491. spin_lock_irqsave(&udc->lock, flags);
  1492. if (vbus_is_present(udc) && udc->vbus_prev == 0) {
  1493. toggle_bias(1);
  1494. usba_writel(udc, CTRL, USBA_ENABLE_MASK);
  1495. usba_writel(udc, INT_ENB, USBA_END_OF_RESET);
  1496. }
  1497. spin_unlock_irqrestore(&udc->lock, flags);
  1498. return 0;
  1499. }
  1500. static int atmel_usba_stop(struct usb_gadget *gadget,
  1501. struct usb_gadget_driver *driver)
  1502. {
  1503. struct usba_udc *udc = container_of(gadget, struct usba_udc, gadget);
  1504. unsigned long flags;
  1505. if (gpio_is_valid(udc->vbus_pin))
  1506. disable_irq(gpio_to_irq(udc->vbus_pin));
  1507. spin_lock_irqsave(&udc->lock, flags);
  1508. udc->gadget.speed = USB_SPEED_UNKNOWN;
  1509. reset_all_endpoints(udc);
  1510. spin_unlock_irqrestore(&udc->lock, flags);
  1511. /* This will also disable the DP pullup */
  1512. toggle_bias(0);
  1513. usba_writel(udc, CTRL, USBA_DISABLE_MASK);
  1514. udc->driver = NULL;
  1515. clk_disable(udc->hclk);
  1516. clk_disable(udc->pclk);
  1517. DBG(DBG_GADGET, "unregistered driver `%s'\n", driver->driver.name);
  1518. return 0;
  1519. }
  1520. static int __init usba_udc_probe(struct platform_device *pdev)
  1521. {
  1522. struct usba_platform_data *pdata = pdev->dev.platform_data;
  1523. struct resource *regs, *fifo;
  1524. struct clk *pclk, *hclk;
  1525. struct usba_udc *udc;
  1526. static struct usba_ep *usba_ep;
  1527. int irq, ret, i;
  1528. udc = devm_kzalloc(&pdev->dev, sizeof(*udc), GFP_KERNEL);
  1529. if (!udc)
  1530. return -ENOMEM;
  1531. udc->gadget = usba_gadget_template;
  1532. INIT_LIST_HEAD(&udc->gadget.ep_list);
  1533. regs = platform_get_resource(pdev, IORESOURCE_MEM, CTRL_IOMEM_ID);
  1534. fifo = platform_get_resource(pdev, IORESOURCE_MEM, FIFO_IOMEM_ID);
  1535. if (!regs || !fifo || !pdata)
  1536. return -ENXIO;
  1537. irq = platform_get_irq(pdev, 0);
  1538. if (irq < 0)
  1539. return irq;
  1540. pclk = clk_get(&pdev->dev, "pclk");
  1541. if (IS_ERR(pclk))
  1542. return PTR_ERR(pclk);
  1543. hclk = clk_get(&pdev->dev, "hclk");
  1544. if (IS_ERR(hclk)) {
  1545. ret = PTR_ERR(hclk);
  1546. goto err_get_hclk;
  1547. }
  1548. spin_lock_init(&udc->lock);
  1549. udc->pdev = pdev;
  1550. udc->pclk = pclk;
  1551. udc->hclk = hclk;
  1552. udc->vbus_pin = -ENODEV;
  1553. ret = -ENOMEM;
  1554. udc->regs = ioremap(regs->start, resource_size(regs));
  1555. if (!udc->regs) {
  1556. dev_err(&pdev->dev, "Unable to map I/O memory, aborting.\n");
  1557. goto err_map_regs;
  1558. }
  1559. dev_info(&pdev->dev, "MMIO registers at 0x%08lx mapped at %p\n",
  1560. (unsigned long)regs->start, udc->regs);
  1561. udc->fifo = ioremap(fifo->start, resource_size(fifo));
  1562. if (!udc->fifo) {
  1563. dev_err(&pdev->dev, "Unable to map FIFO, aborting.\n");
  1564. goto err_map_fifo;
  1565. }
  1566. dev_info(&pdev->dev, "FIFO at 0x%08lx mapped at %p\n",
  1567. (unsigned long)fifo->start, udc->fifo);
  1568. platform_set_drvdata(pdev, udc);
  1569. /* Make sure we start from a clean slate */
  1570. clk_enable(pclk);
  1571. toggle_bias(0);
  1572. usba_writel(udc, CTRL, USBA_DISABLE_MASK);
  1573. clk_disable(pclk);
  1574. usba_ep = kzalloc(sizeof(struct usba_ep) * pdata->num_ep,
  1575. GFP_KERNEL);
  1576. if (!usba_ep)
  1577. goto err_alloc_ep;
  1578. udc->usba_ep = usba_ep;
  1579. udc->gadget.ep0 = &usba_ep[0].ep;
  1580. INIT_LIST_HEAD(&usba_ep[0].ep.ep_list);
  1581. usba_ep[0].ep_regs = udc->regs + USBA_EPT_BASE(0);
  1582. usba_ep[0].dma_regs = udc->regs + USBA_DMA_BASE(0);
  1583. usba_ep[0].fifo = udc->fifo + USBA_FIFO_BASE(0);
  1584. usba_ep[0].ep.ops = &usba_ep_ops;
  1585. usba_ep[0].ep.name = pdata->ep[0].name;
  1586. usba_ep[0].ep.maxpacket = pdata->ep[0].fifo_size;
  1587. usba_ep[0].udc = udc;
  1588. INIT_LIST_HEAD(&usba_ep[0].queue);
  1589. usba_ep[0].fifo_size = pdata->ep[0].fifo_size;
  1590. usba_ep[0].nr_banks = pdata->ep[0].nr_banks;
  1591. usba_ep[0].index = pdata->ep[0].index;
  1592. usba_ep[0].can_dma = pdata->ep[0].can_dma;
  1593. usba_ep[0].can_isoc = pdata->ep[0].can_isoc;
  1594. for (i = 1; i < pdata->num_ep; i++) {
  1595. struct usba_ep *ep = &usba_ep[i];
  1596. ep->ep_regs = udc->regs + USBA_EPT_BASE(i);
  1597. ep->dma_regs = udc->regs + USBA_DMA_BASE(i);
  1598. ep->fifo = udc->fifo + USBA_FIFO_BASE(i);
  1599. ep->ep.ops = &usba_ep_ops;
  1600. ep->ep.name = pdata->ep[i].name;
  1601. ep->ep.maxpacket = pdata->ep[i].fifo_size;
  1602. ep->udc = udc;
  1603. INIT_LIST_HEAD(&ep->queue);
  1604. ep->fifo_size = pdata->ep[i].fifo_size;
  1605. ep->nr_banks = pdata->ep[i].nr_banks;
  1606. ep->index = pdata->ep[i].index;
  1607. ep->can_dma = pdata->ep[i].can_dma;
  1608. ep->can_isoc = pdata->ep[i].can_isoc;
  1609. list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
  1610. }
  1611. ret = request_irq(irq, usba_udc_irq, 0, "atmel_usba_udc", udc);
  1612. if (ret) {
  1613. dev_err(&pdev->dev, "Cannot request irq %d (error %d)\n",
  1614. irq, ret);
  1615. goto err_request_irq;
  1616. }
  1617. udc->irq = irq;
  1618. if (gpio_is_valid(pdata->vbus_pin)) {
  1619. if (!gpio_request(pdata->vbus_pin, "atmel_usba_udc")) {
  1620. udc->vbus_pin = pdata->vbus_pin;
  1621. udc->vbus_pin_inverted = pdata->vbus_pin_inverted;
  1622. ret = request_irq(gpio_to_irq(udc->vbus_pin),
  1623. usba_vbus_irq, 0,
  1624. "atmel_usba_udc", udc);
  1625. if (ret) {
  1626. gpio_free(udc->vbus_pin);
  1627. udc->vbus_pin = -ENODEV;
  1628. dev_warn(&udc->pdev->dev,
  1629. "failed to request vbus irq; "
  1630. "assuming always on\n");
  1631. } else {
  1632. disable_irq(gpio_to_irq(udc->vbus_pin));
  1633. }
  1634. } else {
  1635. /* gpio_request fail so use -EINVAL for gpio_is_valid */
  1636. udc->vbus_pin = -EINVAL;
  1637. }
  1638. }
  1639. ret = usb_add_gadget_udc(&pdev->dev, &udc->gadget);
  1640. if (ret)
  1641. goto err_add_udc;
  1642. usba_init_debugfs(udc);
  1643. for (i = 1; i < pdata->num_ep; i++)
  1644. usba_ep_init_debugfs(udc, &usba_ep[i]);
  1645. return 0;
  1646. err_add_udc:
  1647. if (gpio_is_valid(pdata->vbus_pin)) {
  1648. free_irq(gpio_to_irq(udc->vbus_pin), udc);
  1649. gpio_free(udc->vbus_pin);
  1650. }
  1651. free_irq(irq, udc);
  1652. err_request_irq:
  1653. kfree(usba_ep);
  1654. err_alloc_ep:
  1655. iounmap(udc->fifo);
  1656. err_map_fifo:
  1657. iounmap(udc->regs);
  1658. err_map_regs:
  1659. clk_put(hclk);
  1660. err_get_hclk:
  1661. clk_put(pclk);
  1662. platform_set_drvdata(pdev, NULL);
  1663. return ret;
  1664. }
  1665. static int __exit usba_udc_remove(struct platform_device *pdev)
  1666. {
  1667. struct usba_udc *udc;
  1668. int i;
  1669. struct usba_platform_data *pdata = pdev->dev.platform_data;
  1670. udc = platform_get_drvdata(pdev);
  1671. usb_del_gadget_udc(&udc->gadget);
  1672. for (i = 1; i < pdata->num_ep; i++)
  1673. usba_ep_cleanup_debugfs(&udc->usba_ep[i]);
  1674. usba_cleanup_debugfs(udc);
  1675. if (gpio_is_valid(udc->vbus_pin)) {
  1676. free_irq(gpio_to_irq(udc->vbus_pin), udc);
  1677. gpio_free(udc->vbus_pin);
  1678. }
  1679. free_irq(udc->irq, udc);
  1680. kfree(usba_ep);
  1681. iounmap(udc->fifo);
  1682. iounmap(udc->regs);
  1683. clk_put(udc->hclk);
  1684. clk_put(udc->pclk);
  1685. return 0;
  1686. }
  1687. static struct platform_driver udc_driver = {
  1688. .remove = __exit_p(usba_udc_remove),
  1689. .driver = {
  1690. .name = "atmel_usba_udc",
  1691. .owner = THIS_MODULE,
  1692. },
  1693. };
  1694. module_platform_driver_probe(udc_driver, usba_udc_probe);
  1695. MODULE_DESCRIPTION("Atmel USBA UDC driver");
  1696. MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
  1697. MODULE_LICENSE("GPL");
  1698. MODULE_ALIAS("platform:atmel_usba_udc");