Acasă Explorează Ajutor
Înregistrare Autentificare
phyus
/
linux-vybrid_public
8
0
Bifurcare 0
Fisiere Probleme 0 Trageți solicitările 0 Wiki
Arbore: e8beacbb85
Ramuri Etichete
linux-vybrid_pu...
/
drivers
/
spi
/
spi-fsl-spi.h

spi-fsl-spi.h 1.7 KB
Istoric Crud

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061 
  1. /*
    2. 

  2.  * Freescale SPI controller driver.
    3. 

  3.  *
    4. 

  4.  * Maintainer: Kumar Gala
    5. 

  5.  *
    6. 

  6.  * Copyright (C) 2006 Polycom, Inc.
    7. 

  7.  * Copyright 2010 Freescale Semiconductor, Inc.
    8. 

  8.  *
    9. 

  9.  * CPM SPI and QE buffer descriptors mode support:
    10. 

  10.  * Copyright (c) 2009  MontaVista Software, Inc.
    11. 

  11.  * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
    12. 

  12.  *
    13. 

  13.  * This program is free software; you can redistribute  it and/or modify it
    14. 

  14.  * under  the terms of  the GNU General  Public License as published by the
    15. 

  15.  * Free Software Foundation;  either version 2 of the  License, or (at your
    16. 

  16.  * option) any later version.
    17. 

  17.  */
    18. 

  18. 

  19. #ifndef __SPI_FSL_SPI_H__
    20. 

  20. #define __SPI_FSL_SPI_H__
    21. 

  21. 

  22. /* SPI Controller registers */
    23. 

  23. struct fsl_spi_reg {
    24. 

  24. 	u8 res1[0x20];
    25. 

  25. 	__be32 mode;
    26. 

  26. 	__be32 event;
    27. 

  27. 	__be32 mask;
    28. 

  28. 	__be32 command;
    29. 

  29. 	__be32 transmit;
    30. 

  30. 	__be32 receive;
    31. 

  31. };
    32. 

  32. 

  33. /* SPI Controller mode register definitions */
    34. 

  34. #define	SPMODE_LOOP		(1 << 30)
    35. 

  35. #define	SPMODE_CI_INACTIVEHIGH	(1 << 29)
    36. 

  36. #define	SPMODE_CP_BEGIN_EDGECLK	(1 << 28)
    37. 

  37. #define	SPMODE_DIV16		(1 << 27)
    38. 

  38. #define	SPMODE_REV		(1 << 26)
    39. 

  39. #define	SPMODE_MS		(1 << 25)
    40. 

  40. #define	SPMODE_ENABLE		(1 << 24)
    41. 

  41. #define	SPMODE_LEN(x)		((x) << 20)
    42. 

  42. #define	SPMODE_PM(x)		((x) << 16)
    43. 

  43. #define	SPMODE_OP		(1 << 14)
    44. 

  44. #define	SPMODE_CG(x)		((x) << 7)
    45. 

  45. 

  46. /*
    47. 

  47.  * Default for SPI Mode:
    48. 

  48.  *	SPI MODE 0 (inactive low, phase middle, MSB, 8-bit length, slow clk
    49. 

  49.  */
    50. 

  50. #define	SPMODE_INIT_VAL (SPMODE_CI_INACTIVEHIGH | SPMODE_DIV16 | SPMODE_REV | \
    51. 

  51. 			 SPMODE_MS | SPMODE_LEN(7) | SPMODE_PM(0xf))
    52. 

  52. 

  53. /* SPIE register values */
    54. 

  54. #define	SPIE_NE		0x00000200	/* Not empty */
    55. 

  55. #define	SPIE_NF		0x00000100	/* Not full */
    56. 

  56. 

  57. /* SPIM register values */
    58. 

  58. #define	SPIM_NE		0x00000200	/* Not empty */
    59. 

  59. #define	SPIM_NF		0x00000100	/* Not full */
    60. 

  60. 

  61. #endif /* __SPI_FSL_SPI_H__ */
    62.