pgtable-ppc32.h 11 KB

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  1. #ifndef _ASM_POWERPC_PGTABLE_PPC32_H
  2. #define _ASM_POWERPC_PGTABLE_PPC32_H
  3. #include <asm-generic/pgtable-nopmd.h>
  4. #ifndef __ASSEMBLY__
  5. #include <linux/sched.h>
  6. #include <linux/threads.h>
  7. #include <asm/io.h> /* For sub-arch specific PPC_PIN_SIZE */
  8. extern unsigned long va_to_phys(unsigned long address);
  9. extern pte_t *va_to_pte(unsigned long address);
  10. extern unsigned long ioremap_bot;
  11. #ifdef CONFIG_44x
  12. extern int icache_44x_need_flush;
  13. #endif
  14. #endif /* __ASSEMBLY__ */
  15. /*
  16. * The normal case is that PTEs are 32-bits and we have a 1-page
  17. * 1024-entry pgdir pointing to 1-page 1024-entry PTE pages. -- paulus
  18. *
  19. * For any >32-bit physical address platform, we can use the following
  20. * two level page table layout where the pgdir is 8KB and the MS 13 bits
  21. * are an index to the second level table. The combined pgdir/pmd first
  22. * level has 2048 entries and the second level has 512 64-bit PTE entries.
  23. * -Matt
  24. */
  25. /* PGDIR_SHIFT determines what a top-level page table entry can map */
  26. #define PGDIR_SHIFT (PAGE_SHIFT + PTE_SHIFT)
  27. #define PGDIR_SIZE (1UL << PGDIR_SHIFT)
  28. #define PGDIR_MASK (~(PGDIR_SIZE-1))
  29. /*
  30. * entries per page directory level: our page-table tree is two-level, so
  31. * we don't really have any PMD directory.
  32. */
  33. #ifndef __ASSEMBLY__
  34. #define PTE_TABLE_SIZE (sizeof(pte_t) << PTE_SHIFT)
  35. #define PGD_TABLE_SIZE (sizeof(pgd_t) << (32 - PGDIR_SHIFT))
  36. #endif /* __ASSEMBLY__ */
  37. #define PTRS_PER_PTE (1 << PTE_SHIFT)
  38. #define PTRS_PER_PMD 1
  39. #define PTRS_PER_PGD (1 << (32 - PGDIR_SHIFT))
  40. #define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE)
  41. #define FIRST_USER_ADDRESS 0
  42. #define pte_ERROR(e) \
  43. printk("%s:%d: bad pte %llx.\n", __FILE__, __LINE__, \
  44. (unsigned long long)pte_val(e))
  45. #define pgd_ERROR(e) \
  46. printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
  47. /*
  48. * This is the bottom of the PKMAP area with HIGHMEM or an arbitrary
  49. * value (for now) on others, from where we can start layout kernel
  50. * virtual space that goes below PKMAP and FIXMAP
  51. */
  52. #ifdef CONFIG_HIGHMEM
  53. #define KVIRT_TOP PKMAP_BASE
  54. #else
  55. #define KVIRT_TOP (0xfe000000UL) /* for now, could be FIXMAP_BASE ? */
  56. #endif
  57. /*
  58. * ioremap_bot starts at that address. Early ioremaps move down from there,
  59. * until mem_init() at which point this becomes the top of the vmalloc
  60. * and ioremap space
  61. */
  62. #ifdef CONFIG_NOT_COHERENT_CACHE
  63. #define IOREMAP_TOP ((KVIRT_TOP - CONFIG_CONSISTENT_SIZE) & PAGE_MASK)
  64. #else
  65. #define IOREMAP_TOP KVIRT_TOP
  66. #endif
  67. /*
  68. * Just any arbitrary offset to the start of the vmalloc VM area: the
  69. * current 16MB value just means that there will be a 64MB "hole" after the
  70. * physical memory until the kernel virtual memory starts. That means that
  71. * any out-of-bounds memory accesses will hopefully be caught.
  72. * The vmalloc() routines leaves a hole of 4kB between each vmalloced
  73. * area for the same reason. ;)
  74. *
  75. * We no longer map larger than phys RAM with the BATs so we don't have
  76. * to worry about the VMALLOC_OFFSET causing problems. We do have to worry
  77. * about clashes between our early calls to ioremap() that start growing down
  78. * from ioremap_base being run into the VM area allocations (growing upwards
  79. * from VMALLOC_START). For this reason we have ioremap_bot to check when
  80. * we actually run into our mappings setup in the early boot with the VM
  81. * system. This really does become a problem for machines with good amounts
  82. * of RAM. -- Cort
  83. */
  84. #define VMALLOC_OFFSET (0x1000000) /* 16M */
  85. #ifdef PPC_PIN_SIZE
  86. #define VMALLOC_START (((_ALIGN((long)high_memory, PPC_PIN_SIZE) + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)))
  87. #else
  88. #define VMALLOC_START ((((long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)))
  89. #endif
  90. #define VMALLOC_END ioremap_bot
  91. /*
  92. * Bits in a linux-style PTE. These match the bits in the
  93. * (hardware-defined) PowerPC PTE as closely as possible.
  94. */
  95. #if defined(CONFIG_40x)
  96. #include <asm/pte-40x.h>
  97. #elif defined(CONFIG_44x)
  98. #include <asm/pte-44x.h>
  99. #elif defined(CONFIG_FSL_BOOKE)
  100. #include <asm/pte-fsl-booke.h>
  101. #elif defined(CONFIG_8xx)
  102. #include <asm/pte-8xx.h>
  103. #else /* CONFIG_6xx */
  104. #include <asm/pte-hash32.h>
  105. #endif
  106. /* And here we include common definitions */
  107. #include <asm/pte-common.h>
  108. #ifndef __ASSEMBLY__
  109. #define pte_clear(mm, addr, ptep) \
  110. do { pte_update(ptep, ~_PAGE_HASHPTE, 0); } while (0)
  111. #define pmd_none(pmd) (!pmd_val(pmd))
  112. #define pmd_bad(pmd) (pmd_val(pmd) & _PMD_BAD)
  113. #define pmd_present(pmd) (pmd_val(pmd) & _PMD_PRESENT_MASK)
  114. #define pmd_clear(pmdp) do { pmd_val(*(pmdp)) = 0; } while (0)
  115. /*
  116. * When flushing the tlb entry for a page, we also need to flush the hash
  117. * table entry. flush_hash_pages is assembler (for speed) in hashtable.S.
  118. */
  119. extern int flush_hash_pages(unsigned context, unsigned long va,
  120. unsigned long pmdval, int count);
  121. /* Add an HPTE to the hash table */
  122. extern void add_hash_page(unsigned context, unsigned long va,
  123. unsigned long pmdval);
  124. /* Flush an entry from the TLB/hash table */
  125. extern void flush_hash_entry(struct mm_struct *mm, pte_t *ptep,
  126. unsigned long address);
  127. /*
  128. * PTE updates. This function is called whenever an existing
  129. * valid PTE is updated. This does -not- include set_pte_at()
  130. * which nowadays only sets a new PTE.
  131. *
  132. * Depending on the type of MMU, we may need to use atomic updates
  133. * and the PTE may be either 32 or 64 bit wide. In the later case,
  134. * when using atomic updates, only the low part of the PTE is
  135. * accessed atomically.
  136. *
  137. * In addition, on 44x, we also maintain a global flag indicating
  138. * that an executable user mapping was modified, which is needed
  139. * to properly flush the virtually tagged instruction cache of
  140. * those implementations.
  141. */
  142. #ifndef CONFIG_PTE_64BIT
  143. static inline unsigned long pte_update(pte_t *p,
  144. unsigned long clr,
  145. unsigned long set)
  146. {
  147. #ifdef PTE_ATOMIC_UPDATES
  148. unsigned long old, tmp;
  149. __asm__ __volatile__("\
  150. 1: lwarx %0,0,%3\n\
  151. andc %1,%0,%4\n\
  152. or %1,%1,%5\n"
  153. PPC405_ERR77(0,%3)
  154. " stwcx. %1,0,%3\n\
  155. bne- 1b"
  156. : "=&r" (old), "=&r" (tmp), "=m" (*p)
  157. : "r" (p), "r" (clr), "r" (set), "m" (*p)
  158. : "cc" );
  159. #else /* PTE_ATOMIC_UPDATES */
  160. unsigned long old = pte_val(*p);
  161. *p = __pte((old & ~clr) | set);
  162. #endif /* !PTE_ATOMIC_UPDATES */
  163. #ifdef CONFIG_44x
  164. if ((old & _PAGE_USER) && (old & _PAGE_HWEXEC))
  165. icache_44x_need_flush = 1;
  166. #endif
  167. return old;
  168. }
  169. #else /* CONFIG_PTE_64BIT */
  170. static inline unsigned long long pte_update(pte_t *p,
  171. unsigned long clr,
  172. unsigned long set)
  173. {
  174. #ifdef PTE_ATOMIC_UPDATES
  175. unsigned long long old;
  176. unsigned long tmp;
  177. __asm__ __volatile__("\
  178. 1: lwarx %L0,0,%4\n\
  179. lwzx %0,0,%3\n\
  180. andc %1,%L0,%5\n\
  181. or %1,%1,%6\n"
  182. PPC405_ERR77(0,%3)
  183. " stwcx. %1,0,%4\n\
  184. bne- 1b"
  185. : "=&r" (old), "=&r" (tmp), "=m" (*p)
  186. : "r" (p), "r" ((unsigned long)(p) + 4), "r" (clr), "r" (set), "m" (*p)
  187. : "cc" );
  188. #else /* PTE_ATOMIC_UPDATES */
  189. unsigned long long old = pte_val(*p);
  190. *p = __pte((old & ~(unsigned long long)clr) | set);
  191. #endif /* !PTE_ATOMIC_UPDATES */
  192. #ifdef CONFIG_44x
  193. if ((old & _PAGE_USER) && (old & _PAGE_HWEXEC))
  194. icache_44x_need_flush = 1;
  195. #endif
  196. return old;
  197. }
  198. #endif /* CONFIG_PTE_64BIT */
  199. /*
  200. * 2.6 calls this without flushing the TLB entry; this is wrong
  201. * for our hash-based implementation, we fix that up here.
  202. */
  203. #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
  204. static inline int __ptep_test_and_clear_young(unsigned int context, unsigned long addr, pte_t *ptep)
  205. {
  206. unsigned long old;
  207. old = pte_update(ptep, _PAGE_ACCESSED, 0);
  208. #if _PAGE_HASHPTE != 0
  209. if (old & _PAGE_HASHPTE) {
  210. unsigned long ptephys = __pa(ptep) & PAGE_MASK;
  211. flush_hash_pages(context, addr, ptephys, 1);
  212. }
  213. #endif
  214. return (old & _PAGE_ACCESSED) != 0;
  215. }
  216. #define ptep_test_and_clear_young(__vma, __addr, __ptep) \
  217. __ptep_test_and_clear_young((__vma)->vm_mm->context.id, __addr, __ptep)
  218. #define __HAVE_ARCH_PTEP_GET_AND_CLEAR
  219. static inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr,
  220. pte_t *ptep)
  221. {
  222. return __pte(pte_update(ptep, ~_PAGE_HASHPTE, 0));
  223. }
  224. #define __HAVE_ARCH_PTEP_SET_WRPROTECT
  225. static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr,
  226. pte_t *ptep)
  227. {
  228. pte_update(ptep, (_PAGE_RW | _PAGE_HWWRITE), 0);
  229. }
  230. static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
  231. unsigned long addr, pte_t *ptep)
  232. {
  233. ptep_set_wrprotect(mm, addr, ptep);
  234. }
  235. static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry)
  236. {
  237. unsigned long bits = pte_val(entry) &
  238. (_PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_RW |
  239. _PAGE_HWEXEC | _PAGE_EXEC);
  240. pte_update(ptep, 0, bits);
  241. }
  242. #define __HAVE_ARCH_PTE_SAME
  243. #define pte_same(A,B) (((pte_val(A) ^ pte_val(B)) & ~_PAGE_HASHPTE) == 0)
  244. /*
  245. * Note that on Book E processors, the pmd contains the kernel virtual
  246. * (lowmem) address of the pte page. The physical address is less useful
  247. * because everything runs with translation enabled (even the TLB miss
  248. * handler). On everything else the pmd contains the physical address
  249. * of the pte page. -- paulus
  250. */
  251. #ifndef CONFIG_BOOKE
  252. #define pmd_page_vaddr(pmd) \
  253. ((unsigned long) __va(pmd_val(pmd) & PAGE_MASK))
  254. #define pmd_page(pmd) \
  255. (mem_map + (pmd_val(pmd) >> PAGE_SHIFT))
  256. #else
  257. #define pmd_page_vaddr(pmd) \
  258. ((unsigned long) (pmd_val(pmd) & PAGE_MASK))
  259. #define pmd_page(pmd) \
  260. pfn_to_page((__pa(pmd_val(pmd)) >> PAGE_SHIFT))
  261. #endif
  262. /* to find an entry in a kernel page-table-directory */
  263. #define pgd_offset_k(address) pgd_offset(&init_mm, address)
  264. /* to find an entry in a page-table-directory */
  265. #define pgd_index(address) ((address) >> PGDIR_SHIFT)
  266. #define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
  267. /* Find an entry in the third-level page table.. */
  268. #define pte_index(address) \
  269. (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
  270. #define pte_offset_kernel(dir, addr) \
  271. ((pte_t *) pmd_page_vaddr(*(dir)) + pte_index(addr))
  272. #define pte_offset_map(dir, addr) \
  273. ((pte_t *) kmap_atomic(pmd_page(*(dir)), KM_PTE0) + pte_index(addr))
  274. #define pte_offset_map_nested(dir, addr) \
  275. ((pte_t *) kmap_atomic(pmd_page(*(dir)), KM_PTE1) + pte_index(addr))
  276. #define pte_unmap(pte) kunmap_atomic(pte, KM_PTE0)
  277. #define pte_unmap_nested(pte) kunmap_atomic(pte, KM_PTE1)
  278. /*
  279. * Encode and decode a swap entry.
  280. * Note that the bits we use in a PTE for representing a swap entry
  281. * must not include the _PAGE_PRESENT bit, the _PAGE_FILE bit, or the
  282. *_PAGE_HASHPTE bit (if used). -- paulus
  283. */
  284. #define __swp_type(entry) ((entry).val & 0x1f)
  285. #define __swp_offset(entry) ((entry).val >> 5)
  286. #define __swp_entry(type, offset) ((swp_entry_t) { (type) | ((offset) << 5) })
  287. #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) >> 3 })
  288. #define __swp_entry_to_pte(x) ((pte_t) { (x).val << 3 })
  289. /* Encode and decode a nonlinear file mapping entry */
  290. #define PTE_FILE_MAX_BITS 29
  291. #define pte_to_pgoff(pte) (pte_val(pte) >> 3)
  292. #define pgoff_to_pte(off) ((pte_t) { ((off) << 3) | _PAGE_FILE })
  293. /*
  294. * No page table caches to initialise
  295. */
  296. #define pgtable_cache_init() do { } while (0)
  297. extern int get_pteptr(struct mm_struct *mm, unsigned long addr, pte_t **ptep,
  298. pmd_t **pmdp);
  299. #endif /* !__ASSEMBLY__ */
  300. #endif /* _ASM_POWERPC_PGTABLE_PPC32_H */