perf_counter.h 3.7 KB

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  1. /*
  2. * Performance counter support - PowerPC-specific definitions.
  3. *
  4. * Copyright 2008-2009 Paul Mackerras, IBM Corporation.
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License
  8. * as published by the Free Software Foundation; either version
  9. * 2 of the License, or (at your option) any later version.
  10. */
  11. #include <linux/types.h>
  12. #define MAX_HWCOUNTERS 8
  13. #define MAX_EVENT_ALTERNATIVES 8
  14. #define MAX_LIMITED_HWCOUNTERS 2
  15. /*
  16. * This struct provides the constants and functions needed to
  17. * describe the PMU on a particular POWER-family CPU.
  18. */
  19. struct power_pmu {
  20. int n_counter;
  21. int max_alternatives;
  22. u64 add_fields;
  23. u64 test_adder;
  24. int (*compute_mmcr)(u64 events[], int n_ev,
  25. unsigned int hwc[], u64 mmcr[]);
  26. int (*get_constraint)(u64 event, u64 *mskp, u64 *valp);
  27. int (*get_alternatives)(u64 event, unsigned int flags,
  28. u64 alt[]);
  29. void (*disable_pmc)(unsigned int pmc, u64 mmcr[]);
  30. int (*limited_pmc_event)(u64 event);
  31. u32 flags;
  32. int n_generic;
  33. int *generic_events;
  34. int (*cache_events)[PERF_COUNT_HW_CACHE_MAX]
  35. [PERF_COUNT_HW_CACHE_OP_MAX]
  36. [PERF_COUNT_HW_CACHE_RESULT_MAX];
  37. };
  38. extern struct power_pmu *ppmu;
  39. /*
  40. * Values for power_pmu.flags
  41. */
  42. #define PPMU_LIMITED_PMC5_6 1 /* PMC5/6 have limited function */
  43. #define PPMU_ALT_SIPR 2 /* uses alternate posn for SIPR/HV */
  44. /*
  45. * Values for flags to get_alternatives()
  46. */
  47. #define PPMU_LIMITED_PMC_OK 1 /* can put this on a limited PMC */
  48. #define PPMU_LIMITED_PMC_REQD 2 /* have to put this on a limited PMC */
  49. #define PPMU_ONLY_COUNT_RUN 4 /* only counting in run state */
  50. struct pt_regs;
  51. extern unsigned long perf_misc_flags(struct pt_regs *regs);
  52. #define perf_misc_flags(regs) perf_misc_flags(regs)
  53. extern unsigned long perf_instruction_pointer(struct pt_regs *regs);
  54. /*
  55. * The power_pmu.get_constraint function returns a 64-bit value and
  56. * a 64-bit mask that express the constraints between this event and
  57. * other events.
  58. *
  59. * The value and mask are divided up into (non-overlapping) bitfields
  60. * of three different types:
  61. *
  62. * Select field: this expresses the constraint that some set of bits
  63. * in MMCR* needs to be set to a specific value for this event. For a
  64. * select field, the mask contains 1s in every bit of the field, and
  65. * the value contains a unique value for each possible setting of the
  66. * MMCR* bits. The constraint checking code will ensure that two events
  67. * that set the same field in their masks have the same value in their
  68. * value dwords.
  69. *
  70. * Add field: this expresses the constraint that there can be at most
  71. * N events in a particular class. A field of k bits can be used for
  72. * N <= 2^(k-1) - 1. The mask has the most significant bit of the field
  73. * set (and the other bits 0), and the value has only the least significant
  74. * bit of the field set. In addition, the 'add_fields' and 'test_adder'
  75. * in the struct power_pmu for this processor come into play. The
  76. * add_fields value contains 1 in the LSB of the field, and the
  77. * test_adder contains 2^(k-1) - 1 - N in the field.
  78. *
  79. * NAND field: this expresses the constraint that you may not have events
  80. * in all of a set of classes. (For example, on PPC970, you can't select
  81. * events from the FPU, ISU and IDU simultaneously, although any two are
  82. * possible.) For N classes, the field is N+1 bits wide, and each class
  83. * is assigned one bit from the least-significant N bits. The mask has
  84. * only the most-significant bit set, and the value has only the bit
  85. * for the event's class set. The test_adder has the least significant
  86. * bit set in the field.
  87. *
  88. * If an event is not subject to the constraint expressed by a particular
  89. * field, then it will have 0 in both the mask and value for that field.
  90. */