netxen_nic_init.c 47 KB

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  1. /*
  2. * Copyright (C) 2003 - 2009 NetXen, Inc.
  3. * Copyright (C) 2009 - QLogic Corporation.
  4. * All rights reserved.
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License
  8. * as published by the Free Software Foundation; either version 2
  9. * of the License, or (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful, but
  12. * WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
  19. * MA 02111-1307, USA.
  20. *
  21. * The full GNU General Public License is included in this distribution
  22. * in the file called "COPYING".
  23. *
  24. */
  25. #include <linux/netdevice.h>
  26. #include <linux/delay.h>
  27. #include <linux/slab.h>
  28. #include <linux/if_vlan.h>
  29. #include "netxen_nic.h"
  30. #include "netxen_nic_hw.h"
  31. struct crb_addr_pair {
  32. u32 addr;
  33. u32 data;
  34. };
  35. #define NETXEN_MAX_CRB_XFORM 60
  36. static unsigned int crb_addr_xform[NETXEN_MAX_CRB_XFORM];
  37. #define NETXEN_ADDR_ERROR (0xffffffff)
  38. #define crb_addr_transform(name) \
  39. crb_addr_xform[NETXEN_HW_PX_MAP_CRB_##name] = \
  40. NETXEN_HW_CRB_HUB_AGT_ADR_##name << 20
  41. #define NETXEN_NIC_XDMA_RESET 0x8000ff
  42. static void
  43. netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter,
  44. struct nx_host_rds_ring *rds_ring);
  45. static int netxen_p3_has_mn(struct netxen_adapter *adapter);
  46. static void crb_addr_transform_setup(void)
  47. {
  48. crb_addr_transform(XDMA);
  49. crb_addr_transform(TIMR);
  50. crb_addr_transform(SRE);
  51. crb_addr_transform(SQN3);
  52. crb_addr_transform(SQN2);
  53. crb_addr_transform(SQN1);
  54. crb_addr_transform(SQN0);
  55. crb_addr_transform(SQS3);
  56. crb_addr_transform(SQS2);
  57. crb_addr_transform(SQS1);
  58. crb_addr_transform(SQS0);
  59. crb_addr_transform(RPMX7);
  60. crb_addr_transform(RPMX6);
  61. crb_addr_transform(RPMX5);
  62. crb_addr_transform(RPMX4);
  63. crb_addr_transform(RPMX3);
  64. crb_addr_transform(RPMX2);
  65. crb_addr_transform(RPMX1);
  66. crb_addr_transform(RPMX0);
  67. crb_addr_transform(ROMUSB);
  68. crb_addr_transform(SN);
  69. crb_addr_transform(QMN);
  70. crb_addr_transform(QMS);
  71. crb_addr_transform(PGNI);
  72. crb_addr_transform(PGND);
  73. crb_addr_transform(PGN3);
  74. crb_addr_transform(PGN2);
  75. crb_addr_transform(PGN1);
  76. crb_addr_transform(PGN0);
  77. crb_addr_transform(PGSI);
  78. crb_addr_transform(PGSD);
  79. crb_addr_transform(PGS3);
  80. crb_addr_transform(PGS2);
  81. crb_addr_transform(PGS1);
  82. crb_addr_transform(PGS0);
  83. crb_addr_transform(PS);
  84. crb_addr_transform(PH);
  85. crb_addr_transform(NIU);
  86. crb_addr_transform(I2Q);
  87. crb_addr_transform(EG);
  88. crb_addr_transform(MN);
  89. crb_addr_transform(MS);
  90. crb_addr_transform(CAS2);
  91. crb_addr_transform(CAS1);
  92. crb_addr_transform(CAS0);
  93. crb_addr_transform(CAM);
  94. crb_addr_transform(C2C1);
  95. crb_addr_transform(C2C0);
  96. crb_addr_transform(SMB);
  97. crb_addr_transform(OCM0);
  98. crb_addr_transform(I2C0);
  99. }
  100. void netxen_release_rx_buffers(struct netxen_adapter *adapter)
  101. {
  102. struct netxen_recv_context *recv_ctx;
  103. struct nx_host_rds_ring *rds_ring;
  104. struct netxen_rx_buffer *rx_buf;
  105. int i, ring;
  106. recv_ctx = &adapter->recv_ctx;
  107. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  108. rds_ring = &recv_ctx->rds_rings[ring];
  109. for (i = 0; i < rds_ring->num_desc; ++i) {
  110. rx_buf = &(rds_ring->rx_buf_arr[i]);
  111. if (rx_buf->state == NETXEN_BUFFER_FREE)
  112. continue;
  113. pci_unmap_single(adapter->pdev,
  114. rx_buf->dma,
  115. rds_ring->dma_size,
  116. PCI_DMA_FROMDEVICE);
  117. if (rx_buf->skb != NULL)
  118. dev_kfree_skb_any(rx_buf->skb);
  119. }
  120. }
  121. }
  122. void netxen_release_tx_buffers(struct netxen_adapter *adapter)
  123. {
  124. struct netxen_cmd_buffer *cmd_buf;
  125. struct netxen_skb_frag *buffrag;
  126. int i, j;
  127. struct nx_host_tx_ring *tx_ring = adapter->tx_ring;
  128. cmd_buf = tx_ring->cmd_buf_arr;
  129. for (i = 0; i < tx_ring->num_desc; i++) {
  130. buffrag = cmd_buf->frag_array;
  131. if (buffrag->dma) {
  132. pci_unmap_single(adapter->pdev, buffrag->dma,
  133. buffrag->length, PCI_DMA_TODEVICE);
  134. buffrag->dma = 0ULL;
  135. }
  136. for (j = 0; j < cmd_buf->frag_count; j++) {
  137. buffrag++;
  138. if (buffrag->dma) {
  139. pci_unmap_page(adapter->pdev, buffrag->dma,
  140. buffrag->length,
  141. PCI_DMA_TODEVICE);
  142. buffrag->dma = 0ULL;
  143. }
  144. }
  145. if (cmd_buf->skb) {
  146. dev_kfree_skb_any(cmd_buf->skb);
  147. cmd_buf->skb = NULL;
  148. }
  149. cmd_buf++;
  150. }
  151. }
  152. void netxen_free_sw_resources(struct netxen_adapter *adapter)
  153. {
  154. struct netxen_recv_context *recv_ctx;
  155. struct nx_host_rds_ring *rds_ring;
  156. struct nx_host_tx_ring *tx_ring;
  157. int ring;
  158. recv_ctx = &adapter->recv_ctx;
  159. if (recv_ctx->rds_rings == NULL)
  160. goto skip_rds;
  161. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  162. rds_ring = &recv_ctx->rds_rings[ring];
  163. vfree(rds_ring->rx_buf_arr);
  164. rds_ring->rx_buf_arr = NULL;
  165. }
  166. kfree(recv_ctx->rds_rings);
  167. skip_rds:
  168. if (adapter->tx_ring == NULL)
  169. return;
  170. tx_ring = adapter->tx_ring;
  171. vfree(tx_ring->cmd_buf_arr);
  172. kfree(tx_ring);
  173. adapter->tx_ring = NULL;
  174. }
  175. int netxen_alloc_sw_resources(struct netxen_adapter *adapter)
  176. {
  177. struct netxen_recv_context *recv_ctx;
  178. struct nx_host_rds_ring *rds_ring;
  179. struct nx_host_sds_ring *sds_ring;
  180. struct nx_host_tx_ring *tx_ring;
  181. struct netxen_rx_buffer *rx_buf;
  182. int ring, i, size;
  183. struct netxen_cmd_buffer *cmd_buf_arr;
  184. struct net_device *netdev = adapter->netdev;
  185. struct pci_dev *pdev = adapter->pdev;
  186. size = sizeof(struct nx_host_tx_ring);
  187. tx_ring = kzalloc(size, GFP_KERNEL);
  188. if (tx_ring == NULL) {
  189. dev_err(&pdev->dev, "%s: failed to allocate tx ring struct\n",
  190. netdev->name);
  191. return -ENOMEM;
  192. }
  193. adapter->tx_ring = tx_ring;
  194. tx_ring->num_desc = adapter->num_txd;
  195. tx_ring->txq = netdev_get_tx_queue(netdev, 0);
  196. cmd_buf_arr = vzalloc(TX_BUFF_RINGSIZE(tx_ring));
  197. if (cmd_buf_arr == NULL) {
  198. dev_err(&pdev->dev, "%s: failed to allocate cmd buffer ring\n",
  199. netdev->name);
  200. goto err_out;
  201. }
  202. tx_ring->cmd_buf_arr = cmd_buf_arr;
  203. recv_ctx = &adapter->recv_ctx;
  204. size = adapter->max_rds_rings * sizeof (struct nx_host_rds_ring);
  205. rds_ring = kzalloc(size, GFP_KERNEL);
  206. if (rds_ring == NULL) {
  207. dev_err(&pdev->dev, "%s: failed to allocate rds ring struct\n",
  208. netdev->name);
  209. goto err_out;
  210. }
  211. recv_ctx->rds_rings = rds_ring;
  212. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  213. rds_ring = &recv_ctx->rds_rings[ring];
  214. switch (ring) {
  215. case RCV_RING_NORMAL:
  216. rds_ring->num_desc = adapter->num_rxd;
  217. if (adapter->ahw.cut_through) {
  218. rds_ring->dma_size =
  219. NX_CT_DEFAULT_RX_BUF_LEN;
  220. rds_ring->skb_size =
  221. NX_CT_DEFAULT_RX_BUF_LEN;
  222. } else {
  223. if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
  224. rds_ring->dma_size =
  225. NX_P3_RX_BUF_MAX_LEN;
  226. else
  227. rds_ring->dma_size =
  228. NX_P2_RX_BUF_MAX_LEN;
  229. rds_ring->skb_size =
  230. rds_ring->dma_size + NET_IP_ALIGN;
  231. }
  232. break;
  233. case RCV_RING_JUMBO:
  234. rds_ring->num_desc = adapter->num_jumbo_rxd;
  235. if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
  236. rds_ring->dma_size =
  237. NX_P3_RX_JUMBO_BUF_MAX_LEN;
  238. else
  239. rds_ring->dma_size =
  240. NX_P2_RX_JUMBO_BUF_MAX_LEN;
  241. if (adapter->capabilities & NX_CAP0_HW_LRO)
  242. rds_ring->dma_size += NX_LRO_BUFFER_EXTRA;
  243. rds_ring->skb_size =
  244. rds_ring->dma_size + NET_IP_ALIGN;
  245. break;
  246. case RCV_RING_LRO:
  247. rds_ring->num_desc = adapter->num_lro_rxd;
  248. rds_ring->dma_size = NX_RX_LRO_BUFFER_LENGTH;
  249. rds_ring->skb_size = rds_ring->dma_size + NET_IP_ALIGN;
  250. break;
  251. }
  252. rds_ring->rx_buf_arr = vzalloc(RCV_BUFF_RINGSIZE(rds_ring));
  253. if (rds_ring->rx_buf_arr == NULL)
  254. /* free whatever was already allocated */
  255. goto err_out;
  256. INIT_LIST_HEAD(&rds_ring->free_list);
  257. /*
  258. * Now go through all of them, set reference handles
  259. * and put them in the queues.
  260. */
  261. rx_buf = rds_ring->rx_buf_arr;
  262. for (i = 0; i < rds_ring->num_desc; i++) {
  263. list_add_tail(&rx_buf->list,
  264. &rds_ring->free_list);
  265. rx_buf->ref_handle = i;
  266. rx_buf->state = NETXEN_BUFFER_FREE;
  267. rx_buf++;
  268. }
  269. spin_lock_init(&rds_ring->lock);
  270. }
  271. for (ring = 0; ring < adapter->max_sds_rings; ring++) {
  272. sds_ring = &recv_ctx->sds_rings[ring];
  273. sds_ring->irq = adapter->msix_entries[ring].vector;
  274. sds_ring->adapter = adapter;
  275. sds_ring->num_desc = adapter->num_rxd;
  276. for (i = 0; i < NUM_RCV_DESC_RINGS; i++)
  277. INIT_LIST_HEAD(&sds_ring->free_list[i]);
  278. }
  279. return 0;
  280. err_out:
  281. netxen_free_sw_resources(adapter);
  282. return -ENOMEM;
  283. }
  284. /*
  285. * netxen_decode_crb_addr(0 - utility to translate from internal Phantom CRB
  286. * address to external PCI CRB address.
  287. */
  288. static u32 netxen_decode_crb_addr(u32 addr)
  289. {
  290. int i;
  291. u32 base_addr, offset, pci_base;
  292. crb_addr_transform_setup();
  293. pci_base = NETXEN_ADDR_ERROR;
  294. base_addr = addr & 0xfff00000;
  295. offset = addr & 0x000fffff;
  296. for (i = 0; i < NETXEN_MAX_CRB_XFORM; i++) {
  297. if (crb_addr_xform[i] == base_addr) {
  298. pci_base = i << 20;
  299. break;
  300. }
  301. }
  302. if (pci_base == NETXEN_ADDR_ERROR)
  303. return pci_base;
  304. else
  305. return pci_base + offset;
  306. }
  307. #define NETXEN_MAX_ROM_WAIT_USEC 100
  308. static int netxen_wait_rom_done(struct netxen_adapter *adapter)
  309. {
  310. long timeout = 0;
  311. long done = 0;
  312. cond_resched();
  313. while (done == 0) {
  314. done = NXRD32(adapter, NETXEN_ROMUSB_GLB_STATUS);
  315. done &= 2;
  316. if (++timeout >= NETXEN_MAX_ROM_WAIT_USEC) {
  317. dev_err(&adapter->pdev->dev,
  318. "Timeout reached waiting for rom done");
  319. return -EIO;
  320. }
  321. udelay(1);
  322. }
  323. return 0;
  324. }
  325. static int do_rom_fast_read(struct netxen_adapter *adapter,
  326. int addr, int *valp)
  327. {
  328. NXWR32(adapter, NETXEN_ROMUSB_ROM_ADDRESS, addr);
  329. NXWR32(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
  330. NXWR32(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 3);
  331. NXWR32(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE, 0xb);
  332. if (netxen_wait_rom_done(adapter)) {
  333. printk("Error waiting for rom done\n");
  334. return -EIO;
  335. }
  336. /* reset abyte_cnt and dummy_byte_cnt */
  337. NXWR32(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
  338. udelay(10);
  339. NXWR32(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
  340. *valp = NXRD32(adapter, NETXEN_ROMUSB_ROM_RDATA);
  341. return 0;
  342. }
  343. static int do_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
  344. u8 *bytes, size_t size)
  345. {
  346. int addridx;
  347. int ret = 0;
  348. for (addridx = addr; addridx < (addr + size); addridx += 4) {
  349. int v;
  350. ret = do_rom_fast_read(adapter, addridx, &v);
  351. if (ret != 0)
  352. break;
  353. *(__le32 *)bytes = cpu_to_le32(v);
  354. bytes += 4;
  355. }
  356. return ret;
  357. }
  358. int
  359. netxen_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
  360. u8 *bytes, size_t size)
  361. {
  362. int ret;
  363. ret = netxen_rom_lock(adapter);
  364. if (ret < 0)
  365. return ret;
  366. ret = do_rom_fast_read_words(adapter, addr, bytes, size);
  367. netxen_rom_unlock(adapter);
  368. return ret;
  369. }
  370. int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp)
  371. {
  372. int ret;
  373. if (netxen_rom_lock(adapter) != 0)
  374. return -EIO;
  375. ret = do_rom_fast_read(adapter, addr, valp);
  376. netxen_rom_unlock(adapter);
  377. return ret;
  378. }
  379. #define NETXEN_BOARDTYPE 0x4008
  380. #define NETXEN_BOARDNUM 0x400c
  381. #define NETXEN_CHIPNUM 0x4010
  382. int netxen_pinit_from_rom(struct netxen_adapter *adapter)
  383. {
  384. int addr, val;
  385. int i, n, init_delay = 0;
  386. struct crb_addr_pair *buf;
  387. unsigned offset;
  388. u32 off;
  389. /* resetall */
  390. netxen_rom_lock(adapter);
  391. NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, 0xfeffffff);
  392. netxen_rom_unlock(adapter);
  393. if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  394. if (netxen_rom_fast_read(adapter, 0, &n) != 0 ||
  395. (n != 0xcafecafe) ||
  396. netxen_rom_fast_read(adapter, 4, &n) != 0) {
  397. printk(KERN_ERR "%s: ERROR Reading crb_init area: "
  398. "n: %08x\n", netxen_nic_driver_name, n);
  399. return -EIO;
  400. }
  401. offset = n & 0xffffU;
  402. n = (n >> 16) & 0xffffU;
  403. } else {
  404. if (netxen_rom_fast_read(adapter, 0, &n) != 0 ||
  405. !(n & 0x80000000)) {
  406. printk(KERN_ERR "%s: ERROR Reading crb_init area: "
  407. "n: %08x\n", netxen_nic_driver_name, n);
  408. return -EIO;
  409. }
  410. offset = 1;
  411. n &= ~0x80000000;
  412. }
  413. if (n >= 1024) {
  414. printk(KERN_ERR "%s:n=0x%x Error! NetXen card flash not"
  415. " initialized.\n", __func__, n);
  416. return -EIO;
  417. }
  418. buf = kcalloc(n, sizeof(struct crb_addr_pair), GFP_KERNEL);
  419. if (buf == NULL)
  420. return -ENOMEM;
  421. for (i = 0; i < n; i++) {
  422. if (netxen_rom_fast_read(adapter, 8*i + 4*offset, &val) != 0 ||
  423. netxen_rom_fast_read(adapter, 8*i + 4*offset + 4, &addr) != 0) {
  424. kfree(buf);
  425. return -EIO;
  426. }
  427. buf[i].addr = addr;
  428. buf[i].data = val;
  429. }
  430. for (i = 0; i < n; i++) {
  431. off = netxen_decode_crb_addr(buf[i].addr);
  432. if (off == NETXEN_ADDR_ERROR) {
  433. printk(KERN_ERR"CRB init value out of range %x\n",
  434. buf[i].addr);
  435. continue;
  436. }
  437. off += NETXEN_PCI_CRBSPACE;
  438. if (off & 1)
  439. continue;
  440. /* skipping cold reboot MAGIC */
  441. if (off == NETXEN_CAM_RAM(0x1fc))
  442. continue;
  443. if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  444. if (off == (NETXEN_CRB_I2C0 + 0x1c))
  445. continue;
  446. /* do not reset PCI */
  447. if (off == (ROMUSB_GLB + 0xbc))
  448. continue;
  449. if (off == (ROMUSB_GLB + 0xa8))
  450. continue;
  451. if (off == (ROMUSB_GLB + 0xc8)) /* core clock */
  452. continue;
  453. if (off == (ROMUSB_GLB + 0x24)) /* MN clock */
  454. continue;
  455. if (off == (ROMUSB_GLB + 0x1c)) /* MS clock */
  456. continue;
  457. if ((off & 0x0ff00000) == NETXEN_CRB_DDR_NET)
  458. continue;
  459. if (off == (NETXEN_CRB_PEG_NET_1 + 0x18) &&
  460. !NX_IS_REVISION_P3P(adapter->ahw.revision_id))
  461. buf[i].data = 0x1020;
  462. /* skip the function enable register */
  463. if (off == NETXEN_PCIE_REG(PCIE_SETUP_FUNCTION))
  464. continue;
  465. if (off == NETXEN_PCIE_REG(PCIE_SETUP_FUNCTION2))
  466. continue;
  467. if ((off & 0x0ff00000) == NETXEN_CRB_SMB)
  468. continue;
  469. }
  470. init_delay = 1;
  471. /* After writing this register, HW needs time for CRB */
  472. /* to quiet down (else crb_window returns 0xffffffff) */
  473. if (off == NETXEN_ROMUSB_GLB_SW_RESET) {
  474. init_delay = 1000;
  475. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  476. /* hold xdma in reset also */
  477. buf[i].data = NETXEN_NIC_XDMA_RESET;
  478. buf[i].data = 0x8000ff;
  479. }
  480. }
  481. NXWR32(adapter, off, buf[i].data);
  482. msleep(init_delay);
  483. }
  484. kfree(buf);
  485. /* disable_peg_cache_all */
  486. /* unreset_net_cache */
  487. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  488. val = NXRD32(adapter, NETXEN_ROMUSB_GLB_SW_RESET);
  489. NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, (val & 0xffffff0f));
  490. }
  491. /* p2dn replyCount */
  492. NXWR32(adapter, NETXEN_CRB_PEG_NET_D + 0xec, 0x1e);
  493. /* disable_peg_cache 0 */
  494. NXWR32(adapter, NETXEN_CRB_PEG_NET_D + 0x4c, 8);
  495. /* disable_peg_cache 1 */
  496. NXWR32(adapter, NETXEN_CRB_PEG_NET_I + 0x4c, 8);
  497. /* peg_clr_all */
  498. /* peg_clr 0 */
  499. NXWR32(adapter, NETXEN_CRB_PEG_NET_0 + 0x8, 0);
  500. NXWR32(adapter, NETXEN_CRB_PEG_NET_0 + 0xc, 0);
  501. /* peg_clr 1 */
  502. NXWR32(adapter, NETXEN_CRB_PEG_NET_1 + 0x8, 0);
  503. NXWR32(adapter, NETXEN_CRB_PEG_NET_1 + 0xc, 0);
  504. /* peg_clr 2 */
  505. NXWR32(adapter, NETXEN_CRB_PEG_NET_2 + 0x8, 0);
  506. NXWR32(adapter, NETXEN_CRB_PEG_NET_2 + 0xc, 0);
  507. /* peg_clr 3 */
  508. NXWR32(adapter, NETXEN_CRB_PEG_NET_3 + 0x8, 0);
  509. NXWR32(adapter, NETXEN_CRB_PEG_NET_3 + 0xc, 0);
  510. return 0;
  511. }
  512. static struct uni_table_desc *nx_get_table_desc(const u8 *unirom, int section)
  513. {
  514. uint32_t i;
  515. struct uni_table_desc *directory = (struct uni_table_desc *) &unirom[0];
  516. __le32 entries = cpu_to_le32(directory->num_entries);
  517. for (i = 0; i < entries; i++) {
  518. __le32 offs = cpu_to_le32(directory->findex) +
  519. (i * cpu_to_le32(directory->entry_size));
  520. __le32 tab_type = cpu_to_le32(*((u32 *)&unirom[offs] + 8));
  521. if (tab_type == section)
  522. return (struct uni_table_desc *) &unirom[offs];
  523. }
  524. return NULL;
  525. }
  526. #define QLCNIC_FILEHEADER_SIZE (14 * 4)
  527. static int
  528. netxen_nic_validate_header(struct netxen_adapter *adapter)
  529. {
  530. const u8 *unirom = adapter->fw->data;
  531. struct uni_table_desc *directory = (struct uni_table_desc *) &unirom[0];
  532. u32 fw_file_size = adapter->fw->size;
  533. u32 tab_size;
  534. __le32 entries;
  535. __le32 entry_size;
  536. if (fw_file_size < QLCNIC_FILEHEADER_SIZE)
  537. return -EINVAL;
  538. entries = cpu_to_le32(directory->num_entries);
  539. entry_size = cpu_to_le32(directory->entry_size);
  540. tab_size = cpu_to_le32(directory->findex) + (entries * entry_size);
  541. if (fw_file_size < tab_size)
  542. return -EINVAL;
  543. return 0;
  544. }
  545. static int
  546. netxen_nic_validate_bootld(struct netxen_adapter *adapter)
  547. {
  548. struct uni_table_desc *tab_desc;
  549. struct uni_data_desc *descr;
  550. const u8 *unirom = adapter->fw->data;
  551. __le32 idx = cpu_to_le32(*((int *)&unirom[adapter->file_prd_off] +
  552. NX_UNI_BOOTLD_IDX_OFF));
  553. u32 offs;
  554. u32 tab_size;
  555. u32 data_size;
  556. tab_desc = nx_get_table_desc(unirom, NX_UNI_DIR_SECT_BOOTLD);
  557. if (!tab_desc)
  558. return -EINVAL;
  559. tab_size = cpu_to_le32(tab_desc->findex) +
  560. (cpu_to_le32(tab_desc->entry_size) * (idx + 1));
  561. if (adapter->fw->size < tab_size)
  562. return -EINVAL;
  563. offs = cpu_to_le32(tab_desc->findex) +
  564. (cpu_to_le32(tab_desc->entry_size) * (idx));
  565. descr = (struct uni_data_desc *)&unirom[offs];
  566. data_size = cpu_to_le32(descr->findex) + cpu_to_le32(descr->size);
  567. if (adapter->fw->size < data_size)
  568. return -EINVAL;
  569. return 0;
  570. }
  571. static int
  572. netxen_nic_validate_fw(struct netxen_adapter *adapter)
  573. {
  574. struct uni_table_desc *tab_desc;
  575. struct uni_data_desc *descr;
  576. const u8 *unirom = adapter->fw->data;
  577. __le32 idx = cpu_to_le32(*((int *)&unirom[adapter->file_prd_off] +
  578. NX_UNI_FIRMWARE_IDX_OFF));
  579. u32 offs;
  580. u32 tab_size;
  581. u32 data_size;
  582. tab_desc = nx_get_table_desc(unirom, NX_UNI_DIR_SECT_FW);
  583. if (!tab_desc)
  584. return -EINVAL;
  585. tab_size = cpu_to_le32(tab_desc->findex) +
  586. (cpu_to_le32(tab_desc->entry_size) * (idx + 1));
  587. if (adapter->fw->size < tab_size)
  588. return -EINVAL;
  589. offs = cpu_to_le32(tab_desc->findex) +
  590. (cpu_to_le32(tab_desc->entry_size) * (idx));
  591. descr = (struct uni_data_desc *)&unirom[offs];
  592. data_size = cpu_to_le32(descr->findex) + cpu_to_le32(descr->size);
  593. if (adapter->fw->size < data_size)
  594. return -EINVAL;
  595. return 0;
  596. }
  597. static int
  598. netxen_nic_validate_product_offs(struct netxen_adapter *adapter)
  599. {
  600. struct uni_table_desc *ptab_descr;
  601. const u8 *unirom = adapter->fw->data;
  602. int mn_present = (NX_IS_REVISION_P2(adapter->ahw.revision_id)) ?
  603. 1 : netxen_p3_has_mn(adapter);
  604. __le32 entries;
  605. __le32 entry_size;
  606. u32 tab_size;
  607. u32 i;
  608. ptab_descr = nx_get_table_desc(unirom, NX_UNI_DIR_SECT_PRODUCT_TBL);
  609. if (ptab_descr == NULL)
  610. return -EINVAL;
  611. entries = cpu_to_le32(ptab_descr->num_entries);
  612. entry_size = cpu_to_le32(ptab_descr->entry_size);
  613. tab_size = cpu_to_le32(ptab_descr->findex) + (entries * entry_size);
  614. if (adapter->fw->size < tab_size)
  615. return -EINVAL;
  616. nomn:
  617. for (i = 0; i < entries; i++) {
  618. __le32 flags, file_chiprev, offs;
  619. u8 chiprev = adapter->ahw.revision_id;
  620. uint32_t flagbit;
  621. offs = cpu_to_le32(ptab_descr->findex) +
  622. (i * cpu_to_le32(ptab_descr->entry_size));
  623. flags = cpu_to_le32(*((int *)&unirom[offs] + NX_UNI_FLAGS_OFF));
  624. file_chiprev = cpu_to_le32(*((int *)&unirom[offs] +
  625. NX_UNI_CHIP_REV_OFF));
  626. flagbit = mn_present ? 1 : 2;
  627. if ((chiprev == file_chiprev) &&
  628. ((1ULL << flagbit) & flags)) {
  629. adapter->file_prd_off = offs;
  630. return 0;
  631. }
  632. }
  633. if (mn_present && NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  634. mn_present = 0;
  635. goto nomn;
  636. }
  637. return -EINVAL;
  638. }
  639. static int
  640. netxen_nic_validate_unified_romimage(struct netxen_adapter *adapter)
  641. {
  642. if (netxen_nic_validate_header(adapter)) {
  643. dev_err(&adapter->pdev->dev,
  644. "unified image: header validation failed\n");
  645. return -EINVAL;
  646. }
  647. if (netxen_nic_validate_product_offs(adapter)) {
  648. dev_err(&adapter->pdev->dev,
  649. "unified image: product validation failed\n");
  650. return -EINVAL;
  651. }
  652. if (netxen_nic_validate_bootld(adapter)) {
  653. dev_err(&adapter->pdev->dev,
  654. "unified image: bootld validation failed\n");
  655. return -EINVAL;
  656. }
  657. if (netxen_nic_validate_fw(adapter)) {
  658. dev_err(&adapter->pdev->dev,
  659. "unified image: firmware validation failed\n");
  660. return -EINVAL;
  661. }
  662. return 0;
  663. }
  664. static struct uni_data_desc *nx_get_data_desc(struct netxen_adapter *adapter,
  665. u32 section, u32 idx_offset)
  666. {
  667. const u8 *unirom = adapter->fw->data;
  668. int idx = cpu_to_le32(*((int *)&unirom[adapter->file_prd_off] +
  669. idx_offset));
  670. struct uni_table_desc *tab_desc;
  671. __le32 offs;
  672. tab_desc = nx_get_table_desc(unirom, section);
  673. if (tab_desc == NULL)
  674. return NULL;
  675. offs = cpu_to_le32(tab_desc->findex) +
  676. (cpu_to_le32(tab_desc->entry_size) * idx);
  677. return (struct uni_data_desc *)&unirom[offs];
  678. }
  679. static u8 *
  680. nx_get_bootld_offs(struct netxen_adapter *adapter)
  681. {
  682. u32 offs = NETXEN_BOOTLD_START;
  683. if (adapter->fw_type == NX_UNIFIED_ROMIMAGE)
  684. offs = cpu_to_le32((nx_get_data_desc(adapter,
  685. NX_UNI_DIR_SECT_BOOTLD,
  686. NX_UNI_BOOTLD_IDX_OFF))->findex);
  687. return (u8 *)&adapter->fw->data[offs];
  688. }
  689. static u8 *
  690. nx_get_fw_offs(struct netxen_adapter *adapter)
  691. {
  692. u32 offs = NETXEN_IMAGE_START;
  693. if (adapter->fw_type == NX_UNIFIED_ROMIMAGE)
  694. offs = cpu_to_le32((nx_get_data_desc(adapter,
  695. NX_UNI_DIR_SECT_FW,
  696. NX_UNI_FIRMWARE_IDX_OFF))->findex);
  697. return (u8 *)&adapter->fw->data[offs];
  698. }
  699. static __le32
  700. nx_get_fw_size(struct netxen_adapter *adapter)
  701. {
  702. if (adapter->fw_type == NX_UNIFIED_ROMIMAGE)
  703. return cpu_to_le32((nx_get_data_desc(adapter,
  704. NX_UNI_DIR_SECT_FW,
  705. NX_UNI_FIRMWARE_IDX_OFF))->size);
  706. else
  707. return cpu_to_le32(
  708. *(u32 *)&adapter->fw->data[NX_FW_SIZE_OFFSET]);
  709. }
  710. static __le32
  711. nx_get_fw_version(struct netxen_adapter *adapter)
  712. {
  713. struct uni_data_desc *fw_data_desc;
  714. const struct firmware *fw = adapter->fw;
  715. __le32 major, minor, sub;
  716. const u8 *ver_str;
  717. int i, ret = 0;
  718. if (adapter->fw_type == NX_UNIFIED_ROMIMAGE) {
  719. fw_data_desc = nx_get_data_desc(adapter,
  720. NX_UNI_DIR_SECT_FW, NX_UNI_FIRMWARE_IDX_OFF);
  721. ver_str = fw->data + cpu_to_le32(fw_data_desc->findex) +
  722. cpu_to_le32(fw_data_desc->size) - 17;
  723. for (i = 0; i < 12; i++) {
  724. if (!strncmp(&ver_str[i], "REV=", 4)) {
  725. ret = sscanf(&ver_str[i+4], "%u.%u.%u ",
  726. &major, &minor, &sub);
  727. break;
  728. }
  729. }
  730. if (ret != 3)
  731. return 0;
  732. return major + (minor << 8) + (sub << 16);
  733. } else
  734. return cpu_to_le32(*(u32 *)&fw->data[NX_FW_VERSION_OFFSET]);
  735. }
  736. static __le32
  737. nx_get_bios_version(struct netxen_adapter *adapter)
  738. {
  739. const struct firmware *fw = adapter->fw;
  740. __le32 bios_ver, prd_off = adapter->file_prd_off;
  741. if (adapter->fw_type == NX_UNIFIED_ROMIMAGE) {
  742. bios_ver = cpu_to_le32(*((u32 *) (&fw->data[prd_off])
  743. + NX_UNI_BIOS_VERSION_OFF));
  744. return (bios_ver << 16) + ((bios_ver >> 8) & 0xff00) +
  745. (bios_ver >> 24);
  746. } else
  747. return cpu_to_le32(*(u32 *)&fw->data[NX_BIOS_VERSION_OFFSET]);
  748. }
  749. int
  750. netxen_need_fw_reset(struct netxen_adapter *adapter)
  751. {
  752. u32 count, old_count;
  753. u32 val, version, major, minor, build;
  754. int i, timeout;
  755. u8 fw_type;
  756. /* NX2031 firmware doesn't support heartbit */
  757. if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
  758. return 1;
  759. if (adapter->need_fw_reset)
  760. return 1;
  761. /* last attempt had failed */
  762. if (NXRD32(adapter, CRB_CMDPEG_STATE) == PHAN_INITIALIZE_FAILED)
  763. return 1;
  764. old_count = NXRD32(adapter, NETXEN_PEG_ALIVE_COUNTER);
  765. for (i = 0; i < 10; i++) {
  766. timeout = msleep_interruptible(200);
  767. if (timeout) {
  768. NXWR32(adapter, CRB_CMDPEG_STATE,
  769. PHAN_INITIALIZE_FAILED);
  770. return -EINTR;
  771. }
  772. count = NXRD32(adapter, NETXEN_PEG_ALIVE_COUNTER);
  773. if (count != old_count)
  774. break;
  775. }
  776. /* firmware is dead */
  777. if (count == old_count)
  778. return 1;
  779. /* check if we have got newer or different file firmware */
  780. if (adapter->fw) {
  781. val = nx_get_fw_version(adapter);
  782. version = NETXEN_DECODE_VERSION(val);
  783. major = NXRD32(adapter, NETXEN_FW_VERSION_MAJOR);
  784. minor = NXRD32(adapter, NETXEN_FW_VERSION_MINOR);
  785. build = NXRD32(adapter, NETXEN_FW_VERSION_SUB);
  786. if (version > NETXEN_VERSION_CODE(major, minor, build))
  787. return 1;
  788. if (version == NETXEN_VERSION_CODE(major, minor, build) &&
  789. adapter->fw_type != NX_UNIFIED_ROMIMAGE) {
  790. val = NXRD32(adapter, NETXEN_MIU_MN_CONTROL);
  791. fw_type = (val & 0x4) ?
  792. NX_P3_CT_ROMIMAGE : NX_P3_MN_ROMIMAGE;
  793. if (adapter->fw_type != fw_type)
  794. return 1;
  795. }
  796. }
  797. return 0;
  798. }
  799. #define NETXEN_MIN_P3_FW_SUPP NETXEN_VERSION_CODE(4, 0, 505)
  800. int
  801. netxen_check_flash_fw_compatibility(struct netxen_adapter *adapter)
  802. {
  803. u32 flash_fw_ver, min_fw_ver;
  804. if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
  805. return 0;
  806. if (netxen_rom_fast_read(adapter,
  807. NX_FW_VERSION_OFFSET, (int *)&flash_fw_ver)) {
  808. dev_err(&adapter->pdev->dev, "Unable to read flash fw"
  809. "version\n");
  810. return -EIO;
  811. }
  812. flash_fw_ver = NETXEN_DECODE_VERSION(flash_fw_ver);
  813. min_fw_ver = NETXEN_MIN_P3_FW_SUPP;
  814. if (flash_fw_ver >= min_fw_ver)
  815. return 0;
  816. dev_info(&adapter->pdev->dev, "Flash fw[%d.%d.%d] is < min fw supported"
  817. "[4.0.505]. Please update firmware on flash\n",
  818. _major(flash_fw_ver), _minor(flash_fw_ver),
  819. _build(flash_fw_ver));
  820. return -EINVAL;
  821. }
  822. static char *fw_name[] = {
  823. NX_P2_MN_ROMIMAGE_NAME,
  824. NX_P3_CT_ROMIMAGE_NAME,
  825. NX_P3_MN_ROMIMAGE_NAME,
  826. NX_UNIFIED_ROMIMAGE_NAME,
  827. NX_FLASH_ROMIMAGE_NAME,
  828. };
  829. int
  830. netxen_load_firmware(struct netxen_adapter *adapter)
  831. {
  832. u64 *ptr64;
  833. u32 i, flashaddr, size;
  834. const struct firmware *fw = adapter->fw;
  835. struct pci_dev *pdev = adapter->pdev;
  836. dev_info(&pdev->dev, "loading firmware from %s\n",
  837. fw_name[adapter->fw_type]);
  838. if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
  839. NXWR32(adapter, NETXEN_ROMUSB_GLB_CAS_RST, 1);
  840. if (fw) {
  841. __le64 data;
  842. size = (NETXEN_IMAGE_START - NETXEN_BOOTLD_START) / 8;
  843. ptr64 = (u64 *)nx_get_bootld_offs(adapter);
  844. flashaddr = NETXEN_BOOTLD_START;
  845. for (i = 0; i < size; i++) {
  846. data = cpu_to_le64(ptr64[i]);
  847. if (adapter->pci_mem_write(adapter, flashaddr, data))
  848. return -EIO;
  849. flashaddr += 8;
  850. }
  851. size = (__force u32)nx_get_fw_size(adapter) / 8;
  852. ptr64 = (u64 *)nx_get_fw_offs(adapter);
  853. flashaddr = NETXEN_IMAGE_START;
  854. for (i = 0; i < size; i++) {
  855. data = cpu_to_le64(ptr64[i]);
  856. if (adapter->pci_mem_write(adapter,
  857. flashaddr, data))
  858. return -EIO;
  859. flashaddr += 8;
  860. }
  861. size = (__force u32)nx_get_fw_size(adapter) % 8;
  862. if (size) {
  863. data = cpu_to_le64(ptr64[i]);
  864. if (adapter->pci_mem_write(adapter,
  865. flashaddr, data))
  866. return -EIO;
  867. }
  868. } else {
  869. u64 data;
  870. u32 hi, lo;
  871. size = (NETXEN_IMAGE_START - NETXEN_BOOTLD_START) / 8;
  872. flashaddr = NETXEN_BOOTLD_START;
  873. for (i = 0; i < size; i++) {
  874. if (netxen_rom_fast_read(adapter,
  875. flashaddr, (int *)&lo) != 0)
  876. return -EIO;
  877. if (netxen_rom_fast_read(adapter,
  878. flashaddr + 4, (int *)&hi) != 0)
  879. return -EIO;
  880. /* hi, lo are already in host endian byteorder */
  881. data = (((u64)hi << 32) | lo);
  882. if (adapter->pci_mem_write(adapter,
  883. flashaddr, data))
  884. return -EIO;
  885. flashaddr += 8;
  886. }
  887. }
  888. msleep(1);
  889. if (NX_IS_REVISION_P3P(adapter->ahw.revision_id)) {
  890. NXWR32(adapter, NETXEN_CRB_PEG_NET_0 + 0x18, 0x1020);
  891. NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, 0x80001e);
  892. } else if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
  893. NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, 0x80001d);
  894. else {
  895. NXWR32(adapter, NETXEN_ROMUSB_GLB_CHIP_CLK_CTRL, 0x3fff);
  896. NXWR32(adapter, NETXEN_ROMUSB_GLB_CAS_RST, 0);
  897. }
  898. return 0;
  899. }
  900. static int
  901. netxen_validate_firmware(struct netxen_adapter *adapter)
  902. {
  903. __le32 val;
  904. __le32 flash_fw_ver;
  905. u32 file_fw_ver, min_ver, bios;
  906. struct pci_dev *pdev = adapter->pdev;
  907. const struct firmware *fw = adapter->fw;
  908. u8 fw_type = adapter->fw_type;
  909. u32 crbinit_fix_fw;
  910. if (fw_type == NX_UNIFIED_ROMIMAGE) {
  911. if (netxen_nic_validate_unified_romimage(adapter))
  912. return -EINVAL;
  913. } else {
  914. val = cpu_to_le32(*(u32 *)&fw->data[NX_FW_MAGIC_OFFSET]);
  915. if ((__force u32)val != NETXEN_BDINFO_MAGIC)
  916. return -EINVAL;
  917. if (fw->size < NX_FW_MIN_SIZE)
  918. return -EINVAL;
  919. }
  920. val = nx_get_fw_version(adapter);
  921. if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
  922. min_ver = NETXEN_MIN_P3_FW_SUPP;
  923. else
  924. min_ver = NETXEN_VERSION_CODE(3, 4, 216);
  925. file_fw_ver = NETXEN_DECODE_VERSION(val);
  926. if ((_major(file_fw_ver) > _NETXEN_NIC_LINUX_MAJOR) ||
  927. (file_fw_ver < min_ver)) {
  928. dev_err(&pdev->dev,
  929. "%s: firmware version %d.%d.%d unsupported\n",
  930. fw_name[fw_type], _major(file_fw_ver), _minor(file_fw_ver),
  931. _build(file_fw_ver));
  932. return -EINVAL;
  933. }
  934. val = nx_get_bios_version(adapter);
  935. netxen_rom_fast_read(adapter, NX_BIOS_VERSION_OFFSET, (int *)&bios);
  936. if ((__force u32)val != bios) {
  937. dev_err(&pdev->dev, "%s: firmware bios is incompatible\n",
  938. fw_name[fw_type]);
  939. return -EINVAL;
  940. }
  941. if (netxen_rom_fast_read(adapter,
  942. NX_FW_VERSION_OFFSET, (int *)&flash_fw_ver)) {
  943. dev_err(&pdev->dev, "Unable to read flash fw version\n");
  944. return -EIO;
  945. }
  946. flash_fw_ver = NETXEN_DECODE_VERSION(flash_fw_ver);
  947. /* New fw from file is not allowed, if fw on flash is < 4.0.554 */
  948. crbinit_fix_fw = NETXEN_VERSION_CODE(4, 0, 554);
  949. if (file_fw_ver >= crbinit_fix_fw && flash_fw_ver < crbinit_fix_fw &&
  950. NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  951. dev_err(&pdev->dev, "Incompatibility detected between driver "
  952. "and firmware version on flash. This configuration "
  953. "is not recommended. Please update the firmware on "
  954. "flash immediately\n");
  955. return -EINVAL;
  956. }
  957. /* check if flashed firmware is newer only for no-mn and P2 case*/
  958. if (!netxen_p3_has_mn(adapter) ||
  959. NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  960. if (flash_fw_ver > file_fw_ver) {
  961. dev_info(&pdev->dev, "%s: firmware is older than flash\n",
  962. fw_name[fw_type]);
  963. return -EINVAL;
  964. }
  965. }
  966. NXWR32(adapter, NETXEN_CAM_RAM(0x1fc), NETXEN_BDINFO_MAGIC);
  967. return 0;
  968. }
  969. static void
  970. nx_get_next_fwtype(struct netxen_adapter *adapter)
  971. {
  972. u8 fw_type;
  973. switch (adapter->fw_type) {
  974. case NX_UNKNOWN_ROMIMAGE:
  975. fw_type = NX_UNIFIED_ROMIMAGE;
  976. break;
  977. case NX_UNIFIED_ROMIMAGE:
  978. if (NX_IS_REVISION_P3P(adapter->ahw.revision_id))
  979. fw_type = NX_FLASH_ROMIMAGE;
  980. else if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
  981. fw_type = NX_P2_MN_ROMIMAGE;
  982. else if (netxen_p3_has_mn(adapter))
  983. fw_type = NX_P3_MN_ROMIMAGE;
  984. else
  985. fw_type = NX_P3_CT_ROMIMAGE;
  986. break;
  987. case NX_P3_MN_ROMIMAGE:
  988. fw_type = NX_P3_CT_ROMIMAGE;
  989. break;
  990. case NX_P2_MN_ROMIMAGE:
  991. case NX_P3_CT_ROMIMAGE:
  992. default:
  993. fw_type = NX_FLASH_ROMIMAGE;
  994. break;
  995. }
  996. adapter->fw_type = fw_type;
  997. }
  998. static int
  999. netxen_p3_has_mn(struct netxen_adapter *adapter)
  1000. {
  1001. u32 capability, flashed_ver;
  1002. capability = 0;
  1003. /* NX2031 always had MN */
  1004. if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
  1005. return 1;
  1006. netxen_rom_fast_read(adapter,
  1007. NX_FW_VERSION_OFFSET, (int *)&flashed_ver);
  1008. flashed_ver = NETXEN_DECODE_VERSION(flashed_ver);
  1009. if (flashed_ver >= NETXEN_VERSION_CODE(4, 0, 220)) {
  1010. capability = NXRD32(adapter, NX_PEG_TUNE_CAPABILITY);
  1011. if (capability & NX_PEG_TUNE_MN_PRESENT)
  1012. return 1;
  1013. }
  1014. return 0;
  1015. }
  1016. void netxen_request_firmware(struct netxen_adapter *adapter)
  1017. {
  1018. struct pci_dev *pdev = adapter->pdev;
  1019. int rc = 0;
  1020. adapter->fw_type = NX_UNKNOWN_ROMIMAGE;
  1021. next:
  1022. nx_get_next_fwtype(adapter);
  1023. if (adapter->fw_type == NX_FLASH_ROMIMAGE) {
  1024. adapter->fw = NULL;
  1025. } else {
  1026. rc = request_firmware(&adapter->fw,
  1027. fw_name[adapter->fw_type], &pdev->dev);
  1028. if (rc != 0)
  1029. goto next;
  1030. rc = netxen_validate_firmware(adapter);
  1031. if (rc != 0) {
  1032. release_firmware(adapter->fw);
  1033. msleep(1);
  1034. goto next;
  1035. }
  1036. }
  1037. }
  1038. void
  1039. netxen_release_firmware(struct netxen_adapter *adapter)
  1040. {
  1041. release_firmware(adapter->fw);
  1042. adapter->fw = NULL;
  1043. }
  1044. int netxen_init_dummy_dma(struct netxen_adapter *adapter)
  1045. {
  1046. u64 addr;
  1047. u32 hi, lo;
  1048. if (!NX_IS_REVISION_P2(adapter->ahw.revision_id))
  1049. return 0;
  1050. adapter->dummy_dma.addr = pci_alloc_consistent(adapter->pdev,
  1051. NETXEN_HOST_DUMMY_DMA_SIZE,
  1052. &adapter->dummy_dma.phys_addr);
  1053. if (adapter->dummy_dma.addr == NULL) {
  1054. dev_err(&adapter->pdev->dev,
  1055. "ERROR: Could not allocate dummy DMA memory\n");
  1056. return -ENOMEM;
  1057. }
  1058. addr = (uint64_t) adapter->dummy_dma.phys_addr;
  1059. hi = (addr >> 32) & 0xffffffff;
  1060. lo = addr & 0xffffffff;
  1061. NXWR32(adapter, CRB_HOST_DUMMY_BUF_ADDR_HI, hi);
  1062. NXWR32(adapter, CRB_HOST_DUMMY_BUF_ADDR_LO, lo);
  1063. return 0;
  1064. }
  1065. /*
  1066. * NetXen DMA watchdog control:
  1067. *
  1068. * Bit 0 : enabled => R/O: 1 watchdog active, 0 inactive
  1069. * Bit 1 : disable_request => 1 req disable dma watchdog
  1070. * Bit 2 : enable_request => 1 req enable dma watchdog
  1071. * Bit 3-31 : unused
  1072. */
  1073. void netxen_free_dummy_dma(struct netxen_adapter *adapter)
  1074. {
  1075. int i = 100;
  1076. u32 ctrl;
  1077. if (!NX_IS_REVISION_P2(adapter->ahw.revision_id))
  1078. return;
  1079. if (!adapter->dummy_dma.addr)
  1080. return;
  1081. ctrl = NXRD32(adapter, NETXEN_DMA_WATCHDOG_CTRL);
  1082. if ((ctrl & 0x1) != 0) {
  1083. NXWR32(adapter, NETXEN_DMA_WATCHDOG_CTRL, (ctrl | 0x2));
  1084. while ((ctrl & 0x1) != 0) {
  1085. msleep(50);
  1086. ctrl = NXRD32(adapter, NETXEN_DMA_WATCHDOG_CTRL);
  1087. if (--i == 0)
  1088. break;
  1089. }
  1090. }
  1091. if (i) {
  1092. pci_free_consistent(adapter->pdev,
  1093. NETXEN_HOST_DUMMY_DMA_SIZE,
  1094. adapter->dummy_dma.addr,
  1095. adapter->dummy_dma.phys_addr);
  1096. adapter->dummy_dma.addr = NULL;
  1097. } else
  1098. dev_err(&adapter->pdev->dev, "dma_watchdog_shutdown failed\n");
  1099. }
  1100. int netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val)
  1101. {
  1102. u32 val = 0;
  1103. int retries = 60;
  1104. if (pegtune_val)
  1105. return 0;
  1106. do {
  1107. val = NXRD32(adapter, CRB_CMDPEG_STATE);
  1108. switch (val) {
  1109. case PHAN_INITIALIZE_COMPLETE:
  1110. case PHAN_INITIALIZE_ACK:
  1111. return 0;
  1112. case PHAN_INITIALIZE_FAILED:
  1113. goto out_err;
  1114. default:
  1115. break;
  1116. }
  1117. msleep(500);
  1118. } while (--retries);
  1119. NXWR32(adapter, CRB_CMDPEG_STATE, PHAN_INITIALIZE_FAILED);
  1120. out_err:
  1121. dev_warn(&adapter->pdev->dev, "firmware init failed\n");
  1122. return -EIO;
  1123. }
  1124. static int
  1125. netxen_receive_peg_ready(struct netxen_adapter *adapter)
  1126. {
  1127. u32 val = 0;
  1128. int retries = 2000;
  1129. do {
  1130. val = NXRD32(adapter, CRB_RCVPEG_STATE);
  1131. if (val == PHAN_PEG_RCV_INITIALIZED)
  1132. return 0;
  1133. msleep(10);
  1134. } while (--retries);
  1135. if (!retries) {
  1136. printk(KERN_ERR "Receive Peg initialization not "
  1137. "complete, state: 0x%x.\n", val);
  1138. return -EIO;
  1139. }
  1140. return 0;
  1141. }
  1142. int netxen_init_firmware(struct netxen_adapter *adapter)
  1143. {
  1144. int err;
  1145. err = netxen_receive_peg_ready(adapter);
  1146. if (err)
  1147. return err;
  1148. NXWR32(adapter, CRB_NIC_CAPABILITIES_HOST, INTR_SCHEME_PERPORT);
  1149. NXWR32(adapter, CRB_MPORT_MODE, MPORT_MULTI_FUNCTION_MODE);
  1150. NXWR32(adapter, CRB_CMDPEG_STATE, PHAN_INITIALIZE_ACK);
  1151. if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
  1152. NXWR32(adapter, CRB_NIC_MSI_MODE_HOST, MSI_MODE_MULTIFUNC);
  1153. return err;
  1154. }
  1155. static void
  1156. netxen_handle_linkevent(struct netxen_adapter *adapter, nx_fw_msg_t *msg)
  1157. {
  1158. u32 cable_OUI;
  1159. u16 cable_len;
  1160. u16 link_speed;
  1161. u8 link_status, module, duplex, autoneg;
  1162. struct net_device *netdev = adapter->netdev;
  1163. adapter->has_link_events = 1;
  1164. cable_OUI = msg->body[1] & 0xffffffff;
  1165. cable_len = (msg->body[1] >> 32) & 0xffff;
  1166. link_speed = (msg->body[1] >> 48) & 0xffff;
  1167. link_status = msg->body[2] & 0xff;
  1168. duplex = (msg->body[2] >> 16) & 0xff;
  1169. autoneg = (msg->body[2] >> 24) & 0xff;
  1170. module = (msg->body[2] >> 8) & 0xff;
  1171. if (module == LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE) {
  1172. printk(KERN_INFO "%s: unsupported cable: OUI 0x%x, length %d\n",
  1173. netdev->name, cable_OUI, cable_len);
  1174. } else if (module == LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN) {
  1175. printk(KERN_INFO "%s: unsupported cable length %d\n",
  1176. netdev->name, cable_len);
  1177. }
  1178. netxen_advert_link_change(adapter, link_status);
  1179. /* update link parameters */
  1180. if (duplex == LINKEVENT_FULL_DUPLEX)
  1181. adapter->link_duplex = DUPLEX_FULL;
  1182. else
  1183. adapter->link_duplex = DUPLEX_HALF;
  1184. adapter->module_type = module;
  1185. adapter->link_autoneg = autoneg;
  1186. adapter->link_speed = link_speed;
  1187. }
  1188. static void
  1189. netxen_handle_fw_message(int desc_cnt, int index,
  1190. struct nx_host_sds_ring *sds_ring)
  1191. {
  1192. nx_fw_msg_t msg;
  1193. struct status_desc *desc;
  1194. int i = 0, opcode;
  1195. while (desc_cnt > 0 && i < 8) {
  1196. desc = &sds_ring->desc_head[index];
  1197. msg.words[i++] = le64_to_cpu(desc->status_desc_data[0]);
  1198. msg.words[i++] = le64_to_cpu(desc->status_desc_data[1]);
  1199. index = get_next_index(index, sds_ring->num_desc);
  1200. desc_cnt--;
  1201. }
  1202. opcode = netxen_get_nic_msg_opcode(msg.body[0]);
  1203. switch (opcode) {
  1204. case NX_NIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE:
  1205. netxen_handle_linkevent(sds_ring->adapter, &msg);
  1206. break;
  1207. default:
  1208. break;
  1209. }
  1210. }
  1211. static int
  1212. netxen_alloc_rx_skb(struct netxen_adapter *adapter,
  1213. struct nx_host_rds_ring *rds_ring,
  1214. struct netxen_rx_buffer *buffer)
  1215. {
  1216. struct sk_buff *skb;
  1217. dma_addr_t dma;
  1218. struct pci_dev *pdev = adapter->pdev;
  1219. buffer->skb = netdev_alloc_skb(adapter->netdev, rds_ring->skb_size);
  1220. if (!buffer->skb)
  1221. return 1;
  1222. skb = buffer->skb;
  1223. if (!adapter->ahw.cut_through)
  1224. skb_reserve(skb, 2);
  1225. dma = pci_map_single(pdev, skb->data,
  1226. rds_ring->dma_size, PCI_DMA_FROMDEVICE);
  1227. if (pci_dma_mapping_error(pdev, dma)) {
  1228. dev_kfree_skb_any(skb);
  1229. buffer->skb = NULL;
  1230. return 1;
  1231. }
  1232. buffer->skb = skb;
  1233. buffer->dma = dma;
  1234. buffer->state = NETXEN_BUFFER_BUSY;
  1235. return 0;
  1236. }
  1237. static struct sk_buff *netxen_process_rxbuf(struct netxen_adapter *adapter,
  1238. struct nx_host_rds_ring *rds_ring, u16 index, u16 cksum)
  1239. {
  1240. struct netxen_rx_buffer *buffer;
  1241. struct sk_buff *skb;
  1242. buffer = &rds_ring->rx_buf_arr[index];
  1243. pci_unmap_single(adapter->pdev, buffer->dma, rds_ring->dma_size,
  1244. PCI_DMA_FROMDEVICE);
  1245. skb = buffer->skb;
  1246. if (!skb)
  1247. goto no_skb;
  1248. if (likely((adapter->netdev->features & NETIF_F_RXCSUM)
  1249. && cksum == STATUS_CKSUM_OK)) {
  1250. adapter->stats.csummed++;
  1251. skb->ip_summed = CHECKSUM_UNNECESSARY;
  1252. } else
  1253. skb->ip_summed = CHECKSUM_NONE;
  1254. skb->dev = adapter->netdev;
  1255. buffer->skb = NULL;
  1256. no_skb:
  1257. buffer->state = NETXEN_BUFFER_FREE;
  1258. return skb;
  1259. }
  1260. static struct netxen_rx_buffer *
  1261. netxen_process_rcv(struct netxen_adapter *adapter,
  1262. struct nx_host_sds_ring *sds_ring,
  1263. int ring, u64 sts_data0)
  1264. {
  1265. struct net_device *netdev = adapter->netdev;
  1266. struct netxen_recv_context *recv_ctx = &adapter->recv_ctx;
  1267. struct netxen_rx_buffer *buffer;
  1268. struct sk_buff *skb;
  1269. struct nx_host_rds_ring *rds_ring;
  1270. int index, length, cksum, pkt_offset;
  1271. if (unlikely(ring >= adapter->max_rds_rings))
  1272. return NULL;
  1273. rds_ring = &recv_ctx->rds_rings[ring];
  1274. index = netxen_get_sts_refhandle(sts_data0);
  1275. if (unlikely(index >= rds_ring->num_desc))
  1276. return NULL;
  1277. buffer = &rds_ring->rx_buf_arr[index];
  1278. length = netxen_get_sts_totallength(sts_data0);
  1279. cksum = netxen_get_sts_status(sts_data0);
  1280. pkt_offset = netxen_get_sts_pkt_offset(sts_data0);
  1281. skb = netxen_process_rxbuf(adapter, rds_ring, index, cksum);
  1282. if (!skb)
  1283. return buffer;
  1284. if (length > rds_ring->skb_size)
  1285. skb_put(skb, rds_ring->skb_size);
  1286. else
  1287. skb_put(skb, length);
  1288. if (pkt_offset)
  1289. skb_pull(skb, pkt_offset);
  1290. skb->protocol = eth_type_trans(skb, netdev);
  1291. napi_gro_receive(&sds_ring->napi, skb);
  1292. adapter->stats.rx_pkts++;
  1293. adapter->stats.rxbytes += length;
  1294. return buffer;
  1295. }
  1296. #define TCP_HDR_SIZE 20
  1297. #define TCP_TS_OPTION_SIZE 12
  1298. #define TCP_TS_HDR_SIZE (TCP_HDR_SIZE + TCP_TS_OPTION_SIZE)
  1299. static struct netxen_rx_buffer *
  1300. netxen_process_lro(struct netxen_adapter *adapter,
  1301. struct nx_host_sds_ring *sds_ring,
  1302. int ring, u64 sts_data0, u64 sts_data1)
  1303. {
  1304. struct net_device *netdev = adapter->netdev;
  1305. struct netxen_recv_context *recv_ctx = &adapter->recv_ctx;
  1306. struct netxen_rx_buffer *buffer;
  1307. struct sk_buff *skb;
  1308. struct nx_host_rds_ring *rds_ring;
  1309. struct iphdr *iph;
  1310. struct tcphdr *th;
  1311. bool push, timestamp;
  1312. int l2_hdr_offset, l4_hdr_offset;
  1313. int index;
  1314. u16 lro_length, length, data_offset;
  1315. u32 seq_number;
  1316. u8 vhdr_len = 0;
  1317. if (unlikely(ring > adapter->max_rds_rings))
  1318. return NULL;
  1319. rds_ring = &recv_ctx->rds_rings[ring];
  1320. index = netxen_get_lro_sts_refhandle(sts_data0);
  1321. if (unlikely(index > rds_ring->num_desc))
  1322. return NULL;
  1323. buffer = &rds_ring->rx_buf_arr[index];
  1324. timestamp = netxen_get_lro_sts_timestamp(sts_data0);
  1325. lro_length = netxen_get_lro_sts_length(sts_data0);
  1326. l2_hdr_offset = netxen_get_lro_sts_l2_hdr_offset(sts_data0);
  1327. l4_hdr_offset = netxen_get_lro_sts_l4_hdr_offset(sts_data0);
  1328. push = netxen_get_lro_sts_push_flag(sts_data0);
  1329. seq_number = netxen_get_lro_sts_seq_number(sts_data1);
  1330. skb = netxen_process_rxbuf(adapter, rds_ring, index, STATUS_CKSUM_OK);
  1331. if (!skb)
  1332. return buffer;
  1333. if (timestamp)
  1334. data_offset = l4_hdr_offset + TCP_TS_HDR_SIZE;
  1335. else
  1336. data_offset = l4_hdr_offset + TCP_HDR_SIZE;
  1337. skb_put(skb, lro_length + data_offset);
  1338. skb_pull(skb, l2_hdr_offset);
  1339. skb->protocol = eth_type_trans(skb, netdev);
  1340. if (skb->protocol == htons(ETH_P_8021Q))
  1341. vhdr_len = VLAN_HLEN;
  1342. iph = (struct iphdr *)(skb->data + vhdr_len);
  1343. th = (struct tcphdr *)((skb->data + vhdr_len) + (iph->ihl << 2));
  1344. length = (iph->ihl << 2) + (th->doff << 2) + lro_length;
  1345. iph->tot_len = htons(length);
  1346. iph->check = 0;
  1347. iph->check = ip_fast_csum((unsigned char *)iph, iph->ihl);
  1348. th->psh = push;
  1349. th->seq = htonl(seq_number);
  1350. length = skb->len;
  1351. if (adapter->flags & NETXEN_FW_MSS_CAP)
  1352. skb_shinfo(skb)->gso_size = netxen_get_lro_sts_mss(sts_data1);
  1353. netif_receive_skb(skb);
  1354. adapter->stats.lro_pkts++;
  1355. adapter->stats.rxbytes += length;
  1356. return buffer;
  1357. }
  1358. #define netxen_merge_rx_buffers(list, head) \
  1359. do { list_splice_tail_init(list, head); } while (0);
  1360. int
  1361. netxen_process_rcv_ring(struct nx_host_sds_ring *sds_ring, int max)
  1362. {
  1363. struct netxen_adapter *adapter = sds_ring->adapter;
  1364. struct list_head *cur;
  1365. struct status_desc *desc;
  1366. struct netxen_rx_buffer *rxbuf;
  1367. u32 consumer = sds_ring->consumer;
  1368. int count = 0;
  1369. u64 sts_data0, sts_data1;
  1370. int opcode, ring = 0, desc_cnt;
  1371. while (count < max) {
  1372. desc = &sds_ring->desc_head[consumer];
  1373. sts_data0 = le64_to_cpu(desc->status_desc_data[0]);
  1374. if (!(sts_data0 & STATUS_OWNER_HOST))
  1375. break;
  1376. desc_cnt = netxen_get_sts_desc_cnt(sts_data0);
  1377. opcode = netxen_get_sts_opcode(sts_data0);
  1378. switch (opcode) {
  1379. case NETXEN_NIC_RXPKT_DESC:
  1380. case NETXEN_OLD_RXPKT_DESC:
  1381. case NETXEN_NIC_SYN_OFFLOAD:
  1382. ring = netxen_get_sts_type(sts_data0);
  1383. rxbuf = netxen_process_rcv(adapter, sds_ring,
  1384. ring, sts_data0);
  1385. break;
  1386. case NETXEN_NIC_LRO_DESC:
  1387. ring = netxen_get_lro_sts_type(sts_data0);
  1388. sts_data1 = le64_to_cpu(desc->status_desc_data[1]);
  1389. rxbuf = netxen_process_lro(adapter, sds_ring,
  1390. ring, sts_data0, sts_data1);
  1391. break;
  1392. case NETXEN_NIC_RESPONSE_DESC:
  1393. netxen_handle_fw_message(desc_cnt, consumer, sds_ring);
  1394. default:
  1395. goto skip;
  1396. }
  1397. WARN_ON(desc_cnt > 1);
  1398. if (rxbuf)
  1399. list_add_tail(&rxbuf->list, &sds_ring->free_list[ring]);
  1400. skip:
  1401. for (; desc_cnt > 0; desc_cnt--) {
  1402. desc = &sds_ring->desc_head[consumer];
  1403. desc->status_desc_data[0] =
  1404. cpu_to_le64(STATUS_OWNER_PHANTOM);
  1405. consumer = get_next_index(consumer, sds_ring->num_desc);
  1406. }
  1407. count++;
  1408. }
  1409. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  1410. struct nx_host_rds_ring *rds_ring =
  1411. &adapter->recv_ctx.rds_rings[ring];
  1412. if (!list_empty(&sds_ring->free_list[ring])) {
  1413. list_for_each(cur, &sds_ring->free_list[ring]) {
  1414. rxbuf = list_entry(cur,
  1415. struct netxen_rx_buffer, list);
  1416. netxen_alloc_rx_skb(adapter, rds_ring, rxbuf);
  1417. }
  1418. spin_lock(&rds_ring->lock);
  1419. netxen_merge_rx_buffers(&sds_ring->free_list[ring],
  1420. &rds_ring->free_list);
  1421. spin_unlock(&rds_ring->lock);
  1422. }
  1423. netxen_post_rx_buffers_nodb(adapter, rds_ring);
  1424. }
  1425. if (count) {
  1426. sds_ring->consumer = consumer;
  1427. NXWRIO(adapter, sds_ring->crb_sts_consumer, consumer);
  1428. }
  1429. return count;
  1430. }
  1431. /* Process Command status ring */
  1432. int netxen_process_cmd_ring(struct netxen_adapter *adapter)
  1433. {
  1434. u32 sw_consumer, hw_consumer;
  1435. int count = 0, i;
  1436. struct netxen_cmd_buffer *buffer;
  1437. struct pci_dev *pdev = adapter->pdev;
  1438. struct net_device *netdev = adapter->netdev;
  1439. struct netxen_skb_frag *frag;
  1440. int done = 0;
  1441. struct nx_host_tx_ring *tx_ring = adapter->tx_ring;
  1442. if (!spin_trylock(&adapter->tx_clean_lock))
  1443. return 1;
  1444. sw_consumer = tx_ring->sw_consumer;
  1445. hw_consumer = le32_to_cpu(*(tx_ring->hw_consumer));
  1446. while (sw_consumer != hw_consumer) {
  1447. buffer = &tx_ring->cmd_buf_arr[sw_consumer];
  1448. if (buffer->skb) {
  1449. frag = &buffer->frag_array[0];
  1450. pci_unmap_single(pdev, frag->dma, frag->length,
  1451. PCI_DMA_TODEVICE);
  1452. frag->dma = 0ULL;
  1453. for (i = 1; i < buffer->frag_count; i++) {
  1454. frag++; /* Get the next frag */
  1455. pci_unmap_page(pdev, frag->dma, frag->length,
  1456. PCI_DMA_TODEVICE);
  1457. frag->dma = 0ULL;
  1458. }
  1459. adapter->stats.xmitfinished++;
  1460. dev_kfree_skb_any(buffer->skb);
  1461. buffer->skb = NULL;
  1462. }
  1463. sw_consumer = get_next_index(sw_consumer, tx_ring->num_desc);
  1464. if (++count >= MAX_STATUS_HANDLE)
  1465. break;
  1466. }
  1467. if (count && netif_running(netdev)) {
  1468. tx_ring->sw_consumer = sw_consumer;
  1469. smp_mb();
  1470. if (netif_queue_stopped(netdev) && netif_carrier_ok(netdev))
  1471. if (netxen_tx_avail(tx_ring) > TX_STOP_THRESH)
  1472. netif_wake_queue(netdev);
  1473. adapter->tx_timeo_cnt = 0;
  1474. }
  1475. /*
  1476. * If everything is freed up to consumer then check if the ring is full
  1477. * If the ring is full then check if more needs to be freed and
  1478. * schedule the call back again.
  1479. *
  1480. * This happens when there are 2 CPUs. One could be freeing and the
  1481. * other filling it. If the ring is full when we get out of here and
  1482. * the card has already interrupted the host then the host can miss the
  1483. * interrupt.
  1484. *
  1485. * There is still a possible race condition and the host could miss an
  1486. * interrupt. The card has to take care of this.
  1487. */
  1488. hw_consumer = le32_to_cpu(*(tx_ring->hw_consumer));
  1489. done = (sw_consumer == hw_consumer);
  1490. spin_unlock(&adapter->tx_clean_lock);
  1491. return done;
  1492. }
  1493. void
  1494. netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ringid,
  1495. struct nx_host_rds_ring *rds_ring)
  1496. {
  1497. struct rcv_desc *pdesc;
  1498. struct netxen_rx_buffer *buffer;
  1499. int producer, count = 0;
  1500. netxen_ctx_msg msg = 0;
  1501. struct list_head *head;
  1502. producer = rds_ring->producer;
  1503. head = &rds_ring->free_list;
  1504. while (!list_empty(head)) {
  1505. buffer = list_entry(head->next, struct netxen_rx_buffer, list);
  1506. if (!buffer->skb) {
  1507. if (netxen_alloc_rx_skb(adapter, rds_ring, buffer))
  1508. break;
  1509. }
  1510. count++;
  1511. list_del(&buffer->list);
  1512. /* make a rcv descriptor */
  1513. pdesc = &rds_ring->desc_head[producer];
  1514. pdesc->addr_buffer = cpu_to_le64(buffer->dma);
  1515. pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
  1516. pdesc->buffer_length = cpu_to_le32(rds_ring->dma_size);
  1517. producer = get_next_index(producer, rds_ring->num_desc);
  1518. }
  1519. if (count) {
  1520. rds_ring->producer = producer;
  1521. NXWRIO(adapter, rds_ring->crb_rcv_producer,
  1522. (producer-1) & (rds_ring->num_desc-1));
  1523. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  1524. /*
  1525. * Write a doorbell msg to tell phanmon of change in
  1526. * receive ring producer
  1527. * Only for firmware version < 4.0.0
  1528. */
  1529. netxen_set_msg_peg_id(msg, NETXEN_RCV_PEG_DB_ID);
  1530. netxen_set_msg_privid(msg);
  1531. netxen_set_msg_count(msg,
  1532. ((producer - 1) &
  1533. (rds_ring->num_desc - 1)));
  1534. netxen_set_msg_ctxid(msg, adapter->portnum);
  1535. netxen_set_msg_opcode(msg, NETXEN_RCV_PRODUCER(ringid));
  1536. NXWRIO(adapter, DB_NORMALIZE(adapter,
  1537. NETXEN_RCV_PRODUCER_OFFSET), msg);
  1538. }
  1539. }
  1540. }
  1541. static void
  1542. netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter,
  1543. struct nx_host_rds_ring *rds_ring)
  1544. {
  1545. struct rcv_desc *pdesc;
  1546. struct netxen_rx_buffer *buffer;
  1547. int producer, count = 0;
  1548. struct list_head *head;
  1549. if (!spin_trylock(&rds_ring->lock))
  1550. return;
  1551. producer = rds_ring->producer;
  1552. head = &rds_ring->free_list;
  1553. while (!list_empty(head)) {
  1554. buffer = list_entry(head->next, struct netxen_rx_buffer, list);
  1555. if (!buffer->skb) {
  1556. if (netxen_alloc_rx_skb(adapter, rds_ring, buffer))
  1557. break;
  1558. }
  1559. count++;
  1560. list_del(&buffer->list);
  1561. /* make a rcv descriptor */
  1562. pdesc = &rds_ring->desc_head[producer];
  1563. pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
  1564. pdesc->buffer_length = cpu_to_le32(rds_ring->dma_size);
  1565. pdesc->addr_buffer = cpu_to_le64(buffer->dma);
  1566. producer = get_next_index(producer, rds_ring->num_desc);
  1567. }
  1568. if (count) {
  1569. rds_ring->producer = producer;
  1570. NXWRIO(adapter, rds_ring->crb_rcv_producer,
  1571. (producer - 1) & (rds_ring->num_desc - 1));
  1572. }
  1573. spin_unlock(&rds_ring->lock);
  1574. }
  1575. void netxen_nic_clear_stats(struct netxen_adapter *adapter)
  1576. {
  1577. memset(&adapter->stats, 0, sizeof(adapter->stats));
  1578. }