Kconfig 34 KB

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  1. config SYMBOL_PREFIX
  2. string
  3. default "_"
  4. config MMU
  5. def_bool n
  6. config FPU
  7. def_bool n
  8. config RWSEM_GENERIC_SPINLOCK
  9. def_bool y
  10. config RWSEM_XCHGADD_ALGORITHM
  11. def_bool n
  12. config BLACKFIN
  13. def_bool y
  14. select HAVE_ARCH_KGDB
  15. select HAVE_ARCH_TRACEHOOK
  16. select HAVE_DYNAMIC_FTRACE
  17. select HAVE_FTRACE_MCOUNT_RECORD
  18. select HAVE_FUNCTION_GRAPH_TRACER
  19. select HAVE_FUNCTION_TRACER
  20. select HAVE_FUNCTION_TRACE_MCOUNT_TEST
  21. select HAVE_IDE
  22. select HAVE_IRQ_WORK
  23. select HAVE_KERNEL_GZIP if RAMKERNEL
  24. select HAVE_KERNEL_BZIP2 if RAMKERNEL
  25. select HAVE_KERNEL_LZMA if RAMKERNEL
  26. select HAVE_KERNEL_LZO if RAMKERNEL
  27. select HAVE_OPROFILE
  28. select HAVE_PERF_EVENTS
  29. select ARCH_WANT_OPTIONAL_GPIOLIB
  30. select HAVE_GENERIC_HARDIRQS
  31. select GENERIC_ATOMIC64
  32. select GENERIC_IRQ_PROBE
  33. select IRQ_PER_CPU if SMP
  34. select HAVE_NMI_WATCHDOG if NMI_WATCHDOG
  35. select GENERIC_SMP_IDLE_THREAD
  36. config GENERIC_CSUM
  37. def_bool y
  38. config GENERIC_BUG
  39. def_bool y
  40. depends on BUG
  41. config ZONE_DMA
  42. def_bool y
  43. config GENERIC_GPIO
  44. def_bool y
  45. config FORCE_MAX_ZONEORDER
  46. int
  47. default "14"
  48. config GENERIC_CALIBRATE_DELAY
  49. def_bool y
  50. config LOCKDEP_SUPPORT
  51. def_bool y
  52. config STACKTRACE_SUPPORT
  53. def_bool y
  54. config TRACE_IRQFLAGS_SUPPORT
  55. def_bool y
  56. source "init/Kconfig"
  57. source "kernel/Kconfig.preempt"
  58. source "kernel/Kconfig.freezer"
  59. menu "Blackfin Processor Options"
  60. comment "Processor and Board Settings"
  61. choice
  62. prompt "CPU"
  63. default BF533
  64. config BF512
  65. bool "BF512"
  66. help
  67. BF512 Processor Support.
  68. config BF514
  69. bool "BF514"
  70. help
  71. BF514 Processor Support.
  72. config BF516
  73. bool "BF516"
  74. help
  75. BF516 Processor Support.
  76. config BF518
  77. bool "BF518"
  78. help
  79. BF518 Processor Support.
  80. config BF522
  81. bool "BF522"
  82. help
  83. BF522 Processor Support.
  84. config BF523
  85. bool "BF523"
  86. help
  87. BF523 Processor Support.
  88. config BF524
  89. bool "BF524"
  90. help
  91. BF524 Processor Support.
  92. config BF525
  93. bool "BF525"
  94. help
  95. BF525 Processor Support.
  96. config BF526
  97. bool "BF526"
  98. help
  99. BF526 Processor Support.
  100. config BF527
  101. bool "BF527"
  102. help
  103. BF527 Processor Support.
  104. config BF531
  105. bool "BF531"
  106. help
  107. BF531 Processor Support.
  108. config BF532
  109. bool "BF532"
  110. help
  111. BF532 Processor Support.
  112. config BF533
  113. bool "BF533"
  114. help
  115. BF533 Processor Support.
  116. config BF534
  117. bool "BF534"
  118. help
  119. BF534 Processor Support.
  120. config BF536
  121. bool "BF536"
  122. help
  123. BF536 Processor Support.
  124. config BF537
  125. bool "BF537"
  126. help
  127. BF537 Processor Support.
  128. config BF538
  129. bool "BF538"
  130. help
  131. BF538 Processor Support.
  132. config BF539
  133. bool "BF539"
  134. help
  135. BF539 Processor Support.
  136. config BF542_std
  137. bool "BF542"
  138. help
  139. BF542 Processor Support.
  140. config BF542M
  141. bool "BF542m"
  142. help
  143. BF542 Processor Support.
  144. config BF544_std
  145. bool "BF544"
  146. help
  147. BF544 Processor Support.
  148. config BF544M
  149. bool "BF544m"
  150. help
  151. BF544 Processor Support.
  152. config BF547_std
  153. bool "BF547"
  154. help
  155. BF547 Processor Support.
  156. config BF547M
  157. bool "BF547m"
  158. help
  159. BF547 Processor Support.
  160. config BF548_std
  161. bool "BF548"
  162. help
  163. BF548 Processor Support.
  164. config BF548M
  165. bool "BF548m"
  166. help
  167. BF548 Processor Support.
  168. config BF549_std
  169. bool "BF549"
  170. help
  171. BF549 Processor Support.
  172. config BF549M
  173. bool "BF549m"
  174. help
  175. BF549 Processor Support.
  176. config BF561
  177. bool "BF561"
  178. help
  179. BF561 Processor Support.
  180. config BF609
  181. bool "BF609"
  182. select CLKDEV_LOOKUP
  183. help
  184. BF609 Processor Support.
  185. endchoice
  186. config SMP
  187. depends on BF561
  188. select TICKSOURCE_CORETMR
  189. bool "Symmetric multi-processing support"
  190. ---help---
  191. This enables support for systems with more than one CPU,
  192. like the dual core BF561. If you have a system with only one
  193. CPU, say N. If you have a system with more than one CPU, say Y.
  194. If you don't know what to do here, say N.
  195. config NR_CPUS
  196. int
  197. depends on SMP
  198. default 2 if BF561
  199. config HOTPLUG_CPU
  200. bool "Support for hot-pluggable CPUs"
  201. depends on SMP && HOTPLUG
  202. default y
  203. config BF_REV_MIN
  204. int
  205. default 0 if (BF51x || BF52x || (BF54x && !BF54xM)) || BF60x
  206. default 2 if (BF537 || BF536 || BF534)
  207. default 3 if (BF561 || BF533 || BF532 || BF531 || BF54xM)
  208. default 4 if (BF538 || BF539)
  209. config BF_REV_MAX
  210. int
  211. default 2 if (BF51x || BF52x || (BF54x && !BF54xM)) || BF60x
  212. default 3 if (BF537 || BF536 || BF534 || BF54xM)
  213. default 5 if (BF561 || BF538 || BF539)
  214. default 6 if (BF533 || BF532 || BF531)
  215. choice
  216. prompt "Silicon Rev"
  217. default BF_REV_0_0 if (BF51x || BF52x || BF60x)
  218. default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM))
  219. default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561)
  220. config BF_REV_0_0
  221. bool "0.0"
  222. depends on (BF51x || BF52x || (BF54x && !BF54xM) || BF60x)
  223. config BF_REV_0_1
  224. bool "0.1"
  225. depends on (BF51x || BF52x || (BF54x && !BF54xM))
  226. config BF_REV_0_2
  227. bool "0.2"
  228. depends on (BF51x || BF52x || BF537 || BF536 || BF534 || (BF54x && !BF54xM))
  229. config BF_REV_0_3
  230. bool "0.3"
  231. depends on (BF54xM || BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)
  232. config BF_REV_0_4
  233. bool "0.4"
  234. depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
  235. config BF_REV_0_5
  236. bool "0.5"
  237. depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
  238. config BF_REV_0_6
  239. bool "0.6"
  240. depends on (BF533 || BF532 || BF531)
  241. config BF_REV_ANY
  242. bool "any"
  243. config BF_REV_NONE
  244. bool "none"
  245. endchoice
  246. config BF53x
  247. bool
  248. depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
  249. default y
  250. config MEM_MT48LC64M4A2FB_7E
  251. bool
  252. depends on (BFIN533_STAMP)
  253. default y
  254. config MEM_MT48LC16M16A2TG_75
  255. bool
  256. depends on (BFIN533_EZKIT || BFIN561_EZKIT \
  257. || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM_E \
  258. || BFIN537_BLUETECHNIX_CM_U || H8606_HVSISTEMAS \
  259. || BFIN527_BLUETECHNIX_CM)
  260. default y
  261. config MEM_MT48LC32M8A2_75
  262. bool
  263. depends on (BFIN518F_EZBRD || BFIN537_STAMP || PNAV10 || BFIN538_EZKIT)
  264. default y
  265. config MEM_MT48LC8M32B2B5_7
  266. bool
  267. depends on (BFIN561_BLUETECHNIX_CM)
  268. default y
  269. config MEM_MT48LC32M16A2TG_75
  270. bool
  271. depends on (BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN532_IP0X || BLACKSTAMP || BFIN527_AD7160EVAL)
  272. default y
  273. config MEM_MT48H32M16LFCJ_75
  274. bool
  275. depends on (BFIN526_EZBRD)
  276. default y
  277. source "arch/blackfin/mach-bf518/Kconfig"
  278. source "arch/blackfin/mach-bf527/Kconfig"
  279. source "arch/blackfin/mach-bf533/Kconfig"
  280. source "arch/blackfin/mach-bf561/Kconfig"
  281. source "arch/blackfin/mach-bf537/Kconfig"
  282. source "arch/blackfin/mach-bf538/Kconfig"
  283. source "arch/blackfin/mach-bf548/Kconfig"
  284. source "arch/blackfin/mach-bf609/Kconfig"
  285. menu "Board customizations"
  286. config CMDLINE_BOOL
  287. bool "Default bootloader kernel arguments"
  288. config CMDLINE
  289. string "Initial kernel command string"
  290. depends on CMDLINE_BOOL
  291. default "console=ttyBF0,57600"
  292. help
  293. If you don't have a boot loader capable of passing a command line string
  294. to the kernel, you may specify one here. As a minimum, you should specify
  295. the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
  296. config BOOT_LOAD
  297. hex "Kernel load address for booting"
  298. default "0x1000"
  299. range 0x1000 0x20000000
  300. help
  301. This option allows you to set the load address of the kernel.
  302. This can be useful if you are on a board which has a small amount
  303. of memory or you wish to reserve some memory at the beginning of
  304. the address space.
  305. Note that you need to keep this value above 4k (0x1000) as this
  306. memory region is used to capture NULL pointer references as well
  307. as some core kernel functions.
  308. config PHY_RAM_BASE_ADDRESS
  309. hex "Physical RAM Base"
  310. default 0x0
  311. help
  312. set BF609 FPGA physical SRAM base address
  313. config ROM_BASE
  314. hex "Kernel ROM Base"
  315. depends on ROMKERNEL
  316. default "0x20040040"
  317. range 0x20000000 0x20400000 if !(BF54x || BF561)
  318. range 0x20000000 0x30000000 if (BF54x || BF561)
  319. help
  320. Make sure your ROM base does not include any file-header
  321. information that is prepended to the kernel.
  322. For example, the bootable U-Boot format (created with
  323. mkimage) has a 64 byte header (0x40). So while the image
  324. you write to flash might start at say 0x20080000, you have
  325. to add 0x40 to get the kernel's ROM base as it will come
  326. after the header.
  327. comment "Clock/PLL Setup"
  328. config CLKIN_HZ
  329. int "Frequency of the crystal on the board in Hz"
  330. default "10000000" if BFIN532_IP0X
  331. default "11059200" if BFIN533_STAMP
  332. default "24576000" if PNAV10
  333. default "25000000" # most people use this
  334. default "27000000" if BFIN533_EZKIT
  335. default "30000000" if BFIN561_EZKIT
  336. default "24000000" if BFIN527_AD7160EVAL
  337. help
  338. The frequency of CLKIN crystal oscillator on the board in Hz.
  339. Warning: This value should match the crystal on the board. Otherwise,
  340. peripherals won't work properly.
  341. config BFIN_KERNEL_CLOCK
  342. bool "Re-program Clocks while Kernel boots?"
  343. default n
  344. help
  345. This option decides if kernel clocks are re-programed from the
  346. bootloader settings. If the clocks are not set, the SDRAM settings
  347. are also not changed, and the Bootloader does 100% of the hardware
  348. configuration.
  349. config PLL_BYPASS
  350. bool "Bypass PLL"
  351. depends on BFIN_KERNEL_CLOCK && (!BF60x)
  352. default n
  353. config CLKIN_HALF
  354. bool "Half Clock In"
  355. depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
  356. default n
  357. help
  358. If this is set the clock will be divided by 2, before it goes to the PLL.
  359. config VCO_MULT
  360. int "VCO Multiplier"
  361. depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
  362. range 1 64
  363. default "22" if BFIN533_EZKIT
  364. default "45" if BFIN533_STAMP
  365. default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT)
  366. default "22" if BFIN533_BLUETECHNIX_CM
  367. default "20" if (BFIN537_BLUETECHNIX_CM_E || BFIN537_BLUETECHNIX_CM_U || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
  368. default "20" if (BFIN561_EZKIT || BF609)
  369. default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD)
  370. default "25" if BFIN527_AD7160EVAL
  371. help
  372. This controls the frequency of the on-chip PLL. This can be between 1 and 64.
  373. PLL Frequency = (Crystal Frequency) * (this setting)
  374. choice
  375. prompt "Core Clock Divider"
  376. depends on BFIN_KERNEL_CLOCK
  377. default CCLK_DIV_1
  378. help
  379. This sets the frequency of the core. It can be 1, 2, 4 or 8
  380. Core Frequency = (PLL frequency) / (this setting)
  381. config CCLK_DIV_1
  382. bool "1"
  383. config CCLK_DIV_2
  384. bool "2"
  385. config CCLK_DIV_4
  386. bool "4"
  387. config CCLK_DIV_8
  388. bool "8"
  389. endchoice
  390. config SCLK_DIV
  391. int "System Clock Divider"
  392. depends on BFIN_KERNEL_CLOCK
  393. range 1 15
  394. default 4
  395. help
  396. This sets the frequency of the system clock (including SDRAM or DDR) on
  397. !BF60x else it set the clock for system buses and provides the
  398. source from which SCLK0 and SCLK1 are derived.
  399. This can be between 1 and 15
  400. System Clock = (PLL frequency) / (this setting)
  401. config SCLK0_DIV
  402. int "System Clock0 Divider"
  403. depends on BFIN_KERNEL_CLOCK && BF60x
  404. range 1 15
  405. default 1
  406. help
  407. This sets the frequency of the system clock0 for PVP and all other
  408. peripherals not clocked by SCLK1.
  409. This can be between 1 and 15
  410. System Clock0 = (System Clock) / (this setting)
  411. config SCLK1_DIV
  412. int "System Clock1 Divider"
  413. depends on BFIN_KERNEL_CLOCK && BF60x
  414. range 1 15
  415. default 1
  416. help
  417. This sets the frequency of the system clock1 (including SPORT, SPI and ACM).
  418. This can be between 1 and 15
  419. System Clock1 = (System Clock) / (this setting)
  420. config DCLK_DIV
  421. int "DDR Clock Divider"
  422. depends on BFIN_KERNEL_CLOCK && BF60x
  423. range 1 15
  424. default 2
  425. help
  426. This sets the frequency of the DDR memory.
  427. This can be between 1 and 15
  428. DDR Clock = (PLL frequency) / (this setting)
  429. choice
  430. prompt "DDR SDRAM Chip Type"
  431. depends on BFIN_KERNEL_CLOCK
  432. depends on BF54x
  433. default MEM_MT46V32M16_5B
  434. config MEM_MT46V32M16_6T
  435. bool "MT46V32M16_6T"
  436. config MEM_MT46V32M16_5B
  437. bool "MT46V32M16_5B"
  438. endchoice
  439. choice
  440. prompt "DDR/SDRAM Timing"
  441. depends on BFIN_KERNEL_CLOCK && !BF60x
  442. default BFIN_KERNEL_CLOCK_MEMINIT_CALC
  443. help
  444. This option allows you to specify Blackfin SDRAM/DDR Timing parameters
  445. The calculated SDRAM timing parameters may not be 100%
  446. accurate - This option is therefore marked experimental.
  447. config BFIN_KERNEL_CLOCK_MEMINIT_CALC
  448. bool "Calculate Timings (EXPERIMENTAL)"
  449. depends on EXPERIMENTAL
  450. config BFIN_KERNEL_CLOCK_MEMINIT_SPEC
  451. bool "Provide accurate Timings based on target SCLK"
  452. help
  453. Please consult the Blackfin Hardware Reference Manuals as well
  454. as the memory device datasheet.
  455. http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram
  456. endchoice
  457. menu "Memory Init Control"
  458. depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC
  459. config MEM_DDRCTL0
  460. depends on BF54x
  461. hex "DDRCTL0"
  462. default 0x0
  463. config MEM_DDRCTL1
  464. depends on BF54x
  465. hex "DDRCTL1"
  466. default 0x0
  467. config MEM_DDRCTL2
  468. depends on BF54x
  469. hex "DDRCTL2"
  470. default 0x0
  471. config MEM_EBIU_DDRQUE
  472. depends on BF54x
  473. hex "DDRQUE"
  474. default 0x0
  475. config MEM_SDRRC
  476. depends on !BF54x
  477. hex "SDRRC"
  478. default 0x0
  479. config MEM_SDGCTL
  480. depends on !BF54x
  481. hex "SDGCTL"
  482. default 0x0
  483. endmenu
  484. #
  485. # Max & Min Speeds for various Chips
  486. #
  487. config MAX_VCO_HZ
  488. int
  489. default 400000000 if BF512
  490. default 400000000 if BF514
  491. default 400000000 if BF516
  492. default 400000000 if BF518
  493. default 400000000 if BF522
  494. default 600000000 if BF523
  495. default 400000000 if BF524
  496. default 600000000 if BF525
  497. default 400000000 if BF526
  498. default 600000000 if BF527
  499. default 400000000 if BF531
  500. default 400000000 if BF532
  501. default 750000000 if BF533
  502. default 500000000 if BF534
  503. default 400000000 if BF536
  504. default 600000000 if BF537
  505. default 533333333 if BF538
  506. default 533333333 if BF539
  507. default 600000000 if BF542
  508. default 533333333 if BF544
  509. default 600000000 if BF547
  510. default 600000000 if BF548
  511. default 533333333 if BF549
  512. default 600000000 if BF561
  513. default 800000000 if BF609
  514. config MIN_VCO_HZ
  515. int
  516. default 50000000
  517. config MAX_SCLK_HZ
  518. int
  519. default 200000000 if BF609
  520. default 133333333
  521. config MIN_SCLK_HZ
  522. int
  523. default 27000000
  524. comment "Kernel Timer/Scheduler"
  525. source kernel/Kconfig.hz
  526. config GENERIC_CLOCKEVENTS
  527. bool "Generic clock events"
  528. default y
  529. menu "Clock event device"
  530. depends on GENERIC_CLOCKEVENTS
  531. config TICKSOURCE_GPTMR0
  532. bool "GPTimer0"
  533. depends on !SMP
  534. select BFIN_GPTIMERS
  535. config TICKSOURCE_CORETMR
  536. bool "Core timer"
  537. default y
  538. endmenu
  539. menu "Clock souce"
  540. depends on GENERIC_CLOCKEVENTS
  541. config CYCLES_CLOCKSOURCE
  542. bool "CYCLES"
  543. default y
  544. depends on !BFIN_SCRATCH_REG_CYCLES
  545. depends on !SMP
  546. help
  547. If you say Y here, you will enable support for using the 'cycles'
  548. registers as a clock source. Doing so means you will be unable to
  549. safely write to the 'cycles' register during runtime. You will
  550. still be able to read it (such as for performance monitoring), but
  551. writing the registers will most likely crash the kernel.
  552. config GPTMR0_CLOCKSOURCE
  553. bool "GPTimer0"
  554. select BFIN_GPTIMERS
  555. depends on !TICKSOURCE_GPTMR0
  556. endmenu
  557. config ARCH_USES_GETTIMEOFFSET
  558. depends on !GENERIC_CLOCKEVENTS
  559. def_bool y
  560. source kernel/time/Kconfig
  561. comment "Misc"
  562. choice
  563. prompt "Blackfin Exception Scratch Register"
  564. default BFIN_SCRATCH_REG_RETN
  565. help
  566. Select the resource to reserve for the Exception handler:
  567. - RETN: Non-Maskable Interrupt (NMI)
  568. - RETE: Exception Return (JTAG/ICE)
  569. - CYCLES: Performance counter
  570. If you are unsure, please select "RETN".
  571. config BFIN_SCRATCH_REG_RETN
  572. bool "RETN"
  573. help
  574. Use the RETN register in the Blackfin exception handler
  575. as a stack scratch register. This means you cannot
  576. safely use NMI on the Blackfin while running Linux, but
  577. you can debug the system with a JTAG ICE and use the
  578. CYCLES performance registers.
  579. If you are unsure, please select "RETN".
  580. config BFIN_SCRATCH_REG_RETE
  581. bool "RETE"
  582. help
  583. Use the RETE register in the Blackfin exception handler
  584. as a stack scratch register. This means you cannot
  585. safely use a JTAG ICE while debugging a Blackfin board,
  586. but you can safely use the CYCLES performance registers
  587. and the NMI.
  588. If you are unsure, please select "RETN".
  589. config BFIN_SCRATCH_REG_CYCLES
  590. bool "CYCLES"
  591. help
  592. Use the CYCLES register in the Blackfin exception handler
  593. as a stack scratch register. This means you cannot
  594. safely use the CYCLES performance registers on a Blackfin
  595. board at anytime, but you can debug the system with a JTAG
  596. ICE and use the NMI.
  597. If you are unsure, please select "RETN".
  598. endchoice
  599. endmenu
  600. menu "Blackfin Kernel Optimizations"
  601. comment "Memory Optimizations"
  602. config I_ENTRY_L1
  603. bool "Locate interrupt entry code in L1 Memory"
  604. default y
  605. depends on !SMP
  606. help
  607. If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
  608. into L1 instruction memory. (less latency)
  609. config EXCPT_IRQ_SYSC_L1
  610. bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
  611. default y
  612. depends on !SMP
  613. help
  614. If enabled, the entire ASM lowlevel exception and interrupt entry code
  615. (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
  616. (less latency)
  617. config DO_IRQ_L1
  618. bool "Locate frequently called do_irq dispatcher function in L1 Memory"
  619. default y
  620. depends on !SMP
  621. help
  622. If enabled, the frequently called do_irq dispatcher function is linked
  623. into L1 instruction memory. (less latency)
  624. config CORE_TIMER_IRQ_L1
  625. bool "Locate frequently called timer_interrupt() function in L1 Memory"
  626. default y
  627. depends on !SMP
  628. help
  629. If enabled, the frequently called timer_interrupt() function is linked
  630. into L1 instruction memory. (less latency)
  631. config IDLE_L1
  632. bool "Locate frequently idle function in L1 Memory"
  633. default y
  634. depends on !SMP
  635. help
  636. If enabled, the frequently called idle function is linked
  637. into L1 instruction memory. (less latency)
  638. config SCHEDULE_L1
  639. bool "Locate kernel schedule function in L1 Memory"
  640. default y
  641. depends on !SMP
  642. help
  643. If enabled, the frequently called kernel schedule is linked
  644. into L1 instruction memory. (less latency)
  645. config ARITHMETIC_OPS_L1
  646. bool "Locate kernel owned arithmetic functions in L1 Memory"
  647. default y
  648. depends on !SMP
  649. help
  650. If enabled, arithmetic functions are linked
  651. into L1 instruction memory. (less latency)
  652. config ACCESS_OK_L1
  653. bool "Locate access_ok function in L1 Memory"
  654. default y
  655. depends on !SMP
  656. help
  657. If enabled, the access_ok function is linked
  658. into L1 instruction memory. (less latency)
  659. config MEMSET_L1
  660. bool "Locate memset function in L1 Memory"
  661. default y
  662. depends on !SMP
  663. help
  664. If enabled, the memset function is linked
  665. into L1 instruction memory. (less latency)
  666. config MEMCPY_L1
  667. bool "Locate memcpy function in L1 Memory"
  668. default y
  669. depends on !SMP
  670. help
  671. If enabled, the memcpy function is linked
  672. into L1 instruction memory. (less latency)
  673. config STRCMP_L1
  674. bool "locate strcmp function in L1 Memory"
  675. default y
  676. depends on !SMP
  677. help
  678. If enabled, the strcmp function is linked
  679. into L1 instruction memory (less latency).
  680. config STRNCMP_L1
  681. bool "locate strncmp function in L1 Memory"
  682. default y
  683. depends on !SMP
  684. help
  685. If enabled, the strncmp function is linked
  686. into L1 instruction memory (less latency).
  687. config STRCPY_L1
  688. bool "locate strcpy function in L1 Memory"
  689. default y
  690. depends on !SMP
  691. help
  692. If enabled, the strcpy function is linked
  693. into L1 instruction memory (less latency).
  694. config STRNCPY_L1
  695. bool "locate strncpy function in L1 Memory"
  696. default y
  697. depends on !SMP
  698. help
  699. If enabled, the strncpy function is linked
  700. into L1 instruction memory (less latency).
  701. config SYS_BFIN_SPINLOCK_L1
  702. bool "Locate sys_bfin_spinlock function in L1 Memory"
  703. default y
  704. depends on !SMP
  705. help
  706. If enabled, sys_bfin_spinlock function is linked
  707. into L1 instruction memory. (less latency)
  708. config IP_CHECKSUM_L1
  709. bool "Locate IP Checksum function in L1 Memory"
  710. default n
  711. depends on !SMP
  712. help
  713. If enabled, the IP Checksum function is linked
  714. into L1 instruction memory. (less latency)
  715. config CACHELINE_ALIGNED_L1
  716. bool "Locate cacheline_aligned data to L1 Data Memory"
  717. default y if !BF54x
  718. default n if BF54x
  719. depends on !SMP && !BF531 && !CRC32
  720. help
  721. If enabled, cacheline_aligned data is linked
  722. into L1 data memory. (less latency)
  723. config SYSCALL_TAB_L1
  724. bool "Locate Syscall Table L1 Data Memory"
  725. default n
  726. depends on !SMP && !BF531
  727. help
  728. If enabled, the Syscall LUT is linked
  729. into L1 data memory. (less latency)
  730. config CPLB_SWITCH_TAB_L1
  731. bool "Locate CPLB Switch Tables L1 Data Memory"
  732. default n
  733. depends on !SMP && !BF531
  734. help
  735. If enabled, the CPLB Switch Tables are linked
  736. into L1 data memory. (less latency)
  737. config ICACHE_FLUSH_L1
  738. bool "Locate icache flush funcs in L1 Inst Memory"
  739. default y
  740. help
  741. If enabled, the Blackfin icache flushing functions are linked
  742. into L1 instruction memory.
  743. Note that this might be required to address anomalies, but
  744. these functions are pretty small, so it shouldn't be too bad.
  745. If you are using a processor affected by an anomaly, the build
  746. system will double check for you and prevent it.
  747. config DCACHE_FLUSH_L1
  748. bool "Locate dcache flush funcs in L1 Inst Memory"
  749. default y
  750. depends on !SMP
  751. help
  752. If enabled, the Blackfin dcache flushing functions are linked
  753. into L1 instruction memory.
  754. config APP_STACK_L1
  755. bool "Support locating application stack in L1 Scratch Memory"
  756. default y
  757. depends on !SMP
  758. help
  759. If enabled the application stack can be located in L1
  760. scratch memory (less latency).
  761. Currently only works with FLAT binaries.
  762. config EXCEPTION_L1_SCRATCH
  763. bool "Locate exception stack in L1 Scratch Memory"
  764. default n
  765. depends on !SMP && !APP_STACK_L1
  766. help
  767. Whenever an exception occurs, use the L1 Scratch memory for
  768. stack storage. You cannot place the stacks of FLAT binaries
  769. in L1 when using this option.
  770. If you don't use L1 Scratch, then you should say Y here.
  771. comment "Speed Optimizations"
  772. config BFIN_INS_LOWOVERHEAD
  773. bool "ins[bwl] low overhead, higher interrupt latency"
  774. default y
  775. depends on !SMP
  776. help
  777. Reads on the Blackfin are speculative. In Blackfin terms, this means
  778. they can be interrupted at any time (even after they have been issued
  779. on to the external bus), and re-issued after the interrupt occurs.
  780. For memory - this is not a big deal, since memory does not change if
  781. it sees a read.
  782. If a FIFO is sitting on the end of the read, it will see two reads,
  783. when the core only sees one since the FIFO receives both the read
  784. which is cancelled (and not delivered to the core) and the one which
  785. is re-issued (which is delivered to the core).
  786. To solve this, interrupts are turned off before reads occur to
  787. I/O space. This option controls which the overhead/latency of
  788. controlling interrupts during this time
  789. "n" turns interrupts off every read
  790. (higher overhead, but lower interrupt latency)
  791. "y" turns interrupts off every loop
  792. (low overhead, but longer interrupt latency)
  793. default behavior is to leave this set to on (type "Y"). If you are experiencing
  794. interrupt latency issues, it is safe and OK to turn this off.
  795. endmenu
  796. choice
  797. prompt "Kernel executes from"
  798. help
  799. Choose the memory type that the kernel will be running in.
  800. config RAMKERNEL
  801. bool "RAM"
  802. help
  803. The kernel will be resident in RAM when running.
  804. config ROMKERNEL
  805. bool "ROM"
  806. help
  807. The kernel will be resident in FLASH/ROM when running.
  808. endchoice
  809. # Common code uses "ROMKERNEL" or "XIP_KERNEL", so define both
  810. config XIP_KERNEL
  811. bool
  812. default y
  813. depends on ROMKERNEL
  814. source "mm/Kconfig"
  815. config BFIN_GPTIMERS
  816. tristate "Enable Blackfin General Purpose Timers API"
  817. default n
  818. help
  819. Enable support for the General Purpose Timers API. If you
  820. are unsure, say N.
  821. To compile this driver as a module, choose M here: the module
  822. will be called gptimers.
  823. config HAVE_PWM
  824. tristate "Enable PWM API support"
  825. depends on BFIN_GPTIMERS
  826. help
  827. Enable support for the Pulse Width Modulation framework (as
  828. found in linux/pwm.h).
  829. To compile this driver as a module, choose M here: the module
  830. will be called pwm.
  831. choice
  832. prompt "Uncached DMA region"
  833. default DMA_UNCACHED_1M
  834. config DMA_UNCACHED_4M
  835. bool "Enable 4M DMA region"
  836. config DMA_UNCACHED_2M
  837. bool "Enable 2M DMA region"
  838. config DMA_UNCACHED_1M
  839. bool "Enable 1M DMA region"
  840. config DMA_UNCACHED_512K
  841. bool "Enable 512K DMA region"
  842. config DMA_UNCACHED_256K
  843. bool "Enable 256K DMA region"
  844. config DMA_UNCACHED_128K
  845. bool "Enable 128K DMA region"
  846. config DMA_UNCACHED_NONE
  847. bool "Disable DMA region"
  848. endchoice
  849. comment "Cache Support"
  850. config BFIN_ICACHE
  851. bool "Enable ICACHE"
  852. default y
  853. config BFIN_EXTMEM_ICACHEABLE
  854. bool "Enable ICACHE for external memory"
  855. depends on BFIN_ICACHE
  856. default y
  857. config BFIN_L2_ICACHEABLE
  858. bool "Enable ICACHE for L2 SRAM"
  859. depends on BFIN_ICACHE
  860. depends on BF54x || BF561
  861. default n
  862. config BFIN_DCACHE
  863. bool "Enable DCACHE"
  864. default y
  865. config BFIN_DCACHE_BANKA
  866. bool "Enable only 16k BankA DCACHE - BankB is SRAM"
  867. depends on BFIN_DCACHE && !BF531
  868. default n
  869. config BFIN_EXTMEM_DCACHEABLE
  870. bool "Enable DCACHE for external memory"
  871. depends on BFIN_DCACHE
  872. default y
  873. choice
  874. prompt "External memory DCACHE policy"
  875. depends on BFIN_EXTMEM_DCACHEABLE
  876. default BFIN_EXTMEM_WRITEBACK if !SMP
  877. default BFIN_EXTMEM_WRITETHROUGH if SMP
  878. config BFIN_EXTMEM_WRITEBACK
  879. bool "Write back"
  880. depends on !SMP
  881. help
  882. Write Back Policy:
  883. Cached data will be written back to SDRAM only when needed.
  884. This can give a nice increase in performance, but beware of
  885. broken drivers that do not properly invalidate/flush their
  886. cache.
  887. Write Through Policy:
  888. Cached data will always be written back to SDRAM when the
  889. cache is updated. This is a completely safe setting, but
  890. performance is worse than Write Back.
  891. If you are unsure of the options and you want to be safe,
  892. then go with Write Through.
  893. config BFIN_EXTMEM_WRITETHROUGH
  894. bool "Write through"
  895. help
  896. Write Back Policy:
  897. Cached data will be written back to SDRAM only when needed.
  898. This can give a nice increase in performance, but beware of
  899. broken drivers that do not properly invalidate/flush their
  900. cache.
  901. Write Through Policy:
  902. Cached data will always be written back to SDRAM when the
  903. cache is updated. This is a completely safe setting, but
  904. performance is worse than Write Back.
  905. If you are unsure of the options and you want to be safe,
  906. then go with Write Through.
  907. endchoice
  908. config BFIN_L2_DCACHEABLE
  909. bool "Enable DCACHE for L2 SRAM"
  910. depends on BFIN_DCACHE
  911. depends on (BF54x || BF561 || BF60x) && !SMP
  912. default n
  913. choice
  914. prompt "L2 SRAM DCACHE policy"
  915. depends on BFIN_L2_DCACHEABLE
  916. default BFIN_L2_WRITEBACK
  917. config BFIN_L2_WRITEBACK
  918. bool "Write back"
  919. config BFIN_L2_WRITETHROUGH
  920. bool "Write through"
  921. endchoice
  922. comment "Memory Protection Unit"
  923. config MPU
  924. bool "Enable the memory protection unit (EXPERIMENTAL)"
  925. default n
  926. help
  927. Use the processor's MPU to protect applications from accessing
  928. memory they do not own. This comes at a performance penalty
  929. and is recommended only for debugging.
  930. comment "Asynchronous Memory Configuration"
  931. menu "EBIU_AMGCTL Global Control"
  932. depends on !BF60x
  933. config C_AMCKEN
  934. bool "Enable CLKOUT"
  935. default y
  936. config C_CDPRIO
  937. bool "DMA has priority over core for ext. accesses"
  938. default n
  939. config C_B0PEN
  940. depends on BF561
  941. bool "Bank 0 16 bit packing enable"
  942. default y
  943. config C_B1PEN
  944. depends on BF561
  945. bool "Bank 1 16 bit packing enable"
  946. default y
  947. config C_B2PEN
  948. depends on BF561
  949. bool "Bank 2 16 bit packing enable"
  950. default y
  951. config C_B3PEN
  952. depends on BF561
  953. bool "Bank 3 16 bit packing enable"
  954. default n
  955. choice
  956. prompt "Enable Asynchronous Memory Banks"
  957. default C_AMBEN_ALL
  958. config C_AMBEN
  959. bool "Disable All Banks"
  960. config C_AMBEN_B0
  961. bool "Enable Bank 0"
  962. config C_AMBEN_B0_B1
  963. bool "Enable Bank 0 & 1"
  964. config C_AMBEN_B0_B1_B2
  965. bool "Enable Bank 0 & 1 & 2"
  966. config C_AMBEN_ALL
  967. bool "Enable All Banks"
  968. endchoice
  969. endmenu
  970. menu "EBIU_AMBCTL Control"
  971. depends on !BF60x
  972. config BANK_0
  973. hex "Bank 0 (AMBCTL0.L)"
  974. default 0x7BB0
  975. help
  976. These are the low 16 bits of the EBIU_AMBCTL0 MMR which are
  977. used to control the Asynchronous Memory Bank 0 settings.
  978. config BANK_1
  979. hex "Bank 1 (AMBCTL0.H)"
  980. default 0x7BB0
  981. default 0x5558 if BF54x
  982. help
  983. These are the high 16 bits of the EBIU_AMBCTL0 MMR which are
  984. used to control the Asynchronous Memory Bank 1 settings.
  985. config BANK_2
  986. hex "Bank 2 (AMBCTL1.L)"
  987. default 0x7BB0
  988. help
  989. These are the low 16 bits of the EBIU_AMBCTL1 MMR which are
  990. used to control the Asynchronous Memory Bank 2 settings.
  991. config BANK_3
  992. hex "Bank 3 (AMBCTL1.H)"
  993. default 0x99B3
  994. help
  995. These are the high 16 bits of the EBIU_AMBCTL1 MMR which are
  996. used to control the Asynchronous Memory Bank 3 settings.
  997. endmenu
  998. config EBIU_MBSCTLVAL
  999. hex "EBIU Bank Select Control Register"
  1000. depends on BF54x
  1001. default 0
  1002. config EBIU_MODEVAL
  1003. hex "Flash Memory Mode Control Register"
  1004. depends on BF54x
  1005. default 1
  1006. config EBIU_FCTLVAL
  1007. hex "Flash Memory Bank Control Register"
  1008. depends on BF54x
  1009. default 6
  1010. endmenu
  1011. #############################################################################
  1012. menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
  1013. config PCI
  1014. bool "PCI support"
  1015. depends on BROKEN
  1016. help
  1017. Support for PCI bus.
  1018. source "drivers/pci/Kconfig"
  1019. source "drivers/pcmcia/Kconfig"
  1020. source "drivers/pci/hotplug/Kconfig"
  1021. endmenu
  1022. menu "Executable file formats"
  1023. source "fs/Kconfig.binfmt"
  1024. endmenu
  1025. menu "Power management options"
  1026. source "kernel/power/Kconfig"
  1027. config ARCH_SUSPEND_POSSIBLE
  1028. def_bool y
  1029. choice
  1030. prompt "Standby Power Saving Mode"
  1031. depends on PM && !BF60x
  1032. default PM_BFIN_SLEEP_DEEPER
  1033. config PM_BFIN_SLEEP_DEEPER
  1034. bool "Sleep Deeper"
  1035. help
  1036. Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
  1037. power dissipation by disabling the clock to the processor core (CCLK).
  1038. Furthermore, Standby sets the internal power supply voltage (VDDINT)
  1039. to 0.85 V to provide the greatest power savings, while preserving the
  1040. processor state.
  1041. The PLL and system clock (SCLK) continue to operate at a very low
  1042. frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
  1043. the SDRAM is put into Self Refresh Mode. Typically an external event
  1044. such as GPIO interrupt or RTC activity wakes up the processor.
  1045. Various Peripherals such as UART, SPORT, PPI may not function as
  1046. normal during Sleep Deeper, due to the reduced SCLK frequency.
  1047. When in the sleep mode, system DMA access to L1 memory is not supported.
  1048. If unsure, select "Sleep Deeper".
  1049. config PM_BFIN_SLEEP
  1050. bool "Sleep"
  1051. help
  1052. Sleep Mode (High Power Savings) - The sleep mode reduces power
  1053. dissipation by disabling the clock to the processor core (CCLK).
  1054. The PLL and system clock (SCLK), however, continue to operate in
  1055. this mode. Typically an external event or RTC activity will wake
  1056. up the processor. When in the sleep mode, system DMA access to L1
  1057. memory is not supported.
  1058. If unsure, select "Sleep Deeper".
  1059. endchoice
  1060. comment "Possible Suspend Mem / Hibernate Wake-Up Sources"
  1061. depends on PM
  1062. config PM_BFIN_WAKE_PH6
  1063. bool "Allow Wake-Up from on-chip PHY or PH6 GP"
  1064. depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537)
  1065. default n
  1066. help
  1067. Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up)
  1068. config PM_BFIN_WAKE_GP
  1069. bool "Allow Wake-Up from GPIOs"
  1070. depends on PM && BF54x
  1071. default n
  1072. help
  1073. Enable General-Purpose Wake-Up (Voltage Regulator Power-Up)
  1074. (all processors, except ADSP-BF549). This option sets
  1075. the general-purpose wake-up enable (GPWE) control bit to enable
  1076. wake-up upon detection of an active low signal on the /GPW (PH7) pin.
  1077. On ADSP-BF549 this option enables the same functionality on the
  1078. /MRXON pin also PH7.
  1079. config PM_BFIN_WAKE_PA15
  1080. bool "Allow Wake-Up from PA15"
  1081. depends on PM && BF60x
  1082. default n
  1083. help
  1084. Enable PA15 Wake-Up
  1085. config PM_BFIN_WAKE_PA15_POL
  1086. int "Wake-up priority"
  1087. depends on PM_BFIN_WAKE_PA15
  1088. default 0
  1089. help
  1090. Wake-Up priority 0(low) 1(high)
  1091. config PM_BFIN_WAKE_PB15
  1092. bool "Allow Wake-Up from PB15"
  1093. depends on PM && BF60x
  1094. default n
  1095. help
  1096. Enable PB15 Wake-Up
  1097. config PM_BFIN_WAKE_PB15_POL
  1098. int "Wake-up priority"
  1099. depends on PM_BFIN_WAKE_PB15
  1100. default 0
  1101. help
  1102. Wake-Up priority 0(low) 1(high)
  1103. config PM_BFIN_WAKE_PC15
  1104. bool "Allow Wake-Up from PC15"
  1105. depends on PM && BF60x
  1106. default n
  1107. help
  1108. Enable PC15 Wake-Up
  1109. config PM_BFIN_WAKE_PC15_POL
  1110. int "Wake-up priority"
  1111. depends on PM_BFIN_WAKE_PC15
  1112. default 0
  1113. help
  1114. Wake-Up priority 0(low) 1(high)
  1115. config PM_BFIN_WAKE_PD06
  1116. bool "Allow Wake-Up from PD06(ETH0_PHYINT)"
  1117. depends on PM && BF60x
  1118. default n
  1119. help
  1120. Enable PD06(ETH0_PHYINT) Wake-up
  1121. config PM_BFIN_WAKE_PD06_POL
  1122. int "Wake-up priority"
  1123. depends on PM_BFIN_WAKE_PD06
  1124. default 0
  1125. help
  1126. Wake-Up priority 0(low) 1(high)
  1127. config PM_BFIN_WAKE_PE12
  1128. bool "Allow Wake-Up from PE12(ETH1_PHYINT, PUSH BUTTON)"
  1129. depends on PM && BF60x
  1130. default n
  1131. help
  1132. Enable PE12(ETH1_PHYINT, PUSH BUTTON) Wake-up
  1133. config PM_BFIN_WAKE_PE12_POL
  1134. int "Wake-up priority"
  1135. depends on PM_BFIN_WAKE_PE12
  1136. default 0
  1137. help
  1138. Wake-Up priority 0(low) 1(high)
  1139. config PM_BFIN_WAKE_PG04
  1140. bool "Allow Wake-Up from PG04(CAN0_RX)"
  1141. depends on PM && BF60x
  1142. default n
  1143. help
  1144. Enable PG04(CAN0_RX) Wake-up
  1145. config PM_BFIN_WAKE_PG04_POL
  1146. int "Wake-up priority"
  1147. depends on PM_BFIN_WAKE_PG04
  1148. default 0
  1149. help
  1150. Wake-Up priority 0(low) 1(high)
  1151. config PM_BFIN_WAKE_PG13
  1152. bool "Allow Wake-Up from PG13"
  1153. depends on PM && BF60x
  1154. default n
  1155. help
  1156. Enable PG13 Wake-Up
  1157. config PM_BFIN_WAKE_PG13_POL
  1158. int "Wake-up priority"
  1159. depends on PM_BFIN_WAKE_PG13
  1160. default 0
  1161. help
  1162. Wake-Up priority 0(low) 1(high)
  1163. config PM_BFIN_WAKE_USB
  1164. bool "Allow Wake-Up from (USB)"
  1165. depends on PM && BF60x
  1166. default n
  1167. help
  1168. Enable (USB) Wake-up
  1169. config PM_BFIN_WAKE_USB_POL
  1170. int "Wake-up priority"
  1171. depends on PM_BFIN_WAKE_USB
  1172. default 0
  1173. help
  1174. Wake-Up priority 0(low) 1(high)
  1175. endmenu
  1176. menu "CPU Frequency scaling"
  1177. source "drivers/cpufreq/Kconfig"
  1178. config BFIN_CPU_FREQ
  1179. bool
  1180. depends on CPU_FREQ
  1181. select CPU_FREQ_TABLE
  1182. default y
  1183. config CPU_VOLTAGE
  1184. bool "CPU Voltage scaling"
  1185. depends on EXPERIMENTAL
  1186. depends on CPU_FREQ
  1187. default n
  1188. help
  1189. Say Y here if you want CPU voltage scaling according to the CPU frequency.
  1190. This option violates the PLL BYPASS recommendation in the Blackfin Processor
  1191. manuals. There is a theoretical risk that during VDDINT transitions
  1192. the PLL may unlock.
  1193. endmenu
  1194. source "net/Kconfig"
  1195. source "drivers/Kconfig"
  1196. source "drivers/firmware/Kconfig"
  1197. source "fs/Kconfig"
  1198. source "arch/blackfin/Kconfig.debug"
  1199. source "security/Kconfig"
  1200. source "crypto/Kconfig"
  1201. source "lib/Kconfig"