radeon_ring.c 11 KB

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  1. /*
  2. * Copyright 2008 Advanced Micro Devices, Inc.
  3. * Copyright 2008 Red Hat Inc.
  4. * Copyright 2009 Jerome Glisse.
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a
  7. * copy of this software and associated documentation files (the "Software"),
  8. * to deal in the Software without restriction, including without limitation
  9. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10. * and/or sell copies of the Software, and to permit persons to whom the
  11. * Software is furnished to do so, subject to the following conditions:
  12. *
  13. * The above copyright notice and this permission notice shall be included in
  14. * all copies or substantial portions of the Software.
  15. *
  16. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22. * OTHER DEALINGS IN THE SOFTWARE.
  23. *
  24. * Authors: Dave Airlie
  25. * Alex Deucher
  26. * Jerome Glisse
  27. */
  28. #include <linux/seq_file.h>
  29. #include "drmP.h"
  30. #include "radeon_drm.h"
  31. #include "radeon_reg.h"
  32. #include "radeon.h"
  33. #include "atom.h"
  34. int radeon_debugfs_ib_init(struct radeon_device *rdev);
  35. void radeon_ib_bogus_cleanup(struct radeon_device *rdev)
  36. {
  37. struct radeon_ib *ib, *n;
  38. list_for_each_entry_safe(ib, n, &rdev->ib_pool.bogus_ib, list) {
  39. list_del(&ib->list);
  40. vfree(ib->ptr);
  41. kfree(ib);
  42. }
  43. }
  44. void radeon_ib_bogus_add(struct radeon_device *rdev, struct radeon_ib *ib)
  45. {
  46. struct radeon_ib *bib;
  47. bib = kmalloc(sizeof(*bib), GFP_KERNEL);
  48. if (bib == NULL)
  49. return;
  50. bib->ptr = vmalloc(ib->length_dw * 4);
  51. if (bib->ptr == NULL) {
  52. kfree(bib);
  53. return;
  54. }
  55. memcpy(bib->ptr, ib->ptr, ib->length_dw * 4);
  56. bib->length_dw = ib->length_dw;
  57. mutex_lock(&rdev->ib_pool.mutex);
  58. list_add_tail(&bib->list, &rdev->ib_pool.bogus_ib);
  59. mutex_unlock(&rdev->ib_pool.mutex);
  60. }
  61. /*
  62. * IB.
  63. */
  64. int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib)
  65. {
  66. struct radeon_fence *fence;
  67. struct radeon_ib *nib;
  68. int r = 0, i, c;
  69. *ib = NULL;
  70. r = radeon_fence_create(rdev, &fence);
  71. if (r) {
  72. dev_err(rdev->dev, "failed to create fence for new IB\n");
  73. return r;
  74. }
  75. mutex_lock(&rdev->ib_pool.mutex);
  76. for (i = rdev->ib_pool.head_id, c = 0, nib = NULL; c < RADEON_IB_POOL_SIZE; c++, i++) {
  77. i &= (RADEON_IB_POOL_SIZE - 1);
  78. if (rdev->ib_pool.ibs[i].free) {
  79. nib = &rdev->ib_pool.ibs[i];
  80. break;
  81. }
  82. }
  83. if (nib == NULL) {
  84. /* This should never happen, it means we allocated all
  85. * IB and haven't scheduled one yet, return EBUSY to
  86. * userspace hoping that on ioctl recall we get better
  87. * luck
  88. */
  89. dev_err(rdev->dev, "no free indirect buffer !\n");
  90. mutex_unlock(&rdev->ib_pool.mutex);
  91. radeon_fence_unref(&fence);
  92. return -EBUSY;
  93. }
  94. rdev->ib_pool.head_id = (nib->idx + 1) & (RADEON_IB_POOL_SIZE - 1);
  95. nib->free = false;
  96. if (nib->fence) {
  97. mutex_unlock(&rdev->ib_pool.mutex);
  98. r = radeon_fence_wait(nib->fence, false);
  99. if (r) {
  100. dev_err(rdev->dev, "error waiting fence of IB(%u:0x%016lX:%u)\n",
  101. nib->idx, (unsigned long)nib->gpu_addr, nib->length_dw);
  102. mutex_lock(&rdev->ib_pool.mutex);
  103. nib->free = true;
  104. mutex_unlock(&rdev->ib_pool.mutex);
  105. radeon_fence_unref(&fence);
  106. return r;
  107. }
  108. mutex_lock(&rdev->ib_pool.mutex);
  109. }
  110. radeon_fence_unref(&nib->fence);
  111. nib->fence = fence;
  112. nib->length_dw = 0;
  113. mutex_unlock(&rdev->ib_pool.mutex);
  114. *ib = nib;
  115. return 0;
  116. }
  117. void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib)
  118. {
  119. struct radeon_ib *tmp = *ib;
  120. *ib = NULL;
  121. if (tmp == NULL) {
  122. return;
  123. }
  124. mutex_lock(&rdev->ib_pool.mutex);
  125. tmp->free = true;
  126. mutex_unlock(&rdev->ib_pool.mutex);
  127. }
  128. int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib)
  129. {
  130. int r = 0;
  131. if (!ib->length_dw || !rdev->cp.ready) {
  132. /* TODO: Nothings in the ib we should report. */
  133. DRM_ERROR("radeon: couldn't schedule IB(%u).\n", ib->idx);
  134. return -EINVAL;
  135. }
  136. /* 64 dwords should be enough for fence too */
  137. r = radeon_ring_lock(rdev, 64);
  138. if (r) {
  139. DRM_ERROR("radeon: scheduling IB failled (%d).\n", r);
  140. return r;
  141. }
  142. radeon_ring_ib_execute(rdev, ib);
  143. radeon_fence_emit(rdev, ib->fence);
  144. mutex_lock(&rdev->ib_pool.mutex);
  145. /* once scheduled IB is considered free and protected by the fence */
  146. ib->free = true;
  147. mutex_unlock(&rdev->ib_pool.mutex);
  148. radeon_ring_unlock_commit(rdev);
  149. return 0;
  150. }
  151. int radeon_ib_pool_init(struct radeon_device *rdev)
  152. {
  153. void *ptr;
  154. uint64_t gpu_addr;
  155. int i;
  156. int r = 0;
  157. if (rdev->ib_pool.robj)
  158. return 0;
  159. INIT_LIST_HEAD(&rdev->ib_pool.bogus_ib);
  160. /* Allocate 1M object buffer */
  161. r = radeon_bo_create(rdev, NULL, RADEON_IB_POOL_SIZE*64*1024,
  162. true, RADEON_GEM_DOMAIN_GTT,
  163. &rdev->ib_pool.robj);
  164. if (r) {
  165. DRM_ERROR("radeon: failed to ib pool (%d).\n", r);
  166. return r;
  167. }
  168. r = radeon_bo_reserve(rdev->ib_pool.robj, false);
  169. if (unlikely(r != 0))
  170. return r;
  171. r = radeon_bo_pin(rdev->ib_pool.robj, RADEON_GEM_DOMAIN_GTT, &gpu_addr);
  172. if (r) {
  173. radeon_bo_unreserve(rdev->ib_pool.robj);
  174. DRM_ERROR("radeon: failed to pin ib pool (%d).\n", r);
  175. return r;
  176. }
  177. r = radeon_bo_kmap(rdev->ib_pool.robj, &ptr);
  178. radeon_bo_unreserve(rdev->ib_pool.robj);
  179. if (r) {
  180. DRM_ERROR("radeon: failed to map ib poll (%d).\n", r);
  181. return r;
  182. }
  183. for (i = 0; i < RADEON_IB_POOL_SIZE; i++) {
  184. unsigned offset;
  185. offset = i * 64 * 1024;
  186. rdev->ib_pool.ibs[i].gpu_addr = gpu_addr + offset;
  187. rdev->ib_pool.ibs[i].ptr = ptr + offset;
  188. rdev->ib_pool.ibs[i].idx = i;
  189. rdev->ib_pool.ibs[i].length_dw = 0;
  190. rdev->ib_pool.ibs[i].free = true;
  191. }
  192. rdev->ib_pool.head_id = 0;
  193. rdev->ib_pool.ready = true;
  194. DRM_INFO("radeon: ib pool ready.\n");
  195. if (radeon_debugfs_ib_init(rdev)) {
  196. DRM_ERROR("Failed to register debugfs file for IB !\n");
  197. }
  198. return r;
  199. }
  200. void radeon_ib_pool_fini(struct radeon_device *rdev)
  201. {
  202. int r;
  203. if (!rdev->ib_pool.ready) {
  204. return;
  205. }
  206. mutex_lock(&rdev->ib_pool.mutex);
  207. radeon_ib_bogus_cleanup(rdev);
  208. if (rdev->ib_pool.robj) {
  209. r = radeon_bo_reserve(rdev->ib_pool.robj, false);
  210. if (likely(r == 0)) {
  211. radeon_bo_kunmap(rdev->ib_pool.robj);
  212. radeon_bo_unpin(rdev->ib_pool.robj);
  213. radeon_bo_unreserve(rdev->ib_pool.robj);
  214. }
  215. radeon_bo_unref(&rdev->ib_pool.robj);
  216. rdev->ib_pool.robj = NULL;
  217. }
  218. mutex_unlock(&rdev->ib_pool.mutex);
  219. }
  220. /*
  221. * Ring.
  222. */
  223. void radeon_ring_free_size(struct radeon_device *rdev)
  224. {
  225. if (rdev->family >= CHIP_R600)
  226. rdev->cp.rptr = RREG32(R600_CP_RB_RPTR);
  227. else
  228. rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
  229. /* This works because ring_size is a power of 2 */
  230. rdev->cp.ring_free_dw = (rdev->cp.rptr + (rdev->cp.ring_size / 4));
  231. rdev->cp.ring_free_dw -= rdev->cp.wptr;
  232. rdev->cp.ring_free_dw &= rdev->cp.ptr_mask;
  233. if (!rdev->cp.ring_free_dw) {
  234. rdev->cp.ring_free_dw = rdev->cp.ring_size / 4;
  235. }
  236. }
  237. int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw)
  238. {
  239. int r;
  240. /* Align requested size with padding so unlock_commit can
  241. * pad safely */
  242. ndw = (ndw + rdev->cp.align_mask) & ~rdev->cp.align_mask;
  243. mutex_lock(&rdev->cp.mutex);
  244. while (ndw > (rdev->cp.ring_free_dw - 1)) {
  245. radeon_ring_free_size(rdev);
  246. if (ndw < rdev->cp.ring_free_dw) {
  247. break;
  248. }
  249. r = radeon_fence_wait_next(rdev);
  250. if (r) {
  251. mutex_unlock(&rdev->cp.mutex);
  252. return r;
  253. }
  254. }
  255. rdev->cp.count_dw = ndw;
  256. rdev->cp.wptr_old = rdev->cp.wptr;
  257. return 0;
  258. }
  259. void radeon_ring_unlock_commit(struct radeon_device *rdev)
  260. {
  261. unsigned count_dw_pad;
  262. unsigned i;
  263. /* We pad to match fetch size */
  264. count_dw_pad = (rdev->cp.align_mask + 1) -
  265. (rdev->cp.wptr & rdev->cp.align_mask);
  266. for (i = 0; i < count_dw_pad; i++) {
  267. radeon_ring_write(rdev, 2 << 30);
  268. }
  269. DRM_MEMORYBARRIER();
  270. radeon_cp_commit(rdev);
  271. mutex_unlock(&rdev->cp.mutex);
  272. }
  273. void radeon_ring_unlock_undo(struct radeon_device *rdev)
  274. {
  275. rdev->cp.wptr = rdev->cp.wptr_old;
  276. mutex_unlock(&rdev->cp.mutex);
  277. }
  278. int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size)
  279. {
  280. int r;
  281. rdev->cp.ring_size = ring_size;
  282. /* Allocate ring buffer */
  283. if (rdev->cp.ring_obj == NULL) {
  284. r = radeon_bo_create(rdev, NULL, rdev->cp.ring_size, true,
  285. RADEON_GEM_DOMAIN_GTT,
  286. &rdev->cp.ring_obj);
  287. if (r) {
  288. dev_err(rdev->dev, "(%d) ring create failed\n", r);
  289. return r;
  290. }
  291. r = radeon_bo_reserve(rdev->cp.ring_obj, false);
  292. if (unlikely(r != 0))
  293. return r;
  294. r = radeon_bo_pin(rdev->cp.ring_obj, RADEON_GEM_DOMAIN_GTT,
  295. &rdev->cp.gpu_addr);
  296. if (r) {
  297. radeon_bo_unreserve(rdev->cp.ring_obj);
  298. dev_err(rdev->dev, "(%d) ring pin failed\n", r);
  299. return r;
  300. }
  301. r = radeon_bo_kmap(rdev->cp.ring_obj,
  302. (void **)&rdev->cp.ring);
  303. radeon_bo_unreserve(rdev->cp.ring_obj);
  304. if (r) {
  305. dev_err(rdev->dev, "(%d) ring map failed\n", r);
  306. return r;
  307. }
  308. }
  309. rdev->cp.ptr_mask = (rdev->cp.ring_size / 4) - 1;
  310. rdev->cp.ring_free_dw = rdev->cp.ring_size / 4;
  311. return 0;
  312. }
  313. void radeon_ring_fini(struct radeon_device *rdev)
  314. {
  315. int r;
  316. mutex_lock(&rdev->cp.mutex);
  317. if (rdev->cp.ring_obj) {
  318. r = radeon_bo_reserve(rdev->cp.ring_obj, false);
  319. if (likely(r == 0)) {
  320. radeon_bo_kunmap(rdev->cp.ring_obj);
  321. radeon_bo_unpin(rdev->cp.ring_obj);
  322. radeon_bo_unreserve(rdev->cp.ring_obj);
  323. }
  324. radeon_bo_unref(&rdev->cp.ring_obj);
  325. rdev->cp.ring = NULL;
  326. rdev->cp.ring_obj = NULL;
  327. }
  328. mutex_unlock(&rdev->cp.mutex);
  329. }
  330. /*
  331. * Debugfs info
  332. */
  333. #if defined(CONFIG_DEBUG_FS)
  334. static int radeon_debugfs_ib_info(struct seq_file *m, void *data)
  335. {
  336. struct drm_info_node *node = (struct drm_info_node *) m->private;
  337. struct radeon_ib *ib = node->info_ent->data;
  338. unsigned i;
  339. if (ib == NULL) {
  340. return 0;
  341. }
  342. seq_printf(m, "IB %04u\n", ib->idx);
  343. seq_printf(m, "IB fence %p\n", ib->fence);
  344. seq_printf(m, "IB size %05u dwords\n", ib->length_dw);
  345. for (i = 0; i < ib->length_dw; i++) {
  346. seq_printf(m, "[%05u]=0x%08X\n", i, ib->ptr[i]);
  347. }
  348. return 0;
  349. }
  350. static int radeon_debugfs_ib_bogus_info(struct seq_file *m, void *data)
  351. {
  352. struct drm_info_node *node = (struct drm_info_node *) m->private;
  353. struct radeon_device *rdev = node->info_ent->data;
  354. struct radeon_ib *ib;
  355. unsigned i;
  356. mutex_lock(&rdev->ib_pool.mutex);
  357. if (list_empty(&rdev->ib_pool.bogus_ib)) {
  358. mutex_unlock(&rdev->ib_pool.mutex);
  359. seq_printf(m, "no bogus IB recorded\n");
  360. return 0;
  361. }
  362. ib = list_first_entry(&rdev->ib_pool.bogus_ib, struct radeon_ib, list);
  363. list_del_init(&ib->list);
  364. mutex_unlock(&rdev->ib_pool.mutex);
  365. seq_printf(m, "IB size %05u dwords\n", ib->length_dw);
  366. for (i = 0; i < ib->length_dw; i++) {
  367. seq_printf(m, "[%05u]=0x%08X\n", i, ib->ptr[i]);
  368. }
  369. vfree(ib->ptr);
  370. kfree(ib);
  371. return 0;
  372. }
  373. static struct drm_info_list radeon_debugfs_ib_list[RADEON_IB_POOL_SIZE];
  374. static char radeon_debugfs_ib_names[RADEON_IB_POOL_SIZE][32];
  375. static struct drm_info_list radeon_debugfs_ib_bogus_info_list[] = {
  376. {"radeon_ib_bogus", radeon_debugfs_ib_bogus_info, 0, NULL},
  377. };
  378. #endif
  379. int radeon_debugfs_ib_init(struct radeon_device *rdev)
  380. {
  381. #if defined(CONFIG_DEBUG_FS)
  382. unsigned i;
  383. int r;
  384. radeon_debugfs_ib_bogus_info_list[0].data = rdev;
  385. r = radeon_debugfs_add_files(rdev, radeon_debugfs_ib_bogus_info_list, 1);
  386. if (r)
  387. return r;
  388. for (i = 0; i < RADEON_IB_POOL_SIZE; i++) {
  389. sprintf(radeon_debugfs_ib_names[i], "radeon_ib_%04u", i);
  390. radeon_debugfs_ib_list[i].name = radeon_debugfs_ib_names[i];
  391. radeon_debugfs_ib_list[i].show = &radeon_debugfs_ib_info;
  392. radeon_debugfs_ib_list[i].driver_features = 0;
  393. radeon_debugfs_ib_list[i].data = &rdev->ib_pool.ibs[i];
  394. }
  395. return radeon_debugfs_add_files(rdev, radeon_debugfs_ib_list,
  396. RADEON_IB_POOL_SIZE);
  397. #else
  398. return 0;
  399. #endif
  400. }