ps3vram.c 18 KB

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  1. /**
  2. * ps3vram - Use extra PS3 video ram as MTD block device.
  3. *
  4. * Copyright (c) 2007-2008 Jim Paris <jim@jtan.com>
  5. * Added support RSX DMA Vivien Chappelier <vivien.chappelier@free.fr>
  6. */
  7. #include <linux/io.h>
  8. #include <linux/init.h>
  9. #include <linux/kernel.h>
  10. #include <linux/list.h>
  11. #include <linux/module.h>
  12. #include <linux/moduleparam.h>
  13. #include <linux/slab.h>
  14. #include <linux/version.h>
  15. #include <linux/gfp.h>
  16. #include <linux/delay.h>
  17. #include <linux/mtd/mtd.h>
  18. #include <asm/lv1call.h>
  19. #include <asm/ps3.h>
  20. #define DEVICE_NAME "ps3vram"
  21. #define XDR_BUF_SIZE (2 * 1024 * 1024) /* XDR buffer (must be 1MiB aligned) */
  22. #define XDR_IOIF 0x0c000000
  23. #define FIFO_BASE XDR_IOIF
  24. #define FIFO_SIZE (64 * 1024)
  25. #define DMA_PAGE_SIZE (4 * 1024)
  26. #define CACHE_PAGE_SIZE (256 * 1024)
  27. #define CACHE_PAGE_COUNT ((XDR_BUF_SIZE - FIFO_SIZE) / CACHE_PAGE_SIZE)
  28. #define CACHE_OFFSET CACHE_PAGE_SIZE
  29. #define FIFO_OFFSET 0
  30. #define CTRL_PUT 0x10
  31. #define CTRL_GET 0x11
  32. #define CTRL_TOP 0x15
  33. #define UPLOAD_SUBCH 1
  34. #define DOWNLOAD_SUBCH 2
  35. #define NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN 0x0000030c
  36. #define NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY 0x00000104
  37. #define L1GPU_CONTEXT_ATTRIBUTE_FB_BLIT 0x601
  38. struct mtd_info ps3vram_mtd;
  39. #define CACHE_PAGE_PRESENT 1
  40. #define CACHE_PAGE_DIRTY 2
  41. #define dbg(fmt, args...) \
  42. pr_debug("%s:%d " fmt "\n", __func__, __LINE__, ## args)
  43. struct ps3vram_tag {
  44. unsigned int address;
  45. unsigned int flags;
  46. };
  47. struct ps3vram_cache {
  48. unsigned int page_count;
  49. unsigned int page_size;
  50. struct ps3vram_tag *tags;
  51. };
  52. struct ps3vram_priv {
  53. uint64_t memory_handle;
  54. uint64_t context_handle;
  55. uint8_t *base;
  56. uint32_t *ctrl;
  57. uint32_t *reports;
  58. uint8_t *xdr_buf;
  59. uint32_t *fifo_base;
  60. uint32_t *fifo_ptr;
  61. struct ps3vram_cache cache;
  62. /* Used to serialize cache/DMA operations */
  63. struct mutex lock;
  64. };
  65. #define DMA_NOTIFIER_HANDLE_BASE 0x66604200 /* first DMA notifier handle */
  66. #define DMA_NOTIFIER_OFFSET_BASE 0x1000 /* first DMA notifier offset */
  67. #define DMA_NOTIFIER_SIZE 0x40
  68. #define NOTIFIER 7 /* notifier used for completion report */
  69. /* A trailing '-' means to subtract off ps3fb_videomemory.size */
  70. char *size = "256M-";
  71. module_param(size, charp, 0);
  72. MODULE_PARM_DESC(size, "memory size");
  73. static inline uint32_t *ps3vram_get_notifier(uint32_t *reports, int notifier)
  74. {
  75. return (void *) reports +
  76. DMA_NOTIFIER_OFFSET_BASE +
  77. DMA_NOTIFIER_SIZE * notifier;
  78. }
  79. static void ps3vram_notifier_reset(struct mtd_info *mtd)
  80. {
  81. int i;
  82. struct ps3vram_priv *priv = mtd->priv;
  83. uint32_t *notify = ps3vram_get_notifier(priv->reports, NOTIFIER);
  84. for (i = 0; i < 4; i++)
  85. notify[i] = 0xffffffff;
  86. }
  87. static int ps3vram_notifier_wait(struct mtd_info *mtd, int timeout_ms)
  88. {
  89. struct ps3vram_priv *priv = mtd->priv;
  90. uint32_t *notify = ps3vram_get_notifier(priv->reports, NOTIFIER);
  91. timeout_ms *= 1000;
  92. do {
  93. if (notify[3] == 0)
  94. return 0;
  95. if (timeout_ms)
  96. udelay(1);
  97. } while (timeout_ms--);
  98. return -1;
  99. }
  100. static void ps3vram_init_ring(struct mtd_info *mtd)
  101. {
  102. struct ps3vram_priv *priv = mtd->priv;
  103. priv->ctrl[CTRL_PUT] = FIFO_BASE + FIFO_OFFSET;
  104. priv->ctrl[CTRL_GET] = FIFO_BASE + FIFO_OFFSET;
  105. }
  106. static int ps3vram_wait_ring(struct mtd_info *mtd, int timeout)
  107. {
  108. struct ps3vram_priv *priv = mtd->priv;
  109. /* wait until setup commands are processed */
  110. timeout *= 1000;
  111. while (--timeout) {
  112. if (priv->ctrl[CTRL_PUT] == priv->ctrl[CTRL_GET])
  113. break;
  114. udelay(1);
  115. }
  116. if (timeout == 0) {
  117. pr_err("FIFO timeout (%08x/%08x/%08x)\n", priv->ctrl[CTRL_PUT],
  118. priv->ctrl[CTRL_GET], priv->ctrl[CTRL_TOP]);
  119. return -ETIMEDOUT;
  120. }
  121. return 0;
  122. }
  123. static inline void ps3vram_out_ring(struct ps3vram_priv *priv, uint32_t data)
  124. {
  125. *(priv->fifo_ptr)++ = data;
  126. }
  127. static inline void ps3vram_begin_ring(struct ps3vram_priv *priv, uint32_t chan,
  128. uint32_t tag, uint32_t size)
  129. {
  130. ps3vram_out_ring(priv, (size << 18) | (chan << 13) | tag);
  131. }
  132. static void ps3vram_rewind_ring(struct mtd_info *mtd)
  133. {
  134. struct ps3vram_priv *priv = mtd->priv;
  135. u64 status;
  136. ps3vram_out_ring(priv, 0x20000000 | (FIFO_BASE + FIFO_OFFSET));
  137. priv->ctrl[CTRL_PUT] = FIFO_BASE + FIFO_OFFSET;
  138. /* asking the HV for a blit will kick the fifo */
  139. status = lv1_gpu_context_attribute(priv->context_handle,
  140. L1GPU_CONTEXT_ATTRIBUTE_FB_BLIT,
  141. 0, 0, 0, 0);
  142. if (status)
  143. pr_err("ps3vram: lv1_gpu_context_attribute FB_BLIT failed\n");
  144. priv->fifo_ptr = priv->fifo_base;
  145. }
  146. static void ps3vram_fire_ring(struct mtd_info *mtd)
  147. {
  148. struct ps3vram_priv *priv = mtd->priv;
  149. u64 status;
  150. mutex_lock(&ps3_gpu_mutex);
  151. priv->ctrl[CTRL_PUT] = FIFO_BASE + FIFO_OFFSET +
  152. (priv->fifo_ptr - priv->fifo_base) * sizeof(uint32_t);
  153. /* asking the HV for a blit will kick the fifo */
  154. status = lv1_gpu_context_attribute(priv->context_handle,
  155. L1GPU_CONTEXT_ATTRIBUTE_FB_BLIT,
  156. 0, 0, 0, 0);
  157. if (status)
  158. pr_err("ps3vram: lv1_gpu_context_attribute FB_BLIT failed\n");
  159. if ((priv->fifo_ptr - priv->fifo_base) * sizeof(uint32_t) >
  160. FIFO_SIZE - 1024) {
  161. dbg("fifo full, rewinding");
  162. ps3vram_wait_ring(mtd, 200);
  163. ps3vram_rewind_ring(mtd);
  164. }
  165. mutex_unlock(&ps3_gpu_mutex);
  166. }
  167. static void ps3vram_bind(struct mtd_info *mtd)
  168. {
  169. struct ps3vram_priv *priv = mtd->priv;
  170. ps3vram_begin_ring(priv, UPLOAD_SUBCH, 0, 1);
  171. ps3vram_out_ring(priv, 0x31337303);
  172. ps3vram_begin_ring(priv, UPLOAD_SUBCH, 0x180, 3);
  173. ps3vram_out_ring(priv, DMA_NOTIFIER_HANDLE_BASE + NOTIFIER);
  174. ps3vram_out_ring(priv, 0xfeed0001); /* DMA system RAM instance */
  175. ps3vram_out_ring(priv, 0xfeed0000); /* DMA video RAM instance */
  176. ps3vram_begin_ring(priv, DOWNLOAD_SUBCH, 0, 1);
  177. ps3vram_out_ring(priv, 0x3137c0de);
  178. ps3vram_begin_ring(priv, DOWNLOAD_SUBCH, 0x180, 3);
  179. ps3vram_out_ring(priv, DMA_NOTIFIER_HANDLE_BASE + NOTIFIER);
  180. ps3vram_out_ring(priv, 0xfeed0000); /* DMA video RAM instance */
  181. ps3vram_out_ring(priv, 0xfeed0001); /* DMA system RAM instance */
  182. ps3vram_fire_ring(mtd);
  183. }
  184. static int ps3vram_upload(struct mtd_info *mtd, unsigned int src_offset,
  185. unsigned int dst_offset, int len, int count)
  186. {
  187. struct ps3vram_priv *priv = mtd->priv;
  188. ps3vram_begin_ring(priv, UPLOAD_SUBCH,
  189. NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8);
  190. ps3vram_out_ring(priv, XDR_IOIF + src_offset);
  191. ps3vram_out_ring(priv, dst_offset);
  192. ps3vram_out_ring(priv, len);
  193. ps3vram_out_ring(priv, len);
  194. ps3vram_out_ring(priv, len);
  195. ps3vram_out_ring(priv, count);
  196. ps3vram_out_ring(priv, (1 << 8) | 1);
  197. ps3vram_out_ring(priv, 0);
  198. ps3vram_notifier_reset(mtd);
  199. ps3vram_begin_ring(priv, UPLOAD_SUBCH,
  200. NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY, 1);
  201. ps3vram_out_ring(priv, 0);
  202. ps3vram_begin_ring(priv, UPLOAD_SUBCH, 0x100, 1);
  203. ps3vram_out_ring(priv, 0);
  204. ps3vram_fire_ring(mtd);
  205. if (ps3vram_notifier_wait(mtd, 200) < 0) {
  206. pr_err("notifier timeout\n");
  207. return -1;
  208. }
  209. return 0;
  210. }
  211. static int ps3vram_download(struct mtd_info *mtd, unsigned int src_offset,
  212. unsigned int dst_offset, int len, int count)
  213. {
  214. struct ps3vram_priv *priv = mtd->priv;
  215. ps3vram_begin_ring(priv, DOWNLOAD_SUBCH,
  216. NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8);
  217. ps3vram_out_ring(priv, src_offset);
  218. ps3vram_out_ring(priv, XDR_IOIF + dst_offset);
  219. ps3vram_out_ring(priv, len);
  220. ps3vram_out_ring(priv, len);
  221. ps3vram_out_ring(priv, len);
  222. ps3vram_out_ring(priv, count);
  223. ps3vram_out_ring(priv, (1 << 8) | 1);
  224. ps3vram_out_ring(priv, 0);
  225. ps3vram_notifier_reset(mtd);
  226. ps3vram_begin_ring(priv, DOWNLOAD_SUBCH,
  227. NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY, 1);
  228. ps3vram_out_ring(priv, 0);
  229. ps3vram_begin_ring(priv, DOWNLOAD_SUBCH, 0x100, 1);
  230. ps3vram_out_ring(priv, 0);
  231. ps3vram_fire_ring(mtd);
  232. if (ps3vram_notifier_wait(mtd, 200) < 0) {
  233. pr_err("notifier timeout\n");
  234. return -1;
  235. }
  236. return 0;
  237. }
  238. static void ps3vram_cache_evict(struct mtd_info *mtd, int entry)
  239. {
  240. struct ps3vram_priv *priv = mtd->priv;
  241. struct ps3vram_cache *cache = &priv->cache;
  242. if (cache->tags[entry].flags & CACHE_PAGE_DIRTY) {
  243. dbg("flushing %d : 0x%08x", entry, cache->tags[entry].address);
  244. if (ps3vram_upload(mtd,
  245. CACHE_OFFSET + entry * cache->page_size,
  246. cache->tags[entry].address,
  247. DMA_PAGE_SIZE,
  248. cache->page_size / DMA_PAGE_SIZE) < 0) {
  249. pr_err("failed to upload from 0x%x to 0x%x size 0x%x\n",
  250. entry * cache->page_size,
  251. cache->tags[entry].address,
  252. cache->page_size);
  253. }
  254. cache->tags[entry].flags &= ~CACHE_PAGE_DIRTY;
  255. }
  256. }
  257. static void ps3vram_cache_load(struct mtd_info *mtd, int entry,
  258. unsigned int address)
  259. {
  260. struct ps3vram_priv *priv = mtd->priv;
  261. struct ps3vram_cache *cache = &priv->cache;
  262. dbg("fetching %d : 0x%08x", entry, address);
  263. if (ps3vram_download(mtd,
  264. address,
  265. CACHE_OFFSET + entry * cache->page_size,
  266. DMA_PAGE_SIZE,
  267. cache->page_size / DMA_PAGE_SIZE) < 0) {
  268. pr_err("failed to download from 0x%x to 0x%x size 0x%x\n",
  269. address,
  270. entry * cache->page_size,
  271. cache->page_size);
  272. }
  273. cache->tags[entry].address = address;
  274. cache->tags[entry].flags |= CACHE_PAGE_PRESENT;
  275. }
  276. static void ps3vram_cache_flush(struct mtd_info *mtd)
  277. {
  278. struct ps3vram_priv *priv = mtd->priv;
  279. struct ps3vram_cache *cache = &priv->cache;
  280. int i;
  281. dbg("FLUSH");
  282. for (i = 0; i < cache->page_count; i++) {
  283. ps3vram_cache_evict(mtd, i);
  284. cache->tags[i].flags = 0;
  285. }
  286. }
  287. static unsigned int ps3vram_cache_match(struct mtd_info *mtd, loff_t address)
  288. {
  289. struct ps3vram_priv *priv = mtd->priv;
  290. struct ps3vram_cache *cache = &priv->cache;
  291. unsigned int base;
  292. unsigned int offset;
  293. int i;
  294. static int counter;
  295. offset = (unsigned int) (address & (cache->page_size - 1));
  296. base = (unsigned int) (address - offset);
  297. /* fully associative check */
  298. for (i = 0; i < cache->page_count; i++) {
  299. if ((cache->tags[i].flags & CACHE_PAGE_PRESENT) &&
  300. cache->tags[i].address == base) {
  301. dbg("found entry %d : 0x%08x",
  302. i, cache->tags[i].address);
  303. return i;
  304. }
  305. }
  306. /* choose a random entry */
  307. i = (jiffies + (counter++)) % cache->page_count;
  308. dbg("using cache entry %d", i);
  309. ps3vram_cache_evict(mtd, i);
  310. ps3vram_cache_load(mtd, i, base);
  311. return i;
  312. }
  313. static int ps3vram_cache_init(struct mtd_info *mtd)
  314. {
  315. struct ps3vram_priv *priv = mtd->priv;
  316. pr_info("creating cache: %d entries, %d bytes pages\n",
  317. CACHE_PAGE_COUNT, CACHE_PAGE_SIZE);
  318. priv->cache.page_count = CACHE_PAGE_COUNT;
  319. priv->cache.page_size = CACHE_PAGE_SIZE;
  320. priv->cache.tags = kzalloc(sizeof(struct ps3vram_tag) *
  321. CACHE_PAGE_COUNT, GFP_KERNEL);
  322. if (priv->cache.tags == NULL) {
  323. pr_err("could not allocate cache tags\n");
  324. return -ENOMEM;
  325. }
  326. return 0;
  327. }
  328. static void ps3vram_cache_cleanup(struct mtd_info *mtd)
  329. {
  330. struct ps3vram_priv *priv = mtd->priv;
  331. ps3vram_cache_flush(mtd);
  332. kfree(priv->cache.tags);
  333. }
  334. static int ps3vram_erase(struct mtd_info *mtd, struct erase_info *instr)
  335. {
  336. struct ps3vram_priv *priv = mtd->priv;
  337. if (instr->addr + instr->len > mtd->size)
  338. return -EINVAL;
  339. mutex_lock(&priv->lock);
  340. ps3vram_cache_flush(mtd);
  341. /* Set bytes to 0xFF */
  342. memset(priv->base + instr->addr, 0xFF, instr->len);
  343. mutex_unlock(&priv->lock);
  344. instr->state = MTD_ERASE_DONE;
  345. mtd_erase_callback(instr);
  346. return 0;
  347. }
  348. static int ps3vram_read(struct mtd_info *mtd, loff_t from, size_t len,
  349. size_t *retlen, u_char *buf)
  350. {
  351. struct ps3vram_priv *priv = mtd->priv;
  352. unsigned int cached, count;
  353. dbg("from = 0x%08x len = 0x%zx", (unsigned int) from, len);
  354. if (from >= mtd->size)
  355. return -EINVAL;
  356. if (len > mtd->size - from)
  357. len = mtd->size - from;
  358. /* Copy from vram to buf */
  359. count = len;
  360. while (count) {
  361. unsigned int offset, avail;
  362. unsigned int entry;
  363. offset = (unsigned int) (from & (priv->cache.page_size - 1));
  364. avail = priv->cache.page_size - offset;
  365. mutex_lock(&priv->lock);
  366. entry = ps3vram_cache_match(mtd, from);
  367. cached = CACHE_OFFSET + entry * priv->cache.page_size + offset;
  368. dbg("from=%08x cached=%08x offset=%08x avail=%08x count=%08x",
  369. (unsigned)from, cached, offset, avail, count);
  370. if (avail > count)
  371. avail = count;
  372. memcpy(buf, priv->xdr_buf + cached, avail);
  373. mutex_unlock(&priv->lock);
  374. buf += avail;
  375. count -= avail;
  376. from += avail;
  377. }
  378. *retlen = len;
  379. return 0;
  380. }
  381. static int ps3vram_write(struct mtd_info *mtd, loff_t to, size_t len,
  382. size_t *retlen, const u_char *buf)
  383. {
  384. struct ps3vram_priv *priv = mtd->priv;
  385. unsigned int cached, count;
  386. if (to >= mtd->size)
  387. return -EINVAL;
  388. if (len > mtd->size - to)
  389. len = mtd->size - to;
  390. /* Copy from buf to vram */
  391. count = len;
  392. while (count) {
  393. unsigned int offset, avail;
  394. unsigned int entry;
  395. offset = (unsigned int) (to & (priv->cache.page_size - 1));
  396. avail = priv->cache.page_size - offset;
  397. mutex_lock(&priv->lock);
  398. entry = ps3vram_cache_match(mtd, to);
  399. cached = CACHE_OFFSET + entry * priv->cache.page_size + offset;
  400. dbg("to=%08x cached=%08x offset=%08x avail=%08x count=%08x",
  401. (unsigned) to, cached, offset, avail, count);
  402. if (avail > count)
  403. avail = count;
  404. memcpy(priv->xdr_buf + cached, buf, avail);
  405. priv->cache.tags[entry].flags |= CACHE_PAGE_DIRTY;
  406. mutex_unlock(&priv->lock);
  407. buf += avail;
  408. count -= avail;
  409. to += avail;
  410. }
  411. *retlen = len;
  412. return 0;
  413. }
  414. static int __devinit ps3vram_probe(struct ps3_system_bus_device *dev)
  415. {
  416. struct ps3vram_priv *priv;
  417. uint64_t status;
  418. uint64_t ddr_lpar, ctrl_lpar, info_lpar, reports_lpar;
  419. int64_t ddr_size;
  420. uint64_t reports_size;
  421. int ret = -ENOMEM;
  422. char *rest;
  423. ret = -EIO;
  424. ps3vram_mtd.priv = kzalloc(sizeof(struct ps3vram_priv), GFP_KERNEL);
  425. if (!ps3vram_mtd.priv)
  426. goto out;
  427. priv = ps3vram_mtd.priv;
  428. mutex_init(&priv->lock);
  429. /* Allocate XDR buffer (1MiB aligned) */
  430. priv->xdr_buf = (uint8_t *) __get_free_pages(GFP_KERNEL,
  431. get_order(XDR_BUF_SIZE));
  432. if (priv->xdr_buf == NULL) {
  433. pr_err("ps3vram: could not allocate XDR buffer\n");
  434. ret = -ENOMEM;
  435. goto out_free_priv;
  436. }
  437. /* Put FIFO at begginning of XDR buffer */
  438. priv->fifo_base = (uint32_t *) (priv->xdr_buf + FIFO_OFFSET);
  439. priv->fifo_ptr = priv->fifo_base;
  440. /* XXX: Need to open GPU, in case ps3fb or snd_ps3 aren't loaded */
  441. if (ps3_open_hv_device(dev)) {
  442. pr_err("ps3vram: ps3_open_hv_device failed\n");
  443. ret = -EAGAIN;
  444. goto out_close_gpu;
  445. }
  446. /* Request memory */
  447. status = -1;
  448. ddr_size = memparse(size, &rest);
  449. if (*rest == '-')
  450. ddr_size -= ps3fb_videomemory.size;
  451. ddr_size = ALIGN(ddr_size, 1024*1024);
  452. if (ddr_size <= 0) {
  453. printk(KERN_ERR "ps3vram: specified size is too small\n");
  454. ret = -EINVAL;
  455. goto out_close_gpu;
  456. }
  457. while (ddr_size > 0) {
  458. status = lv1_gpu_memory_allocate(ddr_size, 0, 0, 0, 0,
  459. &priv->memory_handle,
  460. &ddr_lpar);
  461. if (status == 0)
  462. break;
  463. ddr_size -= 1024*1024;
  464. }
  465. if (status != 0 || ddr_size <= 0) {
  466. pr_err("ps3vram: lv1_gpu_memory_allocate failed\n");
  467. ret = -ENOMEM;
  468. goto out_free_xdr_buf;
  469. }
  470. pr_info("ps3vram: allocated %u MiB of DDR memory\n",
  471. (unsigned int) (ddr_size / 1024 / 1024));
  472. /* Request context */
  473. status = lv1_gpu_context_allocate(priv->memory_handle,
  474. 0,
  475. &priv->context_handle,
  476. &ctrl_lpar,
  477. &info_lpar,
  478. &reports_lpar,
  479. &reports_size);
  480. if (status) {
  481. pr_err("ps3vram: lv1_gpu_context_allocate failed\n");
  482. ret = -ENOMEM;
  483. goto out_free_memory;
  484. }
  485. /* Map XDR buffer to RSX */
  486. status = lv1_gpu_context_iomap(priv->context_handle, XDR_IOIF,
  487. ps3_mm_phys_to_lpar(__pa(priv->xdr_buf)),
  488. XDR_BUF_SIZE, 0);
  489. if (status) {
  490. pr_err("ps3vram: lv1_gpu_context_iomap failed\n");
  491. ret = -ENOMEM;
  492. goto out_free_context;
  493. }
  494. priv->base = ioremap(ddr_lpar, ddr_size);
  495. if (!priv->base) {
  496. pr_err("ps3vram: ioremap failed\n");
  497. ret = -ENOMEM;
  498. goto out_free_context;
  499. }
  500. priv->ctrl = ioremap(ctrl_lpar, 64 * 1024);
  501. if (!priv->ctrl) {
  502. pr_err("ps3vram: ioremap failed\n");
  503. ret = -ENOMEM;
  504. goto out_unmap_vram;
  505. }
  506. priv->reports = ioremap(reports_lpar, reports_size);
  507. if (!priv->reports) {
  508. pr_err("ps3vram: ioremap failed\n");
  509. ret = -ENOMEM;
  510. goto out_unmap_ctrl;
  511. }
  512. mutex_lock(&ps3_gpu_mutex);
  513. ps3vram_init_ring(&ps3vram_mtd);
  514. mutex_unlock(&ps3_gpu_mutex);
  515. ps3vram_mtd.name = "ps3vram";
  516. ps3vram_mtd.size = ddr_size;
  517. ps3vram_mtd.flags = MTD_CAP_RAM;
  518. ps3vram_mtd.erase = ps3vram_erase;
  519. ps3vram_mtd.point = NULL;
  520. ps3vram_mtd.unpoint = NULL;
  521. ps3vram_mtd.read = ps3vram_read;
  522. ps3vram_mtd.write = ps3vram_write;
  523. ps3vram_mtd.owner = THIS_MODULE;
  524. ps3vram_mtd.type = MTD_RAM;
  525. ps3vram_mtd.erasesize = CACHE_PAGE_SIZE;
  526. ps3vram_mtd.writesize = 1;
  527. ps3vram_bind(&ps3vram_mtd);
  528. mutex_lock(&ps3_gpu_mutex);
  529. ret = ps3vram_wait_ring(&ps3vram_mtd, 100);
  530. mutex_unlock(&ps3_gpu_mutex);
  531. if (ret < 0) {
  532. pr_err("failed to initialize channels\n");
  533. ret = -ETIMEDOUT;
  534. goto out_unmap_reports;
  535. }
  536. ps3vram_cache_init(&ps3vram_mtd);
  537. if (add_mtd_device(&ps3vram_mtd)) {
  538. pr_err("ps3vram: failed to register device\n");
  539. ret = -EAGAIN;
  540. goto out_cache_cleanup;
  541. }
  542. pr_info("ps3vram mtd device registered, %lu bytes\n", ddr_size);
  543. return 0;
  544. out_cache_cleanup:
  545. ps3vram_cache_cleanup(&ps3vram_mtd);
  546. out_unmap_reports:
  547. iounmap(priv->reports);
  548. out_unmap_ctrl:
  549. iounmap(priv->ctrl);
  550. out_unmap_vram:
  551. iounmap(priv->base);
  552. out_free_context:
  553. lv1_gpu_context_free(priv->context_handle);
  554. out_free_memory:
  555. lv1_gpu_memory_free(priv->memory_handle);
  556. out_close_gpu:
  557. ps3_close_hv_device(dev);
  558. out_free_xdr_buf:
  559. free_pages((unsigned long) priv->xdr_buf, get_order(XDR_BUF_SIZE));
  560. out_free_priv:
  561. kfree(ps3vram_mtd.priv);
  562. ps3vram_mtd.priv = NULL;
  563. out:
  564. return ret;
  565. }
  566. static int ps3vram_shutdown(struct ps3_system_bus_device *dev)
  567. {
  568. struct ps3vram_priv *priv;
  569. priv = ps3vram_mtd.priv;
  570. del_mtd_device(&ps3vram_mtd);
  571. ps3vram_cache_cleanup(&ps3vram_mtd);
  572. iounmap(priv->reports);
  573. iounmap(priv->ctrl);
  574. iounmap(priv->base);
  575. lv1_gpu_context_free(priv->context_handle);
  576. lv1_gpu_memory_free(priv->memory_handle);
  577. ps3_close_hv_device(dev);
  578. free_pages((unsigned long) priv->xdr_buf, get_order(XDR_BUF_SIZE));
  579. kfree(priv);
  580. return 0;
  581. }
  582. static struct ps3_system_bus_driver ps3vram_driver = {
  583. .match_id = PS3_MATCH_ID_GPU,
  584. .match_sub_id = PS3_MATCH_SUB_ID_GPU_RAMDISK,
  585. .core.name = DEVICE_NAME,
  586. .core.owner = THIS_MODULE,
  587. .probe = ps3vram_probe,
  588. .remove = ps3vram_shutdown,
  589. .shutdown = ps3vram_shutdown,
  590. };
  591. static int __init ps3vram_init(void)
  592. {
  593. return ps3_system_bus_driver_register(&ps3vram_driver);
  594. }
  595. static void __exit ps3vram_exit(void)
  596. {
  597. ps3_system_bus_driver_unregister(&ps3vram_driver);
  598. }
  599. module_init(ps3vram_init);
  600. module_exit(ps3vram_exit);
  601. MODULE_LICENSE("GPL");
  602. MODULE_AUTHOR("Jim Paris <jim@jtan.com>");
  603. MODULE_DESCRIPTION("MTD driver for PS3 video RAM");
  604. MODULE_ALIAS(PS3_MODULE_ALIAS_GPU_RAMDISK);