i915_debugfs.c 38 KB

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  1. /*
  2. * Copyright © 2008 Intel Corporation
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice (including the next
  12. * paragraph) shall be included in all copies or substantial portions of the
  13. * Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  18. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21. * IN THE SOFTWARE.
  22. *
  23. * Authors:
  24. * Eric Anholt <eric@anholt.net>
  25. * Keith Packard <keithp@keithp.com>
  26. *
  27. */
  28. #include <linux/seq_file.h>
  29. #include <linux/debugfs.h>
  30. #include <linux/slab.h>
  31. #include "drmP.h"
  32. #include "drm.h"
  33. #include "intel_drv.h"
  34. #include "intel_ringbuffer.h"
  35. #include "i915_drm.h"
  36. #include "i915_drv.h"
  37. #define DRM_I915_RING_DEBUG 1
  38. #if defined(CONFIG_DEBUG_FS)
  39. enum {
  40. ACTIVE_LIST,
  41. FLUSHING_LIST,
  42. INACTIVE_LIST,
  43. PINNED_LIST,
  44. DEFERRED_FREE_LIST,
  45. };
  46. static const char *yesno(int v)
  47. {
  48. return v ? "yes" : "no";
  49. }
  50. static int i915_capabilities(struct seq_file *m, void *data)
  51. {
  52. struct drm_info_node *node = (struct drm_info_node *) m->private;
  53. struct drm_device *dev = node->minor->dev;
  54. const struct intel_device_info *info = INTEL_INFO(dev);
  55. seq_printf(m, "gen: %d\n", info->gen);
  56. #define B(x) seq_printf(m, #x ": %s\n", yesno(info->x))
  57. B(is_mobile);
  58. B(is_i85x);
  59. B(is_i915g);
  60. B(is_i945gm);
  61. B(is_g33);
  62. B(need_gfx_hws);
  63. B(is_g4x);
  64. B(is_pineview);
  65. B(is_broadwater);
  66. B(is_crestline);
  67. B(has_fbc);
  68. B(has_pipe_cxsr);
  69. B(has_hotplug);
  70. B(cursor_needs_physical);
  71. B(has_overlay);
  72. B(overlay_needs_physical);
  73. B(supports_tv);
  74. B(has_bsd_ring);
  75. B(has_blt_ring);
  76. #undef B
  77. return 0;
  78. }
  79. static const char *get_pin_flag(struct drm_i915_gem_object *obj)
  80. {
  81. if (obj->user_pin_count > 0)
  82. return "P";
  83. else if (obj->pin_count > 0)
  84. return "p";
  85. else
  86. return " ";
  87. }
  88. static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
  89. {
  90. switch (obj->tiling_mode) {
  91. default:
  92. case I915_TILING_NONE: return " ";
  93. case I915_TILING_X: return "X";
  94. case I915_TILING_Y: return "Y";
  95. }
  96. }
  97. static const char *agp_type_str(int type)
  98. {
  99. switch (type) {
  100. case 0: return " uncached";
  101. case 1: return " snooped";
  102. default: return "";
  103. }
  104. }
  105. static void
  106. describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
  107. {
  108. seq_printf(m, "%p: %s%s %8zd %04x %04x %d %d%s%s%s",
  109. &obj->base,
  110. get_pin_flag(obj),
  111. get_tiling_flag(obj),
  112. obj->base.size,
  113. obj->base.read_domains,
  114. obj->base.write_domain,
  115. obj->last_rendering_seqno,
  116. obj->last_fenced_seqno,
  117. agp_type_str(obj->agp_type == AGP_USER_CACHED_MEMORY),
  118. obj->dirty ? " dirty" : "",
  119. obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
  120. if (obj->base.name)
  121. seq_printf(m, " (name: %d)", obj->base.name);
  122. if (obj->fence_reg != I915_FENCE_REG_NONE)
  123. seq_printf(m, " (fence: %d)", obj->fence_reg);
  124. if (obj->gtt_space != NULL)
  125. seq_printf(m, " (gtt offset: %08x, size: %08x)",
  126. obj->gtt_offset, (unsigned int)obj->gtt_space->size);
  127. if (obj->pin_mappable || obj->fault_mappable) {
  128. char s[3], *t = s;
  129. if (obj->pin_mappable)
  130. *t++ = 'p';
  131. if (obj->fault_mappable)
  132. *t++ = 'f';
  133. *t = '\0';
  134. seq_printf(m, " (%s mappable)", s);
  135. }
  136. if (obj->ring != NULL)
  137. seq_printf(m, " (%s)", obj->ring->name);
  138. }
  139. static int i915_gem_object_list_info(struct seq_file *m, void *data)
  140. {
  141. struct drm_info_node *node = (struct drm_info_node *) m->private;
  142. uintptr_t list = (uintptr_t) node->info_ent->data;
  143. struct list_head *head;
  144. struct drm_device *dev = node->minor->dev;
  145. drm_i915_private_t *dev_priv = dev->dev_private;
  146. struct drm_i915_gem_object *obj;
  147. size_t total_obj_size, total_gtt_size;
  148. int count, ret;
  149. ret = mutex_lock_interruptible(&dev->struct_mutex);
  150. if (ret)
  151. return ret;
  152. switch (list) {
  153. case ACTIVE_LIST:
  154. seq_printf(m, "Active:\n");
  155. head = &dev_priv->mm.active_list;
  156. break;
  157. case INACTIVE_LIST:
  158. seq_printf(m, "Inactive:\n");
  159. head = &dev_priv->mm.inactive_list;
  160. break;
  161. case PINNED_LIST:
  162. seq_printf(m, "Pinned:\n");
  163. head = &dev_priv->mm.pinned_list;
  164. break;
  165. case FLUSHING_LIST:
  166. seq_printf(m, "Flushing:\n");
  167. head = &dev_priv->mm.flushing_list;
  168. break;
  169. case DEFERRED_FREE_LIST:
  170. seq_printf(m, "Deferred free:\n");
  171. head = &dev_priv->mm.deferred_free_list;
  172. break;
  173. default:
  174. mutex_unlock(&dev->struct_mutex);
  175. return -EINVAL;
  176. }
  177. total_obj_size = total_gtt_size = count = 0;
  178. list_for_each_entry(obj, head, mm_list) {
  179. seq_printf(m, " ");
  180. describe_obj(m, obj);
  181. seq_printf(m, "\n");
  182. total_obj_size += obj->base.size;
  183. total_gtt_size += obj->gtt_space->size;
  184. count++;
  185. }
  186. mutex_unlock(&dev->struct_mutex);
  187. seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
  188. count, total_obj_size, total_gtt_size);
  189. return 0;
  190. }
  191. #define count_objects(list, member) do { \
  192. list_for_each_entry(obj, list, member) { \
  193. size += obj->gtt_space->size; \
  194. ++count; \
  195. if (obj->map_and_fenceable) { \
  196. mappable_size += obj->gtt_space->size; \
  197. ++mappable_count; \
  198. } \
  199. } \
  200. } while(0)
  201. static int i915_gem_object_info(struct seq_file *m, void* data)
  202. {
  203. struct drm_info_node *node = (struct drm_info_node *) m->private;
  204. struct drm_device *dev = node->minor->dev;
  205. struct drm_i915_private *dev_priv = dev->dev_private;
  206. u32 count, mappable_count;
  207. size_t size, mappable_size;
  208. struct drm_i915_gem_object *obj;
  209. int ret;
  210. ret = mutex_lock_interruptible(&dev->struct_mutex);
  211. if (ret)
  212. return ret;
  213. seq_printf(m, "%u objects, %zu bytes\n",
  214. dev_priv->mm.object_count,
  215. dev_priv->mm.object_memory);
  216. size = count = mappable_size = mappable_count = 0;
  217. count_objects(&dev_priv->mm.gtt_list, gtt_list);
  218. seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
  219. count, mappable_count, size, mappable_size);
  220. size = count = mappable_size = mappable_count = 0;
  221. count_objects(&dev_priv->mm.active_list, mm_list);
  222. count_objects(&dev_priv->mm.flushing_list, mm_list);
  223. seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n",
  224. count, mappable_count, size, mappable_size);
  225. size = count = mappable_size = mappable_count = 0;
  226. count_objects(&dev_priv->mm.pinned_list, mm_list);
  227. seq_printf(m, " %u [%u] pinned objects, %zu [%zu] bytes\n",
  228. count, mappable_count, size, mappable_size);
  229. size = count = mappable_size = mappable_count = 0;
  230. count_objects(&dev_priv->mm.inactive_list, mm_list);
  231. seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n",
  232. count, mappable_count, size, mappable_size);
  233. size = count = mappable_size = mappable_count = 0;
  234. count_objects(&dev_priv->mm.deferred_free_list, mm_list);
  235. seq_printf(m, " %u [%u] freed objects, %zu [%zu] bytes\n",
  236. count, mappable_count, size, mappable_size);
  237. size = count = mappable_size = mappable_count = 0;
  238. list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) {
  239. if (obj->fault_mappable) {
  240. size += obj->gtt_space->size;
  241. ++count;
  242. }
  243. if (obj->pin_mappable) {
  244. mappable_size += obj->gtt_space->size;
  245. ++mappable_count;
  246. }
  247. }
  248. seq_printf(m, "%u pinned mappable objects, %zu bytes\n",
  249. mappable_count, mappable_size);
  250. seq_printf(m, "%u fault mappable objects, %zu bytes\n",
  251. count, size);
  252. seq_printf(m, "%zu [%zu] gtt total\n",
  253. dev_priv->mm.gtt_total, dev_priv->mm.mappable_gtt_total);
  254. mutex_unlock(&dev->struct_mutex);
  255. return 0;
  256. }
  257. static int i915_gem_gtt_info(struct seq_file *m, void* data)
  258. {
  259. struct drm_info_node *node = (struct drm_info_node *) m->private;
  260. struct drm_device *dev = node->minor->dev;
  261. struct drm_i915_private *dev_priv = dev->dev_private;
  262. struct drm_i915_gem_object *obj;
  263. size_t total_obj_size, total_gtt_size;
  264. int count, ret;
  265. ret = mutex_lock_interruptible(&dev->struct_mutex);
  266. if (ret)
  267. return ret;
  268. total_obj_size = total_gtt_size = count = 0;
  269. list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) {
  270. seq_printf(m, " ");
  271. describe_obj(m, obj);
  272. seq_printf(m, "\n");
  273. total_obj_size += obj->base.size;
  274. total_gtt_size += obj->gtt_space->size;
  275. count++;
  276. }
  277. mutex_unlock(&dev->struct_mutex);
  278. seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
  279. count, total_obj_size, total_gtt_size);
  280. return 0;
  281. }
  282. static int i915_gem_pageflip_info(struct seq_file *m, void *data)
  283. {
  284. struct drm_info_node *node = (struct drm_info_node *) m->private;
  285. struct drm_device *dev = node->minor->dev;
  286. unsigned long flags;
  287. struct intel_crtc *crtc;
  288. list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
  289. const char pipe = pipe_name(crtc->pipe);
  290. const char plane = plane_name(crtc->plane);
  291. struct intel_unpin_work *work;
  292. spin_lock_irqsave(&dev->event_lock, flags);
  293. work = crtc->unpin_work;
  294. if (work == NULL) {
  295. seq_printf(m, "No flip due on pipe %c (plane %c)\n",
  296. pipe, plane);
  297. } else {
  298. if (!work->pending) {
  299. seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
  300. pipe, plane);
  301. } else {
  302. seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
  303. pipe, plane);
  304. }
  305. if (work->enable_stall_check)
  306. seq_printf(m, "Stall check enabled, ");
  307. else
  308. seq_printf(m, "Stall check waiting for page flip ioctl, ");
  309. seq_printf(m, "%d prepares\n", work->pending);
  310. if (work->old_fb_obj) {
  311. struct drm_i915_gem_object *obj = work->old_fb_obj;
  312. if (obj)
  313. seq_printf(m, "Old framebuffer gtt_offset 0x%08x\n", obj->gtt_offset);
  314. }
  315. if (work->pending_flip_obj) {
  316. struct drm_i915_gem_object *obj = work->pending_flip_obj;
  317. if (obj)
  318. seq_printf(m, "New framebuffer gtt_offset 0x%08x\n", obj->gtt_offset);
  319. }
  320. }
  321. spin_unlock_irqrestore(&dev->event_lock, flags);
  322. }
  323. return 0;
  324. }
  325. static int i915_gem_request_info(struct seq_file *m, void *data)
  326. {
  327. struct drm_info_node *node = (struct drm_info_node *) m->private;
  328. struct drm_device *dev = node->minor->dev;
  329. drm_i915_private_t *dev_priv = dev->dev_private;
  330. struct drm_i915_gem_request *gem_request;
  331. int ret, count;
  332. ret = mutex_lock_interruptible(&dev->struct_mutex);
  333. if (ret)
  334. return ret;
  335. count = 0;
  336. if (!list_empty(&dev_priv->ring[RCS].request_list)) {
  337. seq_printf(m, "Render requests:\n");
  338. list_for_each_entry(gem_request,
  339. &dev_priv->ring[RCS].request_list,
  340. list) {
  341. seq_printf(m, " %d @ %d\n",
  342. gem_request->seqno,
  343. (int) (jiffies - gem_request->emitted_jiffies));
  344. }
  345. count++;
  346. }
  347. if (!list_empty(&dev_priv->ring[VCS].request_list)) {
  348. seq_printf(m, "BSD requests:\n");
  349. list_for_each_entry(gem_request,
  350. &dev_priv->ring[VCS].request_list,
  351. list) {
  352. seq_printf(m, " %d @ %d\n",
  353. gem_request->seqno,
  354. (int) (jiffies - gem_request->emitted_jiffies));
  355. }
  356. count++;
  357. }
  358. if (!list_empty(&dev_priv->ring[BCS].request_list)) {
  359. seq_printf(m, "BLT requests:\n");
  360. list_for_each_entry(gem_request,
  361. &dev_priv->ring[BCS].request_list,
  362. list) {
  363. seq_printf(m, " %d @ %d\n",
  364. gem_request->seqno,
  365. (int) (jiffies - gem_request->emitted_jiffies));
  366. }
  367. count++;
  368. }
  369. mutex_unlock(&dev->struct_mutex);
  370. if (count == 0)
  371. seq_printf(m, "No requests\n");
  372. return 0;
  373. }
  374. static void i915_ring_seqno_info(struct seq_file *m,
  375. struct intel_ring_buffer *ring)
  376. {
  377. if (ring->get_seqno) {
  378. seq_printf(m, "Current sequence (%s): %d\n",
  379. ring->name, ring->get_seqno(ring));
  380. seq_printf(m, "Waiter sequence (%s): %d\n",
  381. ring->name, ring->waiting_seqno);
  382. seq_printf(m, "IRQ sequence (%s): %d\n",
  383. ring->name, ring->irq_seqno);
  384. }
  385. }
  386. static int i915_gem_seqno_info(struct seq_file *m, void *data)
  387. {
  388. struct drm_info_node *node = (struct drm_info_node *) m->private;
  389. struct drm_device *dev = node->minor->dev;
  390. drm_i915_private_t *dev_priv = dev->dev_private;
  391. int ret, i;
  392. ret = mutex_lock_interruptible(&dev->struct_mutex);
  393. if (ret)
  394. return ret;
  395. for (i = 0; i < I915_NUM_RINGS; i++)
  396. i915_ring_seqno_info(m, &dev_priv->ring[i]);
  397. mutex_unlock(&dev->struct_mutex);
  398. return 0;
  399. }
  400. static int i915_interrupt_info(struct seq_file *m, void *data)
  401. {
  402. struct drm_info_node *node = (struct drm_info_node *) m->private;
  403. struct drm_device *dev = node->minor->dev;
  404. drm_i915_private_t *dev_priv = dev->dev_private;
  405. int ret, i, pipe;
  406. ret = mutex_lock_interruptible(&dev->struct_mutex);
  407. if (ret)
  408. return ret;
  409. if (!HAS_PCH_SPLIT(dev)) {
  410. seq_printf(m, "Interrupt enable: %08x\n",
  411. I915_READ(IER));
  412. seq_printf(m, "Interrupt identity: %08x\n",
  413. I915_READ(IIR));
  414. seq_printf(m, "Interrupt mask: %08x\n",
  415. I915_READ(IMR));
  416. for_each_pipe(pipe)
  417. seq_printf(m, "Pipe %c stat: %08x\n",
  418. pipe_name(pipe),
  419. I915_READ(PIPESTAT(pipe)));
  420. } else {
  421. seq_printf(m, "North Display Interrupt enable: %08x\n",
  422. I915_READ(DEIER));
  423. seq_printf(m, "North Display Interrupt identity: %08x\n",
  424. I915_READ(DEIIR));
  425. seq_printf(m, "North Display Interrupt mask: %08x\n",
  426. I915_READ(DEIMR));
  427. seq_printf(m, "South Display Interrupt enable: %08x\n",
  428. I915_READ(SDEIER));
  429. seq_printf(m, "South Display Interrupt identity: %08x\n",
  430. I915_READ(SDEIIR));
  431. seq_printf(m, "South Display Interrupt mask: %08x\n",
  432. I915_READ(SDEIMR));
  433. seq_printf(m, "Graphics Interrupt enable: %08x\n",
  434. I915_READ(GTIER));
  435. seq_printf(m, "Graphics Interrupt identity: %08x\n",
  436. I915_READ(GTIIR));
  437. seq_printf(m, "Graphics Interrupt mask: %08x\n",
  438. I915_READ(GTIMR));
  439. }
  440. seq_printf(m, "Interrupts received: %d\n",
  441. atomic_read(&dev_priv->irq_received));
  442. for (i = 0; i < I915_NUM_RINGS; i++) {
  443. if (IS_GEN6(dev)) {
  444. seq_printf(m, "Graphics Interrupt mask (%s): %08x\n",
  445. dev_priv->ring[i].name,
  446. I915_READ_IMR(&dev_priv->ring[i]));
  447. }
  448. i915_ring_seqno_info(m, &dev_priv->ring[i]);
  449. }
  450. mutex_unlock(&dev->struct_mutex);
  451. return 0;
  452. }
  453. static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
  454. {
  455. struct drm_info_node *node = (struct drm_info_node *) m->private;
  456. struct drm_device *dev = node->minor->dev;
  457. drm_i915_private_t *dev_priv = dev->dev_private;
  458. int i, ret;
  459. ret = mutex_lock_interruptible(&dev->struct_mutex);
  460. if (ret)
  461. return ret;
  462. seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
  463. seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
  464. for (i = 0; i < dev_priv->num_fence_regs; i++) {
  465. struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
  466. seq_printf(m, "Fenced object[%2d] = ", i);
  467. if (obj == NULL)
  468. seq_printf(m, "unused");
  469. else
  470. describe_obj(m, obj);
  471. seq_printf(m, "\n");
  472. }
  473. mutex_unlock(&dev->struct_mutex);
  474. return 0;
  475. }
  476. static int i915_hws_info(struct seq_file *m, void *data)
  477. {
  478. struct drm_info_node *node = (struct drm_info_node *) m->private;
  479. struct drm_device *dev = node->minor->dev;
  480. drm_i915_private_t *dev_priv = dev->dev_private;
  481. struct intel_ring_buffer *ring;
  482. const volatile u32 __iomem *hws;
  483. int i;
  484. ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
  485. hws = (volatile u32 __iomem *)ring->status_page.page_addr;
  486. if (hws == NULL)
  487. return 0;
  488. for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
  489. seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
  490. i * 4,
  491. hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
  492. }
  493. return 0;
  494. }
  495. static void i915_dump_object(struct seq_file *m,
  496. struct io_mapping *mapping,
  497. struct drm_i915_gem_object *obj)
  498. {
  499. int page, page_count, i;
  500. page_count = obj->base.size / PAGE_SIZE;
  501. for (page = 0; page < page_count; page++) {
  502. u32 *mem = io_mapping_map_wc(mapping,
  503. obj->gtt_offset + page * PAGE_SIZE);
  504. for (i = 0; i < PAGE_SIZE; i += 4)
  505. seq_printf(m, "%08x : %08x\n", i, mem[i / 4]);
  506. io_mapping_unmap(mem);
  507. }
  508. }
  509. static int i915_batchbuffer_info(struct seq_file *m, void *data)
  510. {
  511. struct drm_info_node *node = (struct drm_info_node *) m->private;
  512. struct drm_device *dev = node->minor->dev;
  513. drm_i915_private_t *dev_priv = dev->dev_private;
  514. struct drm_i915_gem_object *obj;
  515. int ret;
  516. ret = mutex_lock_interruptible(&dev->struct_mutex);
  517. if (ret)
  518. return ret;
  519. list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) {
  520. if (obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) {
  521. seq_printf(m, "--- gtt_offset = 0x%08x\n", obj->gtt_offset);
  522. i915_dump_object(m, dev_priv->mm.gtt_mapping, obj);
  523. }
  524. }
  525. mutex_unlock(&dev->struct_mutex);
  526. return 0;
  527. }
  528. static int i915_ringbuffer_data(struct seq_file *m, void *data)
  529. {
  530. struct drm_info_node *node = (struct drm_info_node *) m->private;
  531. struct drm_device *dev = node->minor->dev;
  532. drm_i915_private_t *dev_priv = dev->dev_private;
  533. struct intel_ring_buffer *ring;
  534. int ret;
  535. ret = mutex_lock_interruptible(&dev->struct_mutex);
  536. if (ret)
  537. return ret;
  538. ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
  539. if (!ring->obj) {
  540. seq_printf(m, "No ringbuffer setup\n");
  541. } else {
  542. const u8 __iomem *virt = ring->virtual_start;
  543. uint32_t off;
  544. for (off = 0; off < ring->size; off += 4) {
  545. uint32_t *ptr = (uint32_t *)(virt + off);
  546. seq_printf(m, "%08x : %08x\n", off, *ptr);
  547. }
  548. }
  549. mutex_unlock(&dev->struct_mutex);
  550. return 0;
  551. }
  552. static int i915_ringbuffer_info(struct seq_file *m, void *data)
  553. {
  554. struct drm_info_node *node = (struct drm_info_node *) m->private;
  555. struct drm_device *dev = node->minor->dev;
  556. drm_i915_private_t *dev_priv = dev->dev_private;
  557. struct intel_ring_buffer *ring;
  558. ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
  559. if (ring->size == 0)
  560. return 0;
  561. seq_printf(m, "Ring %s:\n", ring->name);
  562. seq_printf(m, " Head : %08x\n", I915_READ_HEAD(ring) & HEAD_ADDR);
  563. seq_printf(m, " Tail : %08x\n", I915_READ_TAIL(ring) & TAIL_ADDR);
  564. seq_printf(m, " Size : %08x\n", ring->size);
  565. seq_printf(m, " Active : %08x\n", intel_ring_get_active_head(ring));
  566. seq_printf(m, " NOPID : %08x\n", I915_READ_NOPID(ring));
  567. if (IS_GEN6(dev)) {
  568. seq_printf(m, " Sync 0 : %08x\n", I915_READ_SYNC_0(ring));
  569. seq_printf(m, " Sync 1 : %08x\n", I915_READ_SYNC_1(ring));
  570. }
  571. seq_printf(m, " Control : %08x\n", I915_READ_CTL(ring));
  572. seq_printf(m, " Start : %08x\n", I915_READ_START(ring));
  573. return 0;
  574. }
  575. static const char *ring_str(int ring)
  576. {
  577. switch (ring) {
  578. case RING_RENDER: return " render";
  579. case RING_BSD: return " bsd";
  580. case RING_BLT: return " blt";
  581. default: return "";
  582. }
  583. }
  584. static const char *pin_flag(int pinned)
  585. {
  586. if (pinned > 0)
  587. return " P";
  588. else if (pinned < 0)
  589. return " p";
  590. else
  591. return "";
  592. }
  593. static const char *tiling_flag(int tiling)
  594. {
  595. switch (tiling) {
  596. default:
  597. case I915_TILING_NONE: return "";
  598. case I915_TILING_X: return " X";
  599. case I915_TILING_Y: return " Y";
  600. }
  601. }
  602. static const char *dirty_flag(int dirty)
  603. {
  604. return dirty ? " dirty" : "";
  605. }
  606. static const char *purgeable_flag(int purgeable)
  607. {
  608. return purgeable ? " purgeable" : "";
  609. }
  610. static void print_error_buffers(struct seq_file *m,
  611. const char *name,
  612. struct drm_i915_error_buffer *err,
  613. int count)
  614. {
  615. seq_printf(m, "%s [%d]:\n", name, count);
  616. while (count--) {
  617. seq_printf(m, " %08x %8u %04x %04x %08x%s%s%s%s%s%s",
  618. err->gtt_offset,
  619. err->size,
  620. err->read_domains,
  621. err->write_domain,
  622. err->seqno,
  623. pin_flag(err->pinned),
  624. tiling_flag(err->tiling),
  625. dirty_flag(err->dirty),
  626. purgeable_flag(err->purgeable),
  627. ring_str(err->ring),
  628. agp_type_str(err->agp_type));
  629. if (err->name)
  630. seq_printf(m, " (name: %d)", err->name);
  631. if (err->fence_reg != I915_FENCE_REG_NONE)
  632. seq_printf(m, " (fence: %d)", err->fence_reg);
  633. seq_printf(m, "\n");
  634. err++;
  635. }
  636. }
  637. static int i915_error_state(struct seq_file *m, void *unused)
  638. {
  639. struct drm_info_node *node = (struct drm_info_node *) m->private;
  640. struct drm_device *dev = node->minor->dev;
  641. drm_i915_private_t *dev_priv = dev->dev_private;
  642. struct drm_i915_error_state *error;
  643. unsigned long flags;
  644. int i, page, offset, elt;
  645. spin_lock_irqsave(&dev_priv->error_lock, flags);
  646. if (!dev_priv->first_error) {
  647. seq_printf(m, "no error state collected\n");
  648. goto out;
  649. }
  650. error = dev_priv->first_error;
  651. seq_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec,
  652. error->time.tv_usec);
  653. seq_printf(m, "PCI ID: 0x%04x\n", dev->pci_device);
  654. seq_printf(m, "EIR: 0x%08x\n", error->eir);
  655. seq_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er);
  656. if (INTEL_INFO(dev)->gen >= 6) {
  657. seq_printf(m, "ERROR: 0x%08x\n", error->error);
  658. seq_printf(m, "Blitter command stream:\n");
  659. seq_printf(m, " ACTHD: 0x%08x\n", error->bcs_acthd);
  660. seq_printf(m, " IPEIR: 0x%08x\n", error->bcs_ipeir);
  661. seq_printf(m, " IPEHR: 0x%08x\n", error->bcs_ipehr);
  662. seq_printf(m, " INSTDONE: 0x%08x\n", error->bcs_instdone);
  663. seq_printf(m, " seqno: 0x%08x\n", error->bcs_seqno);
  664. seq_printf(m, "Video (BSD) command stream:\n");
  665. seq_printf(m, " ACTHD: 0x%08x\n", error->vcs_acthd);
  666. seq_printf(m, " IPEIR: 0x%08x\n", error->vcs_ipeir);
  667. seq_printf(m, " IPEHR: 0x%08x\n", error->vcs_ipehr);
  668. seq_printf(m, " INSTDONE: 0x%08x\n", error->vcs_instdone);
  669. seq_printf(m, " seqno: 0x%08x\n", error->vcs_seqno);
  670. }
  671. seq_printf(m, "Render command stream:\n");
  672. seq_printf(m, " ACTHD: 0x%08x\n", error->acthd);
  673. seq_printf(m, " IPEIR: 0x%08x\n", error->ipeir);
  674. seq_printf(m, " IPEHR: 0x%08x\n", error->ipehr);
  675. seq_printf(m, " INSTDONE: 0x%08x\n", error->instdone);
  676. if (INTEL_INFO(dev)->gen >= 4) {
  677. seq_printf(m, " INSTDONE1: 0x%08x\n", error->instdone1);
  678. seq_printf(m, " INSTPS: 0x%08x\n", error->instps);
  679. }
  680. seq_printf(m, " INSTPM: 0x%08x\n", error->instpm);
  681. seq_printf(m, " seqno: 0x%08x\n", error->seqno);
  682. for (i = 0; i < 16; i++)
  683. seq_printf(m, " fence[%d] = %08llx\n", i, error->fence[i]);
  684. if (error->active_bo)
  685. print_error_buffers(m, "Active",
  686. error->active_bo,
  687. error->active_bo_count);
  688. if (error->pinned_bo)
  689. print_error_buffers(m, "Pinned",
  690. error->pinned_bo,
  691. error->pinned_bo_count);
  692. for (i = 0; i < ARRAY_SIZE(error->batchbuffer); i++) {
  693. if (error->batchbuffer[i]) {
  694. struct drm_i915_error_object *obj = error->batchbuffer[i];
  695. seq_printf(m, "%s --- gtt_offset = 0x%08x\n",
  696. dev_priv->ring[i].name,
  697. obj->gtt_offset);
  698. offset = 0;
  699. for (page = 0; page < obj->page_count; page++) {
  700. for (elt = 0; elt < PAGE_SIZE/4; elt++) {
  701. seq_printf(m, "%08x : %08x\n", offset, obj->pages[page][elt]);
  702. offset += 4;
  703. }
  704. }
  705. }
  706. }
  707. for (i = 0; i < ARRAY_SIZE(error->ringbuffer); i++) {
  708. if (error->ringbuffer[i]) {
  709. struct drm_i915_error_object *obj = error->ringbuffer[i];
  710. seq_printf(m, "%s --- ringbuffer = 0x%08x\n",
  711. dev_priv->ring[i].name,
  712. obj->gtt_offset);
  713. offset = 0;
  714. for (page = 0; page < obj->page_count; page++) {
  715. for (elt = 0; elt < PAGE_SIZE/4; elt++) {
  716. seq_printf(m, "%08x : %08x\n",
  717. offset,
  718. obj->pages[page][elt]);
  719. offset += 4;
  720. }
  721. }
  722. }
  723. }
  724. if (error->overlay)
  725. intel_overlay_print_error_state(m, error->overlay);
  726. if (error->display)
  727. intel_display_print_error_state(m, dev, error->display);
  728. out:
  729. spin_unlock_irqrestore(&dev_priv->error_lock, flags);
  730. return 0;
  731. }
  732. static int i915_rstdby_delays(struct seq_file *m, void *unused)
  733. {
  734. struct drm_info_node *node = (struct drm_info_node *) m->private;
  735. struct drm_device *dev = node->minor->dev;
  736. drm_i915_private_t *dev_priv = dev->dev_private;
  737. u16 crstanddelay = I915_READ16(CRSTANDVID);
  738. seq_printf(m, "w/ctx: %d, w/o ctx: %d\n", (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f));
  739. return 0;
  740. }
  741. static int i915_cur_delayinfo(struct seq_file *m, void *unused)
  742. {
  743. struct drm_info_node *node = (struct drm_info_node *) m->private;
  744. struct drm_device *dev = node->minor->dev;
  745. drm_i915_private_t *dev_priv = dev->dev_private;
  746. if (IS_GEN5(dev)) {
  747. u16 rgvswctl = I915_READ16(MEMSWCTL);
  748. u16 rgvstat = I915_READ16(MEMSTAT_ILK);
  749. seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
  750. seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
  751. seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
  752. MEMSTAT_VID_SHIFT);
  753. seq_printf(m, "Current P-state: %d\n",
  754. (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
  755. } else if (IS_GEN6(dev)) {
  756. u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
  757. u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
  758. u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
  759. u32 rpstat;
  760. u32 rpupei, rpcurup, rpprevup;
  761. u32 rpdownei, rpcurdown, rpprevdown;
  762. int max_freq;
  763. /* RPSTAT1 is in the GT power well */
  764. __gen6_gt_force_wake_get(dev_priv);
  765. rpstat = I915_READ(GEN6_RPSTAT1);
  766. rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
  767. rpcurup = I915_READ(GEN6_RP_CUR_UP);
  768. rpprevup = I915_READ(GEN6_RP_PREV_UP);
  769. rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
  770. rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
  771. rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
  772. seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
  773. seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
  774. seq_printf(m, "Render p-state ratio: %d\n",
  775. (gt_perf_status & 0xff00) >> 8);
  776. seq_printf(m, "Render p-state VID: %d\n",
  777. gt_perf_status & 0xff);
  778. seq_printf(m, "Render p-state limit: %d\n",
  779. rp_state_limits & 0xff);
  780. seq_printf(m, "CAGF: %dMHz\n", ((rpstat & GEN6_CAGF_MASK) >>
  781. GEN6_CAGF_SHIFT) * 50);
  782. seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
  783. GEN6_CURICONT_MASK);
  784. seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
  785. GEN6_CURBSYTAVG_MASK);
  786. seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
  787. GEN6_CURBSYTAVG_MASK);
  788. seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
  789. GEN6_CURIAVG_MASK);
  790. seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
  791. GEN6_CURBSYTAVG_MASK);
  792. seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
  793. GEN6_CURBSYTAVG_MASK);
  794. max_freq = (rp_state_cap & 0xff0000) >> 16;
  795. seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
  796. max_freq * 50);
  797. max_freq = (rp_state_cap & 0xff00) >> 8;
  798. seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
  799. max_freq * 50);
  800. max_freq = rp_state_cap & 0xff;
  801. seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
  802. max_freq * 50);
  803. __gen6_gt_force_wake_put(dev_priv);
  804. } else {
  805. seq_printf(m, "no P-state info available\n");
  806. }
  807. return 0;
  808. }
  809. static int i915_delayfreq_table(struct seq_file *m, void *unused)
  810. {
  811. struct drm_info_node *node = (struct drm_info_node *) m->private;
  812. struct drm_device *dev = node->minor->dev;
  813. drm_i915_private_t *dev_priv = dev->dev_private;
  814. u32 delayfreq;
  815. int i;
  816. for (i = 0; i < 16; i++) {
  817. delayfreq = I915_READ(PXVFREQ_BASE + i * 4);
  818. seq_printf(m, "P%02dVIDFREQ: 0x%08x (VID: %d)\n", i, delayfreq,
  819. (delayfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT);
  820. }
  821. return 0;
  822. }
  823. static inline int MAP_TO_MV(int map)
  824. {
  825. return 1250 - (map * 25);
  826. }
  827. static int i915_inttoext_table(struct seq_file *m, void *unused)
  828. {
  829. struct drm_info_node *node = (struct drm_info_node *) m->private;
  830. struct drm_device *dev = node->minor->dev;
  831. drm_i915_private_t *dev_priv = dev->dev_private;
  832. u32 inttoext;
  833. int i;
  834. for (i = 1; i <= 32; i++) {
  835. inttoext = I915_READ(INTTOEXT_BASE_ILK + i * 4);
  836. seq_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext);
  837. }
  838. return 0;
  839. }
  840. static int i915_drpc_info(struct seq_file *m, void *unused)
  841. {
  842. struct drm_info_node *node = (struct drm_info_node *) m->private;
  843. struct drm_device *dev = node->minor->dev;
  844. drm_i915_private_t *dev_priv = dev->dev_private;
  845. u32 rgvmodectl = I915_READ(MEMMODECTL);
  846. u32 rstdbyctl = I915_READ(RSTDBYCTL);
  847. u16 crstandvid = I915_READ16(CRSTANDVID);
  848. seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
  849. "yes" : "no");
  850. seq_printf(m, "Boost freq: %d\n",
  851. (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
  852. MEMMODE_BOOST_FREQ_SHIFT);
  853. seq_printf(m, "HW control enabled: %s\n",
  854. rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
  855. seq_printf(m, "SW control enabled: %s\n",
  856. rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
  857. seq_printf(m, "Gated voltage change: %s\n",
  858. rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
  859. seq_printf(m, "Starting frequency: P%d\n",
  860. (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
  861. seq_printf(m, "Max P-state: P%d\n",
  862. (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
  863. seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
  864. seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
  865. seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
  866. seq_printf(m, "Render standby enabled: %s\n",
  867. (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");
  868. seq_printf(m, "Current RS state: ");
  869. switch (rstdbyctl & RSX_STATUS_MASK) {
  870. case RSX_STATUS_ON:
  871. seq_printf(m, "on\n");
  872. break;
  873. case RSX_STATUS_RC1:
  874. seq_printf(m, "RC1\n");
  875. break;
  876. case RSX_STATUS_RC1E:
  877. seq_printf(m, "RC1E\n");
  878. break;
  879. case RSX_STATUS_RS1:
  880. seq_printf(m, "RS1\n");
  881. break;
  882. case RSX_STATUS_RS2:
  883. seq_printf(m, "RS2 (RC6)\n");
  884. break;
  885. case RSX_STATUS_RS3:
  886. seq_printf(m, "RC3 (RC6+)\n");
  887. break;
  888. default:
  889. seq_printf(m, "unknown\n");
  890. break;
  891. }
  892. return 0;
  893. }
  894. static int i915_fbc_status(struct seq_file *m, void *unused)
  895. {
  896. struct drm_info_node *node = (struct drm_info_node *) m->private;
  897. struct drm_device *dev = node->minor->dev;
  898. drm_i915_private_t *dev_priv = dev->dev_private;
  899. if (!I915_HAS_FBC(dev)) {
  900. seq_printf(m, "FBC unsupported on this chipset\n");
  901. return 0;
  902. }
  903. if (intel_fbc_enabled(dev)) {
  904. seq_printf(m, "FBC enabled\n");
  905. } else {
  906. seq_printf(m, "FBC disabled: ");
  907. switch (dev_priv->no_fbc_reason) {
  908. case FBC_NO_OUTPUT:
  909. seq_printf(m, "no outputs");
  910. break;
  911. case FBC_STOLEN_TOO_SMALL:
  912. seq_printf(m, "not enough stolen memory");
  913. break;
  914. case FBC_UNSUPPORTED_MODE:
  915. seq_printf(m, "mode not supported");
  916. break;
  917. case FBC_MODE_TOO_LARGE:
  918. seq_printf(m, "mode too large");
  919. break;
  920. case FBC_BAD_PLANE:
  921. seq_printf(m, "FBC unsupported on plane");
  922. break;
  923. case FBC_NOT_TILED:
  924. seq_printf(m, "scanout buffer not tiled");
  925. break;
  926. case FBC_MULTIPLE_PIPES:
  927. seq_printf(m, "multiple pipes are enabled");
  928. break;
  929. default:
  930. seq_printf(m, "unknown reason");
  931. }
  932. seq_printf(m, "\n");
  933. }
  934. return 0;
  935. }
  936. static int i915_sr_status(struct seq_file *m, void *unused)
  937. {
  938. struct drm_info_node *node = (struct drm_info_node *) m->private;
  939. struct drm_device *dev = node->minor->dev;
  940. drm_i915_private_t *dev_priv = dev->dev_private;
  941. bool sr_enabled = false;
  942. if (HAS_PCH_SPLIT(dev))
  943. sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
  944. else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
  945. sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
  946. else if (IS_I915GM(dev))
  947. sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
  948. else if (IS_PINEVIEW(dev))
  949. sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
  950. seq_printf(m, "self-refresh: %s\n",
  951. sr_enabled ? "enabled" : "disabled");
  952. return 0;
  953. }
  954. static int i915_emon_status(struct seq_file *m, void *unused)
  955. {
  956. struct drm_info_node *node = (struct drm_info_node *) m->private;
  957. struct drm_device *dev = node->minor->dev;
  958. drm_i915_private_t *dev_priv = dev->dev_private;
  959. unsigned long temp, chipset, gfx;
  960. int ret;
  961. ret = mutex_lock_interruptible(&dev->struct_mutex);
  962. if (ret)
  963. return ret;
  964. temp = i915_mch_val(dev_priv);
  965. chipset = i915_chipset_val(dev_priv);
  966. gfx = i915_gfx_val(dev_priv);
  967. mutex_unlock(&dev->struct_mutex);
  968. seq_printf(m, "GMCH temp: %ld\n", temp);
  969. seq_printf(m, "Chipset power: %ld\n", chipset);
  970. seq_printf(m, "GFX power: %ld\n", gfx);
  971. seq_printf(m, "Total power: %ld\n", chipset + gfx);
  972. return 0;
  973. }
  974. static int i915_gfxec(struct seq_file *m, void *unused)
  975. {
  976. struct drm_info_node *node = (struct drm_info_node *) m->private;
  977. struct drm_device *dev = node->minor->dev;
  978. drm_i915_private_t *dev_priv = dev->dev_private;
  979. seq_printf(m, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4));
  980. return 0;
  981. }
  982. static int i915_opregion(struct seq_file *m, void *unused)
  983. {
  984. struct drm_info_node *node = (struct drm_info_node *) m->private;
  985. struct drm_device *dev = node->minor->dev;
  986. drm_i915_private_t *dev_priv = dev->dev_private;
  987. struct intel_opregion *opregion = &dev_priv->opregion;
  988. int ret;
  989. ret = mutex_lock_interruptible(&dev->struct_mutex);
  990. if (ret)
  991. return ret;
  992. if (opregion->header)
  993. seq_write(m, opregion->header, OPREGION_SIZE);
  994. mutex_unlock(&dev->struct_mutex);
  995. return 0;
  996. }
  997. static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
  998. {
  999. struct drm_info_node *node = (struct drm_info_node *) m->private;
  1000. struct drm_device *dev = node->minor->dev;
  1001. drm_i915_private_t *dev_priv = dev->dev_private;
  1002. struct intel_fbdev *ifbdev;
  1003. struct intel_framebuffer *fb;
  1004. int ret;
  1005. ret = mutex_lock_interruptible(&dev->mode_config.mutex);
  1006. if (ret)
  1007. return ret;
  1008. ifbdev = dev_priv->fbdev;
  1009. fb = to_intel_framebuffer(ifbdev->helper.fb);
  1010. seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, obj ",
  1011. fb->base.width,
  1012. fb->base.height,
  1013. fb->base.depth,
  1014. fb->base.bits_per_pixel);
  1015. describe_obj(m, fb->obj);
  1016. seq_printf(m, "\n");
  1017. list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) {
  1018. if (&fb->base == ifbdev->helper.fb)
  1019. continue;
  1020. seq_printf(m, "user size: %d x %d, depth %d, %d bpp, obj ",
  1021. fb->base.width,
  1022. fb->base.height,
  1023. fb->base.depth,
  1024. fb->base.bits_per_pixel);
  1025. describe_obj(m, fb->obj);
  1026. seq_printf(m, "\n");
  1027. }
  1028. mutex_unlock(&dev->mode_config.mutex);
  1029. return 0;
  1030. }
  1031. static int i915_context_status(struct seq_file *m, void *unused)
  1032. {
  1033. struct drm_info_node *node = (struct drm_info_node *) m->private;
  1034. struct drm_device *dev = node->minor->dev;
  1035. drm_i915_private_t *dev_priv = dev->dev_private;
  1036. int ret;
  1037. ret = mutex_lock_interruptible(&dev->mode_config.mutex);
  1038. if (ret)
  1039. return ret;
  1040. seq_printf(m, "power context ");
  1041. describe_obj(m, dev_priv->pwrctx);
  1042. seq_printf(m, "\n");
  1043. seq_printf(m, "render context ");
  1044. describe_obj(m, dev_priv->renderctx);
  1045. seq_printf(m, "\n");
  1046. mutex_unlock(&dev->mode_config.mutex);
  1047. return 0;
  1048. }
  1049. static int
  1050. i915_wedged_open(struct inode *inode,
  1051. struct file *filp)
  1052. {
  1053. filp->private_data = inode->i_private;
  1054. return 0;
  1055. }
  1056. static ssize_t
  1057. i915_wedged_read(struct file *filp,
  1058. char __user *ubuf,
  1059. size_t max,
  1060. loff_t *ppos)
  1061. {
  1062. struct drm_device *dev = filp->private_data;
  1063. drm_i915_private_t *dev_priv = dev->dev_private;
  1064. char buf[80];
  1065. int len;
  1066. len = snprintf(buf, sizeof (buf),
  1067. "wedged : %d\n",
  1068. atomic_read(&dev_priv->mm.wedged));
  1069. if (len > sizeof (buf))
  1070. len = sizeof (buf);
  1071. return simple_read_from_buffer(ubuf, max, ppos, buf, len);
  1072. }
  1073. static ssize_t
  1074. i915_wedged_write(struct file *filp,
  1075. const char __user *ubuf,
  1076. size_t cnt,
  1077. loff_t *ppos)
  1078. {
  1079. struct drm_device *dev = filp->private_data;
  1080. char buf[20];
  1081. int val = 1;
  1082. if (cnt > 0) {
  1083. if (cnt > sizeof (buf) - 1)
  1084. return -EINVAL;
  1085. if (copy_from_user(buf, ubuf, cnt))
  1086. return -EFAULT;
  1087. buf[cnt] = 0;
  1088. val = simple_strtoul(buf, NULL, 0);
  1089. }
  1090. DRM_INFO("Manually setting wedged to %d\n", val);
  1091. i915_handle_error(dev, val);
  1092. return cnt;
  1093. }
  1094. static const struct file_operations i915_wedged_fops = {
  1095. .owner = THIS_MODULE,
  1096. .open = i915_wedged_open,
  1097. .read = i915_wedged_read,
  1098. .write = i915_wedged_write,
  1099. .llseek = default_llseek,
  1100. };
  1101. /* As the drm_debugfs_init() routines are called before dev->dev_private is
  1102. * allocated we need to hook into the minor for release. */
  1103. static int
  1104. drm_add_fake_info_node(struct drm_minor *minor,
  1105. struct dentry *ent,
  1106. const void *key)
  1107. {
  1108. struct drm_info_node *node;
  1109. node = kmalloc(sizeof(struct drm_info_node), GFP_KERNEL);
  1110. if (node == NULL) {
  1111. debugfs_remove(ent);
  1112. return -ENOMEM;
  1113. }
  1114. node->minor = minor;
  1115. node->dent = ent;
  1116. node->info_ent = (void *) key;
  1117. list_add(&node->list, &minor->debugfs_nodes.list);
  1118. return 0;
  1119. }
  1120. static int i915_wedged_create(struct dentry *root, struct drm_minor *minor)
  1121. {
  1122. struct drm_device *dev = minor->dev;
  1123. struct dentry *ent;
  1124. ent = debugfs_create_file("i915_wedged",
  1125. S_IRUGO | S_IWUSR,
  1126. root, dev,
  1127. &i915_wedged_fops);
  1128. if (IS_ERR(ent))
  1129. return PTR_ERR(ent);
  1130. return drm_add_fake_info_node(minor, ent, &i915_wedged_fops);
  1131. }
  1132. static struct drm_info_list i915_debugfs_list[] = {
  1133. {"i915_capabilities", i915_capabilities, 0},
  1134. {"i915_gem_objects", i915_gem_object_info, 0},
  1135. {"i915_gem_gtt", i915_gem_gtt_info, 0},
  1136. {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
  1137. {"i915_gem_flushing", i915_gem_object_list_info, 0, (void *) FLUSHING_LIST},
  1138. {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
  1139. {"i915_gem_pinned", i915_gem_object_list_info, 0, (void *) PINNED_LIST},
  1140. {"i915_gem_deferred_free", i915_gem_object_list_info, 0, (void *) DEFERRED_FREE_LIST},
  1141. {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
  1142. {"i915_gem_request", i915_gem_request_info, 0},
  1143. {"i915_gem_seqno", i915_gem_seqno_info, 0},
  1144. {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
  1145. {"i915_gem_interrupt", i915_interrupt_info, 0},
  1146. {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
  1147. {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
  1148. {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
  1149. {"i915_ringbuffer_data", i915_ringbuffer_data, 0, (void *)RCS},
  1150. {"i915_ringbuffer_info", i915_ringbuffer_info, 0, (void *)RCS},
  1151. {"i915_bsd_ringbuffer_data", i915_ringbuffer_data, 0, (void *)VCS},
  1152. {"i915_bsd_ringbuffer_info", i915_ringbuffer_info, 0, (void *)VCS},
  1153. {"i915_blt_ringbuffer_data", i915_ringbuffer_data, 0, (void *)BCS},
  1154. {"i915_blt_ringbuffer_info", i915_ringbuffer_info, 0, (void *)BCS},
  1155. {"i915_batchbuffers", i915_batchbuffer_info, 0},
  1156. {"i915_error_state", i915_error_state, 0},
  1157. {"i915_rstdby_delays", i915_rstdby_delays, 0},
  1158. {"i915_cur_delayinfo", i915_cur_delayinfo, 0},
  1159. {"i915_delayfreq_table", i915_delayfreq_table, 0},
  1160. {"i915_inttoext_table", i915_inttoext_table, 0},
  1161. {"i915_drpc_info", i915_drpc_info, 0},
  1162. {"i915_emon_status", i915_emon_status, 0},
  1163. {"i915_gfxec", i915_gfxec, 0},
  1164. {"i915_fbc_status", i915_fbc_status, 0},
  1165. {"i915_sr_status", i915_sr_status, 0},
  1166. {"i915_opregion", i915_opregion, 0},
  1167. {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
  1168. {"i915_context_status", i915_context_status, 0},
  1169. };
  1170. #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
  1171. int i915_debugfs_init(struct drm_minor *minor)
  1172. {
  1173. int ret;
  1174. ret = i915_wedged_create(minor->debugfs_root, minor);
  1175. if (ret)
  1176. return ret;
  1177. return drm_debugfs_create_files(i915_debugfs_list,
  1178. I915_DEBUGFS_ENTRIES,
  1179. minor->debugfs_root, minor);
  1180. }
  1181. void i915_debugfs_cleanup(struct drm_minor *minor)
  1182. {
  1183. drm_debugfs_remove_files(i915_debugfs_list,
  1184. I915_DEBUGFS_ENTRIES, minor);
  1185. drm_debugfs_remove_files((struct drm_info_list *) &i915_wedged_fops,
  1186. 1, minor);
  1187. }
  1188. #endif /* CONFIG_DEBUG_FS */