at91sam9n12.dtsi 11 KB

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  1. /*
  2. * at91sam9n12.dtsi - Device Tree include file for AT91SAM9N12 SoC
  3. *
  4. * Copyright (C) 2012 Atmel,
  5. * 2012 Hong Xu <hong.xu@atmel.com>
  6. *
  7. * Licensed under GPLv2 or later.
  8. */
  9. /include/ "skeleton.dtsi"
  10. / {
  11. model = "Atmel AT91SAM9N12 SoC";
  12. compatible = "atmel,at91sam9n12";
  13. interrupt-parent = <&aic>;
  14. aliases {
  15. serial0 = &dbgu;
  16. serial1 = &usart0;
  17. serial2 = &usart1;
  18. serial3 = &usart2;
  19. serial4 = &usart3;
  20. gpio0 = &pioA;
  21. gpio1 = &pioB;
  22. gpio2 = &pioC;
  23. gpio3 = &pioD;
  24. tcb0 = &tcb0;
  25. tcb1 = &tcb1;
  26. i2c0 = &i2c0;
  27. i2c1 = &i2c1;
  28. ssc0 = &ssc0;
  29. };
  30. cpus {
  31. #address-cells = <0>;
  32. #size-cells = <0>;
  33. cpu {
  34. compatible = "arm,arm926ej-s";
  35. device_type = "cpu";
  36. };
  37. };
  38. memory {
  39. reg = <0x20000000 0x10000000>;
  40. };
  41. ahb {
  42. compatible = "simple-bus";
  43. #address-cells = <1>;
  44. #size-cells = <1>;
  45. ranges;
  46. apb {
  47. compatible = "simple-bus";
  48. #address-cells = <1>;
  49. #size-cells = <1>;
  50. ranges;
  51. aic: interrupt-controller@fffff000 {
  52. #interrupt-cells = <3>;
  53. compatible = "atmel,at91rm9200-aic";
  54. interrupt-controller;
  55. reg = <0xfffff000 0x200>;
  56. };
  57. ramc0: ramc@ffffe800 {
  58. compatible = "atmel,at91sam9g45-ddramc";
  59. reg = <0xffffe800 0x200>;
  60. };
  61. pmc: pmc@fffffc00 {
  62. compatible = "atmel,at91rm9200-pmc";
  63. reg = <0xfffffc00 0x100>;
  64. };
  65. rstc@fffffe00 {
  66. compatible = "atmel,at91sam9g45-rstc";
  67. reg = <0xfffffe00 0x10>;
  68. };
  69. pit: timer@fffffe30 {
  70. compatible = "atmel,at91sam9260-pit";
  71. reg = <0xfffffe30 0xf>;
  72. interrupts = <1 4 7>;
  73. };
  74. shdwc@fffffe10 {
  75. compatible = "atmel,at91sam9x5-shdwc";
  76. reg = <0xfffffe10 0x10>;
  77. };
  78. mmc0: mmc@f0008000 {
  79. compatible = "atmel,hsmci";
  80. reg = <0xf0008000 0x600>;
  81. interrupts = <12 4 0>;
  82. dmas = <&dma 1 0>;
  83. dma-names = "rxtx";
  84. #address-cells = <1>;
  85. #size-cells = <0>;
  86. status = "disabled";
  87. };
  88. tcb0: timer@f8008000 {
  89. compatible = "atmel,at91sam9x5-tcb";
  90. reg = <0xf8008000 0x100>;
  91. interrupts = <17 4 0>;
  92. };
  93. tcb1: timer@f800c000 {
  94. compatible = "atmel,at91sam9x5-tcb";
  95. reg = <0xf800c000 0x100>;
  96. interrupts = <17 4 0>;
  97. };
  98. dma: dma-controller@ffffec00 {
  99. compatible = "atmel,at91sam9g45-dma";
  100. reg = <0xffffec00 0x200>;
  101. interrupts = <20 4 0>;
  102. #dma-cells = <2>;
  103. };
  104. pinctrl@fffff400 {
  105. #address-cells = <1>;
  106. #size-cells = <1>;
  107. compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
  108. ranges = <0xfffff400 0xfffff400 0x800>;
  109. atmel,mux-mask = <
  110. /* A B C */
  111. 0xffffffff 0xffe07983 0x00000000 /* pioA */
  112. 0x00040000 0x00047e0f 0x00000000 /* pioB */
  113. 0xfdffffff 0x07c00000 0xb83fffff /* pioC */
  114. 0x003fffff 0x003f8000 0x00000000 /* pioD */
  115. >;
  116. /* shared pinctrl settings */
  117. dbgu {
  118. pinctrl_dbgu: dbgu-0 {
  119. atmel,pins =
  120. <0 9 0x1 0x0 /* PA9 periph A */
  121. 0 10 0x1 0x1>; /* PA10 periph with pullup */
  122. };
  123. };
  124. usart0 {
  125. pinctrl_usart0: usart0-0 {
  126. atmel,pins =
  127. <0 1 0x1 0x1 /* PA1 periph A with pullup */
  128. 0 0 0x1 0x0>; /* PA0 periph A */
  129. };
  130. pinctrl_usart0_rts: usart0_rts-0 {
  131. atmel,pins =
  132. <0 2 0x1 0x0>; /* PA2 periph A */
  133. };
  134. pinctrl_usart0_cts: usart0_cts-0 {
  135. atmel,pins =
  136. <0 3 0x1 0x0>; /* PA3 periph A */
  137. };
  138. };
  139. usart1 {
  140. pinctrl_usart1: usart1-0 {
  141. atmel,pins =
  142. <0 6 0x1 0x1 /* PA6 periph A with pullup */
  143. 0 5 0x1 0x0>; /* PA5 periph A */
  144. };
  145. };
  146. usart2 {
  147. pinctrl_usart2: usart2-0 {
  148. atmel,pins =
  149. <0 8 0x1 0x1 /* PA8 periph A with pullup */
  150. 0 7 0x1 0x0>; /* PA7 periph A */
  151. };
  152. pinctrl_usart2_rts: usart2_rts-0 {
  153. atmel,pins =
  154. <1 0 0x2 0x0>; /* PB0 periph B */
  155. };
  156. pinctrl_usart2_cts: usart2_cts-0 {
  157. atmel,pins =
  158. <1 1 0x2 0x0>; /* PB1 periph B */
  159. };
  160. };
  161. usart3 {
  162. pinctrl_usart3: usart3-0 {
  163. atmel,pins =
  164. <2 23 0x2 0x1 /* PC23 periph B with pullup */
  165. 2 22 0x2 0x0>; /* PC22 periph B */
  166. };
  167. pinctrl_usart3_rts: usart3_rts-0 {
  168. atmel,pins =
  169. <2 24 0x2 0x0>; /* PC24 periph B */
  170. };
  171. pinctrl_usart3_cts: usart3_cts-0 {
  172. atmel,pins =
  173. <2 25 0x2 0x0>; /* PC25 periph B */
  174. };
  175. };
  176. uart0 {
  177. pinctrl_uart0: uart0-0 {
  178. atmel,pins =
  179. <2 9 0x3 0x1 /* PC9 periph C with pullup */
  180. 2 8 0x3 0x0>; /* PC8 periph C */
  181. };
  182. };
  183. uart1 {
  184. pinctrl_uart1: uart1-0 {
  185. atmel,pins =
  186. <2 16 0x3 0x1 /* PC17 periph C with pullup */
  187. 2 17 0x3 0x0>; /* PC16 periph C */
  188. };
  189. };
  190. nand {
  191. pinctrl_nand: nand-0 {
  192. atmel,pins =
  193. <3 5 0x0 0x1 /* PD5 gpio RDY pin pull_up*/
  194. 3 4 0x0 0x1>; /* PD4 gpio enable pin pull_up */
  195. };
  196. };
  197. mmc0 {
  198. pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {
  199. atmel,pins =
  200. <0 17 0x1 0x0 /* PA17 periph A */
  201. 0 16 0x1 0x1 /* PA16 periph A with pullup */
  202. 0 15 0x1 0x1>; /* PA15 periph A with pullup */
  203. };
  204. pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
  205. atmel,pins =
  206. <0 18 0x1 0x1 /* PA18 periph A with pullup */
  207. 0 19 0x1 0x1 /* PA19 periph A with pullup */
  208. 0 20 0x1 0x1>; /* PA20 periph A with pullup */
  209. };
  210. pinctrl_mmc0_slot0_dat4_7: mmc0_slot0_dat4_7-0 {
  211. atmel,pins =
  212. <0 11 0x2 0x1 /* PA11 periph B with pullup */
  213. 0 12 0x2 0x1 /* PA12 periph B with pullup */
  214. 0 13 0x2 0x1 /* PA13 periph B with pullup */
  215. 0 14 0x2 0x1>; /* PA14 periph B with pullup */
  216. };
  217. };
  218. ssc0 {
  219. pinctrl_ssc0_tx: ssc0_tx-0 {
  220. atmel,pins =
  221. <0 24 0x2 0x0 /* PA24 periph B */
  222. 0 25 0x2 0x0 /* PA25 periph B */
  223. 0 26 0x2 0x0>; /* PA26 periph B */
  224. };
  225. pinctrl_ssc0_rx: ssc0_rx-0 {
  226. atmel,pins =
  227. <0 27 0x2 0x0 /* PA27 periph B */
  228. 0 28 0x2 0x0 /* PA28 periph B */
  229. 0 29 0x2 0x0>; /* PA29 periph B */
  230. };
  231. };
  232. spi0 {
  233. pinctrl_spi0: spi0-0 {
  234. atmel,pins =
  235. <0 11 0x1 0x0 /* PA11 periph A SPI0_MISO pin */
  236. 0 12 0x1 0x0 /* PA12 periph A SPI0_MOSI pin */
  237. 0 13 0x1 0x0>; /* PA13 periph A SPI0_SPCK pin */
  238. };
  239. };
  240. spi1 {
  241. pinctrl_spi1: spi1-0 {
  242. atmel,pins =
  243. <0 21 0x2 0x0 /* PA21 periph B SPI1_MISO pin */
  244. 0 22 0x2 0x0 /* PA22 periph B SPI1_MOSI pin */
  245. 0 23 0x2 0x0>; /* PA23 periph B SPI1_SPCK pin */
  246. };
  247. };
  248. pioA: gpio@fffff400 {
  249. compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
  250. reg = <0xfffff400 0x200>;
  251. interrupts = <2 4 1>;
  252. #gpio-cells = <2>;
  253. gpio-controller;
  254. interrupt-controller;
  255. #interrupt-cells = <2>;
  256. };
  257. pioB: gpio@fffff600 {
  258. compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
  259. reg = <0xfffff600 0x200>;
  260. interrupts = <2 4 1>;
  261. #gpio-cells = <2>;
  262. gpio-controller;
  263. interrupt-controller;
  264. #interrupt-cells = <2>;
  265. };
  266. pioC: gpio@fffff800 {
  267. compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
  268. reg = <0xfffff800 0x200>;
  269. interrupts = <3 4 1>;
  270. #gpio-cells = <2>;
  271. gpio-controller;
  272. interrupt-controller;
  273. #interrupt-cells = <2>;
  274. };
  275. pioD: gpio@fffffa00 {
  276. compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
  277. reg = <0xfffffa00 0x200>;
  278. interrupts = <3 4 1>;
  279. #gpio-cells = <2>;
  280. gpio-controller;
  281. interrupt-controller;
  282. #interrupt-cells = <2>;
  283. };
  284. };
  285. dbgu: serial@fffff200 {
  286. compatible = "atmel,at91sam9260-usart";
  287. reg = <0xfffff200 0x200>;
  288. interrupts = <1 4 7>;
  289. pinctrl-names = "default";
  290. pinctrl-0 = <&pinctrl_dbgu>;
  291. status = "disabled";
  292. };
  293. ssc0: ssc@f0010000 {
  294. compatible = "atmel,at91sam9g45-ssc";
  295. reg = <0xf0010000 0x4000>;
  296. interrupts = <28 4 5>;
  297. pinctrl-names = "default";
  298. pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
  299. status = "disabled";
  300. };
  301. usart0: serial@f801c000 {
  302. compatible = "atmel,at91sam9260-usart";
  303. reg = <0xf801c000 0x4000>;
  304. interrupts = <5 4 5>;
  305. pinctrl-names = "default";
  306. pinctrl-0 = <&pinctrl_usart0>;
  307. status = "disabled";
  308. };
  309. usart1: serial@f8020000 {
  310. compatible = "atmel,at91sam9260-usart";
  311. reg = <0xf8020000 0x4000>;
  312. interrupts = <6 4 5>;
  313. pinctrl-names = "default";
  314. pinctrl-0 = <&pinctrl_usart1>;
  315. status = "disabled";
  316. };
  317. usart2: serial@f8024000 {
  318. compatible = "atmel,at91sam9260-usart";
  319. reg = <0xf8024000 0x4000>;
  320. interrupts = <7 4 5>;
  321. pinctrl-names = "default";
  322. pinctrl-0 = <&pinctrl_usart2>;
  323. status = "disabled";
  324. };
  325. usart3: serial@f8028000 {
  326. compatible = "atmel,at91sam9260-usart";
  327. reg = <0xf8028000 0x4000>;
  328. interrupts = <8 4 5>;
  329. pinctrl-names = "default";
  330. pinctrl-0 = <&pinctrl_usart3>;
  331. status = "disabled";
  332. };
  333. i2c0: i2c@f8010000 {
  334. compatible = "atmel,at91sam9x5-i2c";
  335. reg = <0xf8010000 0x100>;
  336. interrupts = <9 4 6>;
  337. dmas = <&dma 1 13>,
  338. <&dma 1 14>;
  339. dma-names = "tx", "rx";
  340. #address-cells = <1>;
  341. #size-cells = <0>;
  342. status = "disabled";
  343. };
  344. i2c1: i2c@f8014000 {
  345. compatible = "atmel,at91sam9x5-i2c";
  346. reg = <0xf8014000 0x100>;
  347. interrupts = <10 4 6>;
  348. dmas = <&dma 1 15>,
  349. <&dma 1 16>;
  350. dma-names = "tx", "rx";
  351. #address-cells = <1>;
  352. #size-cells = <0>;
  353. status = "disabled";
  354. };
  355. spi0: spi@f0000000 {
  356. #address-cells = <1>;
  357. #size-cells = <0>;
  358. compatible = "atmel,at91rm9200-spi";
  359. reg = <0xf0000000 0x100>;
  360. interrupts = <13 4 3>;
  361. pinctrl-names = "default";
  362. pinctrl-0 = <&pinctrl_spi0>;
  363. status = "disabled";
  364. };
  365. spi1: spi@f0004000 {
  366. #address-cells = <1>;
  367. #size-cells = <0>;
  368. compatible = "atmel,at91rm9200-spi";
  369. reg = <0xf0004000 0x100>;
  370. interrupts = <14 4 3>;
  371. pinctrl-names = "default";
  372. pinctrl-0 = <&pinctrl_spi1>;
  373. status = "disabled";
  374. };
  375. };
  376. nand0: nand@40000000 {
  377. compatible = "atmel,at91rm9200-nand";
  378. #address-cells = <1>;
  379. #size-cells = <1>;
  380. reg = < 0x40000000 0x10000000
  381. 0xffffe000 0x00000600
  382. 0xffffe600 0x00000200
  383. 0x00108000 0x00018000
  384. >;
  385. atmel,pmecc-lookup-table-offset = <0x0 0x8000>;
  386. atmel,nand-addr-offset = <21>;
  387. atmel,nand-cmd-offset = <22>;
  388. pinctrl-names = "default";
  389. pinctrl-0 = <&pinctrl_nand>;
  390. gpios = <&pioD 5 0
  391. &pioD 4 0
  392. 0
  393. >;
  394. status = "disabled";
  395. };
  396. usb0: ohci@00500000 {
  397. compatible = "atmel,at91rm9200-ohci", "usb-ohci";
  398. reg = <0x00500000 0x00100000>;
  399. interrupts = <22 4 2>;
  400. status = "disabled";
  401. };
  402. };
  403. i2c@0 {
  404. compatible = "i2c-gpio";
  405. gpios = <&pioA 30 0 /* sda */
  406. &pioA 31 0 /* scl */
  407. >;
  408. i2c-gpio,sda-open-drain;
  409. i2c-gpio,scl-open-drain;
  410. i2c-gpio,delay-us = <2>; /* ~100 kHz */
  411. #address-cells = <1>;
  412. #size-cells = <0>;
  413. status = "disabled";
  414. };
  415. };