at91sam9260.dtsi 14 KB

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  1. /*
  2. * at91sam9260.dtsi - Device Tree Include file for AT91SAM9260 family SoC
  3. *
  4. * Copyright (C) 2011 Atmel,
  5. * 2011 Nicolas Ferre <nicolas.ferre@atmel.com>,
  6. * 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
  7. *
  8. * Licensed under GPLv2 or later.
  9. */
  10. /include/ "skeleton.dtsi"
  11. / {
  12. model = "Atmel AT91SAM9260 family SoC";
  13. compatible = "atmel,at91sam9260";
  14. interrupt-parent = <&aic>;
  15. aliases {
  16. serial0 = &dbgu;
  17. serial1 = &usart0;
  18. serial2 = &usart1;
  19. serial3 = &usart2;
  20. serial4 = &usart3;
  21. serial5 = &uart0;
  22. serial6 = &uart1;
  23. gpio0 = &pioA;
  24. gpio1 = &pioB;
  25. gpio2 = &pioC;
  26. tcb0 = &tcb0;
  27. tcb1 = &tcb1;
  28. i2c0 = &i2c0;
  29. ssc0 = &ssc0;
  30. };
  31. cpus {
  32. #address-cells = <0>;
  33. #size-cells = <0>;
  34. cpu {
  35. compatible = "arm,arm926ej-s";
  36. device_type = "cpu";
  37. };
  38. };
  39. memory {
  40. reg = <0x20000000 0x04000000>;
  41. };
  42. ahb {
  43. compatible = "simple-bus";
  44. #address-cells = <1>;
  45. #size-cells = <1>;
  46. ranges;
  47. apb {
  48. compatible = "simple-bus";
  49. #address-cells = <1>;
  50. #size-cells = <1>;
  51. ranges;
  52. aic: interrupt-controller@fffff000 {
  53. #interrupt-cells = <3>;
  54. compatible = "atmel,at91rm9200-aic";
  55. interrupt-controller;
  56. reg = <0xfffff000 0x200>;
  57. atmel,external-irqs = <29 30 31>;
  58. };
  59. ramc0: ramc@ffffea00 {
  60. compatible = "atmel,at91sam9260-sdramc";
  61. reg = <0xffffea00 0x200>;
  62. };
  63. pmc: pmc@fffffc00 {
  64. compatible = "atmel,at91rm9200-pmc";
  65. reg = <0xfffffc00 0x100>;
  66. };
  67. rstc@fffffd00 {
  68. compatible = "atmel,at91sam9260-rstc";
  69. reg = <0xfffffd00 0x10>;
  70. };
  71. shdwc@fffffd10 {
  72. compatible = "atmel,at91sam9260-shdwc";
  73. reg = <0xfffffd10 0x10>;
  74. };
  75. pit: timer@fffffd30 {
  76. compatible = "atmel,at91sam9260-pit";
  77. reg = <0xfffffd30 0xf>;
  78. interrupts = <1 4 7>;
  79. };
  80. tcb0: timer@fffa0000 {
  81. compatible = "atmel,at91rm9200-tcb";
  82. reg = <0xfffa0000 0x100>;
  83. interrupts = <17 4 0 18 4 0 19 4 0>;
  84. };
  85. tcb1: timer@fffdc000 {
  86. compatible = "atmel,at91rm9200-tcb";
  87. reg = <0xfffdc000 0x100>;
  88. interrupts = <26 4 0 27 4 0 28 4 0>;
  89. };
  90. pinctrl@fffff400 {
  91. #address-cells = <1>;
  92. #size-cells = <1>;
  93. compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
  94. ranges = <0xfffff400 0xfffff400 0x600>;
  95. atmel,mux-mask = <
  96. /* A B */
  97. 0xffffffff 0xffc00c3b /* pioA */
  98. 0xffffffff 0x7fff3ccf /* pioB */
  99. 0xffffffff 0x007fffff /* pioC */
  100. >;
  101. /* shared pinctrl settings */
  102. dbgu {
  103. pinctrl_dbgu: dbgu-0 {
  104. atmel,pins =
  105. <1 14 0x1 0x0 /* PB14 periph A */
  106. 1 15 0x1 0x1>; /* PB15 periph with pullup */
  107. };
  108. };
  109. usart0 {
  110. pinctrl_usart0: usart0-0 {
  111. atmel,pins =
  112. <1 4 0x1 0x0 /* PB4 periph A */
  113. 1 5 0x1 0x0>; /* PB5 periph A */
  114. };
  115. pinctrl_usart0_rts: usart0_rts-0 {
  116. atmel,pins =
  117. <1 26 0x1 0x0>; /* PB26 periph A */
  118. };
  119. pinctrl_usart0_cts: usart0_cts-0 {
  120. atmel,pins =
  121. <1 27 0x1 0x0>; /* PB27 periph A */
  122. };
  123. pinctrl_usart0_dtr_dsr: usart0_dtr_dsr-0 {
  124. atmel,pins =
  125. <1 24 0x1 0x0 /* PB24 periph A */
  126. 1 22 0x1 0x0>; /* PB22 periph A */
  127. };
  128. pinctrl_usart0_dcd: usart0_dcd-0 {
  129. atmel,pins =
  130. <1 23 0x1 0x0>; /* PB23 periph A */
  131. };
  132. pinctrl_usart0_ri: usart0_ri-0 {
  133. atmel,pins =
  134. <1 25 0x1 0x0>; /* PB25 periph A */
  135. };
  136. };
  137. usart1 {
  138. pinctrl_usart1: usart1-0 {
  139. atmel,pins =
  140. <1 6 0x1 0x1 /* PB6 periph A with pullup */
  141. 1 7 0x1 0x0>; /* PB7 periph A */
  142. };
  143. pinctrl_usart1_rts: usart1_rts-0 {
  144. atmel,pins =
  145. <1 28 0x1 0x0>; /* PB28 periph A */
  146. };
  147. pinctrl_usart1_cts: usart1_cts-0 {
  148. atmel,pins =
  149. <1 29 0x1 0x0>; /* PB29 periph A */
  150. };
  151. };
  152. usart2 {
  153. pinctrl_usart2: usart2-0 {
  154. atmel,pins =
  155. <1 8 0x1 0x1 /* PB8 periph A with pullup */
  156. 1 9 0x1 0x0>; /* PB9 periph A */
  157. };
  158. pinctrl_usart2_rts: usart2_rts-0 {
  159. atmel,pins =
  160. <0 4 0x1 0x0>; /* PA4 periph A */
  161. };
  162. pinctrl_usart2_cts: usart2_cts-0 {
  163. atmel,pins =
  164. <0 5 0x1 0x0>; /* PA5 periph A */
  165. };
  166. };
  167. usart3 {
  168. pinctrl_usart3: usart3-0 {
  169. atmel,pins =
  170. <1 10 0x1 0x1 /* PB10 periph A with pullup */
  171. 1 11 0x1 0x0>; /* PB11 periph A */
  172. };
  173. pinctrl_usart3_rts: usart3_rts-0 {
  174. atmel,pins =
  175. <2 8 0x2 0x0>; /* PC8 periph B */
  176. };
  177. pinctrl_usart3_cts: usart3_cts-0 {
  178. atmel,pins =
  179. <2 10 0x2 0x0>; /* PC10 periph B */
  180. };
  181. };
  182. uart0 {
  183. pinctrl_uart0: uart0-0 {
  184. atmel,pins =
  185. <0 31 0x2 0x1 /* PA31 periph B with pullup */
  186. 0 30 0x2 0x0>; /* PA30 periph B */
  187. };
  188. };
  189. uart1 {
  190. pinctrl_uart1: uart1-0 {
  191. atmel,pins =
  192. <1 12 0x1 0x1 /* PB12 periph A with pullup */
  193. 1 13 0x1 0x0>; /* PB13 periph A */
  194. };
  195. };
  196. nand {
  197. pinctrl_nand: nand-0 {
  198. atmel,pins =
  199. <2 13 0x0 0x1 /* PC13 gpio RDY pin pull_up */
  200. 2 14 0x0 0x1>; /* PC14 gpio enable pin pull_up */
  201. };
  202. };
  203. macb {
  204. pinctrl_macb_rmii: macb_rmii-0 {
  205. atmel,pins =
  206. <0 12 0x1 0x0 /* PA12 periph A */
  207. 0 13 0x1 0x0 /* PA13 periph A */
  208. 0 14 0x1 0x0 /* PA14 periph A */
  209. 0 15 0x1 0x0 /* PA15 periph A */
  210. 0 16 0x1 0x0 /* PA16 periph A */
  211. 0 17 0x1 0x0 /* PA17 periph A */
  212. 0 18 0x1 0x0 /* PA18 periph A */
  213. 0 19 0x1 0x0 /* PA19 periph A */
  214. 0 20 0x1 0x0 /* PA20 periph A */
  215. 0 21 0x1 0x0>; /* PA21 periph A */
  216. };
  217. pinctrl_macb_rmii_mii: macb_rmii_mii-0 {
  218. atmel,pins =
  219. <0 22 0x2 0x0 /* PA22 periph B */
  220. 0 23 0x2 0x0 /* PA23 periph B */
  221. 0 24 0x2 0x0 /* PA24 periph B */
  222. 0 25 0x2 0x0 /* PA25 periph B */
  223. 0 26 0x2 0x0 /* PA26 periph B */
  224. 0 27 0x2 0x0 /* PA27 periph B */
  225. 0 28 0x2 0x0 /* PA28 periph B */
  226. 0 29 0x2 0x0>; /* PA29 periph B */
  227. };
  228. pinctrl_macb_rmii_mii_alt: macb_rmii_mii-1 {
  229. atmel,pins =
  230. <0 10 0x2 0x0 /* PA10 periph B */
  231. 0 11 0x2 0x0 /* PA11 periph B */
  232. 0 24 0x2 0x0 /* PA24 periph B */
  233. 0 25 0x2 0x0 /* PA25 periph B */
  234. 0 26 0x2 0x0 /* PA26 periph B */
  235. 0 27 0x2 0x0 /* PA27 periph B */
  236. 0 28 0x2 0x0 /* PA28 periph B */
  237. 0 29 0x2 0x0>; /* PA29 periph B */
  238. };
  239. };
  240. mmc0 {
  241. pinctrl_mmc0_clk: mmc0_clk-0 {
  242. atmel,pins =
  243. <0 8 0x1 0x0>; /* PA8 periph A */
  244. };
  245. pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 {
  246. atmel,pins =
  247. <0 7 0x1 0x1 /* PA7 periph A with pullup */
  248. 0 6 0x1 0x1>; /* PA6 periph A with pullup */
  249. };
  250. pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
  251. atmel,pins =
  252. <0 9 0x1 0x1 /* PA9 periph A with pullup */
  253. 0 10 0x1 0x1 /* PA10 periph A with pullup */
  254. 0 11 0x1 0x1>; /* PA11 periph A with pullup */
  255. };
  256. pinctrl_mmc0_slot1_cmd_dat0: mmc0_slot1_cmd_dat0-0 {
  257. atmel,pins =
  258. <0 1 0x2 0x1 /* PA1 periph B with pullup */
  259. 0 0 0x2 0x1>; /* PA0 periph B with pullup */
  260. };
  261. pinctrl_mmc0_slot1_dat1_3: mmc0_slot1_dat1_3-0 {
  262. atmel,pins =
  263. <0 5 0x2 0x1 /* PA5 periph B with pullup */
  264. 0 4 0x2 0x1 /* PA4 periph B with pullup */
  265. 0 3 0x2 0x1>; /* PA3 periph B with pullup */
  266. };
  267. };
  268. ssc0 {
  269. pinctrl_ssc0_tx: ssc0_tx-0 {
  270. atmel,pins =
  271. <1 16 0x1 0x0 /* PB16 periph A */
  272. 1 17 0x1 0x0 /* PB17 periph A */
  273. 1 18 0x1 0x0>; /* PB18 periph A */
  274. };
  275. pinctrl_ssc0_rx: ssc0_rx-0 {
  276. atmel,pins =
  277. <1 19 0x1 0x0 /* PB19 periph A */
  278. 1 20 0x1 0x0 /* PB20 periph A */
  279. 1 21 0x1 0x0>; /* PB21 periph A */
  280. };
  281. };
  282. spi0 {
  283. pinctrl_spi0: spi0-0 {
  284. atmel,pins =
  285. <0 0 0x1 0x0 /* PA0 periph A SPI0_MISO pin */
  286. 0 1 0x1 0x0 /* PA1 periph A SPI0_MOSI pin */
  287. 0 2 0x1 0x0>; /* PA2 periph A SPI0_SPCK pin */
  288. };
  289. };
  290. spi1 {
  291. pinctrl_spi1: spi1-0 {
  292. atmel,pins =
  293. <1 0 0x1 0x0 /* PB0 periph A SPI1_MISO pin */
  294. 1 1 0x1 0x0 /* PB1 periph A SPI1_MOSI pin */
  295. 1 2 0x1 0x0>; /* PB2 periph A SPI1_SPCK pin */
  296. };
  297. };
  298. pioA: gpio@fffff400 {
  299. compatible = "atmel,at91rm9200-gpio";
  300. reg = <0xfffff400 0x200>;
  301. interrupts = <2 4 1>;
  302. #gpio-cells = <2>;
  303. gpio-controller;
  304. interrupt-controller;
  305. #interrupt-cells = <2>;
  306. };
  307. pioB: gpio@fffff600 {
  308. compatible = "atmel,at91rm9200-gpio";
  309. reg = <0xfffff600 0x200>;
  310. interrupts = <3 4 1>;
  311. #gpio-cells = <2>;
  312. gpio-controller;
  313. interrupt-controller;
  314. #interrupt-cells = <2>;
  315. };
  316. pioC: gpio@fffff800 {
  317. compatible = "atmel,at91rm9200-gpio";
  318. reg = <0xfffff800 0x200>;
  319. interrupts = <4 4 1>;
  320. #gpio-cells = <2>;
  321. gpio-controller;
  322. interrupt-controller;
  323. #interrupt-cells = <2>;
  324. };
  325. };
  326. dbgu: serial@fffff200 {
  327. compatible = "atmel,at91sam9260-usart";
  328. reg = <0xfffff200 0x200>;
  329. interrupts = <1 4 7>;
  330. pinctrl-names = "default";
  331. pinctrl-0 = <&pinctrl_dbgu>;
  332. status = "disabled";
  333. };
  334. usart0: serial@fffb0000 {
  335. compatible = "atmel,at91sam9260-usart";
  336. reg = <0xfffb0000 0x200>;
  337. interrupts = <6 4 5>;
  338. atmel,use-dma-rx;
  339. atmel,use-dma-tx;
  340. pinctrl-names = "default";
  341. pinctrl-0 = <&pinctrl_usart0>;
  342. status = "disabled";
  343. };
  344. usart1: serial@fffb4000 {
  345. compatible = "atmel,at91sam9260-usart";
  346. reg = <0xfffb4000 0x200>;
  347. interrupts = <7 4 5>;
  348. atmel,use-dma-rx;
  349. atmel,use-dma-tx;
  350. pinctrl-names = "default";
  351. pinctrl-0 = <&pinctrl_usart1>;
  352. status = "disabled";
  353. };
  354. usart2: serial@fffb8000 {
  355. compatible = "atmel,at91sam9260-usart";
  356. reg = <0xfffb8000 0x200>;
  357. interrupts = <8 4 5>;
  358. atmel,use-dma-rx;
  359. atmel,use-dma-tx;
  360. pinctrl-names = "default";
  361. pinctrl-0 = <&pinctrl_usart2>;
  362. status = "disabled";
  363. };
  364. usart3: serial@fffd0000 {
  365. compatible = "atmel,at91sam9260-usart";
  366. reg = <0xfffd0000 0x200>;
  367. interrupts = <23 4 5>;
  368. atmel,use-dma-rx;
  369. atmel,use-dma-tx;
  370. pinctrl-names = "default";
  371. pinctrl-0 = <&pinctrl_usart3>;
  372. status = "disabled";
  373. };
  374. uart0: serial@fffd4000 {
  375. compatible = "atmel,at91sam9260-usart";
  376. reg = <0xfffd4000 0x200>;
  377. interrupts = <24 4 5>;
  378. atmel,use-dma-rx;
  379. atmel,use-dma-tx;
  380. pinctrl-names = "default";
  381. pinctrl-0 = <&pinctrl_uart0>;
  382. status = "disabled";
  383. };
  384. uart1: serial@fffd8000 {
  385. compatible = "atmel,at91sam9260-usart";
  386. reg = <0xfffd8000 0x200>;
  387. interrupts = <25 4 5>;
  388. atmel,use-dma-rx;
  389. atmel,use-dma-tx;
  390. pinctrl-names = "default";
  391. pinctrl-0 = <&pinctrl_uart1>;
  392. status = "disabled";
  393. };
  394. macb0: ethernet@fffc4000 {
  395. compatible = "cdns,at32ap7000-macb", "cdns,macb";
  396. reg = <0xfffc4000 0x100>;
  397. interrupts = <21 4 3>;
  398. pinctrl-names = "default";
  399. pinctrl-0 = <&pinctrl_macb_rmii>;
  400. status = "disabled";
  401. };
  402. usb1: gadget@fffa4000 {
  403. compatible = "atmel,at91rm9200-udc";
  404. reg = <0xfffa4000 0x4000>;
  405. interrupts = <10 4 2>;
  406. status = "disabled";
  407. };
  408. i2c0: i2c@fffac000 {
  409. compatible = "atmel,at91sam9260-i2c";
  410. reg = <0xfffac000 0x100>;
  411. interrupts = <11 4 6>;
  412. #address-cells = <1>;
  413. #size-cells = <0>;
  414. status = "disabled";
  415. };
  416. mmc0: mmc@fffa8000 {
  417. compatible = "atmel,hsmci";
  418. reg = <0xfffa8000 0x600>;
  419. interrupts = <9 4 0>;
  420. #address-cells = <1>;
  421. #size-cells = <0>;
  422. status = "disabled";
  423. };
  424. ssc0: ssc@fffbc000 {
  425. compatible = "atmel,at91rm9200-ssc";
  426. reg = <0xfffbc000 0x4000>;
  427. interrupts = <14 4 5>;
  428. pinctrl-names = "default";
  429. pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
  430. status = "disabled";
  431. };
  432. spi0: spi@fffc8000 {
  433. #address-cells = <1>;
  434. #size-cells = <0>;
  435. compatible = "atmel,at91rm9200-spi";
  436. reg = <0xfffc8000 0x200>;
  437. interrupts = <12 4 3>;
  438. pinctrl-names = "default";
  439. pinctrl-0 = <&pinctrl_spi0>;
  440. status = "disabled";
  441. };
  442. spi1: spi@fffcc000 {
  443. #address-cells = <1>;
  444. #size-cells = <0>;
  445. compatible = "atmel,at91rm9200-spi";
  446. reg = <0xfffcc000 0x200>;
  447. interrupts = <13 4 3>;
  448. pinctrl-names = "default";
  449. pinctrl-0 = <&pinctrl_spi1>;
  450. status = "disabled";
  451. };
  452. adc0: adc@fffe0000 {
  453. compatible = "atmel,at91sam9260-adc";
  454. reg = <0xfffe0000 0x100>;
  455. interrupts = <5 4 0>;
  456. atmel,adc-use-external-triggers;
  457. atmel,adc-channels-used = <0xf>;
  458. atmel,adc-vref = <3300>;
  459. atmel,adc-num-channels = <4>;
  460. atmel,adc-startup-time = <15>;
  461. atmel,adc-channel-base = <0x30>;
  462. atmel,adc-drdy-mask = <0x10000>;
  463. atmel,adc-status-register = <0x1c>;
  464. atmel,adc-trigger-register = <0x04>;
  465. atmel,adc-res = <8 10>;
  466. atmel,adc-res-names = "lowres", "highres";
  467. atmel,adc-use-res = "highres";
  468. trigger@0 {
  469. trigger-name = "timer-counter-0";
  470. trigger-value = <0x1>;
  471. };
  472. trigger@1 {
  473. trigger-name = "timer-counter-1";
  474. trigger-value = <0x3>;
  475. };
  476. trigger@2 {
  477. trigger-name = "timer-counter-2";
  478. trigger-value = <0x5>;
  479. };
  480. trigger@3 {
  481. trigger-name = "external";
  482. trigger-value = <0x13>;
  483. trigger-external;
  484. };
  485. };
  486. watchdog@fffffd40 {
  487. compatible = "atmel,at91sam9260-wdt";
  488. reg = <0xfffffd40 0x10>;
  489. status = "disabled";
  490. };
  491. };
  492. nand0: nand@40000000 {
  493. compatible = "atmel,at91rm9200-nand";
  494. #address-cells = <1>;
  495. #size-cells = <1>;
  496. reg = <0x40000000 0x10000000
  497. 0xffffe800 0x200
  498. >;
  499. atmel,nand-addr-offset = <21>;
  500. atmel,nand-cmd-offset = <22>;
  501. pinctrl-names = "default";
  502. pinctrl-0 = <&pinctrl_nand>;
  503. gpios = <&pioC 13 0
  504. &pioC 14 0
  505. 0
  506. >;
  507. status = "disabled";
  508. };
  509. usb0: ohci@00500000 {
  510. compatible = "atmel,at91rm9200-ohci", "usb-ohci";
  511. reg = <0x00500000 0x100000>;
  512. interrupts = <20 4 2>;
  513. status = "disabled";
  514. };
  515. };
  516. i2c@0 {
  517. compatible = "i2c-gpio";
  518. gpios = <&pioA 23 0 /* sda */
  519. &pioA 24 0 /* scl */
  520. >;
  521. i2c-gpio,sda-open-drain;
  522. i2c-gpio,scl-open-drain;
  523. i2c-gpio,delay-us = <2>; /* ~100 kHz */
  524. #address-cells = <1>;
  525. #size-cells = <0>;
  526. status = "disabled";
  527. };
  528. };