at91rm9200.dtsi 12 KB

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  1. /*
  2. * at91rm9200.dtsi - Device Tree Include file for AT91RM9200 family SoC
  3. *
  4. * Copyright (C) 2011 Atmel,
  5. * 2011 Nicolas Ferre <nicolas.ferre@atmel.com>,
  6. * 2012 Joachim Eastwood <manabian@gmail.com>
  7. *
  8. * Based on at91sam9260.dtsi
  9. *
  10. * Licensed under GPLv2 or later.
  11. */
  12. /include/ "skeleton.dtsi"
  13. / {
  14. model = "Atmel AT91RM9200 family SoC";
  15. compatible = "atmel,at91rm9200";
  16. interrupt-parent = <&aic>;
  17. aliases {
  18. serial0 = &dbgu;
  19. serial1 = &usart0;
  20. serial2 = &usart1;
  21. serial3 = &usart2;
  22. serial4 = &usart3;
  23. gpio0 = &pioA;
  24. gpio1 = &pioB;
  25. gpio2 = &pioC;
  26. gpio3 = &pioD;
  27. tcb0 = &tcb0;
  28. tcb1 = &tcb1;
  29. i2c0 = &i2c0;
  30. ssc0 = &ssc0;
  31. ssc1 = &ssc1;
  32. ssc2 = &ssc2;
  33. };
  34. cpus {
  35. #address-cells = <0>;
  36. #size-cells = <0>;
  37. cpu {
  38. compatible = "arm,arm920t";
  39. device_type = "cpu";
  40. };
  41. };
  42. memory {
  43. reg = <0x20000000 0x04000000>;
  44. };
  45. ahb {
  46. compatible = "simple-bus";
  47. #address-cells = <1>;
  48. #size-cells = <1>;
  49. ranges;
  50. apb {
  51. compatible = "simple-bus";
  52. #address-cells = <1>;
  53. #size-cells = <1>;
  54. ranges;
  55. aic: interrupt-controller@fffff000 {
  56. #interrupt-cells = <3>;
  57. compatible = "atmel,at91rm9200-aic";
  58. interrupt-controller;
  59. reg = <0xfffff000 0x200>;
  60. atmel,external-irqs = <25 26 27 28 29 30 31>;
  61. };
  62. ramc0: ramc@ffffff00 {
  63. compatible = "atmel,at91rm9200-sdramc";
  64. reg = <0xffffff00 0x100>;
  65. };
  66. pmc: pmc@fffffc00 {
  67. compatible = "atmel,at91rm9200-pmc";
  68. reg = <0xfffffc00 0x100>;
  69. };
  70. st: timer@fffffd00 {
  71. compatible = "atmel,at91rm9200-st";
  72. reg = <0xfffffd00 0x100>;
  73. interrupts = <1 4 7>;
  74. };
  75. tcb0: timer@fffa0000 {
  76. compatible = "atmel,at91rm9200-tcb";
  77. reg = <0xfffa0000 0x100>;
  78. interrupts = <17 4 0 18 4 0 19 4 0>;
  79. };
  80. tcb1: timer@fffa4000 {
  81. compatible = "atmel,at91rm9200-tcb";
  82. reg = <0xfffa4000 0x100>;
  83. interrupts = <20 4 0 21 4 0 22 4 0>;
  84. };
  85. i2c0: i2c@fffb8000 {
  86. compatible = "atmel,at91rm9200-i2c";
  87. reg = <0xfffb8000 0x4000>;
  88. interrupts = <12 4 6>;
  89. pinctrl-names = "default";
  90. pinctrl-0 = <&pinctrl_twi>;
  91. #address-cells = <1>;
  92. #size-cells = <0>;
  93. status = "disabled";
  94. };
  95. mmc0: mmc@fffb4000 {
  96. compatible = "atmel,hsmci";
  97. reg = <0xfffb4000 0x4000>;
  98. interrupts = <10 4 0>;
  99. #address-cells = <1>;
  100. #size-cells = <0>;
  101. status = "disabled";
  102. };
  103. ssc0: ssc@fffd0000 {
  104. compatible = "atmel,at91rm9200-ssc";
  105. reg = <0xfffd0000 0x4000>;
  106. interrupts = <14 4 5>;
  107. pinctrl-names = "default";
  108. pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
  109. status = "disable";
  110. };
  111. ssc1: ssc@fffd4000 {
  112. compatible = "atmel,at91rm9200-ssc";
  113. reg = <0xfffd4000 0x4000>;
  114. interrupts = <15 4 5>;
  115. pinctrl-names = "default";
  116. pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
  117. status = "disable";
  118. };
  119. ssc2: ssc@fffd8000 {
  120. compatible = "atmel,at91rm9200-ssc";
  121. reg = <0xfffd8000 0x4000>;
  122. interrupts = <16 4 5>;
  123. pinctrl-names = "default";
  124. pinctrl-0 = <&pinctrl_ssc2_tx &pinctrl_ssc2_rx>;
  125. status = "disable";
  126. };
  127. macb0: ethernet@fffbc000 {
  128. compatible = "cdns,at91rm9200-emac", "cdns,emac";
  129. reg = <0xfffbc000 0x4000>;
  130. interrupts = <24 4 3>;
  131. phy-mode = "rmii";
  132. pinctrl-names = "default";
  133. pinctrl-0 = <&pinctrl_macb_rmii>;
  134. status = "disabled";
  135. };
  136. pinctrl@fffff400 {
  137. #address-cells = <1>;
  138. #size-cells = <1>;
  139. compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
  140. ranges = <0xfffff400 0xfffff400 0x800>;
  141. atmel,mux-mask = <
  142. /* A B */
  143. 0xffffffff 0xffffffff /* pioA */
  144. 0xffffffff 0x083fffff /* pioB */
  145. 0xffff3fff 0x00000000 /* pioC */
  146. 0x03ff87ff 0x0fffff80 /* pioD */
  147. >;
  148. /* shared pinctrl settings */
  149. dbgu {
  150. pinctrl_dbgu: dbgu-0 {
  151. atmel,pins =
  152. <0 30 0x1 0x0 /* PA30 periph A */
  153. 0 31 0x1 0x1>; /* PA31 periph with pullup */
  154. };
  155. };
  156. uart0 {
  157. pinctrl_uart0: uart0-0 {
  158. atmel,pins =
  159. <0 17 0x1 0x0 /* PA17 periph A */
  160. 0 18 0x1 0x0>; /* PA18 periph A */
  161. };
  162. pinctrl_uart0_rts: uart0_rts-0 {
  163. atmel,pins =
  164. <0 20 0x1 0x0>; /* PA20 periph A */
  165. };
  166. pinctrl_uart0_cts: uart0_cts-0 {
  167. atmel,pins =
  168. <0 21 0x1 0x0>; /* PA21 periph A */
  169. };
  170. };
  171. uart1 {
  172. pinctrl_uart1: uart1-0 {
  173. atmel,pins =
  174. <1 20 0x1 0x1 /* PB20 periph A with pullup */
  175. 1 21 0x1 0x0>; /* PB21 periph A */
  176. };
  177. pinctrl_uart1_rts: uart1_rts-0 {
  178. atmel,pins =
  179. <1 24 0x1 0x0>; /* PB24 periph A */
  180. };
  181. pinctrl_uart1_cts: uart1_cts-0 {
  182. atmel,pins =
  183. <1 26 0x1 0x0>; /* PB26 periph A */
  184. };
  185. pinctrl_uart1_dtr_dsr: uart1_dtr_dsr-0 {
  186. atmel,pins =
  187. <1 19 0x1 0x0 /* PB19 periph A */
  188. 1 25 0x1 0x0>; /* PB25 periph A */
  189. };
  190. pinctrl_uart1_dcd: uart1_dcd-0 {
  191. atmel,pins =
  192. <1 23 0x1 0x0>; /* PB23 periph A */
  193. };
  194. pinctrl_uart1_ri: uart1_ri-0 {
  195. atmel,pins =
  196. <1 18 0x1 0x0>; /* PB18 periph A */
  197. };
  198. };
  199. uart2 {
  200. pinctrl_uart2: uart2-0 {
  201. atmel,pins =
  202. <0 22 0x1 0x0 /* PA22 periph A */
  203. 0 23 0x1 0x1>; /* PA23 periph A with pullup */
  204. };
  205. pinctrl_uart2_rts: uart2_rts-0 {
  206. atmel,pins =
  207. <0 30 0x2 0x0>; /* PA30 periph B */
  208. };
  209. pinctrl_uart2_cts: uart2_cts-0 {
  210. atmel,pins =
  211. <0 31 0x2 0x0>; /* PA31 periph B */
  212. };
  213. };
  214. uart3 {
  215. pinctrl_uart3: uart3-0 {
  216. atmel,pins =
  217. <0 5 0x2 0x1 /* PA5 periph B with pullup */
  218. 0 6 0x2 0x0>; /* PA6 periph B */
  219. };
  220. pinctrl_uart3_rts: uart3_rts-0 {
  221. atmel,pins =
  222. <1 0 0x2 0x0>; /* PB0 periph B */
  223. };
  224. pinctrl_uart3_cts: uart3_cts-0 {
  225. atmel,pins =
  226. <1 1 0x2 0x0>; /* PB1 periph B */
  227. };
  228. };
  229. nand {
  230. pinctrl_nand: nand-0 {
  231. atmel,pins =
  232. <2 2 0x0 0x1 /* PC2 gpio RDY pin pull_up */
  233. 1 1 0x0 0x1>; /* PB1 gpio CD pin pull_up */
  234. };
  235. };
  236. macb {
  237. pinctrl_macb_rmii: macb_rmii-0 {
  238. atmel,pins =
  239. <0 7 0x1 0x0 /* PA7 periph A */
  240. 0 8 0x1 0x0 /* PA8 periph A */
  241. 0 9 0x1 0x0 /* PA9 periph A */
  242. 0 10 0x1 0x0 /* PA10 periph A */
  243. 0 11 0x1 0x0 /* PA11 periph A */
  244. 0 12 0x1 0x0 /* PA12 periph A */
  245. 0 13 0x1 0x0 /* PA13 periph A */
  246. 0 14 0x1 0x0 /* PA14 periph A */
  247. 0 15 0x1 0x0 /* PA15 periph A */
  248. 0 16 0x1 0x0>; /* PA16 periph A */
  249. };
  250. pinctrl_macb_rmii_mii: macb_rmii_mii-0 {
  251. atmel,pins =
  252. <1 12 0x2 0x0 /* PB12 periph B */
  253. 1 13 0x2 0x0 /* PB13 periph B */
  254. 1 14 0x2 0x0 /* PB14 periph B */
  255. 1 15 0x2 0x0 /* PB15 periph B */
  256. 1 16 0x2 0x0 /* PB16 periph B */
  257. 1 17 0x2 0x0 /* PB17 periph B */
  258. 1 18 0x2 0x0 /* PB18 periph B */
  259. 1 19 0x2 0x0>; /* PB19 periph B */
  260. };
  261. };
  262. mmc0 {
  263. pinctrl_mmc0_clk: mmc0_clk-0 {
  264. atmel,pins =
  265. <0 27 0x1 0x0>; /* PA27 periph A */
  266. };
  267. pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 {
  268. atmel,pins =
  269. <0 28 0x1 0x1 /* PA28 periph A with pullup */
  270. 0 29 0x1 0x1>; /* PA29 periph A with pullup */
  271. };
  272. pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
  273. atmel,pins =
  274. <1 3 0x2 0x1 /* PB3 periph B with pullup */
  275. 1 4 0x2 0x1 /* PB4 periph B with pullup */
  276. 1 5 0x2 0x1>; /* PB5 periph B with pullup */
  277. };
  278. pinctrl_mmc0_slot1_cmd_dat0: mmc0_slot1_cmd_dat0-0 {
  279. atmel,pins =
  280. <0 8 0x2 0x1 /* PA8 periph B with pullup */
  281. 0 9 0x2 0x1>; /* PA9 periph B with pullup */
  282. };
  283. pinctrl_mmc0_slot1_dat1_3: mmc0_slot1_dat1_3-0 {
  284. atmel,pins =
  285. <0 10 0x2 0x1 /* PA10 periph B with pullup */
  286. 0 11 0x2 0x1 /* PA11 periph B with pullup */
  287. 0 12 0x2 0x1>; /* PA12 periph B with pullup */
  288. };
  289. };
  290. ssc0 {
  291. pinctrl_ssc0_tx: ssc0_tx-0 {
  292. atmel,pins =
  293. <1 0 0x1 0x0 /* PB0 periph A */
  294. 1 1 0x1 0x0 /* PB1 periph A */
  295. 1 2 0x1 0x0>; /* PB2 periph A */
  296. };
  297. pinctrl_ssc0_rx: ssc0_rx-0 {
  298. atmel,pins =
  299. <1 3 0x1 0x0 /* PB3 periph A */
  300. 1 4 0x1 0x0 /* PB4 periph A */
  301. 1 5 0x1 0x0>; /* PB5 periph A */
  302. };
  303. };
  304. ssc1 {
  305. pinctrl_ssc1_tx: ssc1_tx-0 {
  306. atmel,pins =
  307. <1 6 0x1 0x0 /* PB6 periph A */
  308. 1 7 0x1 0x0 /* PB7 periph A */
  309. 1 8 0x1 0x0>; /* PB8 periph A */
  310. };
  311. pinctrl_ssc1_rx: ssc1_rx-0 {
  312. atmel,pins =
  313. <1 9 0x1 0x0 /* PB9 periph A */
  314. 1 10 0x1 0x0 /* PB10 periph A */
  315. 1 11 0x1 0x0>; /* PB11 periph A */
  316. };
  317. };
  318. ssc2 {
  319. pinctrl_ssc2_tx: ssc2_tx-0 {
  320. atmel,pins =
  321. <1 12 0x1 0x0 /* PB12 periph A */
  322. 1 13 0x1 0x0 /* PB13 periph A */
  323. 1 14 0x1 0x0>; /* PB14 periph A */
  324. };
  325. pinctrl_ssc2_rx: ssc2_rx-0 {
  326. atmel,pins =
  327. <1 15 0x1 0x0 /* PB15 periph A */
  328. 1 16 0x1 0x0 /* PB16 periph A */
  329. 1 17 0x1 0x0>; /* PB17 periph A */
  330. };
  331. };
  332. twi {
  333. pinctrl_twi: twi-0 {
  334. atmel,pins =
  335. <0 25 0x1 0x2 /* PA25 periph A with multi drive */
  336. 0 26 0x1 0x2>; /* PA26 periph A with multi drive */
  337. };
  338. pinctrl_twi_gpio: twi_gpio-0 {
  339. atmel,pins =
  340. <0 25 0x0 0x2 /* PA25 GPIO with multi drive */
  341. 0 26 0x0 0x2>; /* PA26 GPIO with multi drive */
  342. };
  343. };
  344. pioA: gpio@fffff400 {
  345. compatible = "atmel,at91rm9200-gpio";
  346. reg = <0xfffff400 0x200>;
  347. interrupts = <2 4 1>;
  348. #gpio-cells = <2>;
  349. gpio-controller;
  350. interrupt-controller;
  351. #interrupt-cells = <2>;
  352. };
  353. pioB: gpio@fffff600 {
  354. compatible = "atmel,at91rm9200-gpio";
  355. reg = <0xfffff600 0x200>;
  356. interrupts = <3 4 1>;
  357. #gpio-cells = <2>;
  358. gpio-controller;
  359. interrupt-controller;
  360. #interrupt-cells = <2>;
  361. };
  362. pioC: gpio@fffff800 {
  363. compatible = "atmel,at91rm9200-gpio";
  364. reg = <0xfffff800 0x200>;
  365. interrupts = <4 4 1>;
  366. #gpio-cells = <2>;
  367. gpio-controller;
  368. interrupt-controller;
  369. #interrupt-cells = <2>;
  370. };
  371. pioD: gpio@fffffa00 {
  372. compatible = "atmel,at91rm9200-gpio";
  373. reg = <0xfffffa00 0x200>;
  374. interrupts = <5 4 1>;
  375. #gpio-cells = <2>;
  376. gpio-controller;
  377. interrupt-controller;
  378. #interrupt-cells = <2>;
  379. };
  380. };
  381. dbgu: serial@fffff200 {
  382. compatible = "atmel,at91rm9200-usart";
  383. reg = <0xfffff200 0x200>;
  384. interrupts = <1 4 7>;
  385. pinctrl-names = "default";
  386. pinctrl-0 = <&pinctrl_dbgu>;
  387. status = "disabled";
  388. };
  389. usart0: serial@fffc0000 {
  390. compatible = "atmel,at91rm9200-usart";
  391. reg = <0xfffc0000 0x200>;
  392. interrupts = <6 4 5>;
  393. atmel,use-dma-rx;
  394. atmel,use-dma-tx;
  395. pinctrl-names = "default";
  396. pinctrl-0 = <&pinctrl_uart0>;
  397. status = "disabled";
  398. };
  399. usart1: serial@fffc4000 {
  400. compatible = "atmel,at91rm9200-usart";
  401. reg = <0xfffc4000 0x200>;
  402. interrupts = <7 4 5>;
  403. atmel,use-dma-rx;
  404. atmel,use-dma-tx;
  405. pinctrl-names = "default";
  406. pinctrl-0 = <&pinctrl_uart1>;
  407. status = "disabled";
  408. };
  409. usart2: serial@fffc8000 {
  410. compatible = "atmel,at91rm9200-usart";
  411. reg = <0xfffc8000 0x200>;
  412. interrupts = <8 4 5>;
  413. atmel,use-dma-rx;
  414. atmel,use-dma-tx;
  415. pinctrl-names = "default";
  416. pinctrl-0 = <&pinctrl_uart2>;
  417. status = "disabled";
  418. };
  419. usart3: serial@fffcc000 {
  420. compatible = "atmel,at91rm9200-usart";
  421. reg = <0xfffcc000 0x200>;
  422. interrupts = <23 4 5>;
  423. atmel,use-dma-rx;
  424. atmel,use-dma-tx;
  425. pinctrl-names = "default";
  426. pinctrl-0 = <&pinctrl_uart3>;
  427. status = "disabled";
  428. };
  429. usb1: gadget@fffb0000 {
  430. compatible = "atmel,at91rm9200-udc";
  431. reg = <0xfffb0000 0x4000>;
  432. interrupts = <11 4 2>;
  433. status = "disabled";
  434. };
  435. };
  436. nand0: nand@40000000 {
  437. compatible = "atmel,at91rm9200-nand";
  438. #address-cells = <1>;
  439. #size-cells = <1>;
  440. reg = <0x40000000 0x10000000>;
  441. atmel,nand-addr-offset = <21>;
  442. atmel,nand-cmd-offset = <22>;
  443. pinctrl-names = "default";
  444. pinctrl-0 = <&pinctrl_nand>;
  445. nand-ecc-mode = "soft";
  446. gpios = <&pioC 2 0
  447. 0
  448. &pioB 1 0
  449. >;
  450. status = "disabled";
  451. };
  452. usb0: ohci@00300000 {
  453. compatible = "atmel,at91rm9200-ohci", "usb-ohci";
  454. reg = <0x00300000 0x100000>;
  455. interrupts = <23 4 2>;
  456. status = "disabled";
  457. };
  458. };
  459. i2c@0 {
  460. compatible = "i2c-gpio";
  461. gpios = <&pioA 25 0 /* sda */
  462. &pioA 26 0 /* scl */
  463. >;
  464. i2c-gpio,sda-open-drain;
  465. i2c-gpio,scl-open-drain;
  466. i2c-gpio,delay-us = <2>; /* ~100 kHz */
  467. pinctrl-names = "default";
  468. pinctrl-0 = <&pinctrl_twi_gpio>;
  469. #address-cells = <1>;
  470. #size-cells = <0>;
  471. status = "disabled";
  472. };
  473. };