intr_hw.c 4.1 KB

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  1. /*
  2. * Tegra host1x Interrupt Management
  3. *
  4. * Copyright (C) 2010 Google, Inc.
  5. * Copyright (c) 2010-2013, NVIDIA Corporation.
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms and conditions of the GNU General Public License,
  9. * version 2, as published by the Free Software Foundation.
  10. *
  11. * This program is distributed in the hope it will be useful, but WITHOUT
  12. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  14. * more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program. If not, see <http://www.gnu.org/licenses/>.
  18. */
  19. #include <linux/interrupt.h>
  20. #include <linux/irq.h>
  21. #include <linux/io.h>
  22. #include <asm/mach/irq.h>
  23. #include "intr.h"
  24. #include "dev.h"
  25. /*
  26. * Sync point threshold interrupt service function
  27. * Handles sync point threshold triggers, in interrupt context
  28. */
  29. static void host1x_intr_syncpt_handle(struct host1x_syncpt *syncpt)
  30. {
  31. unsigned int id = syncpt->id;
  32. struct host1x *host = syncpt->host;
  33. host1x_sync_writel(host, BIT_MASK(id),
  34. HOST1X_SYNC_SYNCPT_THRESH_INT_DISABLE(BIT_WORD(id)));
  35. host1x_sync_writel(host, BIT_MASK(id),
  36. HOST1X_SYNC_SYNCPT_THRESH_CPU0_INT_STATUS(BIT_WORD(id)));
  37. queue_work(host->intr_wq, &syncpt->intr.work);
  38. }
  39. static irqreturn_t syncpt_thresh_isr(int irq, void *dev_id)
  40. {
  41. struct host1x *host = dev_id;
  42. unsigned long reg;
  43. int i, id;
  44. for (i = 0; i <= BIT_WORD(host->info->nb_pts); i++) {
  45. reg = host1x_sync_readl(host,
  46. HOST1X_SYNC_SYNCPT_THRESH_CPU0_INT_STATUS(i));
  47. for_each_set_bit(id, &reg, BITS_PER_LONG) {
  48. struct host1x_syncpt *syncpt =
  49. host->syncpt + (i * BITS_PER_LONG + id);
  50. host1x_intr_syncpt_handle(syncpt);
  51. }
  52. }
  53. return IRQ_HANDLED;
  54. }
  55. static void _host1x_intr_disable_all_syncpt_intrs(struct host1x *host)
  56. {
  57. u32 i;
  58. for (i = 0; i <= BIT_WORD(host->info->nb_pts); ++i) {
  59. host1x_sync_writel(host, 0xffffffffu,
  60. HOST1X_SYNC_SYNCPT_THRESH_INT_DISABLE(i));
  61. host1x_sync_writel(host, 0xffffffffu,
  62. HOST1X_SYNC_SYNCPT_THRESH_CPU0_INT_STATUS(i));
  63. }
  64. }
  65. static int _host1x_intr_init_host_sync(struct host1x *host, u32 cpm,
  66. void (*syncpt_thresh_work)(struct work_struct *))
  67. {
  68. int i, err;
  69. host1x_hw_intr_disable_all_syncpt_intrs(host);
  70. for (i = 0; i < host->info->nb_pts; i++)
  71. INIT_WORK(&host->syncpt[i].intr.work, syncpt_thresh_work);
  72. err = devm_request_irq(host->dev, host->intr_syncpt_irq,
  73. syncpt_thresh_isr, IRQF_SHARED,
  74. "host1x_syncpt", host);
  75. if (IS_ERR_VALUE(err)) {
  76. WARN_ON(1);
  77. return err;
  78. }
  79. /* disable the ip_busy_timeout. this prevents write drops */
  80. host1x_sync_writel(host, 0, HOST1X_SYNC_IP_BUSY_TIMEOUT);
  81. /*
  82. * increase the auto-ack timout to the maximum value. 2d will hang
  83. * otherwise on Tegra2.
  84. */
  85. host1x_sync_writel(host, 0xff, HOST1X_SYNC_CTXSW_TIMEOUT_CFG);
  86. /* update host clocks per usec */
  87. host1x_sync_writel(host, cpm, HOST1X_SYNC_USEC_CLK);
  88. return 0;
  89. }
  90. static void _host1x_intr_set_syncpt_threshold(struct host1x *host,
  91. u32 id, u32 thresh)
  92. {
  93. host1x_sync_writel(host, thresh, HOST1X_SYNC_SYNCPT_INT_THRESH(id));
  94. }
  95. static void _host1x_intr_enable_syncpt_intr(struct host1x *host, u32 id)
  96. {
  97. host1x_sync_writel(host, BIT_MASK(id),
  98. HOST1X_SYNC_SYNCPT_THRESH_INT_ENABLE_CPU0(BIT_WORD(id)));
  99. }
  100. static void _host1x_intr_disable_syncpt_intr(struct host1x *host, u32 id)
  101. {
  102. host1x_sync_writel(host, BIT_MASK(id),
  103. HOST1X_SYNC_SYNCPT_THRESH_INT_DISABLE(BIT_WORD(id)));
  104. host1x_sync_writel(host, BIT_MASK(id),
  105. HOST1X_SYNC_SYNCPT_THRESH_CPU0_INT_STATUS(BIT_WORD(id)));
  106. }
  107. static int _host1x_free_syncpt_irq(struct host1x *host)
  108. {
  109. devm_free_irq(host->dev, host->intr_syncpt_irq, host);
  110. flush_workqueue(host->intr_wq);
  111. return 0;
  112. }
  113. static const struct host1x_intr_ops host1x_intr_ops = {
  114. .init_host_sync = _host1x_intr_init_host_sync,
  115. .set_syncpt_threshold = _host1x_intr_set_syncpt_threshold,
  116. .enable_syncpt_intr = _host1x_intr_enable_syncpt_intr,
  117. .disable_syncpt_intr = _host1x_intr_disable_syncpt_intr,
  118. .disable_all_syncpt_intrs = _host1x_intr_disable_all_syncpt_intrs,
  119. .free_syncpt_irq = _host1x_free_syncpt_irq,
  120. };