dmaengine.c 31 KB

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  1. /*
  2. * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
  3. *
  4. * This program is free software; you can redistribute it and/or modify it
  5. * under the terms of the GNU General Public License as published by the Free
  6. * Software Foundation; either version 2 of the License, or (at your option)
  7. * any later version.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program; if not, write to the Free Software Foundation, Inc., 59
  16. * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  17. *
  18. * The full GNU General Public License is included in this distribution in the
  19. * file called COPYING.
  20. */
  21. /*
  22. * This code implements the DMA subsystem. It provides a HW-neutral interface
  23. * for other kernel code to use asynchronous memory copy capabilities,
  24. * if present, and allows different HW DMA drivers to register as providing
  25. * this capability.
  26. *
  27. * Due to the fact we are accelerating what is already a relatively fast
  28. * operation, the code goes to great lengths to avoid additional overhead,
  29. * such as locking.
  30. *
  31. * LOCKING:
  32. *
  33. * The subsystem keeps a global list of dma_device structs it is protected by a
  34. * mutex, dma_list_mutex.
  35. *
  36. * A subsystem can get access to a channel by calling dmaengine_get() followed
  37. * by dma_find_channel(), or if it has need for an exclusive channel it can call
  38. * dma_request_channel(). Once a channel is allocated a reference is taken
  39. * against its corresponding driver to disable removal.
  40. *
  41. * Each device has a channels list, which runs unlocked but is never modified
  42. * once the device is registered, it's just setup by the driver.
  43. *
  44. * See Documentation/dmaengine.txt for more details
  45. */
  46. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  47. #include <linux/dma-mapping.h>
  48. #include <linux/init.h>
  49. #include <linux/module.h>
  50. #include <linux/mm.h>
  51. #include <linux/device.h>
  52. #include <linux/dmaengine.h>
  53. #include <linux/hardirq.h>
  54. #include <linux/spinlock.h>
  55. #include <linux/percpu.h>
  56. #include <linux/rcupdate.h>
  57. #include <linux/mutex.h>
  58. #include <linux/jiffies.h>
  59. #include <linux/rculist.h>
  60. #include <linux/idr.h>
  61. #include <linux/slab.h>
  62. #include <linux/acpi.h>
  63. #include <linux/acpi_dma.h>
  64. #include <linux/of_dma.h>
  65. #include <linux/mempool.h>
  66. static DEFINE_MUTEX(dma_list_mutex);
  67. static DEFINE_IDR(dma_idr);
  68. static LIST_HEAD(dma_device_list);
  69. static long dmaengine_ref_count;
  70. /* --- sysfs implementation --- */
  71. /**
  72. * dev_to_dma_chan - convert a device pointer to the its sysfs container object
  73. * @dev - device node
  74. *
  75. * Must be called under dma_list_mutex
  76. */
  77. static struct dma_chan *dev_to_dma_chan(struct device *dev)
  78. {
  79. struct dma_chan_dev *chan_dev;
  80. chan_dev = container_of(dev, typeof(*chan_dev), device);
  81. return chan_dev->chan;
  82. }
  83. static ssize_t memcpy_count_show(struct device *dev,
  84. struct device_attribute *attr, char *buf)
  85. {
  86. struct dma_chan *chan;
  87. unsigned long count = 0;
  88. int i;
  89. int err;
  90. mutex_lock(&dma_list_mutex);
  91. chan = dev_to_dma_chan(dev);
  92. if (chan) {
  93. for_each_possible_cpu(i)
  94. count += per_cpu_ptr(chan->local, i)->memcpy_count;
  95. err = sprintf(buf, "%lu\n", count);
  96. } else
  97. err = -ENODEV;
  98. mutex_unlock(&dma_list_mutex);
  99. return err;
  100. }
  101. static DEVICE_ATTR_RO(memcpy_count);
  102. static ssize_t bytes_transferred_show(struct device *dev,
  103. struct device_attribute *attr, char *buf)
  104. {
  105. struct dma_chan *chan;
  106. unsigned long count = 0;
  107. int i;
  108. int err;
  109. mutex_lock(&dma_list_mutex);
  110. chan = dev_to_dma_chan(dev);
  111. if (chan) {
  112. for_each_possible_cpu(i)
  113. count += per_cpu_ptr(chan->local, i)->bytes_transferred;
  114. err = sprintf(buf, "%lu\n", count);
  115. } else
  116. err = -ENODEV;
  117. mutex_unlock(&dma_list_mutex);
  118. return err;
  119. }
  120. static DEVICE_ATTR_RO(bytes_transferred);
  121. static ssize_t in_use_show(struct device *dev, struct device_attribute *attr,
  122. char *buf)
  123. {
  124. struct dma_chan *chan;
  125. int err;
  126. mutex_lock(&dma_list_mutex);
  127. chan = dev_to_dma_chan(dev);
  128. if (chan)
  129. err = sprintf(buf, "%d\n", chan->client_count);
  130. else
  131. err = -ENODEV;
  132. mutex_unlock(&dma_list_mutex);
  133. return err;
  134. }
  135. static DEVICE_ATTR_RO(in_use);
  136. static struct attribute *dma_dev_attrs[] = {
  137. &dev_attr_memcpy_count.attr,
  138. &dev_attr_bytes_transferred.attr,
  139. &dev_attr_in_use.attr,
  140. NULL,
  141. };
  142. ATTRIBUTE_GROUPS(dma_dev);
  143. static void chan_dev_release(struct device *dev)
  144. {
  145. struct dma_chan_dev *chan_dev;
  146. chan_dev = container_of(dev, typeof(*chan_dev), device);
  147. if (atomic_dec_and_test(chan_dev->idr_ref)) {
  148. mutex_lock(&dma_list_mutex);
  149. idr_remove(&dma_idr, chan_dev->dev_id);
  150. mutex_unlock(&dma_list_mutex);
  151. kfree(chan_dev->idr_ref);
  152. }
  153. kfree(chan_dev);
  154. }
  155. static struct class dma_devclass = {
  156. .name = "dma",
  157. .dev_groups = dma_dev_groups,
  158. .dev_release = chan_dev_release,
  159. };
  160. /* --- client and device registration --- */
  161. #define dma_device_satisfies_mask(device, mask) \
  162. __dma_device_satisfies_mask((device), &(mask))
  163. static int
  164. __dma_device_satisfies_mask(struct dma_device *device,
  165. const dma_cap_mask_t *want)
  166. {
  167. dma_cap_mask_t has;
  168. bitmap_and(has.bits, want->bits, device->cap_mask.bits,
  169. DMA_TX_TYPE_END);
  170. return bitmap_equal(want->bits, has.bits, DMA_TX_TYPE_END);
  171. }
  172. static struct module *dma_chan_to_owner(struct dma_chan *chan)
  173. {
  174. return chan->device->dev->driver->owner;
  175. }
  176. /**
  177. * balance_ref_count - catch up the channel reference count
  178. * @chan - channel to balance ->client_count versus dmaengine_ref_count
  179. *
  180. * balance_ref_count must be called under dma_list_mutex
  181. */
  182. static void balance_ref_count(struct dma_chan *chan)
  183. {
  184. struct module *owner = dma_chan_to_owner(chan);
  185. while (chan->client_count < dmaengine_ref_count) {
  186. __module_get(owner);
  187. chan->client_count++;
  188. }
  189. }
  190. /**
  191. * dma_chan_get - try to grab a dma channel's parent driver module
  192. * @chan - channel to grab
  193. *
  194. * Must be called under dma_list_mutex
  195. */
  196. static int dma_chan_get(struct dma_chan *chan)
  197. {
  198. int err = -ENODEV;
  199. struct module *owner = dma_chan_to_owner(chan);
  200. if (chan->client_count) {
  201. __module_get(owner);
  202. err = 0;
  203. } else if (try_module_get(owner))
  204. err = 0;
  205. if (err == 0)
  206. chan->client_count++;
  207. /* allocate upon first client reference */
  208. if (chan->client_count == 1 && err == 0) {
  209. int desc_cnt = chan->device->device_alloc_chan_resources(chan);
  210. if (desc_cnt < 0) {
  211. err = desc_cnt;
  212. chan->client_count = 0;
  213. module_put(owner);
  214. } else if (!dma_has_cap(DMA_PRIVATE, chan->device->cap_mask))
  215. balance_ref_count(chan);
  216. }
  217. return err;
  218. }
  219. /**
  220. * dma_chan_put - drop a reference to a dma channel's parent driver module
  221. * @chan - channel to release
  222. *
  223. * Must be called under dma_list_mutex
  224. */
  225. static void dma_chan_put(struct dma_chan *chan)
  226. {
  227. if (!chan->client_count)
  228. return; /* this channel failed alloc_chan_resources */
  229. chan->client_count--;
  230. module_put(dma_chan_to_owner(chan));
  231. if (chan->client_count == 0)
  232. chan->device->device_free_chan_resources(chan);
  233. }
  234. enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie)
  235. {
  236. enum dma_status status;
  237. unsigned long dma_sync_wait_timeout = jiffies + msecs_to_jiffies(5000);
  238. dma_async_issue_pending(chan);
  239. do {
  240. status = dma_async_is_tx_complete(chan, cookie, NULL, NULL);
  241. if (time_after_eq(jiffies, dma_sync_wait_timeout)) {
  242. pr_err("%s: timeout!\n", __func__);
  243. return DMA_ERROR;
  244. }
  245. if (status != DMA_IN_PROGRESS)
  246. break;
  247. cpu_relax();
  248. } while (1);
  249. return status;
  250. }
  251. EXPORT_SYMBOL(dma_sync_wait);
  252. /**
  253. * dma_cap_mask_all - enable iteration over all operation types
  254. */
  255. static dma_cap_mask_t dma_cap_mask_all;
  256. /**
  257. * dma_chan_tbl_ent - tracks channel allocations per core/operation
  258. * @chan - associated channel for this entry
  259. */
  260. struct dma_chan_tbl_ent {
  261. struct dma_chan *chan;
  262. };
  263. /**
  264. * channel_table - percpu lookup table for memory-to-memory offload providers
  265. */
  266. static struct dma_chan_tbl_ent __percpu *channel_table[DMA_TX_TYPE_END];
  267. static int __init dma_channel_table_init(void)
  268. {
  269. enum dma_transaction_type cap;
  270. int err = 0;
  271. bitmap_fill(dma_cap_mask_all.bits, DMA_TX_TYPE_END);
  272. /* 'interrupt', 'private', and 'slave' are channel capabilities,
  273. * but are not associated with an operation so they do not need
  274. * an entry in the channel_table
  275. */
  276. clear_bit(DMA_INTERRUPT, dma_cap_mask_all.bits);
  277. clear_bit(DMA_PRIVATE, dma_cap_mask_all.bits);
  278. clear_bit(DMA_SLAVE, dma_cap_mask_all.bits);
  279. for_each_dma_cap_mask(cap, dma_cap_mask_all) {
  280. channel_table[cap] = alloc_percpu(struct dma_chan_tbl_ent);
  281. if (!channel_table[cap]) {
  282. err = -ENOMEM;
  283. break;
  284. }
  285. }
  286. if (err) {
  287. pr_err("initialization failure\n");
  288. for_each_dma_cap_mask(cap, dma_cap_mask_all)
  289. if (channel_table[cap])
  290. free_percpu(channel_table[cap]);
  291. }
  292. return err;
  293. }
  294. arch_initcall(dma_channel_table_init);
  295. /**
  296. * dma_find_channel - find a channel to carry out the operation
  297. * @tx_type: transaction type
  298. */
  299. struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type)
  300. {
  301. return this_cpu_read(channel_table[tx_type]->chan);
  302. }
  303. EXPORT_SYMBOL(dma_find_channel);
  304. /*
  305. * net_dma_find_channel - find a channel for net_dma
  306. * net_dma has alignment requirements
  307. */
  308. struct dma_chan *net_dma_find_channel(void)
  309. {
  310. struct dma_chan *chan = dma_find_channel(DMA_MEMCPY);
  311. if (chan && !is_dma_copy_aligned(chan->device, 1, 1, 1))
  312. return NULL;
  313. return chan;
  314. }
  315. EXPORT_SYMBOL(net_dma_find_channel);
  316. /**
  317. * dma_issue_pending_all - flush all pending operations across all channels
  318. */
  319. void dma_issue_pending_all(void)
  320. {
  321. struct dma_device *device;
  322. struct dma_chan *chan;
  323. rcu_read_lock();
  324. list_for_each_entry_rcu(device, &dma_device_list, global_node) {
  325. if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
  326. continue;
  327. list_for_each_entry(chan, &device->channels, device_node)
  328. if (chan->client_count)
  329. device->device_issue_pending(chan);
  330. }
  331. rcu_read_unlock();
  332. }
  333. EXPORT_SYMBOL(dma_issue_pending_all);
  334. /**
  335. * dma_chan_is_local - returns true if the channel is in the same numa-node as the cpu
  336. */
  337. static bool dma_chan_is_local(struct dma_chan *chan, int cpu)
  338. {
  339. int node = dev_to_node(chan->device->dev);
  340. return node == -1 || cpumask_test_cpu(cpu, cpumask_of_node(node));
  341. }
  342. /**
  343. * min_chan - returns the channel with min count and in the same numa-node as the cpu
  344. * @cap: capability to match
  345. * @cpu: cpu index which the channel should be close to
  346. *
  347. * If some channels are close to the given cpu, the one with the lowest
  348. * reference count is returned. Otherwise, cpu is ignored and only the
  349. * reference count is taken into account.
  350. * Must be called under dma_list_mutex.
  351. */
  352. static struct dma_chan *min_chan(enum dma_transaction_type cap, int cpu)
  353. {
  354. struct dma_device *device;
  355. struct dma_chan *chan;
  356. struct dma_chan *min = NULL;
  357. struct dma_chan *localmin = NULL;
  358. list_for_each_entry(device, &dma_device_list, global_node) {
  359. if (!dma_has_cap(cap, device->cap_mask) ||
  360. dma_has_cap(DMA_PRIVATE, device->cap_mask))
  361. continue;
  362. list_for_each_entry(chan, &device->channels, device_node) {
  363. if (!chan->client_count)
  364. continue;
  365. if (!min || chan->table_count < min->table_count)
  366. min = chan;
  367. if (dma_chan_is_local(chan, cpu))
  368. if (!localmin ||
  369. chan->table_count < localmin->table_count)
  370. localmin = chan;
  371. }
  372. }
  373. chan = localmin ? localmin : min;
  374. if (chan)
  375. chan->table_count++;
  376. return chan;
  377. }
  378. /**
  379. * dma_channel_rebalance - redistribute the available channels
  380. *
  381. * Optimize for cpu isolation (each cpu gets a dedicated channel for an
  382. * operation type) in the SMP case, and operation isolation (avoid
  383. * multi-tasking channels) in the non-SMP case. Must be called under
  384. * dma_list_mutex.
  385. */
  386. static void dma_channel_rebalance(void)
  387. {
  388. struct dma_chan *chan;
  389. struct dma_device *device;
  390. int cpu;
  391. int cap;
  392. /* undo the last distribution */
  393. for_each_dma_cap_mask(cap, dma_cap_mask_all)
  394. for_each_possible_cpu(cpu)
  395. per_cpu_ptr(channel_table[cap], cpu)->chan = NULL;
  396. list_for_each_entry(device, &dma_device_list, global_node) {
  397. if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
  398. continue;
  399. list_for_each_entry(chan, &device->channels, device_node)
  400. chan->table_count = 0;
  401. }
  402. /* don't populate the channel_table if no clients are available */
  403. if (!dmaengine_ref_count)
  404. return;
  405. /* redistribute available channels */
  406. for_each_dma_cap_mask(cap, dma_cap_mask_all)
  407. for_each_online_cpu(cpu) {
  408. chan = min_chan(cap, cpu);
  409. per_cpu_ptr(channel_table[cap], cpu)->chan = chan;
  410. }
  411. }
  412. static struct dma_chan *private_candidate(const dma_cap_mask_t *mask,
  413. struct dma_device *dev,
  414. dma_filter_fn fn, void *fn_param)
  415. {
  416. struct dma_chan *chan;
  417. if (!__dma_device_satisfies_mask(dev, mask)) {
  418. pr_debug("%s: wrong capabilities\n", __func__);
  419. return NULL;
  420. }
  421. /* devices with multiple channels need special handling as we need to
  422. * ensure that all channels are either private or public.
  423. */
  424. if (dev->chancnt > 1 && !dma_has_cap(DMA_PRIVATE, dev->cap_mask))
  425. list_for_each_entry(chan, &dev->channels, device_node) {
  426. /* some channels are already publicly allocated */
  427. if (chan->client_count)
  428. return NULL;
  429. }
  430. list_for_each_entry(chan, &dev->channels, device_node) {
  431. if (chan->client_count) {
  432. pr_debug("%s: %s busy\n",
  433. __func__, dma_chan_name(chan));
  434. continue;
  435. }
  436. if (fn && !fn(chan, fn_param)) {
  437. pr_debug("%s: %s filter said false\n",
  438. __func__, dma_chan_name(chan));
  439. continue;
  440. }
  441. return chan;
  442. }
  443. return NULL;
  444. }
  445. /**
  446. * dma_request_slave_channel - try to get specific channel exclusively
  447. * @chan: target channel
  448. */
  449. struct dma_chan *dma_get_slave_channel(struct dma_chan *chan)
  450. {
  451. int err = -EBUSY;
  452. /* lock against __dma_request_channel */
  453. mutex_lock(&dma_list_mutex);
  454. if (chan->client_count == 0) {
  455. err = dma_chan_get(chan);
  456. if (err)
  457. pr_debug("%s: failed to get %s: (%d)\n",
  458. __func__, dma_chan_name(chan), err);
  459. } else
  460. chan = NULL;
  461. mutex_unlock(&dma_list_mutex);
  462. return chan;
  463. }
  464. EXPORT_SYMBOL_GPL(dma_get_slave_channel);
  465. /**
  466. * __dma_request_channel - try to allocate an exclusive channel
  467. * @mask: capabilities that the channel must satisfy
  468. * @fn: optional callback to disposition available channels
  469. * @fn_param: opaque parameter to pass to dma_filter_fn
  470. */
  471. struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask,
  472. dma_filter_fn fn, void *fn_param)
  473. {
  474. struct dma_device *device, *_d;
  475. struct dma_chan *chan = NULL;
  476. int err;
  477. /* Find a channel */
  478. mutex_lock(&dma_list_mutex);
  479. list_for_each_entry_safe(device, _d, &dma_device_list, global_node) {
  480. chan = private_candidate(mask, device, fn, fn_param);
  481. if (chan) {
  482. /* Found a suitable channel, try to grab, prep, and
  483. * return it. We first set DMA_PRIVATE to disable
  484. * balance_ref_count as this channel will not be
  485. * published in the general-purpose allocator
  486. */
  487. dma_cap_set(DMA_PRIVATE, device->cap_mask);
  488. device->privatecnt++;
  489. err = dma_chan_get(chan);
  490. if (err == -ENODEV) {
  491. pr_debug("%s: %s module removed\n",
  492. __func__, dma_chan_name(chan));
  493. list_del_rcu(&device->global_node);
  494. } else if (err)
  495. pr_debug("%s: failed to get %s: (%d)\n",
  496. __func__, dma_chan_name(chan), err);
  497. else
  498. break;
  499. if (--device->privatecnt == 0)
  500. dma_cap_clear(DMA_PRIVATE, device->cap_mask);
  501. chan = NULL;
  502. }
  503. }
  504. mutex_unlock(&dma_list_mutex);
  505. pr_debug("%s: %s (%s)\n",
  506. __func__,
  507. chan ? "success" : "fail",
  508. chan ? dma_chan_name(chan) : NULL);
  509. return chan;
  510. }
  511. EXPORT_SYMBOL_GPL(__dma_request_channel);
  512. /**
  513. * dma_request_slave_channel - try to allocate an exclusive slave channel
  514. * @dev: pointer to client device structure
  515. * @name: slave channel name
  516. */
  517. struct dma_chan *dma_request_slave_channel(struct device *dev, const char *name)
  518. {
  519. /* If device-tree is present get slave info from here */
  520. if (dev->of_node)
  521. return of_dma_request_slave_channel(dev->of_node, name);
  522. /* If device was enumerated by ACPI get slave info from here */
  523. if (ACPI_HANDLE(dev))
  524. return acpi_dma_request_slave_chan_by_name(dev, name);
  525. return NULL;
  526. }
  527. EXPORT_SYMBOL_GPL(dma_request_slave_channel);
  528. void dma_release_channel(struct dma_chan *chan)
  529. {
  530. mutex_lock(&dma_list_mutex);
  531. WARN_ONCE(chan->client_count != 1,
  532. "chan reference count %d != 1\n", chan->client_count);
  533. dma_chan_put(chan);
  534. /* drop PRIVATE cap enabled by __dma_request_channel() */
  535. if (--chan->device->privatecnt == 0)
  536. dma_cap_clear(DMA_PRIVATE, chan->device->cap_mask);
  537. mutex_unlock(&dma_list_mutex);
  538. }
  539. EXPORT_SYMBOL_GPL(dma_release_channel);
  540. /**
  541. * dmaengine_get - register interest in dma_channels
  542. */
  543. void dmaengine_get(void)
  544. {
  545. struct dma_device *device, *_d;
  546. struct dma_chan *chan;
  547. int err;
  548. mutex_lock(&dma_list_mutex);
  549. dmaengine_ref_count++;
  550. /* try to grab channels */
  551. list_for_each_entry_safe(device, _d, &dma_device_list, global_node) {
  552. if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
  553. continue;
  554. list_for_each_entry(chan, &device->channels, device_node) {
  555. err = dma_chan_get(chan);
  556. if (err == -ENODEV) {
  557. /* module removed before we could use it */
  558. list_del_rcu(&device->global_node);
  559. break;
  560. } else if (err)
  561. pr_debug("%s: failed to get %s: (%d)\n",
  562. __func__, dma_chan_name(chan), err);
  563. }
  564. }
  565. /* if this is the first reference and there were channels
  566. * waiting we need to rebalance to get those channels
  567. * incorporated into the channel table
  568. */
  569. if (dmaengine_ref_count == 1)
  570. dma_channel_rebalance();
  571. mutex_unlock(&dma_list_mutex);
  572. }
  573. EXPORT_SYMBOL(dmaengine_get);
  574. /**
  575. * dmaengine_put - let dma drivers be removed when ref_count == 0
  576. */
  577. void dmaengine_put(void)
  578. {
  579. struct dma_device *device;
  580. struct dma_chan *chan;
  581. mutex_lock(&dma_list_mutex);
  582. dmaengine_ref_count--;
  583. BUG_ON(dmaengine_ref_count < 0);
  584. /* drop channel references */
  585. list_for_each_entry(device, &dma_device_list, global_node) {
  586. if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
  587. continue;
  588. list_for_each_entry(chan, &device->channels, device_node)
  589. dma_chan_put(chan);
  590. }
  591. mutex_unlock(&dma_list_mutex);
  592. }
  593. EXPORT_SYMBOL(dmaengine_put);
  594. static bool device_has_all_tx_types(struct dma_device *device)
  595. {
  596. /* A device that satisfies this test has channels that will never cause
  597. * an async_tx channel switch event as all possible operation types can
  598. * be handled.
  599. */
  600. #ifdef CONFIG_ASYNC_TX_DMA
  601. if (!dma_has_cap(DMA_INTERRUPT, device->cap_mask))
  602. return false;
  603. #endif
  604. #if defined(CONFIG_ASYNC_MEMCPY) || defined(CONFIG_ASYNC_MEMCPY_MODULE)
  605. if (!dma_has_cap(DMA_MEMCPY, device->cap_mask))
  606. return false;
  607. #endif
  608. #if defined(CONFIG_ASYNC_XOR) || defined(CONFIG_ASYNC_XOR_MODULE)
  609. if (!dma_has_cap(DMA_XOR, device->cap_mask))
  610. return false;
  611. #ifndef CONFIG_ASYNC_TX_DISABLE_XOR_VAL_DMA
  612. if (!dma_has_cap(DMA_XOR_VAL, device->cap_mask))
  613. return false;
  614. #endif
  615. #endif
  616. #if defined(CONFIG_ASYNC_PQ) || defined(CONFIG_ASYNC_PQ_MODULE)
  617. if (!dma_has_cap(DMA_PQ, device->cap_mask))
  618. return false;
  619. #ifndef CONFIG_ASYNC_TX_DISABLE_PQ_VAL_DMA
  620. if (!dma_has_cap(DMA_PQ_VAL, device->cap_mask))
  621. return false;
  622. #endif
  623. #endif
  624. return true;
  625. }
  626. static int get_dma_id(struct dma_device *device)
  627. {
  628. int rc;
  629. mutex_lock(&dma_list_mutex);
  630. rc = idr_alloc(&dma_idr, NULL, 0, 0, GFP_KERNEL);
  631. if (rc >= 0)
  632. device->dev_id = rc;
  633. mutex_unlock(&dma_list_mutex);
  634. return rc < 0 ? rc : 0;
  635. }
  636. /**
  637. * dma_async_device_register - registers DMA devices found
  638. * @device: &dma_device
  639. */
  640. int dma_async_device_register(struct dma_device *device)
  641. {
  642. int chancnt = 0, rc;
  643. struct dma_chan* chan;
  644. atomic_t *idr_ref;
  645. if (!device)
  646. return -ENODEV;
  647. /* validate device routines */
  648. BUG_ON(dma_has_cap(DMA_MEMCPY, device->cap_mask) &&
  649. !device->device_prep_dma_memcpy);
  650. BUG_ON(dma_has_cap(DMA_XOR, device->cap_mask) &&
  651. !device->device_prep_dma_xor);
  652. BUG_ON(dma_has_cap(DMA_XOR_VAL, device->cap_mask) &&
  653. !device->device_prep_dma_xor_val);
  654. BUG_ON(dma_has_cap(DMA_PQ, device->cap_mask) &&
  655. !device->device_prep_dma_pq);
  656. BUG_ON(dma_has_cap(DMA_PQ_VAL, device->cap_mask) &&
  657. !device->device_prep_dma_pq_val);
  658. BUG_ON(dma_has_cap(DMA_INTERRUPT, device->cap_mask) &&
  659. !device->device_prep_dma_interrupt);
  660. BUG_ON(dma_has_cap(DMA_SG, device->cap_mask) &&
  661. !device->device_prep_dma_sg);
  662. BUG_ON(dma_has_cap(DMA_CYCLIC, device->cap_mask) &&
  663. !device->device_prep_dma_cyclic);
  664. BUG_ON(dma_has_cap(DMA_SLAVE, device->cap_mask) &&
  665. !device->device_control);
  666. BUG_ON(dma_has_cap(DMA_INTERLEAVE, device->cap_mask) &&
  667. !device->device_prep_interleaved_dma);
  668. BUG_ON(!device->device_alloc_chan_resources);
  669. BUG_ON(!device->device_free_chan_resources);
  670. BUG_ON(!device->device_tx_status);
  671. BUG_ON(!device->device_issue_pending);
  672. BUG_ON(!device->dev);
  673. /* note: this only matters in the
  674. * CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH=n case
  675. */
  676. if (device_has_all_tx_types(device))
  677. dma_cap_set(DMA_ASYNC_TX, device->cap_mask);
  678. idr_ref = kmalloc(sizeof(*idr_ref), GFP_KERNEL);
  679. if (!idr_ref)
  680. return -ENOMEM;
  681. rc = get_dma_id(device);
  682. if (rc != 0) {
  683. kfree(idr_ref);
  684. return rc;
  685. }
  686. atomic_set(idr_ref, 0);
  687. /* represent channels in sysfs. Probably want devs too */
  688. list_for_each_entry(chan, &device->channels, device_node) {
  689. rc = -ENOMEM;
  690. chan->local = alloc_percpu(typeof(*chan->local));
  691. if (chan->local == NULL)
  692. goto err_out;
  693. chan->dev = kzalloc(sizeof(*chan->dev), GFP_KERNEL);
  694. if (chan->dev == NULL) {
  695. free_percpu(chan->local);
  696. chan->local = NULL;
  697. goto err_out;
  698. }
  699. chan->chan_id = chancnt++;
  700. chan->dev->device.class = &dma_devclass;
  701. chan->dev->device.parent = device->dev;
  702. chan->dev->chan = chan;
  703. chan->dev->idr_ref = idr_ref;
  704. chan->dev->dev_id = device->dev_id;
  705. atomic_inc(idr_ref);
  706. dev_set_name(&chan->dev->device, "dma%dchan%d",
  707. device->dev_id, chan->chan_id);
  708. rc = device_register(&chan->dev->device);
  709. if (rc) {
  710. free_percpu(chan->local);
  711. chan->local = NULL;
  712. kfree(chan->dev);
  713. atomic_dec(idr_ref);
  714. goto err_out;
  715. }
  716. chan->client_count = 0;
  717. }
  718. device->chancnt = chancnt;
  719. mutex_lock(&dma_list_mutex);
  720. /* take references on public channels */
  721. if (dmaengine_ref_count && !dma_has_cap(DMA_PRIVATE, device->cap_mask))
  722. list_for_each_entry(chan, &device->channels, device_node) {
  723. /* if clients are already waiting for channels we need
  724. * to take references on their behalf
  725. */
  726. if (dma_chan_get(chan) == -ENODEV) {
  727. /* note we can only get here for the first
  728. * channel as the remaining channels are
  729. * guaranteed to get a reference
  730. */
  731. rc = -ENODEV;
  732. mutex_unlock(&dma_list_mutex);
  733. goto err_out;
  734. }
  735. }
  736. list_add_tail_rcu(&device->global_node, &dma_device_list);
  737. if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
  738. device->privatecnt++; /* Always private */
  739. dma_channel_rebalance();
  740. mutex_unlock(&dma_list_mutex);
  741. return 0;
  742. err_out:
  743. /* if we never registered a channel just release the idr */
  744. if (atomic_read(idr_ref) == 0) {
  745. mutex_lock(&dma_list_mutex);
  746. idr_remove(&dma_idr, device->dev_id);
  747. mutex_unlock(&dma_list_mutex);
  748. kfree(idr_ref);
  749. return rc;
  750. }
  751. list_for_each_entry(chan, &device->channels, device_node) {
  752. if (chan->local == NULL)
  753. continue;
  754. mutex_lock(&dma_list_mutex);
  755. chan->dev->chan = NULL;
  756. mutex_unlock(&dma_list_mutex);
  757. device_unregister(&chan->dev->device);
  758. free_percpu(chan->local);
  759. }
  760. return rc;
  761. }
  762. EXPORT_SYMBOL(dma_async_device_register);
  763. /**
  764. * dma_async_device_unregister - unregister a DMA device
  765. * @device: &dma_device
  766. *
  767. * This routine is called by dma driver exit routines, dmaengine holds module
  768. * references to prevent it being called while channels are in use.
  769. */
  770. void dma_async_device_unregister(struct dma_device *device)
  771. {
  772. struct dma_chan *chan;
  773. mutex_lock(&dma_list_mutex);
  774. list_del_rcu(&device->global_node);
  775. dma_channel_rebalance();
  776. mutex_unlock(&dma_list_mutex);
  777. list_for_each_entry(chan, &device->channels, device_node) {
  778. WARN_ONCE(chan->client_count,
  779. "%s called while %d clients hold a reference\n",
  780. __func__, chan->client_count);
  781. mutex_lock(&dma_list_mutex);
  782. chan->dev->chan = NULL;
  783. mutex_unlock(&dma_list_mutex);
  784. device_unregister(&chan->dev->device);
  785. free_percpu(chan->local);
  786. }
  787. }
  788. EXPORT_SYMBOL(dma_async_device_unregister);
  789. struct dmaengine_unmap_pool {
  790. struct kmem_cache *cache;
  791. const char *name;
  792. mempool_t *pool;
  793. size_t size;
  794. };
  795. #define __UNMAP_POOL(x) { .size = x, .name = "dmaengine-unmap-" __stringify(x) }
  796. static struct dmaengine_unmap_pool unmap_pool[] = {
  797. __UNMAP_POOL(2),
  798. #if IS_ENABLED(CONFIG_ASYNC_TX_DMA)
  799. __UNMAP_POOL(16),
  800. __UNMAP_POOL(128),
  801. __UNMAP_POOL(256),
  802. #endif
  803. };
  804. static struct dmaengine_unmap_pool *__get_unmap_pool(int nr)
  805. {
  806. int order = get_count_order(nr);
  807. switch (order) {
  808. case 0 ... 1:
  809. return &unmap_pool[0];
  810. case 2 ... 4:
  811. return &unmap_pool[1];
  812. case 5 ... 7:
  813. return &unmap_pool[2];
  814. case 8:
  815. return &unmap_pool[3];
  816. default:
  817. BUG();
  818. return NULL;
  819. }
  820. }
  821. static void dmaengine_unmap(struct kref *kref)
  822. {
  823. struct dmaengine_unmap_data *unmap = container_of(kref, typeof(*unmap), kref);
  824. struct device *dev = unmap->dev;
  825. int cnt, i;
  826. cnt = unmap->to_cnt;
  827. for (i = 0; i < cnt; i++)
  828. dma_unmap_page(dev, unmap->addr[i], unmap->len,
  829. DMA_TO_DEVICE);
  830. cnt += unmap->from_cnt;
  831. for (; i < cnt; i++)
  832. dma_unmap_page(dev, unmap->addr[i], unmap->len,
  833. DMA_FROM_DEVICE);
  834. cnt += unmap->bidi_cnt;
  835. for (; i < cnt; i++) {
  836. if (unmap->addr[i] == 0)
  837. continue;
  838. dma_unmap_page(dev, unmap->addr[i], unmap->len,
  839. DMA_BIDIRECTIONAL);
  840. }
  841. mempool_free(unmap, __get_unmap_pool(cnt)->pool);
  842. }
  843. void dmaengine_unmap_put(struct dmaengine_unmap_data *unmap)
  844. {
  845. if (unmap)
  846. kref_put(&unmap->kref, dmaengine_unmap);
  847. }
  848. EXPORT_SYMBOL_GPL(dmaengine_unmap_put);
  849. static void dmaengine_destroy_unmap_pool(void)
  850. {
  851. int i;
  852. for (i = 0; i < ARRAY_SIZE(unmap_pool); i++) {
  853. struct dmaengine_unmap_pool *p = &unmap_pool[i];
  854. if (p->pool)
  855. mempool_destroy(p->pool);
  856. p->pool = NULL;
  857. if (p->cache)
  858. kmem_cache_destroy(p->cache);
  859. p->cache = NULL;
  860. }
  861. }
  862. static int __init dmaengine_init_unmap_pool(void)
  863. {
  864. int i;
  865. for (i = 0; i < ARRAY_SIZE(unmap_pool); i++) {
  866. struct dmaengine_unmap_pool *p = &unmap_pool[i];
  867. size_t size;
  868. size = sizeof(struct dmaengine_unmap_data) +
  869. sizeof(dma_addr_t) * p->size;
  870. p->cache = kmem_cache_create(p->name, size, 0,
  871. SLAB_HWCACHE_ALIGN, NULL);
  872. if (!p->cache)
  873. break;
  874. p->pool = mempool_create_slab_pool(1, p->cache);
  875. if (!p->pool)
  876. break;
  877. }
  878. if (i == ARRAY_SIZE(unmap_pool))
  879. return 0;
  880. dmaengine_destroy_unmap_pool();
  881. return -ENOMEM;
  882. }
  883. struct dmaengine_unmap_data *
  884. dmaengine_get_unmap_data(struct device *dev, int nr, gfp_t flags)
  885. {
  886. struct dmaengine_unmap_data *unmap;
  887. unmap = mempool_alloc(__get_unmap_pool(nr)->pool, flags);
  888. if (!unmap)
  889. return NULL;
  890. memset(unmap, 0, sizeof(*unmap));
  891. kref_init(&unmap->kref);
  892. unmap->dev = dev;
  893. return unmap;
  894. }
  895. EXPORT_SYMBOL(dmaengine_get_unmap_data);
  896. /**
  897. * dma_async_memcpy_pg_to_pg - offloaded copy from page to page
  898. * @chan: DMA channel to offload copy to
  899. * @dest_pg: destination page
  900. * @dest_off: offset in page to copy to
  901. * @src_pg: source page
  902. * @src_off: offset in page to copy from
  903. * @len: length
  904. *
  905. * Both @dest_page/@dest_off and @src_page/@src_off must be mappable to a bus
  906. * address according to the DMA mapping API rules for streaming mappings.
  907. * Both @dest_page/@dest_off and @src_page/@src_off must stay memory resident
  908. * (kernel memory or locked user space pages).
  909. */
  910. dma_cookie_t
  911. dma_async_memcpy_pg_to_pg(struct dma_chan *chan, struct page *dest_pg,
  912. unsigned int dest_off, struct page *src_pg, unsigned int src_off,
  913. size_t len)
  914. {
  915. struct dma_device *dev = chan->device;
  916. struct dma_async_tx_descriptor *tx;
  917. struct dmaengine_unmap_data *unmap;
  918. dma_cookie_t cookie;
  919. unsigned long flags;
  920. unmap = dmaengine_get_unmap_data(dev->dev, 2, GFP_NOIO);
  921. if (!unmap)
  922. return -ENOMEM;
  923. unmap->to_cnt = 1;
  924. unmap->from_cnt = 1;
  925. unmap->addr[0] = dma_map_page(dev->dev, src_pg, src_off, len,
  926. DMA_TO_DEVICE);
  927. unmap->addr[1] = dma_map_page(dev->dev, dest_pg, dest_off, len,
  928. DMA_FROM_DEVICE);
  929. unmap->len = len;
  930. flags = DMA_CTRL_ACK;
  931. tx = dev->device_prep_dma_memcpy(chan, unmap->addr[1], unmap->addr[0],
  932. len, flags);
  933. if (!tx) {
  934. dmaengine_unmap_put(unmap);
  935. return -ENOMEM;
  936. }
  937. dma_set_unmap(tx, unmap);
  938. cookie = tx->tx_submit(tx);
  939. dmaengine_unmap_put(unmap);
  940. preempt_disable();
  941. __this_cpu_add(chan->local->bytes_transferred, len);
  942. __this_cpu_inc(chan->local->memcpy_count);
  943. preempt_enable();
  944. return cookie;
  945. }
  946. EXPORT_SYMBOL(dma_async_memcpy_pg_to_pg);
  947. /**
  948. * dma_async_memcpy_buf_to_buf - offloaded copy between virtual addresses
  949. * @chan: DMA channel to offload copy to
  950. * @dest: destination address (virtual)
  951. * @src: source address (virtual)
  952. * @len: length
  953. *
  954. * Both @dest and @src must be mappable to a bus address according to the
  955. * DMA mapping API rules for streaming mappings.
  956. * Both @dest and @src must stay memory resident (kernel memory or locked
  957. * user space pages).
  958. */
  959. dma_cookie_t
  960. dma_async_memcpy_buf_to_buf(struct dma_chan *chan, void *dest,
  961. void *src, size_t len)
  962. {
  963. return dma_async_memcpy_pg_to_pg(chan, virt_to_page(dest),
  964. (unsigned long) dest & ~PAGE_MASK,
  965. virt_to_page(src),
  966. (unsigned long) src & ~PAGE_MASK, len);
  967. }
  968. EXPORT_SYMBOL(dma_async_memcpy_buf_to_buf);
  969. /**
  970. * dma_async_memcpy_buf_to_pg - offloaded copy from address to page
  971. * @chan: DMA channel to offload copy to
  972. * @page: destination page
  973. * @offset: offset in page to copy to
  974. * @kdata: source address (virtual)
  975. * @len: length
  976. *
  977. * Both @page/@offset and @kdata must be mappable to a bus address according
  978. * to the DMA mapping API rules for streaming mappings.
  979. * Both @page/@offset and @kdata must stay memory resident (kernel memory or
  980. * locked user space pages)
  981. */
  982. dma_cookie_t
  983. dma_async_memcpy_buf_to_pg(struct dma_chan *chan, struct page *page,
  984. unsigned int offset, void *kdata, size_t len)
  985. {
  986. return dma_async_memcpy_pg_to_pg(chan, page, offset,
  987. virt_to_page(kdata),
  988. (unsigned long) kdata & ~PAGE_MASK, len);
  989. }
  990. EXPORT_SYMBOL(dma_async_memcpy_buf_to_pg);
  991. void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx,
  992. struct dma_chan *chan)
  993. {
  994. tx->chan = chan;
  995. #ifdef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
  996. spin_lock_init(&tx->lock);
  997. #endif
  998. }
  999. EXPORT_SYMBOL(dma_async_tx_descriptor_init);
  1000. /* dma_wait_for_async_tx - spin wait for a transaction to complete
  1001. * @tx: in-flight transaction to wait on
  1002. */
  1003. enum dma_status
  1004. dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx)
  1005. {
  1006. unsigned long dma_sync_wait_timeout = jiffies + msecs_to_jiffies(5000);
  1007. if (!tx)
  1008. return DMA_COMPLETE;
  1009. while (tx->cookie == -EBUSY) {
  1010. if (time_after_eq(jiffies, dma_sync_wait_timeout)) {
  1011. pr_err("%s timeout waiting for descriptor submission\n",
  1012. __func__);
  1013. return DMA_ERROR;
  1014. }
  1015. cpu_relax();
  1016. }
  1017. return dma_sync_wait(tx->chan, tx->cookie);
  1018. }
  1019. EXPORT_SYMBOL_GPL(dma_wait_for_async_tx);
  1020. /* dma_run_dependencies - helper routine for dma drivers to process
  1021. * (start) dependent operations on their target channel
  1022. * @tx: transaction with dependencies
  1023. */
  1024. void dma_run_dependencies(struct dma_async_tx_descriptor *tx)
  1025. {
  1026. struct dma_async_tx_descriptor *dep = txd_next(tx);
  1027. struct dma_async_tx_descriptor *dep_next;
  1028. struct dma_chan *chan;
  1029. if (!dep)
  1030. return;
  1031. /* we'll submit tx->next now, so clear the link */
  1032. txd_clear_next(tx);
  1033. chan = dep->chan;
  1034. /* keep submitting up until a channel switch is detected
  1035. * in that case we will be called again as a result of
  1036. * processing the interrupt from async_tx_channel_switch
  1037. */
  1038. for (; dep; dep = dep_next) {
  1039. txd_lock(dep);
  1040. txd_clear_parent(dep);
  1041. dep_next = txd_next(dep);
  1042. if (dep_next && dep_next->chan == chan)
  1043. txd_clear_next(dep); /* ->next will be submitted */
  1044. else
  1045. dep_next = NULL; /* submit current dep and terminate */
  1046. txd_unlock(dep);
  1047. dep->tx_submit(dep);
  1048. }
  1049. chan->device->device_issue_pending(chan);
  1050. }
  1051. EXPORT_SYMBOL_GPL(dma_run_dependencies);
  1052. static int __init dma_bus_init(void)
  1053. {
  1054. int err = dmaengine_init_unmap_pool();
  1055. if (err)
  1056. return err;
  1057. return class_register(&dma_devclass);
  1058. }
  1059. arch_initcall(dma_bus_init);