cx88-dvb.c 24 KB

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  1. /*
  2. *
  3. * device driver for Conexant 2388x based TV cards
  4. * MPEG Transport Stream (DVB) routines
  5. *
  6. * (c) 2004, 2005 Chris Pascoe <c.pascoe@itee.uq.edu.au>
  7. * (c) 2004 Gerd Knorr <kraxel@bytesex.org> [SuSE Labs]
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License as published by
  11. * the Free Software Foundation; either version 2 of the License, or
  12. * (at your option) any later version.
  13. *
  14. * This program is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * You should have received a copy of the GNU General Public License
  20. * along with this program; if not, write to the Free Software
  21. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  22. */
  23. #include <linux/module.h>
  24. #include <linux/init.h>
  25. #include <linux/device.h>
  26. #include <linux/fs.h>
  27. #include <linux/kthread.h>
  28. #include <linux/file.h>
  29. #include <linux/suspend.h>
  30. #include "cx88.h"
  31. #include "dvb-pll.h"
  32. #include <media/v4l2-common.h>
  33. #include "mt352.h"
  34. #include "mt352_priv.h"
  35. #if defined(CONFIG_VIDEO_CX88_VP3054) || defined(CONFIG_VIDEO_CX88_VP3054_MODULE)
  36. # include "cx88-vp3054-i2c.h"
  37. #endif
  38. #include "zl10353.h"
  39. #include "cx22702.h"
  40. #include "or51132.h"
  41. #include "lgdt330x.h"
  42. #include "lgh06xf.h"
  43. #include "nxt200x.h"
  44. #include "cx24123.h"
  45. #include "isl6421.h"
  46. MODULE_DESCRIPTION("driver for cx2388x based DVB cards");
  47. MODULE_AUTHOR("Chris Pascoe <c.pascoe@itee.uq.edu.au>");
  48. MODULE_AUTHOR("Gerd Knorr <kraxel@bytesex.org> [SuSE Labs]");
  49. MODULE_LICENSE("GPL");
  50. static unsigned int debug = 0;
  51. module_param(debug, int, 0644);
  52. MODULE_PARM_DESC(debug,"enable debug messages [dvb]");
  53. #define dprintk(level,fmt, arg...) if (debug >= level) \
  54. printk(KERN_DEBUG "%s/2-dvb: " fmt, core->name, ## arg)
  55. /* ------------------------------------------------------------------ */
  56. static int dvb_buf_setup(struct videobuf_queue *q,
  57. unsigned int *count, unsigned int *size)
  58. {
  59. struct cx8802_dev *dev = q->priv_data;
  60. dev->ts_packet_size = 188 * 4;
  61. dev->ts_packet_count = 32;
  62. *size = dev->ts_packet_size * dev->ts_packet_count;
  63. *count = 32;
  64. return 0;
  65. }
  66. static int dvb_buf_prepare(struct videobuf_queue *q,
  67. struct videobuf_buffer *vb, enum v4l2_field field)
  68. {
  69. struct cx8802_dev *dev = q->priv_data;
  70. return cx8802_buf_prepare(q, dev, (struct cx88_buffer*)vb,field);
  71. }
  72. static void dvb_buf_queue(struct videobuf_queue *q, struct videobuf_buffer *vb)
  73. {
  74. struct cx8802_dev *dev = q->priv_data;
  75. cx8802_buf_queue(dev, (struct cx88_buffer*)vb);
  76. }
  77. static void dvb_buf_release(struct videobuf_queue *q,
  78. struct videobuf_buffer *vb)
  79. {
  80. cx88_free_buffer(q, (struct cx88_buffer*)vb);
  81. }
  82. static struct videobuf_queue_ops dvb_qops = {
  83. .buf_setup = dvb_buf_setup,
  84. .buf_prepare = dvb_buf_prepare,
  85. .buf_queue = dvb_buf_queue,
  86. .buf_release = dvb_buf_release,
  87. };
  88. /* ------------------------------------------------------------------ */
  89. static int cx88_dvb_bus_ctrl(struct dvb_frontend* fe, int acquire)
  90. {
  91. struct cx8802_dev *dev= fe->dvb->priv;
  92. struct cx8802_driver *drv = NULL;
  93. int ret = 0;
  94. drv = cx8802_get_driver(dev, CX88_MPEG_DVB);
  95. if (drv) {
  96. if (acquire)
  97. ret = drv->request_acquire(drv);
  98. else
  99. ret = drv->request_release(drv);
  100. }
  101. return ret;
  102. }
  103. /* ------------------------------------------------------------------ */
  104. static int dvico_fusionhdtv_demod_init(struct dvb_frontend* fe)
  105. {
  106. static u8 clock_config [] = { CLOCK_CTL, 0x38, 0x39 };
  107. static u8 reset [] = { RESET, 0x80 };
  108. static u8 adc_ctl_1_cfg [] = { ADC_CTL_1, 0x40 };
  109. static u8 agc_cfg [] = { AGC_TARGET, 0x24, 0x20 };
  110. static u8 gpp_ctl_cfg [] = { GPP_CTL, 0x33 };
  111. static u8 capt_range_cfg[] = { CAPT_RANGE, 0x32 };
  112. mt352_write(fe, clock_config, sizeof(clock_config));
  113. udelay(200);
  114. mt352_write(fe, reset, sizeof(reset));
  115. mt352_write(fe, adc_ctl_1_cfg, sizeof(adc_ctl_1_cfg));
  116. mt352_write(fe, agc_cfg, sizeof(agc_cfg));
  117. mt352_write(fe, gpp_ctl_cfg, sizeof(gpp_ctl_cfg));
  118. mt352_write(fe, capt_range_cfg, sizeof(capt_range_cfg));
  119. return 0;
  120. }
  121. static int dvico_dual_demod_init(struct dvb_frontend *fe)
  122. {
  123. static u8 clock_config [] = { CLOCK_CTL, 0x38, 0x38 };
  124. static u8 reset [] = { RESET, 0x80 };
  125. static u8 adc_ctl_1_cfg [] = { ADC_CTL_1, 0x40 };
  126. static u8 agc_cfg [] = { AGC_TARGET, 0x28, 0x20 };
  127. static u8 gpp_ctl_cfg [] = { GPP_CTL, 0x33 };
  128. static u8 capt_range_cfg[] = { CAPT_RANGE, 0x32 };
  129. mt352_write(fe, clock_config, sizeof(clock_config));
  130. udelay(200);
  131. mt352_write(fe, reset, sizeof(reset));
  132. mt352_write(fe, adc_ctl_1_cfg, sizeof(adc_ctl_1_cfg));
  133. mt352_write(fe, agc_cfg, sizeof(agc_cfg));
  134. mt352_write(fe, gpp_ctl_cfg, sizeof(gpp_ctl_cfg));
  135. mt352_write(fe, capt_range_cfg, sizeof(capt_range_cfg));
  136. return 0;
  137. }
  138. static int dntv_live_dvbt_demod_init(struct dvb_frontend* fe)
  139. {
  140. static u8 clock_config [] = { 0x89, 0x38, 0x39 };
  141. static u8 reset [] = { 0x50, 0x80 };
  142. static u8 adc_ctl_1_cfg [] = { 0x8E, 0x40 };
  143. static u8 agc_cfg [] = { 0x67, 0x10, 0x23, 0x00, 0xFF, 0xFF,
  144. 0x00, 0xFF, 0x00, 0x40, 0x40 };
  145. static u8 dntv_extra[] = { 0xB5, 0x7A };
  146. static u8 capt_range_cfg[] = { 0x75, 0x32 };
  147. mt352_write(fe, clock_config, sizeof(clock_config));
  148. udelay(2000);
  149. mt352_write(fe, reset, sizeof(reset));
  150. mt352_write(fe, adc_ctl_1_cfg, sizeof(adc_ctl_1_cfg));
  151. mt352_write(fe, agc_cfg, sizeof(agc_cfg));
  152. udelay(2000);
  153. mt352_write(fe, dntv_extra, sizeof(dntv_extra));
  154. mt352_write(fe, capt_range_cfg, sizeof(capt_range_cfg));
  155. return 0;
  156. }
  157. static struct mt352_config dvico_fusionhdtv = {
  158. .demod_address = 0x0f,
  159. .demod_init = dvico_fusionhdtv_demod_init,
  160. };
  161. static struct mt352_config dntv_live_dvbt_config = {
  162. .demod_address = 0x0f,
  163. .demod_init = dntv_live_dvbt_demod_init,
  164. };
  165. static struct mt352_config dvico_fusionhdtv_dual = {
  166. .demod_address = 0x0f,
  167. .demod_init = dvico_dual_demod_init,
  168. };
  169. #if defined(CONFIG_VIDEO_CX88_VP3054) || defined(CONFIG_VIDEO_CX88_VP3054_MODULE)
  170. static int dntv_live_dvbt_pro_demod_init(struct dvb_frontend* fe)
  171. {
  172. static u8 clock_config [] = { 0x89, 0x38, 0x38 };
  173. static u8 reset [] = { 0x50, 0x80 };
  174. static u8 adc_ctl_1_cfg [] = { 0x8E, 0x40 };
  175. static u8 agc_cfg [] = { 0x67, 0x10, 0x20, 0x00, 0xFF, 0xFF,
  176. 0x00, 0xFF, 0x00, 0x40, 0x40 };
  177. static u8 dntv_extra[] = { 0xB5, 0x7A };
  178. static u8 capt_range_cfg[] = { 0x75, 0x32 };
  179. mt352_write(fe, clock_config, sizeof(clock_config));
  180. udelay(2000);
  181. mt352_write(fe, reset, sizeof(reset));
  182. mt352_write(fe, adc_ctl_1_cfg, sizeof(adc_ctl_1_cfg));
  183. mt352_write(fe, agc_cfg, sizeof(agc_cfg));
  184. udelay(2000);
  185. mt352_write(fe, dntv_extra, sizeof(dntv_extra));
  186. mt352_write(fe, capt_range_cfg, sizeof(capt_range_cfg));
  187. return 0;
  188. }
  189. static int philips_fmd1216_pll_init(struct dvb_frontend *fe)
  190. {
  191. struct cx8802_dev *dev= fe->dvb->priv;
  192. /* this message is to set up ATC and ALC */
  193. static u8 fmd1216_init[] = { 0x0b, 0xdc, 0x9c, 0xa0 };
  194. struct i2c_msg msg =
  195. { .addr = dev->core->pll_addr, .flags = 0,
  196. .buf = fmd1216_init, .len = sizeof(fmd1216_init) };
  197. int err;
  198. if (fe->ops.i2c_gate_ctrl)
  199. fe->ops.i2c_gate_ctrl(fe, 1);
  200. if ((err = i2c_transfer(&dev->core->i2c_adap, &msg, 1)) != 1) {
  201. if (err < 0)
  202. return err;
  203. else
  204. return -EREMOTEIO;
  205. }
  206. return 0;
  207. }
  208. static int dntv_live_dvbt_pro_tuner_set_params(struct dvb_frontend* fe,
  209. struct dvb_frontend_parameters* params)
  210. {
  211. struct cx8802_dev *dev= fe->dvb->priv;
  212. u8 buf[4];
  213. struct i2c_msg msg =
  214. { .addr = dev->core->pll_addr, .flags = 0,
  215. .buf = buf, .len = 4 };
  216. int err;
  217. /* Switch PLL to DVB mode */
  218. err = philips_fmd1216_pll_init(fe);
  219. if (err)
  220. return err;
  221. /* Tune PLL */
  222. dvb_pll_configure(dev->core->pll_desc, buf,
  223. params->frequency,
  224. params->u.ofdm.bandwidth);
  225. if (fe->ops.i2c_gate_ctrl)
  226. fe->ops.i2c_gate_ctrl(fe, 1);
  227. if ((err = i2c_transfer(&dev->core->i2c_adap, &msg, 1)) != 1) {
  228. printk(KERN_WARNING "cx88-dvb: %s error "
  229. "(addr %02x <- %02x, err = %i)\n",
  230. __FUNCTION__, dev->core->pll_addr, buf[0], err);
  231. if (err < 0)
  232. return err;
  233. else
  234. return -EREMOTEIO;
  235. }
  236. return 0;
  237. }
  238. static struct mt352_config dntv_live_dvbt_pro_config = {
  239. .demod_address = 0x0f,
  240. .no_tuner = 1,
  241. .demod_init = dntv_live_dvbt_pro_demod_init,
  242. };
  243. #endif
  244. static struct zl10353_config dvico_fusionhdtv_hybrid = {
  245. .demod_address = 0x0f,
  246. .no_tuner = 1,
  247. };
  248. static struct zl10353_config dvico_fusionhdtv_plus_v1_1 = {
  249. .demod_address = 0x0f,
  250. };
  251. static struct cx22702_config connexant_refboard_config = {
  252. .demod_address = 0x43,
  253. .output_mode = CX22702_SERIAL_OUTPUT,
  254. };
  255. static struct cx22702_config hauppauge_hvr_config = {
  256. .demod_address = 0x63,
  257. .output_mode = CX22702_SERIAL_OUTPUT,
  258. };
  259. static int or51132_set_ts_param(struct dvb_frontend* fe, int is_punctured)
  260. {
  261. struct cx8802_dev *dev= fe->dvb->priv;
  262. dev->ts_gen_cntrl = is_punctured ? 0x04 : 0x00;
  263. return 0;
  264. }
  265. static struct or51132_config pchdtv_hd3000 = {
  266. .demod_address = 0x15,
  267. .set_ts_params = or51132_set_ts_param,
  268. };
  269. static int lgdt330x_pll_rf_set(struct dvb_frontend* fe, int index)
  270. {
  271. struct cx8802_dev *dev= fe->dvb->priv;
  272. struct cx88_core *core = dev->core;
  273. dprintk(1, "%s: index = %d\n", __FUNCTION__, index);
  274. if (index == 0)
  275. cx_clear(MO_GP0_IO, 8);
  276. else
  277. cx_set(MO_GP0_IO, 8);
  278. return 0;
  279. }
  280. static int lgdt330x_set_ts_param(struct dvb_frontend* fe, int is_punctured)
  281. {
  282. struct cx8802_dev *dev= fe->dvb->priv;
  283. if (is_punctured)
  284. dev->ts_gen_cntrl |= 0x04;
  285. else
  286. dev->ts_gen_cntrl &= ~0x04;
  287. return 0;
  288. }
  289. static struct lgdt330x_config fusionhdtv_3_gold = {
  290. .demod_address = 0x0e,
  291. .demod_chip = LGDT3302,
  292. .serial_mpeg = 0x04, /* TPSERIAL for 3302 in TOP_CONTROL */
  293. .set_ts_params = lgdt330x_set_ts_param,
  294. };
  295. static struct lgdt330x_config fusionhdtv_5_gold = {
  296. .demod_address = 0x0e,
  297. .demod_chip = LGDT3303,
  298. .serial_mpeg = 0x40, /* TPSERIAL for 3303 in TOP_CONTROL */
  299. .set_ts_params = lgdt330x_set_ts_param,
  300. };
  301. static struct lgdt330x_config pchdtv_hd5500 = {
  302. .demod_address = 0x59,
  303. .demod_chip = LGDT3303,
  304. .serial_mpeg = 0x40, /* TPSERIAL for 3303 in TOP_CONTROL */
  305. .set_ts_params = lgdt330x_set_ts_param,
  306. };
  307. static int nxt200x_set_ts_param(struct dvb_frontend* fe, int is_punctured)
  308. {
  309. struct cx8802_dev *dev= fe->dvb->priv;
  310. dev->ts_gen_cntrl = is_punctured ? 0x04 : 0x00;
  311. return 0;
  312. }
  313. static int nxt200x_set_pll_input(u8* buf, int input)
  314. {
  315. if (input)
  316. buf[3] |= 0x08;
  317. else
  318. buf[3] &= ~0x08;
  319. return 0;
  320. }
  321. static struct nxt200x_config ati_hdtvwonder = {
  322. .demod_address = 0x0a,
  323. .set_pll_input = nxt200x_set_pll_input,
  324. .set_ts_params = nxt200x_set_ts_param,
  325. };
  326. static int cx24123_set_ts_param(struct dvb_frontend* fe,
  327. int is_punctured)
  328. {
  329. struct cx8802_dev *dev= fe->dvb->priv;
  330. dev->ts_gen_cntrl = 0x02;
  331. return 0;
  332. }
  333. static int kworld_dvbs_100_set_voltage(struct dvb_frontend* fe,
  334. fe_sec_voltage_t voltage)
  335. {
  336. struct cx8802_dev *dev= fe->dvb->priv;
  337. struct cx88_core *core = dev->core;
  338. if (voltage == SEC_VOLTAGE_OFF)
  339. cx_write(MO_GP0_IO, 0x000006fb);
  340. else
  341. cx_write(MO_GP0_IO, 0x000006f9);
  342. if (core->prev_set_voltage)
  343. return core->prev_set_voltage(fe, voltage);
  344. return 0;
  345. }
  346. static int geniatech_dvbs_set_voltage(struct dvb_frontend *fe,
  347. fe_sec_voltage_t voltage)
  348. {
  349. struct cx8802_dev *dev= fe->dvb->priv;
  350. struct cx88_core *core = dev->core;
  351. if (voltage == SEC_VOLTAGE_OFF) {
  352. dprintk(1,"LNB Voltage OFF\n");
  353. cx_write(MO_GP0_IO, 0x0000efff);
  354. }
  355. if (core->prev_set_voltage)
  356. return core->prev_set_voltage(fe, voltage);
  357. return 0;
  358. }
  359. static struct cx24123_config geniatech_dvbs_config = {
  360. .demod_address = 0x55,
  361. .set_ts_params = cx24123_set_ts_param,
  362. };
  363. static struct cx24123_config hauppauge_novas_config = {
  364. .demod_address = 0x55,
  365. .set_ts_params = cx24123_set_ts_param,
  366. };
  367. static struct cx24123_config kworld_dvbs_100_config = {
  368. .demod_address = 0x15,
  369. .set_ts_params = cx24123_set_ts_param,
  370. .lnb_polarity = 1,
  371. };
  372. static int dvb_register(struct cx8802_dev *dev)
  373. {
  374. /* init struct videobuf_dvb */
  375. dev->dvb.name = dev->core->name;
  376. dev->ts_gen_cntrl = 0x0c;
  377. /* init frontend */
  378. switch (dev->core->board) {
  379. case CX88_BOARD_HAUPPAUGE_DVB_T1:
  380. dev->dvb.frontend = dvb_attach(cx22702_attach,
  381. &connexant_refboard_config,
  382. &dev->core->i2c_adap);
  383. if (dev->dvb.frontend != NULL) {
  384. dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61,
  385. &dev->core->i2c_adap,
  386. &dvb_pll_thomson_dtt759x);
  387. }
  388. break;
  389. case CX88_BOARD_TERRATEC_CINERGY_1400_DVB_T1:
  390. case CX88_BOARD_CONEXANT_DVB_T1:
  391. case CX88_BOARD_KWORLD_DVB_T_CX22702:
  392. case CX88_BOARD_WINFAST_DTV1000:
  393. dev->dvb.frontend = dvb_attach(cx22702_attach,
  394. &connexant_refboard_config,
  395. &dev->core->i2c_adap);
  396. if (dev->dvb.frontend != NULL) {
  397. dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x60,
  398. &dev->core->i2c_adap,
  399. &dvb_pll_thomson_dtt7579);
  400. }
  401. break;
  402. case CX88_BOARD_WINFAST_DTV2000H:
  403. case CX88_BOARD_HAUPPAUGE_HVR1100:
  404. case CX88_BOARD_HAUPPAUGE_HVR1100LP:
  405. dev->dvb.frontend = dvb_attach(cx22702_attach,
  406. &hauppauge_hvr_config,
  407. &dev->core->i2c_adap);
  408. if (dev->dvb.frontend != NULL) {
  409. dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61,
  410. &dev->core->i2c_adap, &dvb_pll_fmd1216me);
  411. }
  412. break;
  413. case CX88_BOARD_DVICO_FUSIONHDTV_DVB_T_PLUS:
  414. dev->dvb.frontend = dvb_attach(mt352_attach,
  415. &dvico_fusionhdtv,
  416. &dev->core->i2c_adap);
  417. if (dev->dvb.frontend != NULL) {
  418. dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x60,
  419. NULL, &dvb_pll_thomson_dtt7579);
  420. break;
  421. }
  422. /* ZL10353 replaces MT352 on later cards */
  423. dev->dvb.frontend = dvb_attach(zl10353_attach,
  424. &dvico_fusionhdtv_plus_v1_1,
  425. &dev->core->i2c_adap);
  426. if (dev->dvb.frontend != NULL) {
  427. dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x60,
  428. NULL, &dvb_pll_thomson_dtt7579);
  429. }
  430. break;
  431. case CX88_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL:
  432. /* The tin box says DEE1601, but it seems to be DTT7579
  433. * compatible, with a slightly different MT352 AGC gain. */
  434. dev->dvb.frontend = dvb_attach(mt352_attach,
  435. &dvico_fusionhdtv_dual,
  436. &dev->core->i2c_adap);
  437. if (dev->dvb.frontend != NULL) {
  438. dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61,
  439. NULL, &dvb_pll_thomson_dtt7579);
  440. break;
  441. }
  442. /* ZL10353 replaces MT352 on later cards */
  443. dev->dvb.frontend = dvb_attach(zl10353_attach,
  444. &dvico_fusionhdtv_plus_v1_1,
  445. &dev->core->i2c_adap);
  446. if (dev->dvb.frontend != NULL) {
  447. dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61,
  448. NULL, &dvb_pll_thomson_dtt7579);
  449. }
  450. break;
  451. case CX88_BOARD_DVICO_FUSIONHDTV_DVB_T1:
  452. dev->dvb.frontend = dvb_attach(mt352_attach,
  453. &dvico_fusionhdtv,
  454. &dev->core->i2c_adap);
  455. if (dev->dvb.frontend != NULL) {
  456. dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61,
  457. NULL, &dvb_pll_lg_z201);
  458. }
  459. break;
  460. case CX88_BOARD_KWORLD_DVB_T:
  461. case CX88_BOARD_DNTV_LIVE_DVB_T:
  462. case CX88_BOARD_ADSTECH_DVB_T_PCI:
  463. dev->dvb.frontend = dvb_attach(mt352_attach,
  464. &dntv_live_dvbt_config,
  465. &dev->core->i2c_adap);
  466. if (dev->dvb.frontend != NULL) {
  467. dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61,
  468. NULL, &dvb_pll_unknown_1);
  469. }
  470. break;
  471. case CX88_BOARD_DNTV_LIVE_DVB_T_PRO:
  472. #if defined(CONFIG_VIDEO_CX88_VP3054) || defined(CONFIG_VIDEO_CX88_VP3054_MODULE)
  473. dev->core->pll_addr = 0x61;
  474. dev->core->pll_desc = &dvb_pll_fmd1216me;
  475. dev->dvb.frontend = dvb_attach(mt352_attach, &dntv_live_dvbt_pro_config,
  476. &((struct vp3054_i2c_state *)dev->card_priv)->adap);
  477. if (dev->dvb.frontend != NULL) {
  478. dev->dvb.frontend->ops.tuner_ops.set_params = dntv_live_dvbt_pro_tuner_set_params;
  479. }
  480. #else
  481. printk("%s: built without vp3054 support\n", dev->core->name);
  482. #endif
  483. break;
  484. case CX88_BOARD_DVICO_FUSIONHDTV_DVB_T_HYBRID:
  485. dev->dvb.frontend = dvb_attach(zl10353_attach,
  486. &dvico_fusionhdtv_hybrid,
  487. &dev->core->i2c_adap);
  488. if (dev->dvb.frontend != NULL) {
  489. dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61,
  490. &dev->core->i2c_adap,
  491. &dvb_pll_thomson_fe6600);
  492. }
  493. break;
  494. case CX88_BOARD_PCHDTV_HD3000:
  495. dev->dvb.frontend = dvb_attach(or51132_attach, &pchdtv_hd3000,
  496. &dev->core->i2c_adap);
  497. if (dev->dvb.frontend != NULL) {
  498. dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61,
  499. &dev->core->i2c_adap,
  500. &dvb_pll_thomson_dtt761x);
  501. }
  502. break;
  503. case CX88_BOARD_DVICO_FUSIONHDTV_3_GOLD_Q:
  504. dev->ts_gen_cntrl = 0x08;
  505. {
  506. /* Do a hardware reset of chip before using it. */
  507. struct cx88_core *core = dev->core;
  508. cx_clear(MO_GP0_IO, 1);
  509. mdelay(100);
  510. cx_set(MO_GP0_IO, 1);
  511. mdelay(200);
  512. /* Select RF connector callback */
  513. fusionhdtv_3_gold.pll_rf_set = lgdt330x_pll_rf_set;
  514. dev->dvb.frontend = dvb_attach(lgdt330x_attach,
  515. &fusionhdtv_3_gold,
  516. &dev->core->i2c_adap);
  517. if (dev->dvb.frontend != NULL) {
  518. dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61,
  519. &dev->core->i2c_adap,
  520. &dvb_pll_microtune_4042);
  521. }
  522. }
  523. break;
  524. case CX88_BOARD_DVICO_FUSIONHDTV_3_GOLD_T:
  525. dev->ts_gen_cntrl = 0x08;
  526. {
  527. /* Do a hardware reset of chip before using it. */
  528. struct cx88_core *core = dev->core;
  529. cx_clear(MO_GP0_IO, 1);
  530. mdelay(100);
  531. cx_set(MO_GP0_IO, 9);
  532. mdelay(200);
  533. dev->dvb.frontend = dvb_attach(lgdt330x_attach,
  534. &fusionhdtv_3_gold,
  535. &dev->core->i2c_adap);
  536. if (dev->dvb.frontend != NULL) {
  537. dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61,
  538. &dev->core->i2c_adap,
  539. &dvb_pll_thomson_dtt761x);
  540. }
  541. }
  542. break;
  543. case CX88_BOARD_DVICO_FUSIONHDTV_5_GOLD:
  544. dev->ts_gen_cntrl = 0x08;
  545. {
  546. /* Do a hardware reset of chip before using it. */
  547. struct cx88_core *core = dev->core;
  548. cx_clear(MO_GP0_IO, 1);
  549. mdelay(100);
  550. cx_set(MO_GP0_IO, 1);
  551. mdelay(200);
  552. dev->dvb.frontend = dvb_attach(lgdt330x_attach,
  553. &fusionhdtv_5_gold,
  554. &dev->core->i2c_adap);
  555. if (dev->dvb.frontend != NULL) {
  556. dvb_attach(lgh06xf_attach, dev->dvb.frontend,
  557. &dev->core->i2c_adap);
  558. }
  559. }
  560. break;
  561. case CX88_BOARD_PCHDTV_HD5500:
  562. dev->ts_gen_cntrl = 0x08;
  563. {
  564. /* Do a hardware reset of chip before using it. */
  565. struct cx88_core *core = dev->core;
  566. cx_clear(MO_GP0_IO, 1);
  567. mdelay(100);
  568. cx_set(MO_GP0_IO, 1);
  569. mdelay(200);
  570. dev->dvb.frontend = dvb_attach(lgdt330x_attach,
  571. &pchdtv_hd5500,
  572. &dev->core->i2c_adap);
  573. if (dev->dvb.frontend != NULL) {
  574. dvb_attach(lgh06xf_attach, dev->dvb.frontend,
  575. &dev->core->i2c_adap);
  576. }
  577. }
  578. break;
  579. case CX88_BOARD_ATI_HDTVWONDER:
  580. dev->dvb.frontend = dvb_attach(nxt200x_attach,
  581. &ati_hdtvwonder,
  582. &dev->core->i2c_adap);
  583. if (dev->dvb.frontend != NULL) {
  584. dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61,
  585. NULL, &dvb_pll_tuv1236d);
  586. }
  587. break;
  588. case CX88_BOARD_HAUPPAUGE_NOVASPLUS_S1:
  589. case CX88_BOARD_HAUPPAUGE_NOVASE2_S1:
  590. dev->dvb.frontend = dvb_attach(cx24123_attach,
  591. &hauppauge_novas_config,
  592. &dev->core->i2c_adap);
  593. if (dev->dvb.frontend) {
  594. dvb_attach(isl6421_attach, dev->dvb.frontend,
  595. &dev->core->i2c_adap, 0x08, 0x00, 0x00);
  596. }
  597. break;
  598. case CX88_BOARD_KWORLD_DVBS_100:
  599. dev->dvb.frontend = dvb_attach(cx24123_attach,
  600. &kworld_dvbs_100_config,
  601. &dev->core->i2c_adap);
  602. if (dev->dvb.frontend) {
  603. dev->core->prev_set_voltage = dev->dvb.frontend->ops.set_voltage;
  604. dev->dvb.frontend->ops.set_voltage = kworld_dvbs_100_set_voltage;
  605. }
  606. break;
  607. case CX88_BOARD_GENIATECH_DVBS:
  608. dev->dvb.frontend = dvb_attach(cx24123_attach,
  609. &geniatech_dvbs_config,
  610. &dev->core->i2c_adap);
  611. if (dev->dvb.frontend) {
  612. dev->core->prev_set_voltage = dev->dvb.frontend->ops.set_voltage;
  613. dev->dvb.frontend->ops.set_voltage = geniatech_dvbs_set_voltage;
  614. }
  615. break;
  616. case CX88_BOARD_HAUPPAUGE_HVR1300:
  617. dev->dvb.frontend = dvb_attach(cx22702_attach,
  618. &hauppauge_hvr_config,
  619. &dev->core->i2c_adap);
  620. if (dev->dvb.frontend != NULL) {
  621. dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61,
  622. &dev->core->i2c_adap, &dvb_pll_fmd1216me);
  623. }
  624. break;
  625. case CX88_BOARD_HAUPPAUGE_HVR3000:
  626. dev->dvb.frontend = dvb_attach(cx22702_attach,
  627. &hauppauge_hvr_config,
  628. &dev->core->i2c_adap);
  629. if (dev->dvb.frontend != NULL) {
  630. dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61,
  631. &dev->core->i2c_adap, &dvb_pll_fmd1216me);
  632. }
  633. break;
  634. default:
  635. printk("%s: The frontend of your DVB/ATSC card isn't supported yet\n",
  636. dev->core->name);
  637. break;
  638. }
  639. if (NULL == dev->dvb.frontend) {
  640. printk("%s: frontend initialization failed\n",dev->core->name);
  641. return -1;
  642. }
  643. if (dev->core->pll_desc) {
  644. dev->dvb.frontend->ops.info.frequency_min = dev->core->pll_desc->min;
  645. dev->dvb.frontend->ops.info.frequency_max = dev->core->pll_desc->max;
  646. }
  647. /* Ensure all frontends negotiate bus access */
  648. dev->dvb.frontend->ops.ts_bus_ctrl = cx88_dvb_bus_ctrl;
  649. /* Put the analog decoder in standby to keep it quiet */
  650. cx88_call_i2c_clients (dev->core, TUNER_SET_STANDBY, NULL);
  651. /* register everything */
  652. return videobuf_dvb_register(&dev->dvb, THIS_MODULE, dev, &dev->pci->dev);
  653. }
  654. /* ----------------------------------------------------------- */
  655. /* CX8802 MPEG -> mini driver - We have been given the hardware */
  656. static int cx8802_dvb_advise_acquire(struct cx8802_driver *drv)
  657. {
  658. struct cx88_core *core = drv->core;
  659. int err = 0;
  660. dprintk( 1, "%s\n", __FUNCTION__);
  661. switch (core->board) {
  662. case CX88_BOARD_HAUPPAUGE_HVR1300:
  663. /* We arrive here with either the cx23416 or the cx22702
  664. * on the bus. Take the bus from the cx23416 and enable the
  665. * cx22702 demod
  666. */
  667. cx_set(MO_GP0_IO, 0x00000080); /* cx22702 out of reset and enable */
  668. cx_clear(MO_GP0_IO, 0x00000004);
  669. udelay(1000);
  670. break;
  671. default:
  672. err = -ENODEV;
  673. }
  674. return err;
  675. }
  676. /* CX8802 MPEG -> mini driver - We no longer have the hardware */
  677. static int cx8802_dvb_advise_release(struct cx8802_driver *drv)
  678. {
  679. struct cx88_core *core = drv->core;
  680. int err = 0;
  681. dprintk( 1, "%s\n", __FUNCTION__);
  682. switch (core->board) {
  683. case CX88_BOARD_HAUPPAUGE_HVR1300:
  684. /* Do Nothing, leave the cx22702 on the bus. */
  685. break;
  686. default:
  687. err = -ENODEV;
  688. }
  689. return err;
  690. }
  691. static int cx8802_dvb_probe(struct cx8802_driver *drv)
  692. {
  693. struct cx88_core *core = drv->core;
  694. struct cx8802_dev *dev = drv->core->dvbdev;
  695. int err;
  696. dprintk( 1, "%s\n", __FUNCTION__);
  697. dprintk( 1, " ->being probed by Card=%d Name=%s, PCI %02x:%02x\n",
  698. core->board,
  699. core->name,
  700. core->pci_bus,
  701. core->pci_slot);
  702. err = -ENODEV;
  703. if (!(cx88_boards[core->board].mpeg & CX88_MPEG_DVB))
  704. goto fail_core;
  705. #if defined(CONFIG_VIDEO_CX88_VP3054) || defined(CONFIG_VIDEO_CX88_VP3054_MODULE)
  706. err = vp3054_i2c_probe(dev);
  707. if (0 != err)
  708. goto fail_core;
  709. #endif
  710. /* dvb stuff */
  711. printk("%s/2: cx2388x based dvb card\n", core->name);
  712. videobuf_queue_init(&dev->dvb.dvbq, &dvb_qops,
  713. dev->pci, &dev->slock,
  714. V4L2_BUF_TYPE_VIDEO_CAPTURE,
  715. V4L2_FIELD_TOP,
  716. sizeof(struct cx88_buffer),
  717. dev);
  718. err = dvb_register(dev);
  719. if (err != 0)
  720. printk("%s dvb_register failed err = %d\n", __FUNCTION__, err);
  721. fail_core:
  722. return err;
  723. }
  724. static int cx8802_dvb_remove(struct cx8802_driver *drv)
  725. {
  726. struct cx8802_dev *dev = drv->core->dvbdev;
  727. /* dvb */
  728. videobuf_dvb_unregister(&dev->dvb);
  729. #if defined(CONFIG_VIDEO_CX88_VP3054) || defined(CONFIG_VIDEO_CX88_VP3054_MODULE)
  730. vp3054_i2c_remove(dev);
  731. #endif
  732. return 0;
  733. }
  734. static struct cx8802_driver cx8802_dvb_driver = {
  735. .type_id = CX88_MPEG_DVB,
  736. .hw_access = CX8802_DRVCTL_SHARED,
  737. .probe = cx8802_dvb_probe,
  738. .remove = cx8802_dvb_remove,
  739. .advise_acquire = cx8802_dvb_advise_acquire,
  740. .advise_release = cx8802_dvb_advise_release,
  741. };
  742. static int dvb_init(void)
  743. {
  744. printk(KERN_INFO "cx2388x dvb driver version %d.%d.%d loaded\n",
  745. (CX88_VERSION_CODE >> 16) & 0xff,
  746. (CX88_VERSION_CODE >> 8) & 0xff,
  747. CX88_VERSION_CODE & 0xff);
  748. #ifdef SNAPSHOT
  749. printk(KERN_INFO "cx2388x: snapshot date %04d-%02d-%02d\n",
  750. SNAPSHOT/10000, (SNAPSHOT/100)%100, SNAPSHOT%100);
  751. #endif
  752. return cx8802_register_driver(&cx8802_dvb_driver);
  753. }
  754. static void dvb_fini(void)
  755. {
  756. cx8802_unregister_driver(&cx8802_dvb_driver);
  757. }
  758. module_init(dvb_init);
  759. module_exit(dvb_fini);
  760. /*
  761. * Local variables:
  762. * c-basic-offset: 8
  763. * compile-command: "make DVB=1"
  764. * End:
  765. */