iwl3945-base.c 233 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved.
  4. *
  5. * Portions of this file are derived from the ipw3945 project, as well
  6. * as portions of the ieee80211 subsystem header files.
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of version 2 of the GNU General Public License as
  10. * published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope that it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  15. * more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along with
  18. * this program; if not, write to the Free Software Foundation, Inc.,
  19. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20. *
  21. * The full GNU General Public License is included in this distribution in the
  22. * file called LICENSE.
  23. *
  24. * Contact Information:
  25. * James P. Ketrenos <ipw2100-admin@linux.intel.com>
  26. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27. *
  28. *****************************************************************************/
  29. #include <linux/kernel.h>
  30. #include <linux/module.h>
  31. #include <linux/version.h>
  32. #include <linux/init.h>
  33. #include <linux/pci.h>
  34. #include <linux/dma-mapping.h>
  35. #include <linux/delay.h>
  36. #include <linux/skbuff.h>
  37. #include <linux/netdevice.h>
  38. #include <linux/wireless.h>
  39. #include <linux/firmware.h>
  40. #include <linux/etherdevice.h>
  41. #include <linux/if_arp.h>
  42. #include <net/ieee80211_radiotap.h>
  43. #include <net/mac80211.h>
  44. #include <asm/div64.h>
  45. #include "iwl-3945-core.h"
  46. #include "iwl-3945.h"
  47. #include "iwl-helpers.h"
  48. #ifdef CONFIG_IWL3945_DEBUG
  49. u32 iwl3945_debug_level;
  50. #endif
  51. static int iwl3945_tx_queue_update_write_ptr(struct iwl3945_priv *priv,
  52. struct iwl3945_tx_queue *txq);
  53. /******************************************************************************
  54. *
  55. * module boiler plate
  56. *
  57. ******************************************************************************/
  58. /* module parameters */
  59. static int iwl3945_param_disable_hw_scan; /* def: 0 = use 3945's h/w scan */
  60. static int iwl3945_param_debug; /* def: 0 = minimal debug log messages */
  61. static int iwl3945_param_disable; /* def: 0 = enable radio */
  62. static int iwl3945_param_antenna; /* def: 0 = both antennas (use diversity) */
  63. int iwl3945_param_hwcrypto; /* def: 0 = use software encryption */
  64. static int iwl3945_param_qos_enable = 1; /* def: 1 = use quality of service */
  65. int iwl3945_param_queues_num = IWL39_MAX_NUM_QUEUES; /* def: 8 Tx queues */
  66. /*
  67. * module name, copyright, version, etc.
  68. * NOTE: DRV_NAME is defined in iwlwifi.h for use by iwl-debug.h and printk
  69. */
  70. #define DRV_DESCRIPTION \
  71. "Intel(R) PRO/Wireless 3945ABG/BG Network Connection driver for Linux"
  72. #ifdef CONFIG_IWL3945_DEBUG
  73. #define VD "d"
  74. #else
  75. #define VD
  76. #endif
  77. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  78. #define VS "s"
  79. #else
  80. #define VS
  81. #endif
  82. #define IWLWIFI_VERSION "1.2.26k" VD VS
  83. #define DRV_COPYRIGHT "Copyright(c) 2003-2008 Intel Corporation"
  84. #define DRV_VERSION IWLWIFI_VERSION
  85. MODULE_DESCRIPTION(DRV_DESCRIPTION);
  86. MODULE_VERSION(DRV_VERSION);
  87. MODULE_AUTHOR(DRV_COPYRIGHT);
  88. MODULE_LICENSE("GPL");
  89. static const struct ieee80211_supported_band *iwl3945_get_band(
  90. struct iwl3945_priv *priv, enum ieee80211_band band)
  91. {
  92. return priv->hw->wiphy->bands[band];
  93. }
  94. static int iwl3945_is_empty_essid(const char *essid, int essid_len)
  95. {
  96. /* Single white space is for Linksys APs */
  97. if (essid_len == 1 && essid[0] == ' ')
  98. return 1;
  99. /* Otherwise, if the entire essid is 0, we assume it is hidden */
  100. while (essid_len) {
  101. essid_len--;
  102. if (essid[essid_len] != '\0')
  103. return 0;
  104. }
  105. return 1;
  106. }
  107. static const char *iwl3945_escape_essid(const char *essid, u8 essid_len)
  108. {
  109. static char escaped[IW_ESSID_MAX_SIZE * 2 + 1];
  110. const char *s = essid;
  111. char *d = escaped;
  112. if (iwl3945_is_empty_essid(essid, essid_len)) {
  113. memcpy(escaped, "<hidden>", sizeof("<hidden>"));
  114. return escaped;
  115. }
  116. essid_len = min(essid_len, (u8) IW_ESSID_MAX_SIZE);
  117. while (essid_len--) {
  118. if (*s == '\0') {
  119. *d++ = '\\';
  120. *d++ = '0';
  121. s++;
  122. } else
  123. *d++ = *s++;
  124. }
  125. *d = '\0';
  126. return escaped;
  127. }
  128. /*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
  129. * DMA services
  130. *
  131. * Theory of operation
  132. *
  133. * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
  134. * of buffer descriptors, each of which points to one or more data buffers for
  135. * the device to read from or fill. Driver and device exchange status of each
  136. * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
  137. * entries in each circular buffer, to protect against confusing empty and full
  138. * queue states.
  139. *
  140. * The device reads or writes the data in the queues via the device's several
  141. * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
  142. *
  143. * For Tx queue, there are low mark and high mark limits. If, after queuing
  144. * the packet for Tx, free space become < low mark, Tx queue stopped. When
  145. * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
  146. * Tx queue resumed.
  147. *
  148. * The 3945 operates with six queues: One receive queue, one transmit queue
  149. * (#4) for sending commands to the device firmware, and four transmit queues
  150. * (#0-3) for data tx via EDCA. An additional 2 HCCA queues are unused.
  151. ***************************************************/
  152. int iwl3945_queue_space(const struct iwl3945_queue *q)
  153. {
  154. int s = q->read_ptr - q->write_ptr;
  155. if (q->read_ptr > q->write_ptr)
  156. s -= q->n_bd;
  157. if (s <= 0)
  158. s += q->n_window;
  159. /* keep some reserve to not confuse empty and full situations */
  160. s -= 2;
  161. if (s < 0)
  162. s = 0;
  163. return s;
  164. }
  165. int iwl3945_x2_queue_used(const struct iwl3945_queue *q, int i)
  166. {
  167. return q->write_ptr > q->read_ptr ?
  168. (i >= q->read_ptr && i < q->write_ptr) :
  169. !(i < q->read_ptr && i >= q->write_ptr);
  170. }
  171. static inline u8 get_cmd_index(struct iwl3945_queue *q, u32 index, int is_huge)
  172. {
  173. /* This is for scan command, the big buffer at end of command array */
  174. if (is_huge)
  175. return q->n_window; /* must be power of 2 */
  176. /* Otherwise, use normal size buffers */
  177. return index & (q->n_window - 1);
  178. }
  179. /**
  180. * iwl3945_queue_init - Initialize queue's high/low-water and read/write indexes
  181. */
  182. static int iwl3945_queue_init(struct iwl3945_priv *priv, struct iwl3945_queue *q,
  183. int count, int slots_num, u32 id)
  184. {
  185. q->n_bd = count;
  186. q->n_window = slots_num;
  187. q->id = id;
  188. /* count must be power-of-two size, otherwise iwl_queue_inc_wrap
  189. * and iwl_queue_dec_wrap are broken. */
  190. BUG_ON(!is_power_of_2(count));
  191. /* slots_num must be power-of-two size, otherwise
  192. * get_cmd_index is broken. */
  193. BUG_ON(!is_power_of_2(slots_num));
  194. q->low_mark = q->n_window / 4;
  195. if (q->low_mark < 4)
  196. q->low_mark = 4;
  197. q->high_mark = q->n_window / 8;
  198. if (q->high_mark < 2)
  199. q->high_mark = 2;
  200. q->write_ptr = q->read_ptr = 0;
  201. return 0;
  202. }
  203. /**
  204. * iwl3945_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue
  205. */
  206. static int iwl3945_tx_queue_alloc(struct iwl3945_priv *priv,
  207. struct iwl3945_tx_queue *txq, u32 id)
  208. {
  209. struct pci_dev *dev = priv->pci_dev;
  210. /* Driver private data, only for Tx (not command) queues,
  211. * not shared with device. */
  212. if (id != IWL_CMD_QUEUE_NUM) {
  213. txq->txb = kmalloc(sizeof(txq->txb[0]) *
  214. TFD_QUEUE_SIZE_MAX, GFP_KERNEL);
  215. if (!txq->txb) {
  216. IWL_ERROR("kmalloc for auxiliary BD "
  217. "structures failed\n");
  218. goto error;
  219. }
  220. } else
  221. txq->txb = NULL;
  222. /* Circular buffer of transmit frame descriptors (TFDs),
  223. * shared with device */
  224. txq->bd = pci_alloc_consistent(dev,
  225. sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX,
  226. &txq->q.dma_addr);
  227. if (!txq->bd) {
  228. IWL_ERROR("pci_alloc_consistent(%zd) failed\n",
  229. sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX);
  230. goto error;
  231. }
  232. txq->q.id = id;
  233. return 0;
  234. error:
  235. kfree(txq->txb);
  236. txq->txb = NULL;
  237. return -ENOMEM;
  238. }
  239. /**
  240. * iwl3945_tx_queue_init - Allocate and initialize one tx/cmd queue
  241. */
  242. int iwl3945_tx_queue_init(struct iwl3945_priv *priv,
  243. struct iwl3945_tx_queue *txq, int slots_num, u32 txq_id)
  244. {
  245. struct pci_dev *dev = priv->pci_dev;
  246. int len;
  247. int rc = 0;
  248. /*
  249. * Alloc buffer array for commands (Tx or other types of commands).
  250. * For the command queue (#4), allocate command space + one big
  251. * command for scan, since scan command is very huge; the system will
  252. * not have two scans at the same time, so only one is needed.
  253. * For data Tx queues (all other queues), no super-size command
  254. * space is needed.
  255. */
  256. len = sizeof(struct iwl3945_cmd) * slots_num;
  257. if (txq_id == IWL_CMD_QUEUE_NUM)
  258. len += IWL_MAX_SCAN_SIZE;
  259. txq->cmd = pci_alloc_consistent(dev, len, &txq->dma_addr_cmd);
  260. if (!txq->cmd)
  261. return -ENOMEM;
  262. /* Alloc driver data array and TFD circular buffer */
  263. rc = iwl3945_tx_queue_alloc(priv, txq, txq_id);
  264. if (rc) {
  265. pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd);
  266. return -ENOMEM;
  267. }
  268. txq->need_update = 0;
  269. /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
  270. * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
  271. BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
  272. /* Initialize queue high/low-water, head/tail indexes */
  273. iwl3945_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id);
  274. /* Tell device where to find queue, enable DMA channel. */
  275. iwl3945_hw_tx_queue_init(priv, txq);
  276. return 0;
  277. }
  278. /**
  279. * iwl3945_tx_queue_free - Deallocate DMA queue.
  280. * @txq: Transmit queue to deallocate.
  281. *
  282. * Empty queue by removing and destroying all BD's.
  283. * Free all buffers.
  284. * 0-fill, but do not free "txq" descriptor structure.
  285. */
  286. void iwl3945_tx_queue_free(struct iwl3945_priv *priv, struct iwl3945_tx_queue *txq)
  287. {
  288. struct iwl3945_queue *q = &txq->q;
  289. struct pci_dev *dev = priv->pci_dev;
  290. int len;
  291. if (q->n_bd == 0)
  292. return;
  293. /* first, empty all BD's */
  294. for (; q->write_ptr != q->read_ptr;
  295. q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd))
  296. iwl3945_hw_txq_free_tfd(priv, txq);
  297. len = sizeof(struct iwl3945_cmd) * q->n_window;
  298. if (q->id == IWL_CMD_QUEUE_NUM)
  299. len += IWL_MAX_SCAN_SIZE;
  300. /* De-alloc array of command/tx buffers */
  301. pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd);
  302. /* De-alloc circular buffer of TFDs */
  303. if (txq->q.n_bd)
  304. pci_free_consistent(dev, sizeof(struct iwl3945_tfd_frame) *
  305. txq->q.n_bd, txq->bd, txq->q.dma_addr);
  306. /* De-alloc array of per-TFD driver data */
  307. kfree(txq->txb);
  308. txq->txb = NULL;
  309. /* 0-fill queue descriptor structure */
  310. memset(txq, 0, sizeof(*txq));
  311. }
  312. const u8 iwl3945_broadcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
  313. /*************** STATION TABLE MANAGEMENT ****
  314. * mac80211 should be examined to determine if sta_info is duplicating
  315. * the functionality provided here
  316. */
  317. /**************************************************************/
  318. #if 0 /* temporary disable till we add real remove station */
  319. /**
  320. * iwl3945_remove_station - Remove driver's knowledge of station.
  321. *
  322. * NOTE: This does not remove station from device's station table.
  323. */
  324. static u8 iwl3945_remove_station(struct iwl3945_priv *priv, const u8 *addr, int is_ap)
  325. {
  326. int index = IWL_INVALID_STATION;
  327. int i;
  328. unsigned long flags;
  329. spin_lock_irqsave(&priv->sta_lock, flags);
  330. if (is_ap)
  331. index = IWL_AP_ID;
  332. else if (is_broadcast_ether_addr(addr))
  333. index = priv->hw_setting.bcast_sta_id;
  334. else
  335. for (i = IWL_STA_ID; i < priv->hw_setting.max_stations; i++)
  336. if (priv->stations[i].used &&
  337. !compare_ether_addr(priv->stations[i].sta.sta.addr,
  338. addr)) {
  339. index = i;
  340. break;
  341. }
  342. if (unlikely(index == IWL_INVALID_STATION))
  343. goto out;
  344. if (priv->stations[index].used) {
  345. priv->stations[index].used = 0;
  346. priv->num_stations--;
  347. }
  348. BUG_ON(priv->num_stations < 0);
  349. out:
  350. spin_unlock_irqrestore(&priv->sta_lock, flags);
  351. return 0;
  352. }
  353. #endif
  354. /**
  355. * iwl3945_clear_stations_table - Clear the driver's station table
  356. *
  357. * NOTE: This does not clear or otherwise alter the device's station table.
  358. */
  359. static void iwl3945_clear_stations_table(struct iwl3945_priv *priv)
  360. {
  361. unsigned long flags;
  362. spin_lock_irqsave(&priv->sta_lock, flags);
  363. priv->num_stations = 0;
  364. memset(priv->stations, 0, sizeof(priv->stations));
  365. spin_unlock_irqrestore(&priv->sta_lock, flags);
  366. }
  367. /**
  368. * iwl3945_add_station - Add station to station tables in driver and device
  369. */
  370. u8 iwl3945_add_station(struct iwl3945_priv *priv, const u8 *addr, int is_ap, u8 flags)
  371. {
  372. int i;
  373. int index = IWL_INVALID_STATION;
  374. struct iwl3945_station_entry *station;
  375. unsigned long flags_spin;
  376. DECLARE_MAC_BUF(mac);
  377. u8 rate;
  378. spin_lock_irqsave(&priv->sta_lock, flags_spin);
  379. if (is_ap)
  380. index = IWL_AP_ID;
  381. else if (is_broadcast_ether_addr(addr))
  382. index = priv->hw_setting.bcast_sta_id;
  383. else
  384. for (i = IWL_STA_ID; i < priv->hw_setting.max_stations; i++) {
  385. if (!compare_ether_addr(priv->stations[i].sta.sta.addr,
  386. addr)) {
  387. index = i;
  388. break;
  389. }
  390. if (!priv->stations[i].used &&
  391. index == IWL_INVALID_STATION)
  392. index = i;
  393. }
  394. /* These two conditions has the same outcome but keep them separate
  395. since they have different meaning */
  396. if (unlikely(index == IWL_INVALID_STATION)) {
  397. spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
  398. return index;
  399. }
  400. if (priv->stations[index].used &&
  401. !compare_ether_addr(priv->stations[index].sta.sta.addr, addr)) {
  402. spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
  403. return index;
  404. }
  405. IWL_DEBUG_ASSOC("Add STA ID %d: %s\n", index, print_mac(mac, addr));
  406. station = &priv->stations[index];
  407. station->used = 1;
  408. priv->num_stations++;
  409. /* Set up the REPLY_ADD_STA command to send to device */
  410. memset(&station->sta, 0, sizeof(struct iwl3945_addsta_cmd));
  411. memcpy(station->sta.sta.addr, addr, ETH_ALEN);
  412. station->sta.mode = 0;
  413. station->sta.sta.sta_id = index;
  414. station->sta.station_flags = 0;
  415. if (priv->band == IEEE80211_BAND_5GHZ)
  416. rate = IWL_RATE_6M_PLCP;
  417. else
  418. rate = IWL_RATE_1M_PLCP;
  419. /* Turn on both antennas for the station... */
  420. station->sta.rate_n_flags =
  421. iwl3945_hw_set_rate_n_flags(rate, RATE_MCS_ANT_AB_MSK);
  422. station->current_rate.rate_n_flags =
  423. le16_to_cpu(station->sta.rate_n_flags);
  424. spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
  425. /* Add station to device's station table */
  426. iwl3945_send_add_station(priv, &station->sta, flags);
  427. return index;
  428. }
  429. /*************** DRIVER STATUS FUNCTIONS *****/
  430. static inline int iwl3945_is_ready(struct iwl3945_priv *priv)
  431. {
  432. /* The adapter is 'ready' if READY and GEO_CONFIGURED bits are
  433. * set but EXIT_PENDING is not */
  434. return test_bit(STATUS_READY, &priv->status) &&
  435. test_bit(STATUS_GEO_CONFIGURED, &priv->status) &&
  436. !test_bit(STATUS_EXIT_PENDING, &priv->status);
  437. }
  438. static inline int iwl3945_is_alive(struct iwl3945_priv *priv)
  439. {
  440. return test_bit(STATUS_ALIVE, &priv->status);
  441. }
  442. static inline int iwl3945_is_init(struct iwl3945_priv *priv)
  443. {
  444. return test_bit(STATUS_INIT, &priv->status);
  445. }
  446. static inline int iwl3945_is_rfkill_sw(struct iwl3945_priv *priv)
  447. {
  448. return test_bit(STATUS_RF_KILL_SW, &priv->status);
  449. }
  450. static inline int iwl3945_is_rfkill_hw(struct iwl3945_priv *priv)
  451. {
  452. return test_bit(STATUS_RF_KILL_HW, &priv->status);
  453. }
  454. static inline int iwl3945_is_rfkill(struct iwl3945_priv *priv)
  455. {
  456. return iwl3945_is_rfkill_hw(priv) ||
  457. iwl3945_is_rfkill_sw(priv);
  458. }
  459. static inline int iwl3945_is_ready_rf(struct iwl3945_priv *priv)
  460. {
  461. if (iwl3945_is_rfkill(priv))
  462. return 0;
  463. return iwl3945_is_ready(priv);
  464. }
  465. /*************** HOST COMMAND QUEUE FUNCTIONS *****/
  466. #define IWL_CMD(x) case x : return #x
  467. static const char *get_cmd_string(u8 cmd)
  468. {
  469. switch (cmd) {
  470. IWL_CMD(REPLY_ALIVE);
  471. IWL_CMD(REPLY_ERROR);
  472. IWL_CMD(REPLY_RXON);
  473. IWL_CMD(REPLY_RXON_ASSOC);
  474. IWL_CMD(REPLY_QOS_PARAM);
  475. IWL_CMD(REPLY_RXON_TIMING);
  476. IWL_CMD(REPLY_ADD_STA);
  477. IWL_CMD(REPLY_REMOVE_STA);
  478. IWL_CMD(REPLY_REMOVE_ALL_STA);
  479. IWL_CMD(REPLY_3945_RX);
  480. IWL_CMD(REPLY_TX);
  481. IWL_CMD(REPLY_RATE_SCALE);
  482. IWL_CMD(REPLY_LEDS_CMD);
  483. IWL_CMD(REPLY_TX_LINK_QUALITY_CMD);
  484. IWL_CMD(RADAR_NOTIFICATION);
  485. IWL_CMD(REPLY_QUIET_CMD);
  486. IWL_CMD(REPLY_CHANNEL_SWITCH);
  487. IWL_CMD(CHANNEL_SWITCH_NOTIFICATION);
  488. IWL_CMD(REPLY_SPECTRUM_MEASUREMENT_CMD);
  489. IWL_CMD(SPECTRUM_MEASURE_NOTIFICATION);
  490. IWL_CMD(POWER_TABLE_CMD);
  491. IWL_CMD(PM_SLEEP_NOTIFICATION);
  492. IWL_CMD(PM_DEBUG_STATISTIC_NOTIFIC);
  493. IWL_CMD(REPLY_SCAN_CMD);
  494. IWL_CMD(REPLY_SCAN_ABORT_CMD);
  495. IWL_CMD(SCAN_START_NOTIFICATION);
  496. IWL_CMD(SCAN_RESULTS_NOTIFICATION);
  497. IWL_CMD(SCAN_COMPLETE_NOTIFICATION);
  498. IWL_CMD(BEACON_NOTIFICATION);
  499. IWL_CMD(REPLY_TX_BEACON);
  500. IWL_CMD(WHO_IS_AWAKE_NOTIFICATION);
  501. IWL_CMD(QUIET_NOTIFICATION);
  502. IWL_CMD(REPLY_TX_PWR_TABLE_CMD);
  503. IWL_CMD(MEASURE_ABORT_NOTIFICATION);
  504. IWL_CMD(REPLY_BT_CONFIG);
  505. IWL_CMD(REPLY_STATISTICS_CMD);
  506. IWL_CMD(STATISTICS_NOTIFICATION);
  507. IWL_CMD(REPLY_CARD_STATE_CMD);
  508. IWL_CMD(CARD_STATE_NOTIFICATION);
  509. IWL_CMD(MISSED_BEACONS_NOTIFICATION);
  510. default:
  511. return "UNKNOWN";
  512. }
  513. }
  514. #define HOST_COMPLETE_TIMEOUT (HZ / 2)
  515. /**
  516. * iwl3945_enqueue_hcmd - enqueue a uCode command
  517. * @priv: device private data point
  518. * @cmd: a point to the ucode command structure
  519. *
  520. * The function returns < 0 values to indicate the operation is
  521. * failed. On success, it turns the index (> 0) of command in the
  522. * command queue.
  523. */
  524. static int iwl3945_enqueue_hcmd(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
  525. {
  526. struct iwl3945_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM];
  527. struct iwl3945_queue *q = &txq->q;
  528. struct iwl3945_tfd_frame *tfd;
  529. u32 *control_flags;
  530. struct iwl3945_cmd *out_cmd;
  531. u32 idx;
  532. u16 fix_size = (u16)(cmd->len + sizeof(out_cmd->hdr));
  533. dma_addr_t phys_addr;
  534. int pad;
  535. u16 count;
  536. int ret;
  537. unsigned long flags;
  538. /* If any of the command structures end up being larger than
  539. * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then
  540. * we will need to increase the size of the TFD entries */
  541. BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) &&
  542. !(cmd->meta.flags & CMD_SIZE_HUGE));
  543. if (iwl3945_is_rfkill(priv)) {
  544. IWL_DEBUG_INFO("Not sending command - RF KILL");
  545. return -EIO;
  546. }
  547. if (iwl3945_queue_space(q) < ((cmd->meta.flags & CMD_ASYNC) ? 2 : 1)) {
  548. IWL_ERROR("No space for Tx\n");
  549. return -ENOSPC;
  550. }
  551. spin_lock_irqsave(&priv->hcmd_lock, flags);
  552. tfd = &txq->bd[q->write_ptr];
  553. memset(tfd, 0, sizeof(*tfd));
  554. control_flags = (u32 *) tfd;
  555. idx = get_cmd_index(q, q->write_ptr, cmd->meta.flags & CMD_SIZE_HUGE);
  556. out_cmd = &txq->cmd[idx];
  557. out_cmd->hdr.cmd = cmd->id;
  558. memcpy(&out_cmd->meta, &cmd->meta, sizeof(cmd->meta));
  559. memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len);
  560. /* At this point, the out_cmd now has all of the incoming cmd
  561. * information */
  562. out_cmd->hdr.flags = 0;
  563. out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(IWL_CMD_QUEUE_NUM) |
  564. INDEX_TO_SEQ(q->write_ptr));
  565. if (out_cmd->meta.flags & CMD_SIZE_HUGE)
  566. out_cmd->hdr.sequence |= cpu_to_le16(SEQ_HUGE_FRAME);
  567. phys_addr = txq->dma_addr_cmd + sizeof(txq->cmd[0]) * idx +
  568. offsetof(struct iwl3945_cmd, hdr);
  569. iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, fix_size);
  570. pad = U32_PAD(cmd->len);
  571. count = TFD_CTL_COUNT_GET(*control_flags);
  572. *control_flags = TFD_CTL_COUNT_SET(count) | TFD_CTL_PAD_SET(pad);
  573. IWL_DEBUG_HC("Sending command %s (#%x), seq: 0x%04X, "
  574. "%d bytes at %d[%d]:%d\n",
  575. get_cmd_string(out_cmd->hdr.cmd),
  576. out_cmd->hdr.cmd, le16_to_cpu(out_cmd->hdr.sequence),
  577. fix_size, q->write_ptr, idx, IWL_CMD_QUEUE_NUM);
  578. txq->need_update = 1;
  579. /* Increment and update queue's write index */
  580. q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
  581. ret = iwl3945_tx_queue_update_write_ptr(priv, txq);
  582. spin_unlock_irqrestore(&priv->hcmd_lock, flags);
  583. return ret ? ret : idx;
  584. }
  585. static int iwl3945_send_cmd_async(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
  586. {
  587. int ret;
  588. BUG_ON(!(cmd->meta.flags & CMD_ASYNC));
  589. /* An asynchronous command can not expect an SKB to be set. */
  590. BUG_ON(cmd->meta.flags & CMD_WANT_SKB);
  591. /* An asynchronous command MUST have a callback. */
  592. BUG_ON(!cmd->meta.u.callback);
  593. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  594. return -EBUSY;
  595. ret = iwl3945_enqueue_hcmd(priv, cmd);
  596. if (ret < 0) {
  597. IWL_ERROR("Error sending %s: iwl3945_enqueue_hcmd failed: %d\n",
  598. get_cmd_string(cmd->id), ret);
  599. return ret;
  600. }
  601. return 0;
  602. }
  603. static int iwl3945_send_cmd_sync(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
  604. {
  605. int cmd_idx;
  606. int ret;
  607. BUG_ON(cmd->meta.flags & CMD_ASYNC);
  608. /* A synchronous command can not have a callback set. */
  609. BUG_ON(cmd->meta.u.callback != NULL);
  610. if (test_and_set_bit(STATUS_HCMD_SYNC_ACTIVE, &priv->status)) {
  611. IWL_ERROR("Error sending %s: Already sending a host command\n",
  612. get_cmd_string(cmd->id));
  613. ret = -EBUSY;
  614. goto out;
  615. }
  616. set_bit(STATUS_HCMD_ACTIVE, &priv->status);
  617. if (cmd->meta.flags & CMD_WANT_SKB)
  618. cmd->meta.source = &cmd->meta;
  619. cmd_idx = iwl3945_enqueue_hcmd(priv, cmd);
  620. if (cmd_idx < 0) {
  621. ret = cmd_idx;
  622. IWL_ERROR("Error sending %s: iwl3945_enqueue_hcmd failed: %d\n",
  623. get_cmd_string(cmd->id), ret);
  624. goto out;
  625. }
  626. ret = wait_event_interruptible_timeout(priv->wait_command_queue,
  627. !test_bit(STATUS_HCMD_ACTIVE, &priv->status),
  628. HOST_COMPLETE_TIMEOUT);
  629. if (!ret) {
  630. if (test_bit(STATUS_HCMD_ACTIVE, &priv->status)) {
  631. IWL_ERROR("Error sending %s: time out after %dms.\n",
  632. get_cmd_string(cmd->id),
  633. jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
  634. clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
  635. ret = -ETIMEDOUT;
  636. goto cancel;
  637. }
  638. }
  639. if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
  640. IWL_DEBUG_INFO("Command %s aborted: RF KILL Switch\n",
  641. get_cmd_string(cmd->id));
  642. ret = -ECANCELED;
  643. goto fail;
  644. }
  645. if (test_bit(STATUS_FW_ERROR, &priv->status)) {
  646. IWL_DEBUG_INFO("Command %s failed: FW Error\n",
  647. get_cmd_string(cmd->id));
  648. ret = -EIO;
  649. goto fail;
  650. }
  651. if ((cmd->meta.flags & CMD_WANT_SKB) && !cmd->meta.u.skb) {
  652. IWL_ERROR("Error: Response NULL in '%s'\n",
  653. get_cmd_string(cmd->id));
  654. ret = -EIO;
  655. goto out;
  656. }
  657. ret = 0;
  658. goto out;
  659. cancel:
  660. if (cmd->meta.flags & CMD_WANT_SKB) {
  661. struct iwl3945_cmd *qcmd;
  662. /* Cancel the CMD_WANT_SKB flag for the cmd in the
  663. * TX cmd queue. Otherwise in case the cmd comes
  664. * in later, it will possibly set an invalid
  665. * address (cmd->meta.source). */
  666. qcmd = &priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_idx];
  667. qcmd->meta.flags &= ~CMD_WANT_SKB;
  668. }
  669. fail:
  670. if (cmd->meta.u.skb) {
  671. dev_kfree_skb_any(cmd->meta.u.skb);
  672. cmd->meta.u.skb = NULL;
  673. }
  674. out:
  675. clear_bit(STATUS_HCMD_SYNC_ACTIVE, &priv->status);
  676. return ret;
  677. }
  678. int iwl3945_send_cmd(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
  679. {
  680. if (cmd->meta.flags & CMD_ASYNC)
  681. return iwl3945_send_cmd_async(priv, cmd);
  682. return iwl3945_send_cmd_sync(priv, cmd);
  683. }
  684. int iwl3945_send_cmd_pdu(struct iwl3945_priv *priv, u8 id, u16 len, const void *data)
  685. {
  686. struct iwl3945_host_cmd cmd = {
  687. .id = id,
  688. .len = len,
  689. .data = data,
  690. };
  691. return iwl3945_send_cmd_sync(priv, &cmd);
  692. }
  693. static int __must_check iwl3945_send_cmd_u32(struct iwl3945_priv *priv, u8 id, u32 val)
  694. {
  695. struct iwl3945_host_cmd cmd = {
  696. .id = id,
  697. .len = sizeof(val),
  698. .data = &val,
  699. };
  700. return iwl3945_send_cmd_sync(priv, &cmd);
  701. }
  702. int iwl3945_send_statistics_request(struct iwl3945_priv *priv)
  703. {
  704. return iwl3945_send_cmd_u32(priv, REPLY_STATISTICS_CMD, 0);
  705. }
  706. /**
  707. * iwl3945_set_rxon_channel - Set the phymode and channel values in staging RXON
  708. * @band: 2.4 or 5 GHz band
  709. * @channel: Any channel valid for the requested band
  710. * In addition to setting the staging RXON, priv->band is also set.
  711. *
  712. * NOTE: Does not commit to the hardware; it sets appropriate bit fields
  713. * in the staging RXON flag structure based on the band
  714. */
  715. static int iwl3945_set_rxon_channel(struct iwl3945_priv *priv,
  716. enum ieee80211_band band,
  717. u16 channel)
  718. {
  719. if (!iwl3945_get_channel_info(priv, band, channel)) {
  720. IWL_DEBUG_INFO("Could not set channel to %d [%d]\n",
  721. channel, band);
  722. return -EINVAL;
  723. }
  724. if ((le16_to_cpu(priv->staging_rxon.channel) == channel) &&
  725. (priv->band == band))
  726. return 0;
  727. priv->staging_rxon.channel = cpu_to_le16(channel);
  728. if (band == IEEE80211_BAND_5GHZ)
  729. priv->staging_rxon.flags &= ~RXON_FLG_BAND_24G_MSK;
  730. else
  731. priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
  732. priv->band = band;
  733. IWL_DEBUG_INFO("Staging channel set to %d [%d]\n", channel, band);
  734. return 0;
  735. }
  736. /**
  737. * iwl3945_check_rxon_cmd - validate RXON structure is valid
  738. *
  739. * NOTE: This is really only useful during development and can eventually
  740. * be #ifdef'd out once the driver is stable and folks aren't actively
  741. * making changes
  742. */
  743. static int iwl3945_check_rxon_cmd(struct iwl3945_rxon_cmd *rxon)
  744. {
  745. int error = 0;
  746. int counter = 1;
  747. if (rxon->flags & RXON_FLG_BAND_24G_MSK) {
  748. error |= le32_to_cpu(rxon->flags &
  749. (RXON_FLG_TGJ_NARROW_BAND_MSK |
  750. RXON_FLG_RADAR_DETECT_MSK));
  751. if (error)
  752. IWL_WARNING("check 24G fields %d | %d\n",
  753. counter++, error);
  754. } else {
  755. error |= (rxon->flags & RXON_FLG_SHORT_SLOT_MSK) ?
  756. 0 : le32_to_cpu(RXON_FLG_SHORT_SLOT_MSK);
  757. if (error)
  758. IWL_WARNING("check 52 fields %d | %d\n",
  759. counter++, error);
  760. error |= le32_to_cpu(rxon->flags & RXON_FLG_CCK_MSK);
  761. if (error)
  762. IWL_WARNING("check 52 CCK %d | %d\n",
  763. counter++, error);
  764. }
  765. error |= (rxon->node_addr[0] | rxon->bssid_addr[0]) & 0x1;
  766. if (error)
  767. IWL_WARNING("check mac addr %d | %d\n", counter++, error);
  768. /* make sure basic rates 6Mbps and 1Mbps are supported */
  769. error |= (((rxon->ofdm_basic_rates & IWL_RATE_6M_MASK) == 0) &&
  770. ((rxon->cck_basic_rates & IWL_RATE_1M_MASK) == 0));
  771. if (error)
  772. IWL_WARNING("check basic rate %d | %d\n", counter++, error);
  773. error |= (le16_to_cpu(rxon->assoc_id) > 2007);
  774. if (error)
  775. IWL_WARNING("check assoc id %d | %d\n", counter++, error);
  776. error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK))
  777. == (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK));
  778. if (error)
  779. IWL_WARNING("check CCK and short slot %d | %d\n",
  780. counter++, error);
  781. error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK))
  782. == (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK));
  783. if (error)
  784. IWL_WARNING("check CCK & auto detect %d | %d\n",
  785. counter++, error);
  786. error |= ((rxon->flags & (RXON_FLG_AUTO_DETECT_MSK |
  787. RXON_FLG_TGG_PROTECT_MSK)) == RXON_FLG_TGG_PROTECT_MSK);
  788. if (error)
  789. IWL_WARNING("check TGG and auto detect %d | %d\n",
  790. counter++, error);
  791. if ((rxon->flags & RXON_FLG_DIS_DIV_MSK))
  792. error |= ((rxon->flags & (RXON_FLG_ANT_B_MSK |
  793. RXON_FLG_ANT_A_MSK)) == 0);
  794. if (error)
  795. IWL_WARNING("check antenna %d %d\n", counter++, error);
  796. if (error)
  797. IWL_WARNING("Tuning to channel %d\n",
  798. le16_to_cpu(rxon->channel));
  799. if (error) {
  800. IWL_ERROR("Not a valid iwl3945_rxon_assoc_cmd field values\n");
  801. return -1;
  802. }
  803. return 0;
  804. }
  805. /**
  806. * iwl3945_full_rxon_required - check if full RXON (vs RXON_ASSOC) cmd is needed
  807. * @priv: staging_rxon is compared to active_rxon
  808. *
  809. * If the RXON structure is changing enough to require a new tune,
  810. * or is clearing the RXON_FILTER_ASSOC_MSK, then return 1 to indicate that
  811. * a new tune (full RXON command, rather than RXON_ASSOC cmd) is required.
  812. */
  813. static int iwl3945_full_rxon_required(struct iwl3945_priv *priv)
  814. {
  815. /* These items are only settable from the full RXON command */
  816. if (!(iwl3945_is_associated(priv)) ||
  817. compare_ether_addr(priv->staging_rxon.bssid_addr,
  818. priv->active_rxon.bssid_addr) ||
  819. compare_ether_addr(priv->staging_rxon.node_addr,
  820. priv->active_rxon.node_addr) ||
  821. compare_ether_addr(priv->staging_rxon.wlap_bssid_addr,
  822. priv->active_rxon.wlap_bssid_addr) ||
  823. (priv->staging_rxon.dev_type != priv->active_rxon.dev_type) ||
  824. (priv->staging_rxon.channel != priv->active_rxon.channel) ||
  825. (priv->staging_rxon.air_propagation !=
  826. priv->active_rxon.air_propagation) ||
  827. (priv->staging_rxon.assoc_id != priv->active_rxon.assoc_id))
  828. return 1;
  829. /* flags, filter_flags, ofdm_basic_rates, and cck_basic_rates can
  830. * be updated with the RXON_ASSOC command -- however only some
  831. * flag transitions are allowed using RXON_ASSOC */
  832. /* Check if we are not switching bands */
  833. if ((priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) !=
  834. (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK))
  835. return 1;
  836. /* Check if we are switching association toggle */
  837. if ((priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) !=
  838. (priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK))
  839. return 1;
  840. return 0;
  841. }
  842. static int iwl3945_send_rxon_assoc(struct iwl3945_priv *priv)
  843. {
  844. int rc = 0;
  845. struct iwl3945_rx_packet *res = NULL;
  846. struct iwl3945_rxon_assoc_cmd rxon_assoc;
  847. struct iwl3945_host_cmd cmd = {
  848. .id = REPLY_RXON_ASSOC,
  849. .len = sizeof(rxon_assoc),
  850. .meta.flags = CMD_WANT_SKB,
  851. .data = &rxon_assoc,
  852. };
  853. const struct iwl3945_rxon_cmd *rxon1 = &priv->staging_rxon;
  854. const struct iwl3945_rxon_cmd *rxon2 = &priv->active_rxon;
  855. if ((rxon1->flags == rxon2->flags) &&
  856. (rxon1->filter_flags == rxon2->filter_flags) &&
  857. (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
  858. (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
  859. IWL_DEBUG_INFO("Using current RXON_ASSOC. Not resending.\n");
  860. return 0;
  861. }
  862. rxon_assoc.flags = priv->staging_rxon.flags;
  863. rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
  864. rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
  865. rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
  866. rxon_assoc.reserved = 0;
  867. rc = iwl3945_send_cmd_sync(priv, &cmd);
  868. if (rc)
  869. return rc;
  870. res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
  871. if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
  872. IWL_ERROR("Bad return from REPLY_RXON_ASSOC command\n");
  873. rc = -EIO;
  874. }
  875. priv->alloc_rxb_skb--;
  876. dev_kfree_skb_any(cmd.meta.u.skb);
  877. return rc;
  878. }
  879. /**
  880. * iwl3945_commit_rxon - commit staging_rxon to hardware
  881. *
  882. * The RXON command in staging_rxon is committed to the hardware and
  883. * the active_rxon structure is updated with the new data. This
  884. * function correctly transitions out of the RXON_ASSOC_MSK state if
  885. * a HW tune is required based on the RXON structure changes.
  886. */
  887. static int iwl3945_commit_rxon(struct iwl3945_priv *priv)
  888. {
  889. /* cast away the const for active_rxon in this function */
  890. struct iwl3945_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
  891. int rc = 0;
  892. DECLARE_MAC_BUF(mac);
  893. if (!iwl3945_is_alive(priv))
  894. return -1;
  895. /* always get timestamp with Rx frame */
  896. priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
  897. /* select antenna */
  898. priv->staging_rxon.flags &=
  899. ~(RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_SEL_MSK);
  900. priv->staging_rxon.flags |= iwl3945_get_antenna_flags(priv);
  901. rc = iwl3945_check_rxon_cmd(&priv->staging_rxon);
  902. if (rc) {
  903. IWL_ERROR("Invalid RXON configuration. Not committing.\n");
  904. return -EINVAL;
  905. }
  906. /* If we don't need to send a full RXON, we can use
  907. * iwl3945_rxon_assoc_cmd which is used to reconfigure filter
  908. * and other flags for the current radio configuration. */
  909. if (!iwl3945_full_rxon_required(priv)) {
  910. rc = iwl3945_send_rxon_assoc(priv);
  911. if (rc) {
  912. IWL_ERROR("Error setting RXON_ASSOC "
  913. "configuration (%d).\n", rc);
  914. return rc;
  915. }
  916. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  917. return 0;
  918. }
  919. /* If we are currently associated and the new config requires
  920. * an RXON_ASSOC and the new config wants the associated mask enabled,
  921. * we must clear the associated from the active configuration
  922. * before we apply the new config */
  923. if (iwl3945_is_associated(priv) &&
  924. (priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK)) {
  925. IWL_DEBUG_INFO("Toggling associated bit on current RXON\n");
  926. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  927. rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON,
  928. sizeof(struct iwl3945_rxon_cmd),
  929. &priv->active_rxon);
  930. /* If the mask clearing failed then we set
  931. * active_rxon back to what it was previously */
  932. if (rc) {
  933. active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
  934. IWL_ERROR("Error clearing ASSOC_MSK on current "
  935. "configuration (%d).\n", rc);
  936. return rc;
  937. }
  938. }
  939. IWL_DEBUG_INFO("Sending RXON\n"
  940. "* with%s RXON_FILTER_ASSOC_MSK\n"
  941. "* channel = %d\n"
  942. "* bssid = %s\n",
  943. ((priv->staging_rxon.filter_flags &
  944. RXON_FILTER_ASSOC_MSK) ? "" : "out"),
  945. le16_to_cpu(priv->staging_rxon.channel),
  946. print_mac(mac, priv->staging_rxon.bssid_addr));
  947. /* Apply the new configuration */
  948. rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON,
  949. sizeof(struct iwl3945_rxon_cmd), &priv->staging_rxon);
  950. if (rc) {
  951. IWL_ERROR("Error setting new configuration (%d).\n", rc);
  952. return rc;
  953. }
  954. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  955. iwl3945_clear_stations_table(priv);
  956. /* If we issue a new RXON command which required a tune then we must
  957. * send a new TXPOWER command or we won't be able to Tx any frames */
  958. rc = iwl3945_hw_reg_send_txpower(priv);
  959. if (rc) {
  960. IWL_ERROR("Error setting Tx power (%d).\n", rc);
  961. return rc;
  962. }
  963. /* Add the broadcast address so we can send broadcast frames */
  964. if (iwl3945_add_station(priv, iwl3945_broadcast_addr, 0, 0) ==
  965. IWL_INVALID_STATION) {
  966. IWL_ERROR("Error adding BROADCAST address for transmit.\n");
  967. return -EIO;
  968. }
  969. /* If we have set the ASSOC_MSK and we are in BSS mode then
  970. * add the IWL_AP_ID to the station rate table */
  971. if (iwl3945_is_associated(priv) &&
  972. (priv->iw_mode == IEEE80211_IF_TYPE_STA))
  973. if (iwl3945_add_station(priv, priv->active_rxon.bssid_addr, 1, 0)
  974. == IWL_INVALID_STATION) {
  975. IWL_ERROR("Error adding AP address for transmit.\n");
  976. return -EIO;
  977. }
  978. /* Init the hardware's rate fallback order based on the band */
  979. rc = iwl3945_init_hw_rate_table(priv);
  980. if (rc) {
  981. IWL_ERROR("Error setting HW rate table: %02X\n", rc);
  982. return -EIO;
  983. }
  984. return 0;
  985. }
  986. static int iwl3945_send_bt_config(struct iwl3945_priv *priv)
  987. {
  988. struct iwl3945_bt_cmd bt_cmd = {
  989. .flags = 3,
  990. .lead_time = 0xAA,
  991. .max_kill = 1,
  992. .kill_ack_mask = 0,
  993. .kill_cts_mask = 0,
  994. };
  995. return iwl3945_send_cmd_pdu(priv, REPLY_BT_CONFIG,
  996. sizeof(struct iwl3945_bt_cmd), &bt_cmd);
  997. }
  998. static int iwl3945_send_scan_abort(struct iwl3945_priv *priv)
  999. {
  1000. int rc = 0;
  1001. struct iwl3945_rx_packet *res;
  1002. struct iwl3945_host_cmd cmd = {
  1003. .id = REPLY_SCAN_ABORT_CMD,
  1004. .meta.flags = CMD_WANT_SKB,
  1005. };
  1006. /* If there isn't a scan actively going on in the hardware
  1007. * then we are in between scan bands and not actually
  1008. * actively scanning, so don't send the abort command */
  1009. if (!test_bit(STATUS_SCAN_HW, &priv->status)) {
  1010. clear_bit(STATUS_SCAN_ABORTING, &priv->status);
  1011. return 0;
  1012. }
  1013. rc = iwl3945_send_cmd_sync(priv, &cmd);
  1014. if (rc) {
  1015. clear_bit(STATUS_SCAN_ABORTING, &priv->status);
  1016. return rc;
  1017. }
  1018. res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
  1019. if (res->u.status != CAN_ABORT_STATUS) {
  1020. /* The scan abort will return 1 for success or
  1021. * 2 for "failure". A failure condition can be
  1022. * due to simply not being in an active scan which
  1023. * can occur if we send the scan abort before we
  1024. * the microcode has notified us that a scan is
  1025. * completed. */
  1026. IWL_DEBUG_INFO("SCAN_ABORT returned %d.\n", res->u.status);
  1027. clear_bit(STATUS_SCAN_ABORTING, &priv->status);
  1028. clear_bit(STATUS_SCAN_HW, &priv->status);
  1029. }
  1030. dev_kfree_skb_any(cmd.meta.u.skb);
  1031. return rc;
  1032. }
  1033. static int iwl3945_card_state_sync_callback(struct iwl3945_priv *priv,
  1034. struct iwl3945_cmd *cmd,
  1035. struct sk_buff *skb)
  1036. {
  1037. return 1;
  1038. }
  1039. /*
  1040. * CARD_STATE_CMD
  1041. *
  1042. * Use: Sets the device's internal card state to enable, disable, or halt
  1043. *
  1044. * When in the 'enable' state the card operates as normal.
  1045. * When in the 'disable' state, the card enters into a low power mode.
  1046. * When in the 'halt' state, the card is shut down and must be fully
  1047. * restarted to come back on.
  1048. */
  1049. static int iwl3945_send_card_state(struct iwl3945_priv *priv, u32 flags, u8 meta_flag)
  1050. {
  1051. struct iwl3945_host_cmd cmd = {
  1052. .id = REPLY_CARD_STATE_CMD,
  1053. .len = sizeof(u32),
  1054. .data = &flags,
  1055. .meta.flags = meta_flag,
  1056. };
  1057. if (meta_flag & CMD_ASYNC)
  1058. cmd.meta.u.callback = iwl3945_card_state_sync_callback;
  1059. return iwl3945_send_cmd(priv, &cmd);
  1060. }
  1061. static int iwl3945_add_sta_sync_callback(struct iwl3945_priv *priv,
  1062. struct iwl3945_cmd *cmd, struct sk_buff *skb)
  1063. {
  1064. struct iwl3945_rx_packet *res = NULL;
  1065. if (!skb) {
  1066. IWL_ERROR("Error: Response NULL in REPLY_ADD_STA.\n");
  1067. return 1;
  1068. }
  1069. res = (struct iwl3945_rx_packet *)skb->data;
  1070. if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
  1071. IWL_ERROR("Bad return from REPLY_ADD_STA (0x%08X)\n",
  1072. res->hdr.flags);
  1073. return 1;
  1074. }
  1075. switch (res->u.add_sta.status) {
  1076. case ADD_STA_SUCCESS_MSK:
  1077. break;
  1078. default:
  1079. break;
  1080. }
  1081. /* We didn't cache the SKB; let the caller free it */
  1082. return 1;
  1083. }
  1084. int iwl3945_send_add_station(struct iwl3945_priv *priv,
  1085. struct iwl3945_addsta_cmd *sta, u8 flags)
  1086. {
  1087. struct iwl3945_rx_packet *res = NULL;
  1088. int rc = 0;
  1089. struct iwl3945_host_cmd cmd = {
  1090. .id = REPLY_ADD_STA,
  1091. .len = sizeof(struct iwl3945_addsta_cmd),
  1092. .meta.flags = flags,
  1093. .data = sta,
  1094. };
  1095. if (flags & CMD_ASYNC)
  1096. cmd.meta.u.callback = iwl3945_add_sta_sync_callback;
  1097. else
  1098. cmd.meta.flags |= CMD_WANT_SKB;
  1099. rc = iwl3945_send_cmd(priv, &cmd);
  1100. if (rc || (flags & CMD_ASYNC))
  1101. return rc;
  1102. res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
  1103. if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
  1104. IWL_ERROR("Bad return from REPLY_ADD_STA (0x%08X)\n",
  1105. res->hdr.flags);
  1106. rc = -EIO;
  1107. }
  1108. if (rc == 0) {
  1109. switch (res->u.add_sta.status) {
  1110. case ADD_STA_SUCCESS_MSK:
  1111. IWL_DEBUG_INFO("REPLY_ADD_STA PASSED\n");
  1112. break;
  1113. default:
  1114. rc = -EIO;
  1115. IWL_WARNING("REPLY_ADD_STA failed\n");
  1116. break;
  1117. }
  1118. }
  1119. priv->alloc_rxb_skb--;
  1120. dev_kfree_skb_any(cmd.meta.u.skb);
  1121. return rc;
  1122. }
  1123. static int iwl3945_update_sta_key_info(struct iwl3945_priv *priv,
  1124. struct ieee80211_key_conf *keyconf,
  1125. u8 sta_id)
  1126. {
  1127. unsigned long flags;
  1128. __le16 key_flags = 0;
  1129. switch (keyconf->alg) {
  1130. case ALG_CCMP:
  1131. key_flags |= STA_KEY_FLG_CCMP;
  1132. key_flags |= cpu_to_le16(
  1133. keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
  1134. key_flags &= ~STA_KEY_FLG_INVALID;
  1135. break;
  1136. case ALG_TKIP:
  1137. case ALG_WEP:
  1138. default:
  1139. return -EINVAL;
  1140. }
  1141. spin_lock_irqsave(&priv->sta_lock, flags);
  1142. priv->stations[sta_id].keyinfo.alg = keyconf->alg;
  1143. priv->stations[sta_id].keyinfo.keylen = keyconf->keylen;
  1144. memcpy(priv->stations[sta_id].keyinfo.key, keyconf->key,
  1145. keyconf->keylen);
  1146. memcpy(priv->stations[sta_id].sta.key.key, keyconf->key,
  1147. keyconf->keylen);
  1148. priv->stations[sta_id].sta.key.key_flags = key_flags;
  1149. priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
  1150. priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  1151. spin_unlock_irqrestore(&priv->sta_lock, flags);
  1152. IWL_DEBUG_INFO("hwcrypto: modify ucode station key info\n");
  1153. iwl3945_send_add_station(priv, &priv->stations[sta_id].sta, 0);
  1154. return 0;
  1155. }
  1156. static int iwl3945_clear_sta_key_info(struct iwl3945_priv *priv, u8 sta_id)
  1157. {
  1158. unsigned long flags;
  1159. spin_lock_irqsave(&priv->sta_lock, flags);
  1160. memset(&priv->stations[sta_id].keyinfo, 0, sizeof(struct iwl3945_hw_key));
  1161. memset(&priv->stations[sta_id].sta.key, 0, sizeof(struct iwl3945_keyinfo));
  1162. priv->stations[sta_id].sta.key.key_flags = STA_KEY_FLG_NO_ENC;
  1163. priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
  1164. priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  1165. spin_unlock_irqrestore(&priv->sta_lock, flags);
  1166. IWL_DEBUG_INFO("hwcrypto: clear ucode station key info\n");
  1167. iwl3945_send_add_station(priv, &priv->stations[sta_id].sta, 0);
  1168. return 0;
  1169. }
  1170. static void iwl3945_clear_free_frames(struct iwl3945_priv *priv)
  1171. {
  1172. struct list_head *element;
  1173. IWL_DEBUG_INFO("%d frames on pre-allocated heap on clear.\n",
  1174. priv->frames_count);
  1175. while (!list_empty(&priv->free_frames)) {
  1176. element = priv->free_frames.next;
  1177. list_del(element);
  1178. kfree(list_entry(element, struct iwl3945_frame, list));
  1179. priv->frames_count--;
  1180. }
  1181. if (priv->frames_count) {
  1182. IWL_WARNING("%d frames still in use. Did we lose one?\n",
  1183. priv->frames_count);
  1184. priv->frames_count = 0;
  1185. }
  1186. }
  1187. static struct iwl3945_frame *iwl3945_get_free_frame(struct iwl3945_priv *priv)
  1188. {
  1189. struct iwl3945_frame *frame;
  1190. struct list_head *element;
  1191. if (list_empty(&priv->free_frames)) {
  1192. frame = kzalloc(sizeof(*frame), GFP_KERNEL);
  1193. if (!frame) {
  1194. IWL_ERROR("Could not allocate frame!\n");
  1195. return NULL;
  1196. }
  1197. priv->frames_count++;
  1198. return frame;
  1199. }
  1200. element = priv->free_frames.next;
  1201. list_del(element);
  1202. return list_entry(element, struct iwl3945_frame, list);
  1203. }
  1204. static void iwl3945_free_frame(struct iwl3945_priv *priv, struct iwl3945_frame *frame)
  1205. {
  1206. memset(frame, 0, sizeof(*frame));
  1207. list_add(&frame->list, &priv->free_frames);
  1208. }
  1209. unsigned int iwl3945_fill_beacon_frame(struct iwl3945_priv *priv,
  1210. struct ieee80211_hdr *hdr,
  1211. const u8 *dest, int left)
  1212. {
  1213. if (!iwl3945_is_associated(priv) || !priv->ibss_beacon ||
  1214. ((priv->iw_mode != IEEE80211_IF_TYPE_IBSS) &&
  1215. (priv->iw_mode != IEEE80211_IF_TYPE_AP)))
  1216. return 0;
  1217. if (priv->ibss_beacon->len > left)
  1218. return 0;
  1219. memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
  1220. return priv->ibss_beacon->len;
  1221. }
  1222. static u8 iwl3945_rate_get_lowest_plcp(int rate_mask)
  1223. {
  1224. u8 i;
  1225. for (i = IWL_RATE_1M_INDEX; i != IWL_RATE_INVALID;
  1226. i = iwl3945_rates[i].next_ieee) {
  1227. if (rate_mask & (1 << i))
  1228. return iwl3945_rates[i].plcp;
  1229. }
  1230. return IWL_RATE_INVALID;
  1231. }
  1232. static int iwl3945_send_beacon_cmd(struct iwl3945_priv *priv)
  1233. {
  1234. struct iwl3945_frame *frame;
  1235. unsigned int frame_size;
  1236. int rc;
  1237. u8 rate;
  1238. frame = iwl3945_get_free_frame(priv);
  1239. if (!frame) {
  1240. IWL_ERROR("Could not obtain free frame buffer for beacon "
  1241. "command.\n");
  1242. return -ENOMEM;
  1243. }
  1244. if (!(priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK)) {
  1245. rate = iwl3945_rate_get_lowest_plcp(priv->active_rate_basic &
  1246. 0xFF0);
  1247. if (rate == IWL_INVALID_RATE)
  1248. rate = IWL_RATE_6M_PLCP;
  1249. } else {
  1250. rate = iwl3945_rate_get_lowest_plcp(priv->active_rate_basic & 0xF);
  1251. if (rate == IWL_INVALID_RATE)
  1252. rate = IWL_RATE_1M_PLCP;
  1253. }
  1254. frame_size = iwl3945_hw_get_beacon_cmd(priv, frame, rate);
  1255. rc = iwl3945_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
  1256. &frame->u.cmd[0]);
  1257. iwl3945_free_frame(priv, frame);
  1258. return rc;
  1259. }
  1260. /******************************************************************************
  1261. *
  1262. * EEPROM related functions
  1263. *
  1264. ******************************************************************************/
  1265. static void get_eeprom_mac(struct iwl3945_priv *priv, u8 *mac)
  1266. {
  1267. memcpy(mac, priv->eeprom.mac_address, 6);
  1268. }
  1269. /*
  1270. * Clear the OWNER_MSK, to establish driver (instead of uCode running on
  1271. * embedded controller) as EEPROM reader; each read is a series of pulses
  1272. * to/from the EEPROM chip, not a single event, so even reads could conflict
  1273. * if they weren't arbitrated by some ownership mechanism. Here, the driver
  1274. * simply claims ownership, which should be safe when this function is called
  1275. * (i.e. before loading uCode!).
  1276. */
  1277. static inline int iwl3945_eeprom_acquire_semaphore(struct iwl3945_priv *priv)
  1278. {
  1279. _iwl3945_clear_bit(priv, CSR_EEPROM_GP, CSR_EEPROM_GP_IF_OWNER_MSK);
  1280. return 0;
  1281. }
  1282. /**
  1283. * iwl3945_eeprom_init - read EEPROM contents
  1284. *
  1285. * Load the EEPROM contents from adapter into priv->eeprom
  1286. *
  1287. * NOTE: This routine uses the non-debug IO access functions.
  1288. */
  1289. int iwl3945_eeprom_init(struct iwl3945_priv *priv)
  1290. {
  1291. u16 *e = (u16 *)&priv->eeprom;
  1292. u32 gp = iwl3945_read32(priv, CSR_EEPROM_GP);
  1293. u32 r;
  1294. int sz = sizeof(priv->eeprom);
  1295. int rc;
  1296. int i;
  1297. u16 addr;
  1298. /* The EEPROM structure has several padding buffers within it
  1299. * and when adding new EEPROM maps is subject to programmer errors
  1300. * which may be very difficult to identify without explicitly
  1301. * checking the resulting size of the eeprom map. */
  1302. BUILD_BUG_ON(sizeof(priv->eeprom) != IWL_EEPROM_IMAGE_SIZE);
  1303. if ((gp & CSR_EEPROM_GP_VALID_MSK) == CSR_EEPROM_GP_BAD_SIGNATURE) {
  1304. IWL_ERROR("EEPROM not found, EEPROM_GP=0x%08x", gp);
  1305. return -ENOENT;
  1306. }
  1307. /* Make sure driver (instead of uCode) is allowed to read EEPROM */
  1308. rc = iwl3945_eeprom_acquire_semaphore(priv);
  1309. if (rc < 0) {
  1310. IWL_ERROR("Failed to acquire EEPROM semaphore.\n");
  1311. return -ENOENT;
  1312. }
  1313. /* eeprom is an array of 16bit values */
  1314. for (addr = 0; addr < sz; addr += sizeof(u16)) {
  1315. _iwl3945_write32(priv, CSR_EEPROM_REG, addr << 1);
  1316. _iwl3945_clear_bit(priv, CSR_EEPROM_REG, CSR_EEPROM_REG_BIT_CMD);
  1317. for (i = 0; i < IWL_EEPROM_ACCESS_TIMEOUT;
  1318. i += IWL_EEPROM_ACCESS_DELAY) {
  1319. r = _iwl3945_read_direct32(priv, CSR_EEPROM_REG);
  1320. if (r & CSR_EEPROM_REG_READ_VALID_MSK)
  1321. break;
  1322. udelay(IWL_EEPROM_ACCESS_DELAY);
  1323. }
  1324. if (!(r & CSR_EEPROM_REG_READ_VALID_MSK)) {
  1325. IWL_ERROR("Time out reading EEPROM[%d]", addr);
  1326. return -ETIMEDOUT;
  1327. }
  1328. e[addr / 2] = le16_to_cpu((__force __le16)(r >> 16));
  1329. }
  1330. return 0;
  1331. }
  1332. static void iwl3945_unset_hw_setting(struct iwl3945_priv *priv)
  1333. {
  1334. if (priv->hw_setting.shared_virt)
  1335. pci_free_consistent(priv->pci_dev,
  1336. sizeof(struct iwl3945_shared),
  1337. priv->hw_setting.shared_virt,
  1338. priv->hw_setting.shared_phys);
  1339. }
  1340. /**
  1341. * iwl3945_supported_rate_to_ie - fill in the supported rate in IE field
  1342. *
  1343. * return : set the bit for each supported rate insert in ie
  1344. */
  1345. static u16 iwl3945_supported_rate_to_ie(u8 *ie, u16 supported_rate,
  1346. u16 basic_rate, int *left)
  1347. {
  1348. u16 ret_rates = 0, bit;
  1349. int i;
  1350. u8 *cnt = ie;
  1351. u8 *rates = ie + 1;
  1352. for (bit = 1, i = 0; i < IWL_RATE_COUNT; i++, bit <<= 1) {
  1353. if (bit & supported_rate) {
  1354. ret_rates |= bit;
  1355. rates[*cnt] = iwl3945_rates[i].ieee |
  1356. ((bit & basic_rate) ? 0x80 : 0x00);
  1357. (*cnt)++;
  1358. (*left)--;
  1359. if ((*left <= 0) ||
  1360. (*cnt >= IWL_SUPPORTED_RATES_IE_LEN))
  1361. break;
  1362. }
  1363. }
  1364. return ret_rates;
  1365. }
  1366. /**
  1367. * iwl3945_fill_probe_req - fill in all required fields and IE for probe request
  1368. */
  1369. static u16 iwl3945_fill_probe_req(struct iwl3945_priv *priv,
  1370. struct ieee80211_mgmt *frame,
  1371. int left, int is_direct)
  1372. {
  1373. int len = 0;
  1374. u8 *pos = NULL;
  1375. u16 active_rates, ret_rates, cck_rates;
  1376. /* Make sure there is enough space for the probe request,
  1377. * two mandatory IEs and the data */
  1378. left -= 24;
  1379. if (left < 0)
  1380. return 0;
  1381. len += 24;
  1382. frame->frame_control = cpu_to_le16(IEEE80211_STYPE_PROBE_REQ);
  1383. memcpy(frame->da, iwl3945_broadcast_addr, ETH_ALEN);
  1384. memcpy(frame->sa, priv->mac_addr, ETH_ALEN);
  1385. memcpy(frame->bssid, iwl3945_broadcast_addr, ETH_ALEN);
  1386. frame->seq_ctrl = 0;
  1387. /* fill in our indirect SSID IE */
  1388. /* ...next IE... */
  1389. left -= 2;
  1390. if (left < 0)
  1391. return 0;
  1392. len += 2;
  1393. pos = &(frame->u.probe_req.variable[0]);
  1394. *pos++ = WLAN_EID_SSID;
  1395. *pos++ = 0;
  1396. /* fill in our direct SSID IE... */
  1397. if (is_direct) {
  1398. /* ...next IE... */
  1399. left -= 2 + priv->essid_len;
  1400. if (left < 0)
  1401. return 0;
  1402. /* ... fill it in... */
  1403. *pos++ = WLAN_EID_SSID;
  1404. *pos++ = priv->essid_len;
  1405. memcpy(pos, priv->essid, priv->essid_len);
  1406. pos += priv->essid_len;
  1407. len += 2 + priv->essid_len;
  1408. }
  1409. /* fill in supported rate */
  1410. /* ...next IE... */
  1411. left -= 2;
  1412. if (left < 0)
  1413. return 0;
  1414. /* ... fill it in... */
  1415. *pos++ = WLAN_EID_SUPP_RATES;
  1416. *pos = 0;
  1417. priv->active_rate = priv->rates_mask;
  1418. active_rates = priv->active_rate;
  1419. priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
  1420. cck_rates = IWL_CCK_RATES_MASK & active_rates;
  1421. ret_rates = iwl3945_supported_rate_to_ie(pos, cck_rates,
  1422. priv->active_rate_basic, &left);
  1423. active_rates &= ~ret_rates;
  1424. ret_rates = iwl3945_supported_rate_to_ie(pos, active_rates,
  1425. priv->active_rate_basic, &left);
  1426. active_rates &= ~ret_rates;
  1427. len += 2 + *pos;
  1428. pos += (*pos) + 1;
  1429. if (active_rates == 0)
  1430. goto fill_end;
  1431. /* fill in supported extended rate */
  1432. /* ...next IE... */
  1433. left -= 2;
  1434. if (left < 0)
  1435. return 0;
  1436. /* ... fill it in... */
  1437. *pos++ = WLAN_EID_EXT_SUPP_RATES;
  1438. *pos = 0;
  1439. iwl3945_supported_rate_to_ie(pos, active_rates,
  1440. priv->active_rate_basic, &left);
  1441. if (*pos > 0)
  1442. len += 2 + *pos;
  1443. fill_end:
  1444. return (u16)len;
  1445. }
  1446. /*
  1447. * QoS support
  1448. */
  1449. static int iwl3945_send_qos_params_command(struct iwl3945_priv *priv,
  1450. struct iwl3945_qosparam_cmd *qos)
  1451. {
  1452. return iwl3945_send_cmd_pdu(priv, REPLY_QOS_PARAM,
  1453. sizeof(struct iwl3945_qosparam_cmd), qos);
  1454. }
  1455. static void iwl3945_reset_qos(struct iwl3945_priv *priv)
  1456. {
  1457. u16 cw_min = 15;
  1458. u16 cw_max = 1023;
  1459. u8 aifs = 2;
  1460. u8 is_legacy = 0;
  1461. unsigned long flags;
  1462. int i;
  1463. spin_lock_irqsave(&priv->lock, flags);
  1464. priv->qos_data.qos_active = 0;
  1465. if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS) {
  1466. if (priv->qos_data.qos_enable)
  1467. priv->qos_data.qos_active = 1;
  1468. if (!(priv->active_rate & 0xfff0)) {
  1469. cw_min = 31;
  1470. is_legacy = 1;
  1471. }
  1472. } else if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
  1473. if (priv->qos_data.qos_enable)
  1474. priv->qos_data.qos_active = 1;
  1475. } else if (!(priv->staging_rxon.flags & RXON_FLG_SHORT_SLOT_MSK)) {
  1476. cw_min = 31;
  1477. is_legacy = 1;
  1478. }
  1479. if (priv->qos_data.qos_active)
  1480. aifs = 3;
  1481. priv->qos_data.def_qos_parm.ac[0].cw_min = cpu_to_le16(cw_min);
  1482. priv->qos_data.def_qos_parm.ac[0].cw_max = cpu_to_le16(cw_max);
  1483. priv->qos_data.def_qos_parm.ac[0].aifsn = aifs;
  1484. priv->qos_data.def_qos_parm.ac[0].edca_txop = 0;
  1485. priv->qos_data.def_qos_parm.ac[0].reserved1 = 0;
  1486. if (priv->qos_data.qos_active) {
  1487. i = 1;
  1488. priv->qos_data.def_qos_parm.ac[i].cw_min = cpu_to_le16(cw_min);
  1489. priv->qos_data.def_qos_parm.ac[i].cw_max = cpu_to_le16(cw_max);
  1490. priv->qos_data.def_qos_parm.ac[i].aifsn = 7;
  1491. priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
  1492. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  1493. i = 2;
  1494. priv->qos_data.def_qos_parm.ac[i].cw_min =
  1495. cpu_to_le16((cw_min + 1) / 2 - 1);
  1496. priv->qos_data.def_qos_parm.ac[i].cw_max =
  1497. cpu_to_le16(cw_max);
  1498. priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
  1499. if (is_legacy)
  1500. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  1501. cpu_to_le16(6016);
  1502. else
  1503. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  1504. cpu_to_le16(3008);
  1505. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  1506. i = 3;
  1507. priv->qos_data.def_qos_parm.ac[i].cw_min =
  1508. cpu_to_le16((cw_min + 1) / 4 - 1);
  1509. priv->qos_data.def_qos_parm.ac[i].cw_max =
  1510. cpu_to_le16((cw_max + 1) / 2 - 1);
  1511. priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
  1512. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  1513. if (is_legacy)
  1514. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  1515. cpu_to_le16(3264);
  1516. else
  1517. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  1518. cpu_to_le16(1504);
  1519. } else {
  1520. for (i = 1; i < 4; i++) {
  1521. priv->qos_data.def_qos_parm.ac[i].cw_min =
  1522. cpu_to_le16(cw_min);
  1523. priv->qos_data.def_qos_parm.ac[i].cw_max =
  1524. cpu_to_le16(cw_max);
  1525. priv->qos_data.def_qos_parm.ac[i].aifsn = aifs;
  1526. priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
  1527. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  1528. }
  1529. }
  1530. IWL_DEBUG_QOS("set QoS to default \n");
  1531. spin_unlock_irqrestore(&priv->lock, flags);
  1532. }
  1533. static void iwl3945_activate_qos(struct iwl3945_priv *priv, u8 force)
  1534. {
  1535. unsigned long flags;
  1536. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1537. return;
  1538. if (!priv->qos_data.qos_enable)
  1539. return;
  1540. spin_lock_irqsave(&priv->lock, flags);
  1541. priv->qos_data.def_qos_parm.qos_flags = 0;
  1542. if (priv->qos_data.qos_cap.q_AP.queue_request &&
  1543. !priv->qos_data.qos_cap.q_AP.txop_request)
  1544. priv->qos_data.def_qos_parm.qos_flags |=
  1545. QOS_PARAM_FLG_TXOP_TYPE_MSK;
  1546. if (priv->qos_data.qos_active)
  1547. priv->qos_data.def_qos_parm.qos_flags |=
  1548. QOS_PARAM_FLG_UPDATE_EDCA_MSK;
  1549. spin_unlock_irqrestore(&priv->lock, flags);
  1550. if (force || iwl3945_is_associated(priv)) {
  1551. IWL_DEBUG_QOS("send QoS cmd with Qos active %d \n",
  1552. priv->qos_data.qos_active);
  1553. iwl3945_send_qos_params_command(priv,
  1554. &(priv->qos_data.def_qos_parm));
  1555. }
  1556. }
  1557. /*
  1558. * Power management (not Tx power!) functions
  1559. */
  1560. #define MSEC_TO_USEC 1024
  1561. #define NOSLP __constant_cpu_to_le32(0)
  1562. #define SLP IWL_POWER_DRIVER_ALLOW_SLEEP_MSK
  1563. #define SLP_TIMEOUT(T) __constant_cpu_to_le32((T) * MSEC_TO_USEC)
  1564. #define SLP_VEC(X0, X1, X2, X3, X4) {__constant_cpu_to_le32(X0), \
  1565. __constant_cpu_to_le32(X1), \
  1566. __constant_cpu_to_le32(X2), \
  1567. __constant_cpu_to_le32(X3), \
  1568. __constant_cpu_to_le32(X4)}
  1569. /* default power management (not Tx power) table values */
  1570. /* for tim 0-10 */
  1571. static struct iwl3945_power_vec_entry range_0[IWL_POWER_AC] = {
  1572. {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0},
  1573. {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500), SLP_VEC(1, 2, 3, 4, 4)}, 0},
  1574. {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300), SLP_VEC(2, 4, 6, 7, 7)}, 0},
  1575. {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100), SLP_VEC(2, 6, 9, 9, 10)}, 0},
  1576. {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 10)}, 1},
  1577. {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25), SLP_VEC(4, 7, 10, 10, 10)}, 1}
  1578. };
  1579. /* for tim > 10 */
  1580. static struct iwl3945_power_vec_entry range_1[IWL_POWER_AC] = {
  1581. {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0},
  1582. {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500),
  1583. SLP_VEC(1, 2, 3, 4, 0xFF)}, 0},
  1584. {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300),
  1585. SLP_VEC(2, 4, 6, 7, 0xFF)}, 0},
  1586. {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100),
  1587. SLP_VEC(2, 6, 9, 9, 0xFF)}, 0},
  1588. {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 0xFF)}, 0},
  1589. {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25),
  1590. SLP_VEC(4, 7, 10, 10, 0xFF)}, 0}
  1591. };
  1592. int iwl3945_power_init_handle(struct iwl3945_priv *priv)
  1593. {
  1594. int rc = 0, i;
  1595. struct iwl3945_power_mgr *pow_data;
  1596. int size = sizeof(struct iwl3945_power_vec_entry) * IWL_POWER_AC;
  1597. u16 pci_pm;
  1598. IWL_DEBUG_POWER("Initialize power \n");
  1599. pow_data = &(priv->power_data);
  1600. memset(pow_data, 0, sizeof(*pow_data));
  1601. pow_data->active_index = IWL_POWER_RANGE_0;
  1602. pow_data->dtim_val = 0xffff;
  1603. memcpy(&pow_data->pwr_range_0[0], &range_0[0], size);
  1604. memcpy(&pow_data->pwr_range_1[0], &range_1[0], size);
  1605. rc = pci_read_config_word(priv->pci_dev, PCI_LINK_CTRL, &pci_pm);
  1606. if (rc != 0)
  1607. return 0;
  1608. else {
  1609. struct iwl3945_powertable_cmd *cmd;
  1610. IWL_DEBUG_POWER("adjust power command flags\n");
  1611. for (i = 0; i < IWL_POWER_AC; i++) {
  1612. cmd = &pow_data->pwr_range_0[i].cmd;
  1613. if (pci_pm & 0x1)
  1614. cmd->flags &= ~IWL_POWER_PCI_PM_MSK;
  1615. else
  1616. cmd->flags |= IWL_POWER_PCI_PM_MSK;
  1617. }
  1618. }
  1619. return rc;
  1620. }
  1621. static int iwl3945_update_power_cmd(struct iwl3945_priv *priv,
  1622. struct iwl3945_powertable_cmd *cmd, u32 mode)
  1623. {
  1624. int rc = 0, i;
  1625. u8 skip;
  1626. u32 max_sleep = 0;
  1627. struct iwl3945_power_vec_entry *range;
  1628. u8 period = 0;
  1629. struct iwl3945_power_mgr *pow_data;
  1630. if (mode > IWL_POWER_INDEX_5) {
  1631. IWL_DEBUG_POWER("Error invalid power mode \n");
  1632. return -1;
  1633. }
  1634. pow_data = &(priv->power_data);
  1635. if (pow_data->active_index == IWL_POWER_RANGE_0)
  1636. range = &pow_data->pwr_range_0[0];
  1637. else
  1638. range = &pow_data->pwr_range_1[1];
  1639. memcpy(cmd, &range[mode].cmd, sizeof(struct iwl3945_powertable_cmd));
  1640. #ifdef IWL_MAC80211_DISABLE
  1641. if (priv->assoc_network != NULL) {
  1642. unsigned long flags;
  1643. period = priv->assoc_network->tim.tim_period;
  1644. }
  1645. #endif /*IWL_MAC80211_DISABLE */
  1646. skip = range[mode].no_dtim;
  1647. if (period == 0) {
  1648. period = 1;
  1649. skip = 0;
  1650. }
  1651. if (skip == 0) {
  1652. max_sleep = period;
  1653. cmd->flags &= ~IWL_POWER_SLEEP_OVER_DTIM_MSK;
  1654. } else {
  1655. __le32 slp_itrvl = cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1];
  1656. max_sleep = (le32_to_cpu(slp_itrvl) / period) * period;
  1657. cmd->flags |= IWL_POWER_SLEEP_OVER_DTIM_MSK;
  1658. }
  1659. for (i = 0; i < IWL_POWER_VEC_SIZE; i++) {
  1660. if (le32_to_cpu(cmd->sleep_interval[i]) > max_sleep)
  1661. cmd->sleep_interval[i] = cpu_to_le32(max_sleep);
  1662. }
  1663. IWL_DEBUG_POWER("Flags value = 0x%08X\n", cmd->flags);
  1664. IWL_DEBUG_POWER("Tx timeout = %u\n", le32_to_cpu(cmd->tx_data_timeout));
  1665. IWL_DEBUG_POWER("Rx timeout = %u\n", le32_to_cpu(cmd->rx_data_timeout));
  1666. IWL_DEBUG_POWER("Sleep interval vector = { %d , %d , %d , %d , %d }\n",
  1667. le32_to_cpu(cmd->sleep_interval[0]),
  1668. le32_to_cpu(cmd->sleep_interval[1]),
  1669. le32_to_cpu(cmd->sleep_interval[2]),
  1670. le32_to_cpu(cmd->sleep_interval[3]),
  1671. le32_to_cpu(cmd->sleep_interval[4]));
  1672. return rc;
  1673. }
  1674. static int iwl3945_send_power_mode(struct iwl3945_priv *priv, u32 mode)
  1675. {
  1676. u32 uninitialized_var(final_mode);
  1677. int rc;
  1678. struct iwl3945_powertable_cmd cmd;
  1679. /* If on battery, set to 3,
  1680. * if plugged into AC power, set to CAM ("continuously aware mode"),
  1681. * else user level */
  1682. switch (mode) {
  1683. case IWL_POWER_BATTERY:
  1684. final_mode = IWL_POWER_INDEX_3;
  1685. break;
  1686. case IWL_POWER_AC:
  1687. final_mode = IWL_POWER_MODE_CAM;
  1688. break;
  1689. default:
  1690. final_mode = mode;
  1691. break;
  1692. }
  1693. iwl3945_update_power_cmd(priv, &cmd, final_mode);
  1694. rc = iwl3945_send_cmd_pdu(priv, POWER_TABLE_CMD, sizeof(cmd), &cmd);
  1695. if (final_mode == IWL_POWER_MODE_CAM)
  1696. clear_bit(STATUS_POWER_PMI, &priv->status);
  1697. else
  1698. set_bit(STATUS_POWER_PMI, &priv->status);
  1699. return rc;
  1700. }
  1701. /**
  1702. * iwl3945_scan_cancel - Cancel any currently executing HW scan
  1703. *
  1704. * NOTE: priv->mutex is not required before calling this function
  1705. */
  1706. static int iwl3945_scan_cancel(struct iwl3945_priv *priv)
  1707. {
  1708. if (!test_bit(STATUS_SCAN_HW, &priv->status)) {
  1709. clear_bit(STATUS_SCANNING, &priv->status);
  1710. return 0;
  1711. }
  1712. if (test_bit(STATUS_SCANNING, &priv->status)) {
  1713. if (!test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  1714. IWL_DEBUG_SCAN("Queuing scan abort.\n");
  1715. set_bit(STATUS_SCAN_ABORTING, &priv->status);
  1716. queue_work(priv->workqueue, &priv->abort_scan);
  1717. } else
  1718. IWL_DEBUG_SCAN("Scan abort already in progress.\n");
  1719. return test_bit(STATUS_SCANNING, &priv->status);
  1720. }
  1721. return 0;
  1722. }
  1723. /**
  1724. * iwl3945_scan_cancel_timeout - Cancel any currently executing HW scan
  1725. * @ms: amount of time to wait (in milliseconds) for scan to abort
  1726. *
  1727. * NOTE: priv->mutex must be held before calling this function
  1728. */
  1729. static int iwl3945_scan_cancel_timeout(struct iwl3945_priv *priv, unsigned long ms)
  1730. {
  1731. unsigned long now = jiffies;
  1732. int ret;
  1733. ret = iwl3945_scan_cancel(priv);
  1734. if (ret && ms) {
  1735. mutex_unlock(&priv->mutex);
  1736. while (!time_after(jiffies, now + msecs_to_jiffies(ms)) &&
  1737. test_bit(STATUS_SCANNING, &priv->status))
  1738. msleep(1);
  1739. mutex_lock(&priv->mutex);
  1740. return test_bit(STATUS_SCANNING, &priv->status);
  1741. }
  1742. return ret;
  1743. }
  1744. #define MAX_UCODE_BEACON_INTERVAL 1024
  1745. #define INTEL_CONN_LISTEN_INTERVAL __constant_cpu_to_le16(0xA)
  1746. static __le16 iwl3945_adjust_beacon_interval(u16 beacon_val)
  1747. {
  1748. u16 new_val = 0;
  1749. u16 beacon_factor = 0;
  1750. beacon_factor =
  1751. (beacon_val + MAX_UCODE_BEACON_INTERVAL)
  1752. / MAX_UCODE_BEACON_INTERVAL;
  1753. new_val = beacon_val / beacon_factor;
  1754. return cpu_to_le16(new_val);
  1755. }
  1756. static void iwl3945_setup_rxon_timing(struct iwl3945_priv *priv)
  1757. {
  1758. u64 interval_tm_unit;
  1759. u64 tsf, result;
  1760. unsigned long flags;
  1761. struct ieee80211_conf *conf = NULL;
  1762. u16 beacon_int = 0;
  1763. conf = ieee80211_get_hw_conf(priv->hw);
  1764. spin_lock_irqsave(&priv->lock, flags);
  1765. priv->rxon_timing.timestamp.dw[1] = cpu_to_le32(priv->timestamp1);
  1766. priv->rxon_timing.timestamp.dw[0] = cpu_to_le32(priv->timestamp0);
  1767. priv->rxon_timing.listen_interval = INTEL_CONN_LISTEN_INTERVAL;
  1768. tsf = priv->timestamp1;
  1769. tsf = ((tsf << 32) | priv->timestamp0);
  1770. beacon_int = priv->beacon_int;
  1771. spin_unlock_irqrestore(&priv->lock, flags);
  1772. if (priv->iw_mode == IEEE80211_IF_TYPE_STA) {
  1773. if (beacon_int == 0) {
  1774. priv->rxon_timing.beacon_interval = cpu_to_le16(100);
  1775. priv->rxon_timing.beacon_init_val = cpu_to_le32(102400);
  1776. } else {
  1777. priv->rxon_timing.beacon_interval =
  1778. cpu_to_le16(beacon_int);
  1779. priv->rxon_timing.beacon_interval =
  1780. iwl3945_adjust_beacon_interval(
  1781. le16_to_cpu(priv->rxon_timing.beacon_interval));
  1782. }
  1783. priv->rxon_timing.atim_window = 0;
  1784. } else {
  1785. priv->rxon_timing.beacon_interval =
  1786. iwl3945_adjust_beacon_interval(conf->beacon_int);
  1787. /* TODO: we need to get atim_window from upper stack
  1788. * for now we set to 0 */
  1789. priv->rxon_timing.atim_window = 0;
  1790. }
  1791. interval_tm_unit =
  1792. (le16_to_cpu(priv->rxon_timing.beacon_interval) * 1024);
  1793. result = do_div(tsf, interval_tm_unit);
  1794. priv->rxon_timing.beacon_init_val =
  1795. cpu_to_le32((u32) ((u64) interval_tm_unit - result));
  1796. IWL_DEBUG_ASSOC
  1797. ("beacon interval %d beacon timer %d beacon tim %d\n",
  1798. le16_to_cpu(priv->rxon_timing.beacon_interval),
  1799. le32_to_cpu(priv->rxon_timing.beacon_init_val),
  1800. le16_to_cpu(priv->rxon_timing.atim_window));
  1801. }
  1802. static int iwl3945_scan_initiate(struct iwl3945_priv *priv)
  1803. {
  1804. if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
  1805. IWL_ERROR("APs don't scan.\n");
  1806. return 0;
  1807. }
  1808. if (!iwl3945_is_ready_rf(priv)) {
  1809. IWL_DEBUG_SCAN("Aborting scan due to not ready.\n");
  1810. return -EIO;
  1811. }
  1812. if (test_bit(STATUS_SCANNING, &priv->status)) {
  1813. IWL_DEBUG_SCAN("Scan already in progress.\n");
  1814. return -EAGAIN;
  1815. }
  1816. if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  1817. IWL_DEBUG_SCAN("Scan request while abort pending. "
  1818. "Queuing.\n");
  1819. return -EAGAIN;
  1820. }
  1821. IWL_DEBUG_INFO("Starting scan...\n");
  1822. if (priv->cfg->sku & IWL_SKU_G)
  1823. priv->scan_bands |= BIT(IEEE80211_BAND_2GHZ);
  1824. if (priv->cfg->sku & IWL_SKU_A)
  1825. priv->scan_bands |= BIT(IEEE80211_BAND_5GHZ);
  1826. set_bit(STATUS_SCANNING, &priv->status);
  1827. priv->scan_start = jiffies;
  1828. priv->scan_pass_start = priv->scan_start;
  1829. queue_work(priv->workqueue, &priv->request_scan);
  1830. return 0;
  1831. }
  1832. static int iwl3945_set_rxon_hwcrypto(struct iwl3945_priv *priv, int hw_decrypt)
  1833. {
  1834. struct iwl3945_rxon_cmd *rxon = &priv->staging_rxon;
  1835. if (hw_decrypt)
  1836. rxon->filter_flags &= ~RXON_FILTER_DIS_DECRYPT_MSK;
  1837. else
  1838. rxon->filter_flags |= RXON_FILTER_DIS_DECRYPT_MSK;
  1839. return 0;
  1840. }
  1841. static void iwl3945_set_flags_for_phymode(struct iwl3945_priv *priv,
  1842. enum ieee80211_band band)
  1843. {
  1844. if (band == IEEE80211_BAND_5GHZ) {
  1845. priv->staging_rxon.flags &=
  1846. ~(RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK
  1847. | RXON_FLG_CCK_MSK);
  1848. priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  1849. } else {
  1850. /* Copied from iwl3945_bg_post_associate() */
  1851. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
  1852. priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  1853. else
  1854. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  1855. if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS)
  1856. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  1857. priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
  1858. priv->staging_rxon.flags |= RXON_FLG_AUTO_DETECT_MSK;
  1859. priv->staging_rxon.flags &= ~RXON_FLG_CCK_MSK;
  1860. }
  1861. }
  1862. /*
  1863. * initialize rxon structure with default values from eeprom
  1864. */
  1865. static void iwl3945_connection_init_rx_config(struct iwl3945_priv *priv)
  1866. {
  1867. const struct iwl3945_channel_info *ch_info;
  1868. memset(&priv->staging_rxon, 0, sizeof(priv->staging_rxon));
  1869. switch (priv->iw_mode) {
  1870. case IEEE80211_IF_TYPE_AP:
  1871. priv->staging_rxon.dev_type = RXON_DEV_TYPE_AP;
  1872. break;
  1873. case IEEE80211_IF_TYPE_STA:
  1874. priv->staging_rxon.dev_type = RXON_DEV_TYPE_ESS;
  1875. priv->staging_rxon.filter_flags = RXON_FILTER_ACCEPT_GRP_MSK;
  1876. break;
  1877. case IEEE80211_IF_TYPE_IBSS:
  1878. priv->staging_rxon.dev_type = RXON_DEV_TYPE_IBSS;
  1879. priv->staging_rxon.flags = RXON_FLG_SHORT_PREAMBLE_MSK;
  1880. priv->staging_rxon.filter_flags = RXON_FILTER_BCON_AWARE_MSK |
  1881. RXON_FILTER_ACCEPT_GRP_MSK;
  1882. break;
  1883. case IEEE80211_IF_TYPE_MNTR:
  1884. priv->staging_rxon.dev_type = RXON_DEV_TYPE_SNIFFER;
  1885. priv->staging_rxon.filter_flags = RXON_FILTER_PROMISC_MSK |
  1886. RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_ACCEPT_GRP_MSK;
  1887. break;
  1888. default:
  1889. IWL_ERROR("Unsupported interface type %d\n", priv->iw_mode);
  1890. break;
  1891. }
  1892. #if 0
  1893. /* TODO: Figure out when short_preamble would be set and cache from
  1894. * that */
  1895. if (!hw_to_local(priv->hw)->short_preamble)
  1896. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  1897. else
  1898. priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  1899. #endif
  1900. ch_info = iwl3945_get_channel_info(priv, priv->band,
  1901. le16_to_cpu(priv->active_rxon.channel));
  1902. if (!ch_info)
  1903. ch_info = &priv->channel_info[0];
  1904. /*
  1905. * in some case A channels are all non IBSS
  1906. * in this case force B/G channel
  1907. */
  1908. if ((priv->iw_mode == IEEE80211_IF_TYPE_IBSS) &&
  1909. !(is_channel_ibss(ch_info)))
  1910. ch_info = &priv->channel_info[0];
  1911. priv->staging_rxon.channel = cpu_to_le16(ch_info->channel);
  1912. if (is_channel_a_band(ch_info))
  1913. priv->band = IEEE80211_BAND_5GHZ;
  1914. else
  1915. priv->band = IEEE80211_BAND_2GHZ;
  1916. iwl3945_set_flags_for_phymode(priv, priv->band);
  1917. priv->staging_rxon.ofdm_basic_rates =
  1918. (IWL_OFDM_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
  1919. priv->staging_rxon.cck_basic_rates =
  1920. (IWL_CCK_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
  1921. }
  1922. static int iwl3945_set_mode(struct iwl3945_priv *priv, int mode)
  1923. {
  1924. if (mode == IEEE80211_IF_TYPE_IBSS) {
  1925. const struct iwl3945_channel_info *ch_info;
  1926. ch_info = iwl3945_get_channel_info(priv,
  1927. priv->band,
  1928. le16_to_cpu(priv->staging_rxon.channel));
  1929. if (!ch_info || !is_channel_ibss(ch_info)) {
  1930. IWL_ERROR("channel %d not IBSS channel\n",
  1931. le16_to_cpu(priv->staging_rxon.channel));
  1932. return -EINVAL;
  1933. }
  1934. }
  1935. priv->iw_mode = mode;
  1936. iwl3945_connection_init_rx_config(priv);
  1937. memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
  1938. iwl3945_clear_stations_table(priv);
  1939. /* dont commit rxon if rf-kill is on*/
  1940. if (!iwl3945_is_ready_rf(priv))
  1941. return -EAGAIN;
  1942. cancel_delayed_work(&priv->scan_check);
  1943. if (iwl3945_scan_cancel_timeout(priv, 100)) {
  1944. IWL_WARNING("Aborted scan still in progress after 100ms\n");
  1945. IWL_DEBUG_MAC80211("leaving - scan abort failed.\n");
  1946. return -EAGAIN;
  1947. }
  1948. iwl3945_commit_rxon(priv);
  1949. return 0;
  1950. }
  1951. static void iwl3945_build_tx_cmd_hwcrypto(struct iwl3945_priv *priv,
  1952. struct ieee80211_tx_info *info,
  1953. struct iwl3945_cmd *cmd,
  1954. struct sk_buff *skb_frag,
  1955. int last_frag)
  1956. {
  1957. struct iwl3945_hw_key *keyinfo =
  1958. &priv->stations[info->control.hw_key->hw_key_idx].keyinfo;
  1959. switch (keyinfo->alg) {
  1960. case ALG_CCMP:
  1961. cmd->cmd.tx.sec_ctl = TX_CMD_SEC_CCM;
  1962. memcpy(cmd->cmd.tx.key, keyinfo->key, keyinfo->keylen);
  1963. IWL_DEBUG_TX("tx_cmd with aes hwcrypto\n");
  1964. break;
  1965. case ALG_TKIP:
  1966. #if 0
  1967. cmd->cmd.tx.sec_ctl = TX_CMD_SEC_TKIP;
  1968. if (last_frag)
  1969. memcpy(cmd->cmd.tx.tkip_mic.byte, skb_frag->tail - 8,
  1970. 8);
  1971. else
  1972. memset(cmd->cmd.tx.tkip_mic.byte, 0, 8);
  1973. #endif
  1974. break;
  1975. case ALG_WEP:
  1976. cmd->cmd.tx.sec_ctl = TX_CMD_SEC_WEP |
  1977. (info->control.hw_key->hw_key_idx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT;
  1978. if (keyinfo->keylen == 13)
  1979. cmd->cmd.tx.sec_ctl |= TX_CMD_SEC_KEY128;
  1980. memcpy(&cmd->cmd.tx.key[3], keyinfo->key, keyinfo->keylen);
  1981. IWL_DEBUG_TX("Configuring packet for WEP encryption "
  1982. "with key %d\n", info->control.hw_key->hw_key_idx);
  1983. break;
  1984. default:
  1985. printk(KERN_ERR "Unknown encode alg %d\n", keyinfo->alg);
  1986. break;
  1987. }
  1988. }
  1989. /*
  1990. * handle build REPLY_TX command notification.
  1991. */
  1992. static void iwl3945_build_tx_cmd_basic(struct iwl3945_priv *priv,
  1993. struct iwl3945_cmd *cmd,
  1994. struct ieee80211_tx_info *info,
  1995. struct ieee80211_hdr *hdr,
  1996. int is_unicast, u8 std_id)
  1997. {
  1998. __le16 fc = hdr->frame_control;
  1999. __le32 tx_flags = cmd->cmd.tx.tx_flags;
  2000. cmd->cmd.tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  2001. if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
  2002. tx_flags |= TX_CMD_FLG_ACK_MSK;
  2003. if (ieee80211_is_mgmt(fc))
  2004. tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
  2005. if (ieee80211_is_probe_resp(fc) &&
  2006. !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
  2007. tx_flags |= TX_CMD_FLG_TSF_MSK;
  2008. } else {
  2009. tx_flags &= (~TX_CMD_FLG_ACK_MSK);
  2010. tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
  2011. }
  2012. cmd->cmd.tx.sta_id = std_id;
  2013. if (ieee80211_has_morefrags(fc))
  2014. tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
  2015. if (ieee80211_is_data_qos(fc)) {
  2016. u8 *qc = ieee80211_get_qos_ctl(hdr);
  2017. cmd->cmd.tx.tid_tspec = qc[0] & 0xf;
  2018. tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
  2019. } else {
  2020. tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
  2021. }
  2022. if (info->flags & IEEE80211_TX_CTL_USE_RTS_CTS) {
  2023. tx_flags |= TX_CMD_FLG_RTS_MSK;
  2024. tx_flags &= ~TX_CMD_FLG_CTS_MSK;
  2025. } else if (info->flags & IEEE80211_TX_CTL_USE_CTS_PROTECT) {
  2026. tx_flags &= ~TX_CMD_FLG_RTS_MSK;
  2027. tx_flags |= TX_CMD_FLG_CTS_MSK;
  2028. }
  2029. if ((tx_flags & TX_CMD_FLG_RTS_MSK) || (tx_flags & TX_CMD_FLG_CTS_MSK))
  2030. tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
  2031. tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
  2032. if (ieee80211_is_mgmt(fc)) {
  2033. if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc))
  2034. cmd->cmd.tx.timeout.pm_frame_timeout = cpu_to_le16(3);
  2035. else
  2036. cmd->cmd.tx.timeout.pm_frame_timeout = cpu_to_le16(2);
  2037. } else {
  2038. cmd->cmd.tx.timeout.pm_frame_timeout = 0;
  2039. #ifdef CONFIG_IWL3945_LEDS
  2040. priv->rxtxpackets += le16_to_cpu(cmd->cmd.tx.len);
  2041. #endif
  2042. }
  2043. cmd->cmd.tx.driver_txop = 0;
  2044. cmd->cmd.tx.tx_flags = tx_flags;
  2045. cmd->cmd.tx.next_frame_len = 0;
  2046. }
  2047. /**
  2048. * iwl3945_get_sta_id - Find station's index within station table
  2049. */
  2050. static int iwl3945_get_sta_id(struct iwl3945_priv *priv, struct ieee80211_hdr *hdr)
  2051. {
  2052. int sta_id;
  2053. u16 fc = le16_to_cpu(hdr->frame_control);
  2054. /* If this frame is broadcast or management, use broadcast station id */
  2055. if (((fc & IEEE80211_FCTL_FTYPE) != IEEE80211_FTYPE_DATA) ||
  2056. is_multicast_ether_addr(hdr->addr1))
  2057. return priv->hw_setting.bcast_sta_id;
  2058. switch (priv->iw_mode) {
  2059. /* If we are a client station in a BSS network, use the special
  2060. * AP station entry (that's the only station we communicate with) */
  2061. case IEEE80211_IF_TYPE_STA:
  2062. return IWL_AP_ID;
  2063. /* If we are an AP, then find the station, or use BCAST */
  2064. case IEEE80211_IF_TYPE_AP:
  2065. sta_id = iwl3945_hw_find_station(priv, hdr->addr1);
  2066. if (sta_id != IWL_INVALID_STATION)
  2067. return sta_id;
  2068. return priv->hw_setting.bcast_sta_id;
  2069. /* If this frame is going out to an IBSS network, find the station,
  2070. * or create a new station table entry */
  2071. case IEEE80211_IF_TYPE_IBSS: {
  2072. DECLARE_MAC_BUF(mac);
  2073. /* Create new station table entry */
  2074. sta_id = iwl3945_hw_find_station(priv, hdr->addr1);
  2075. if (sta_id != IWL_INVALID_STATION)
  2076. return sta_id;
  2077. sta_id = iwl3945_add_station(priv, hdr->addr1, 0, CMD_ASYNC);
  2078. if (sta_id != IWL_INVALID_STATION)
  2079. return sta_id;
  2080. IWL_DEBUG_DROP("Station %s not in station map. "
  2081. "Defaulting to broadcast...\n",
  2082. print_mac(mac, hdr->addr1));
  2083. iwl3945_print_hex_dump(IWL_DL_DROP, (u8 *) hdr, sizeof(*hdr));
  2084. return priv->hw_setting.bcast_sta_id;
  2085. }
  2086. /* If we are in monitor mode, use BCAST. This is required for
  2087. * packet injection. */
  2088. case IEEE80211_IF_TYPE_MNTR:
  2089. return priv->hw_setting.bcast_sta_id;
  2090. default:
  2091. IWL_WARNING("Unknown mode of operation: %d", priv->iw_mode);
  2092. return priv->hw_setting.bcast_sta_id;
  2093. }
  2094. }
  2095. /*
  2096. * start REPLY_TX command process
  2097. */
  2098. static int iwl3945_tx_skb(struct iwl3945_priv *priv, struct sk_buff *skb)
  2099. {
  2100. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
  2101. struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
  2102. struct iwl3945_tfd_frame *tfd;
  2103. u32 *control_flags;
  2104. int txq_id = skb_get_queue_mapping(skb);
  2105. struct iwl3945_tx_queue *txq = NULL;
  2106. struct iwl3945_queue *q = NULL;
  2107. dma_addr_t phys_addr;
  2108. dma_addr_t txcmd_phys;
  2109. struct iwl3945_cmd *out_cmd = NULL;
  2110. u16 len, idx, len_org, hdr_len;
  2111. u8 id;
  2112. u8 unicast;
  2113. u8 sta_id;
  2114. u8 tid = 0;
  2115. u16 seq_number = 0;
  2116. __le16 fc;
  2117. u8 wait_write_ptr = 0;
  2118. u8 *qc = NULL;
  2119. unsigned long flags;
  2120. int rc;
  2121. spin_lock_irqsave(&priv->lock, flags);
  2122. if (iwl3945_is_rfkill(priv)) {
  2123. IWL_DEBUG_DROP("Dropping - RF KILL\n");
  2124. goto drop_unlock;
  2125. }
  2126. if ((ieee80211_get_tx_rate(priv->hw, info)->hw_value & 0xFF) == IWL_INVALID_RATE) {
  2127. IWL_ERROR("ERROR: No TX rate available.\n");
  2128. goto drop_unlock;
  2129. }
  2130. unicast = !is_multicast_ether_addr(hdr->addr1);
  2131. id = 0;
  2132. fc = hdr->frame_control;
  2133. #ifdef CONFIG_IWL3945_DEBUG
  2134. if (ieee80211_is_auth(fc))
  2135. IWL_DEBUG_TX("Sending AUTH frame\n");
  2136. else if (ieee80211_is_assoc_req(fc))
  2137. IWL_DEBUG_TX("Sending ASSOC frame\n");
  2138. else if (ieee80211_is_reassoc_req(fc))
  2139. IWL_DEBUG_TX("Sending REASSOC frame\n");
  2140. #endif
  2141. /* drop all data frame if we are not associated */
  2142. if (ieee80211_is_data(fc) &&
  2143. (priv->iw_mode != IEEE80211_IF_TYPE_MNTR) && /* packet injection */
  2144. (!iwl3945_is_associated(priv) ||
  2145. ((priv->iw_mode == IEEE80211_IF_TYPE_STA) && !priv->assoc_id))) {
  2146. IWL_DEBUG_DROP("Dropping - !iwl3945_is_associated\n");
  2147. goto drop_unlock;
  2148. }
  2149. spin_unlock_irqrestore(&priv->lock, flags);
  2150. hdr_len = ieee80211_get_hdrlen(le16_to_cpu(fc));
  2151. /* Find (or create) index into station table for destination station */
  2152. sta_id = iwl3945_get_sta_id(priv, hdr);
  2153. if (sta_id == IWL_INVALID_STATION) {
  2154. DECLARE_MAC_BUF(mac);
  2155. IWL_DEBUG_DROP("Dropping - INVALID STATION: %s\n",
  2156. print_mac(mac, hdr->addr1));
  2157. goto drop;
  2158. }
  2159. IWL_DEBUG_RATE("station Id %d\n", sta_id);
  2160. if (ieee80211_is_data_qos(fc)) {
  2161. qc = ieee80211_get_qos_ctl(hdr);
  2162. tid = qc[0] & 0xf;
  2163. seq_number = priv->stations[sta_id].tid[tid].seq_number &
  2164. IEEE80211_SCTL_SEQ;
  2165. hdr->seq_ctrl = cpu_to_le16(seq_number) |
  2166. (hdr->seq_ctrl &
  2167. __constant_cpu_to_le16(IEEE80211_SCTL_FRAG));
  2168. seq_number += 0x10;
  2169. }
  2170. /* Descriptor for chosen Tx queue */
  2171. txq = &priv->txq[txq_id];
  2172. q = &txq->q;
  2173. spin_lock_irqsave(&priv->lock, flags);
  2174. /* Set up first empty TFD within this queue's circular TFD buffer */
  2175. tfd = &txq->bd[q->write_ptr];
  2176. memset(tfd, 0, sizeof(*tfd));
  2177. control_flags = (u32 *) tfd;
  2178. idx = get_cmd_index(q, q->write_ptr, 0);
  2179. /* Set up driver data for this TFD */
  2180. memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl3945_tx_info));
  2181. txq->txb[q->write_ptr].skb[0] = skb;
  2182. /* Init first empty entry in queue's array of Tx/cmd buffers */
  2183. out_cmd = &txq->cmd[idx];
  2184. memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
  2185. memset(&out_cmd->cmd.tx, 0, sizeof(out_cmd->cmd.tx));
  2186. /*
  2187. * Set up the Tx-command (not MAC!) header.
  2188. * Store the chosen Tx queue and TFD index within the sequence field;
  2189. * after Tx, uCode's Tx response will return this value so driver can
  2190. * locate the frame within the tx queue and do post-tx processing.
  2191. */
  2192. out_cmd->hdr.cmd = REPLY_TX;
  2193. out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
  2194. INDEX_TO_SEQ(q->write_ptr)));
  2195. /* Copy MAC header from skb into command buffer */
  2196. memcpy(out_cmd->cmd.tx.hdr, hdr, hdr_len);
  2197. /*
  2198. * Use the first empty entry in this queue's command buffer array
  2199. * to contain the Tx command and MAC header concatenated together
  2200. * (payload data will be in another buffer).
  2201. * Size of this varies, due to varying MAC header length.
  2202. * If end is not dword aligned, we'll have 2 extra bytes at the end
  2203. * of the MAC header (device reads on dword boundaries).
  2204. * We'll tell device about this padding later.
  2205. */
  2206. len = priv->hw_setting.tx_cmd_len +
  2207. sizeof(struct iwl3945_cmd_header) + hdr_len;
  2208. len_org = len;
  2209. len = (len + 3) & ~3;
  2210. if (len_org != len)
  2211. len_org = 1;
  2212. else
  2213. len_org = 0;
  2214. /* Physical address of this Tx command's header (not MAC header!),
  2215. * within command buffer array. */
  2216. txcmd_phys = txq->dma_addr_cmd + sizeof(struct iwl3945_cmd) * idx +
  2217. offsetof(struct iwl3945_cmd, hdr);
  2218. /* Add buffer containing Tx command and MAC(!) header to TFD's
  2219. * first entry */
  2220. iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, txcmd_phys, len);
  2221. if (info->control.hw_key)
  2222. iwl3945_build_tx_cmd_hwcrypto(priv, info, out_cmd, skb, 0);
  2223. /* Set up TFD's 2nd entry to point directly to remainder of skb,
  2224. * if any (802.11 null frames have no payload). */
  2225. len = skb->len - hdr_len;
  2226. if (len) {
  2227. phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len,
  2228. len, PCI_DMA_TODEVICE);
  2229. iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, len);
  2230. }
  2231. if (!len)
  2232. /* If there is no payload, then we use only one Tx buffer */
  2233. *control_flags = TFD_CTL_COUNT_SET(1);
  2234. else
  2235. /* Else use 2 buffers.
  2236. * Tell 3945 about any padding after MAC header */
  2237. *control_flags = TFD_CTL_COUNT_SET(2) |
  2238. TFD_CTL_PAD_SET(U32_PAD(len));
  2239. /* Total # bytes to be transmitted */
  2240. len = (u16)skb->len;
  2241. out_cmd->cmd.tx.len = cpu_to_le16(len);
  2242. /* TODO need this for burst mode later on */
  2243. iwl3945_build_tx_cmd_basic(priv, out_cmd, info, hdr, unicast, sta_id);
  2244. /* set is_hcca to 0; it probably will never be implemented */
  2245. iwl3945_hw_build_tx_cmd_rate(priv, out_cmd, info, hdr, sta_id, 0);
  2246. out_cmd->cmd.tx.tx_flags &= ~TX_CMD_FLG_ANT_A_MSK;
  2247. out_cmd->cmd.tx.tx_flags &= ~TX_CMD_FLG_ANT_B_MSK;
  2248. if (!ieee80211_has_morefrags(hdr->frame_control)) {
  2249. txq->need_update = 1;
  2250. if (qc)
  2251. priv->stations[sta_id].tid[tid].seq_number = seq_number;
  2252. } else {
  2253. wait_write_ptr = 1;
  2254. txq->need_update = 0;
  2255. }
  2256. iwl3945_print_hex_dump(IWL_DL_TX, out_cmd->cmd.payload,
  2257. sizeof(out_cmd->cmd.tx));
  2258. iwl3945_print_hex_dump(IWL_DL_TX, (u8 *)out_cmd->cmd.tx.hdr,
  2259. ieee80211_get_hdrlen(le16_to_cpu(fc)));
  2260. /* Tell device the write index *just past* this latest filled TFD */
  2261. q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
  2262. rc = iwl3945_tx_queue_update_write_ptr(priv, txq);
  2263. spin_unlock_irqrestore(&priv->lock, flags);
  2264. if (rc)
  2265. return rc;
  2266. if ((iwl3945_queue_space(q) < q->high_mark)
  2267. && priv->mac80211_registered) {
  2268. if (wait_write_ptr) {
  2269. spin_lock_irqsave(&priv->lock, flags);
  2270. txq->need_update = 1;
  2271. iwl3945_tx_queue_update_write_ptr(priv, txq);
  2272. spin_unlock_irqrestore(&priv->lock, flags);
  2273. }
  2274. ieee80211_stop_queue(priv->hw, skb_get_queue_mapping(skb));
  2275. }
  2276. return 0;
  2277. drop_unlock:
  2278. spin_unlock_irqrestore(&priv->lock, flags);
  2279. drop:
  2280. return -1;
  2281. }
  2282. static void iwl3945_set_rate(struct iwl3945_priv *priv)
  2283. {
  2284. const struct ieee80211_supported_band *sband = NULL;
  2285. struct ieee80211_rate *rate;
  2286. int i;
  2287. sband = iwl3945_get_band(priv, priv->band);
  2288. if (!sband) {
  2289. IWL_ERROR("Failed to set rate: unable to get hw mode\n");
  2290. return;
  2291. }
  2292. priv->active_rate = 0;
  2293. priv->active_rate_basic = 0;
  2294. IWL_DEBUG_RATE("Setting rates for %s GHz\n",
  2295. sband->band == IEEE80211_BAND_2GHZ ? "2.4" : "5");
  2296. for (i = 0; i < sband->n_bitrates; i++) {
  2297. rate = &sband->bitrates[i];
  2298. if ((rate->hw_value < IWL_RATE_COUNT) &&
  2299. !(rate->flags & IEEE80211_CHAN_DISABLED)) {
  2300. IWL_DEBUG_RATE("Adding rate index %d (plcp %d)\n",
  2301. rate->hw_value, iwl3945_rates[rate->hw_value].plcp);
  2302. priv->active_rate |= (1 << rate->hw_value);
  2303. }
  2304. }
  2305. IWL_DEBUG_RATE("Set active_rate = %0x, active_rate_basic = %0x\n",
  2306. priv->active_rate, priv->active_rate_basic);
  2307. /*
  2308. * If a basic rate is configured, then use it (adding IWL_RATE_1M_MASK)
  2309. * otherwise set it to the default of all CCK rates and 6, 12, 24 for
  2310. * OFDM
  2311. */
  2312. if (priv->active_rate_basic & IWL_CCK_BASIC_RATES_MASK)
  2313. priv->staging_rxon.cck_basic_rates =
  2314. ((priv->active_rate_basic &
  2315. IWL_CCK_RATES_MASK) >> IWL_FIRST_CCK_RATE) & 0xF;
  2316. else
  2317. priv->staging_rxon.cck_basic_rates =
  2318. (IWL_CCK_BASIC_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
  2319. if (priv->active_rate_basic & IWL_OFDM_BASIC_RATES_MASK)
  2320. priv->staging_rxon.ofdm_basic_rates =
  2321. ((priv->active_rate_basic &
  2322. (IWL_OFDM_BASIC_RATES_MASK | IWL_RATE_6M_MASK)) >>
  2323. IWL_FIRST_OFDM_RATE) & 0xFF;
  2324. else
  2325. priv->staging_rxon.ofdm_basic_rates =
  2326. (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
  2327. }
  2328. static void iwl3945_radio_kill_sw(struct iwl3945_priv *priv, int disable_radio)
  2329. {
  2330. unsigned long flags;
  2331. if (!!disable_radio == test_bit(STATUS_RF_KILL_SW, &priv->status))
  2332. return;
  2333. IWL_DEBUG_RF_KILL("Manual SW RF KILL set to: RADIO %s\n",
  2334. disable_radio ? "OFF" : "ON");
  2335. if (disable_radio) {
  2336. iwl3945_scan_cancel(priv);
  2337. /* FIXME: This is a workaround for AP */
  2338. if (priv->iw_mode != IEEE80211_IF_TYPE_AP) {
  2339. spin_lock_irqsave(&priv->lock, flags);
  2340. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_SET,
  2341. CSR_UCODE_SW_BIT_RFKILL);
  2342. spin_unlock_irqrestore(&priv->lock, flags);
  2343. iwl3945_send_card_state(priv, CARD_STATE_CMD_DISABLE, 0);
  2344. set_bit(STATUS_RF_KILL_SW, &priv->status);
  2345. }
  2346. return;
  2347. }
  2348. spin_lock_irqsave(&priv->lock, flags);
  2349. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  2350. clear_bit(STATUS_RF_KILL_SW, &priv->status);
  2351. spin_unlock_irqrestore(&priv->lock, flags);
  2352. /* wake up ucode */
  2353. msleep(10);
  2354. spin_lock_irqsave(&priv->lock, flags);
  2355. iwl3945_read32(priv, CSR_UCODE_DRV_GP1);
  2356. if (!iwl3945_grab_nic_access(priv))
  2357. iwl3945_release_nic_access(priv);
  2358. spin_unlock_irqrestore(&priv->lock, flags);
  2359. if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
  2360. IWL_DEBUG_RF_KILL("Can not turn radio back on - "
  2361. "disabled by HW switch\n");
  2362. return;
  2363. }
  2364. if (priv->is_open)
  2365. queue_work(priv->workqueue, &priv->restart);
  2366. return;
  2367. }
  2368. void iwl3945_set_decrypted_flag(struct iwl3945_priv *priv, struct sk_buff *skb,
  2369. u32 decrypt_res, struct ieee80211_rx_status *stats)
  2370. {
  2371. u16 fc =
  2372. le16_to_cpu(((struct ieee80211_hdr *)skb->data)->frame_control);
  2373. if (priv->active_rxon.filter_flags & RXON_FILTER_DIS_DECRYPT_MSK)
  2374. return;
  2375. if (!(fc & IEEE80211_FCTL_PROTECTED))
  2376. return;
  2377. IWL_DEBUG_RX("decrypt_res:0x%x\n", decrypt_res);
  2378. switch (decrypt_res & RX_RES_STATUS_SEC_TYPE_MSK) {
  2379. case RX_RES_STATUS_SEC_TYPE_TKIP:
  2380. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  2381. RX_RES_STATUS_BAD_ICV_MIC)
  2382. stats->flag |= RX_FLAG_MMIC_ERROR;
  2383. case RX_RES_STATUS_SEC_TYPE_WEP:
  2384. case RX_RES_STATUS_SEC_TYPE_CCMP:
  2385. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  2386. RX_RES_STATUS_DECRYPT_OK) {
  2387. IWL_DEBUG_RX("hw decrypt successfully!!!\n");
  2388. stats->flag |= RX_FLAG_DECRYPTED;
  2389. }
  2390. break;
  2391. default:
  2392. break;
  2393. }
  2394. }
  2395. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  2396. #include "iwl-spectrum.h"
  2397. #define BEACON_TIME_MASK_LOW 0x00FFFFFF
  2398. #define BEACON_TIME_MASK_HIGH 0xFF000000
  2399. #define TIME_UNIT 1024
  2400. /*
  2401. * extended beacon time format
  2402. * time in usec will be changed into a 32-bit value in 8:24 format
  2403. * the high 1 byte is the beacon counts
  2404. * the lower 3 bytes is the time in usec within one beacon interval
  2405. */
  2406. static u32 iwl3945_usecs_to_beacons(u32 usec, u32 beacon_interval)
  2407. {
  2408. u32 quot;
  2409. u32 rem;
  2410. u32 interval = beacon_interval * 1024;
  2411. if (!interval || !usec)
  2412. return 0;
  2413. quot = (usec / interval) & (BEACON_TIME_MASK_HIGH >> 24);
  2414. rem = (usec % interval) & BEACON_TIME_MASK_LOW;
  2415. return (quot << 24) + rem;
  2416. }
  2417. /* base is usually what we get from ucode with each received frame,
  2418. * the same as HW timer counter counting down
  2419. */
  2420. static __le32 iwl3945_add_beacon_time(u32 base, u32 addon, u32 beacon_interval)
  2421. {
  2422. u32 base_low = base & BEACON_TIME_MASK_LOW;
  2423. u32 addon_low = addon & BEACON_TIME_MASK_LOW;
  2424. u32 interval = beacon_interval * TIME_UNIT;
  2425. u32 res = (base & BEACON_TIME_MASK_HIGH) +
  2426. (addon & BEACON_TIME_MASK_HIGH);
  2427. if (base_low > addon_low)
  2428. res += base_low - addon_low;
  2429. else if (base_low < addon_low) {
  2430. res += interval + base_low - addon_low;
  2431. res += (1 << 24);
  2432. } else
  2433. res += (1 << 24);
  2434. return cpu_to_le32(res);
  2435. }
  2436. static int iwl3945_get_measurement(struct iwl3945_priv *priv,
  2437. struct ieee80211_measurement_params *params,
  2438. u8 type)
  2439. {
  2440. struct iwl3945_spectrum_cmd spectrum;
  2441. struct iwl3945_rx_packet *res;
  2442. struct iwl3945_host_cmd cmd = {
  2443. .id = REPLY_SPECTRUM_MEASUREMENT_CMD,
  2444. .data = (void *)&spectrum,
  2445. .meta.flags = CMD_WANT_SKB,
  2446. };
  2447. u32 add_time = le64_to_cpu(params->start_time);
  2448. int rc;
  2449. int spectrum_resp_status;
  2450. int duration = le16_to_cpu(params->duration);
  2451. if (iwl3945_is_associated(priv))
  2452. add_time =
  2453. iwl3945_usecs_to_beacons(
  2454. le64_to_cpu(params->start_time) - priv->last_tsf,
  2455. le16_to_cpu(priv->rxon_timing.beacon_interval));
  2456. memset(&spectrum, 0, sizeof(spectrum));
  2457. spectrum.channel_count = cpu_to_le16(1);
  2458. spectrum.flags =
  2459. RXON_FLG_TSF2HOST_MSK | RXON_FLG_ANT_A_MSK | RXON_FLG_DIS_DIV_MSK;
  2460. spectrum.filter_flags = MEASUREMENT_FILTER_FLAG;
  2461. cmd.len = sizeof(spectrum);
  2462. spectrum.len = cpu_to_le16(cmd.len - sizeof(spectrum.len));
  2463. if (iwl3945_is_associated(priv))
  2464. spectrum.start_time =
  2465. iwl3945_add_beacon_time(priv->last_beacon_time,
  2466. add_time,
  2467. le16_to_cpu(priv->rxon_timing.beacon_interval));
  2468. else
  2469. spectrum.start_time = 0;
  2470. spectrum.channels[0].duration = cpu_to_le32(duration * TIME_UNIT);
  2471. spectrum.channels[0].channel = params->channel;
  2472. spectrum.channels[0].type = type;
  2473. if (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK)
  2474. spectrum.flags |= RXON_FLG_BAND_24G_MSK |
  2475. RXON_FLG_AUTO_DETECT_MSK | RXON_FLG_TGG_PROTECT_MSK;
  2476. rc = iwl3945_send_cmd_sync(priv, &cmd);
  2477. if (rc)
  2478. return rc;
  2479. res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
  2480. if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
  2481. IWL_ERROR("Bad return from REPLY_RX_ON_ASSOC command\n");
  2482. rc = -EIO;
  2483. }
  2484. spectrum_resp_status = le16_to_cpu(res->u.spectrum.status);
  2485. switch (spectrum_resp_status) {
  2486. case 0: /* Command will be handled */
  2487. if (res->u.spectrum.id != 0xff) {
  2488. IWL_DEBUG_INFO("Replaced existing measurement: %d\n",
  2489. res->u.spectrum.id);
  2490. priv->measurement_status &= ~MEASUREMENT_READY;
  2491. }
  2492. priv->measurement_status |= MEASUREMENT_ACTIVE;
  2493. rc = 0;
  2494. break;
  2495. case 1: /* Command will not be handled */
  2496. rc = -EAGAIN;
  2497. break;
  2498. }
  2499. dev_kfree_skb_any(cmd.meta.u.skb);
  2500. return rc;
  2501. }
  2502. #endif
  2503. static void iwl3945_rx_reply_alive(struct iwl3945_priv *priv,
  2504. struct iwl3945_rx_mem_buffer *rxb)
  2505. {
  2506. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2507. struct iwl3945_alive_resp *palive;
  2508. struct delayed_work *pwork;
  2509. palive = &pkt->u.alive_frame;
  2510. IWL_DEBUG_INFO("Alive ucode status 0x%08X revision "
  2511. "0x%01X 0x%01X\n",
  2512. palive->is_valid, palive->ver_type,
  2513. palive->ver_subtype);
  2514. if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
  2515. IWL_DEBUG_INFO("Initialization Alive received.\n");
  2516. memcpy(&priv->card_alive_init,
  2517. &pkt->u.alive_frame,
  2518. sizeof(struct iwl3945_init_alive_resp));
  2519. pwork = &priv->init_alive_start;
  2520. } else {
  2521. IWL_DEBUG_INFO("Runtime Alive received.\n");
  2522. memcpy(&priv->card_alive, &pkt->u.alive_frame,
  2523. sizeof(struct iwl3945_alive_resp));
  2524. pwork = &priv->alive_start;
  2525. iwl3945_disable_events(priv);
  2526. }
  2527. /* We delay the ALIVE response by 5ms to
  2528. * give the HW RF Kill time to activate... */
  2529. if (palive->is_valid == UCODE_VALID_OK)
  2530. queue_delayed_work(priv->workqueue, pwork,
  2531. msecs_to_jiffies(5));
  2532. else
  2533. IWL_WARNING("uCode did not respond OK.\n");
  2534. }
  2535. static void iwl3945_rx_reply_add_sta(struct iwl3945_priv *priv,
  2536. struct iwl3945_rx_mem_buffer *rxb)
  2537. {
  2538. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2539. IWL_DEBUG_RX("Received REPLY_ADD_STA: 0x%02X\n", pkt->u.status);
  2540. return;
  2541. }
  2542. static void iwl3945_rx_reply_error(struct iwl3945_priv *priv,
  2543. struct iwl3945_rx_mem_buffer *rxb)
  2544. {
  2545. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2546. IWL_ERROR("Error Reply type 0x%08X cmd %s (0x%02X) "
  2547. "seq 0x%04X ser 0x%08X\n",
  2548. le32_to_cpu(pkt->u.err_resp.error_type),
  2549. get_cmd_string(pkt->u.err_resp.cmd_id),
  2550. pkt->u.err_resp.cmd_id,
  2551. le16_to_cpu(pkt->u.err_resp.bad_cmd_seq_num),
  2552. le32_to_cpu(pkt->u.err_resp.error_info));
  2553. }
  2554. #define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
  2555. static void iwl3945_rx_csa(struct iwl3945_priv *priv, struct iwl3945_rx_mem_buffer *rxb)
  2556. {
  2557. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2558. struct iwl3945_rxon_cmd *rxon = (void *)&priv->active_rxon;
  2559. struct iwl3945_csa_notification *csa = &(pkt->u.csa_notif);
  2560. IWL_DEBUG_11H("CSA notif: channel %d, status %d\n",
  2561. le16_to_cpu(csa->channel), le32_to_cpu(csa->status));
  2562. rxon->channel = csa->channel;
  2563. priv->staging_rxon.channel = csa->channel;
  2564. }
  2565. static void iwl3945_rx_spectrum_measure_notif(struct iwl3945_priv *priv,
  2566. struct iwl3945_rx_mem_buffer *rxb)
  2567. {
  2568. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  2569. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2570. struct iwl3945_spectrum_notification *report = &(pkt->u.spectrum_notif);
  2571. if (!report->state) {
  2572. IWL_DEBUG(IWL_DL_11H | IWL_DL_INFO,
  2573. "Spectrum Measure Notification: Start\n");
  2574. return;
  2575. }
  2576. memcpy(&priv->measure_report, report, sizeof(*report));
  2577. priv->measurement_status |= MEASUREMENT_READY;
  2578. #endif
  2579. }
  2580. static void iwl3945_rx_pm_sleep_notif(struct iwl3945_priv *priv,
  2581. struct iwl3945_rx_mem_buffer *rxb)
  2582. {
  2583. #ifdef CONFIG_IWL3945_DEBUG
  2584. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2585. struct iwl3945_sleep_notification *sleep = &(pkt->u.sleep_notif);
  2586. IWL_DEBUG_RX("sleep mode: %d, src: %d\n",
  2587. sleep->pm_sleep_mode, sleep->pm_wakeup_src);
  2588. #endif
  2589. }
  2590. static void iwl3945_rx_pm_debug_statistics_notif(struct iwl3945_priv *priv,
  2591. struct iwl3945_rx_mem_buffer *rxb)
  2592. {
  2593. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2594. IWL_DEBUG_RADIO("Dumping %d bytes of unhandled "
  2595. "notification for %s:\n",
  2596. le32_to_cpu(pkt->len), get_cmd_string(pkt->hdr.cmd));
  2597. iwl3945_print_hex_dump(IWL_DL_RADIO, pkt->u.raw, le32_to_cpu(pkt->len));
  2598. }
  2599. static void iwl3945_bg_beacon_update(struct work_struct *work)
  2600. {
  2601. struct iwl3945_priv *priv =
  2602. container_of(work, struct iwl3945_priv, beacon_update);
  2603. struct sk_buff *beacon;
  2604. /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
  2605. beacon = ieee80211_beacon_get(priv->hw, priv->vif);
  2606. if (!beacon) {
  2607. IWL_ERROR("update beacon failed\n");
  2608. return;
  2609. }
  2610. mutex_lock(&priv->mutex);
  2611. /* new beacon skb is allocated every time; dispose previous.*/
  2612. if (priv->ibss_beacon)
  2613. dev_kfree_skb(priv->ibss_beacon);
  2614. priv->ibss_beacon = beacon;
  2615. mutex_unlock(&priv->mutex);
  2616. iwl3945_send_beacon_cmd(priv);
  2617. }
  2618. static void iwl3945_rx_beacon_notif(struct iwl3945_priv *priv,
  2619. struct iwl3945_rx_mem_buffer *rxb)
  2620. {
  2621. #ifdef CONFIG_IWL3945_DEBUG
  2622. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2623. struct iwl3945_beacon_notif *beacon = &(pkt->u.beacon_status);
  2624. u8 rate = beacon->beacon_notify_hdr.rate;
  2625. IWL_DEBUG_RX("beacon status %x retries %d iss %d "
  2626. "tsf %d %d rate %d\n",
  2627. le32_to_cpu(beacon->beacon_notify_hdr.status) & TX_STATUS_MSK,
  2628. beacon->beacon_notify_hdr.failure_frame,
  2629. le32_to_cpu(beacon->ibss_mgr_status),
  2630. le32_to_cpu(beacon->high_tsf),
  2631. le32_to_cpu(beacon->low_tsf), rate);
  2632. #endif
  2633. if ((priv->iw_mode == IEEE80211_IF_TYPE_AP) &&
  2634. (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
  2635. queue_work(priv->workqueue, &priv->beacon_update);
  2636. }
  2637. /* Service response to REPLY_SCAN_CMD (0x80) */
  2638. static void iwl3945_rx_reply_scan(struct iwl3945_priv *priv,
  2639. struct iwl3945_rx_mem_buffer *rxb)
  2640. {
  2641. #ifdef CONFIG_IWL3945_DEBUG
  2642. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2643. struct iwl3945_scanreq_notification *notif =
  2644. (struct iwl3945_scanreq_notification *)pkt->u.raw;
  2645. IWL_DEBUG_RX("Scan request status = 0x%x\n", notif->status);
  2646. #endif
  2647. }
  2648. /* Service SCAN_START_NOTIFICATION (0x82) */
  2649. static void iwl3945_rx_scan_start_notif(struct iwl3945_priv *priv,
  2650. struct iwl3945_rx_mem_buffer *rxb)
  2651. {
  2652. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2653. struct iwl3945_scanstart_notification *notif =
  2654. (struct iwl3945_scanstart_notification *)pkt->u.raw;
  2655. priv->scan_start_tsf = le32_to_cpu(notif->tsf_low);
  2656. IWL_DEBUG_SCAN("Scan start: "
  2657. "%d [802.11%s] "
  2658. "(TSF: 0x%08X:%08X) - %d (beacon timer %u)\n",
  2659. notif->channel,
  2660. notif->band ? "bg" : "a",
  2661. notif->tsf_high,
  2662. notif->tsf_low, notif->status, notif->beacon_timer);
  2663. }
  2664. /* Service SCAN_RESULTS_NOTIFICATION (0x83) */
  2665. static void iwl3945_rx_scan_results_notif(struct iwl3945_priv *priv,
  2666. struct iwl3945_rx_mem_buffer *rxb)
  2667. {
  2668. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2669. struct iwl3945_scanresults_notification *notif =
  2670. (struct iwl3945_scanresults_notification *)pkt->u.raw;
  2671. IWL_DEBUG_SCAN("Scan ch.res: "
  2672. "%d [802.11%s] "
  2673. "(TSF: 0x%08X:%08X) - %d "
  2674. "elapsed=%lu usec (%dms since last)\n",
  2675. notif->channel,
  2676. notif->band ? "bg" : "a",
  2677. le32_to_cpu(notif->tsf_high),
  2678. le32_to_cpu(notif->tsf_low),
  2679. le32_to_cpu(notif->statistics[0]),
  2680. le32_to_cpu(notif->tsf_low) - priv->scan_start_tsf,
  2681. jiffies_to_msecs(elapsed_jiffies
  2682. (priv->last_scan_jiffies, jiffies)));
  2683. priv->last_scan_jiffies = jiffies;
  2684. priv->next_scan_jiffies = 0;
  2685. }
  2686. /* Service SCAN_COMPLETE_NOTIFICATION (0x84) */
  2687. static void iwl3945_rx_scan_complete_notif(struct iwl3945_priv *priv,
  2688. struct iwl3945_rx_mem_buffer *rxb)
  2689. {
  2690. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2691. struct iwl3945_scancomplete_notification *scan_notif = (void *)pkt->u.raw;
  2692. IWL_DEBUG_SCAN("Scan complete: %d channels (TSF 0x%08X:%08X) - %d\n",
  2693. scan_notif->scanned_channels,
  2694. scan_notif->tsf_low,
  2695. scan_notif->tsf_high, scan_notif->status);
  2696. /* The HW is no longer scanning */
  2697. clear_bit(STATUS_SCAN_HW, &priv->status);
  2698. /* The scan completion notification came in, so kill that timer... */
  2699. cancel_delayed_work(&priv->scan_check);
  2700. IWL_DEBUG_INFO("Scan pass on %sGHz took %dms\n",
  2701. (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ)) ?
  2702. "2.4" : "5.2",
  2703. jiffies_to_msecs(elapsed_jiffies
  2704. (priv->scan_pass_start, jiffies)));
  2705. /* Remove this scanned band from the list of pending
  2706. * bands to scan, band G precedes A in order of scanning
  2707. * as seen in iwl3945_bg_request_scan */
  2708. if (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ))
  2709. priv->scan_bands &= ~BIT(IEEE80211_BAND_2GHZ);
  2710. else if (priv->scan_bands & BIT(IEEE80211_BAND_5GHZ))
  2711. priv->scan_bands &= ~BIT(IEEE80211_BAND_5GHZ);
  2712. /* If a request to abort was given, or the scan did not succeed
  2713. * then we reset the scan state machine and terminate,
  2714. * re-queuing another scan if one has been requested */
  2715. if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  2716. IWL_DEBUG_INFO("Aborted scan completed.\n");
  2717. clear_bit(STATUS_SCAN_ABORTING, &priv->status);
  2718. } else {
  2719. /* If there are more bands on this scan pass reschedule */
  2720. if (priv->scan_bands > 0)
  2721. goto reschedule;
  2722. }
  2723. priv->last_scan_jiffies = jiffies;
  2724. priv->next_scan_jiffies = 0;
  2725. IWL_DEBUG_INFO("Setting scan to off\n");
  2726. clear_bit(STATUS_SCANNING, &priv->status);
  2727. IWL_DEBUG_INFO("Scan took %dms\n",
  2728. jiffies_to_msecs(elapsed_jiffies(priv->scan_start, jiffies)));
  2729. queue_work(priv->workqueue, &priv->scan_completed);
  2730. return;
  2731. reschedule:
  2732. priv->scan_pass_start = jiffies;
  2733. queue_work(priv->workqueue, &priv->request_scan);
  2734. }
  2735. /* Handle notification from uCode that card's power state is changing
  2736. * due to software, hardware, or critical temperature RFKILL */
  2737. static void iwl3945_rx_card_state_notif(struct iwl3945_priv *priv,
  2738. struct iwl3945_rx_mem_buffer *rxb)
  2739. {
  2740. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2741. u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
  2742. unsigned long status = priv->status;
  2743. IWL_DEBUG_RF_KILL("Card state received: HW:%s SW:%s\n",
  2744. (flags & HW_CARD_DISABLED) ? "Kill" : "On",
  2745. (flags & SW_CARD_DISABLED) ? "Kill" : "On");
  2746. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_SET,
  2747. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  2748. if (flags & HW_CARD_DISABLED)
  2749. set_bit(STATUS_RF_KILL_HW, &priv->status);
  2750. else
  2751. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  2752. if (flags & SW_CARD_DISABLED)
  2753. set_bit(STATUS_RF_KILL_SW, &priv->status);
  2754. else
  2755. clear_bit(STATUS_RF_KILL_SW, &priv->status);
  2756. iwl3945_scan_cancel(priv);
  2757. if ((test_bit(STATUS_RF_KILL_HW, &status) !=
  2758. test_bit(STATUS_RF_KILL_HW, &priv->status)) ||
  2759. (test_bit(STATUS_RF_KILL_SW, &status) !=
  2760. test_bit(STATUS_RF_KILL_SW, &priv->status)))
  2761. queue_work(priv->workqueue, &priv->rf_kill);
  2762. else
  2763. wake_up_interruptible(&priv->wait_command_queue);
  2764. }
  2765. /**
  2766. * iwl3945_setup_rx_handlers - Initialize Rx handler callbacks
  2767. *
  2768. * Setup the RX handlers for each of the reply types sent from the uCode
  2769. * to the host.
  2770. *
  2771. * This function chains into the hardware specific files for them to setup
  2772. * any hardware specific handlers as well.
  2773. */
  2774. static void iwl3945_setup_rx_handlers(struct iwl3945_priv *priv)
  2775. {
  2776. priv->rx_handlers[REPLY_ALIVE] = iwl3945_rx_reply_alive;
  2777. priv->rx_handlers[REPLY_ADD_STA] = iwl3945_rx_reply_add_sta;
  2778. priv->rx_handlers[REPLY_ERROR] = iwl3945_rx_reply_error;
  2779. priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl3945_rx_csa;
  2780. priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
  2781. iwl3945_rx_spectrum_measure_notif;
  2782. priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl3945_rx_pm_sleep_notif;
  2783. priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
  2784. iwl3945_rx_pm_debug_statistics_notif;
  2785. priv->rx_handlers[BEACON_NOTIFICATION] = iwl3945_rx_beacon_notif;
  2786. /*
  2787. * The same handler is used for both the REPLY to a discrete
  2788. * statistics request from the host as well as for the periodic
  2789. * statistics notifications (after received beacons) from the uCode.
  2790. */
  2791. priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl3945_hw_rx_statistics;
  2792. priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl3945_hw_rx_statistics;
  2793. priv->rx_handlers[REPLY_SCAN_CMD] = iwl3945_rx_reply_scan;
  2794. priv->rx_handlers[SCAN_START_NOTIFICATION] = iwl3945_rx_scan_start_notif;
  2795. priv->rx_handlers[SCAN_RESULTS_NOTIFICATION] =
  2796. iwl3945_rx_scan_results_notif;
  2797. priv->rx_handlers[SCAN_COMPLETE_NOTIFICATION] =
  2798. iwl3945_rx_scan_complete_notif;
  2799. priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl3945_rx_card_state_notif;
  2800. /* Set up hardware specific Rx handlers */
  2801. iwl3945_hw_rx_handler_setup(priv);
  2802. }
  2803. /**
  2804. * iwl3945_cmd_queue_reclaim - Reclaim CMD queue entries
  2805. * When FW advances 'R' index, all entries between old and new 'R' index
  2806. * need to be reclaimed.
  2807. */
  2808. static void iwl3945_cmd_queue_reclaim(struct iwl3945_priv *priv,
  2809. int txq_id, int index)
  2810. {
  2811. struct iwl3945_tx_queue *txq = &priv->txq[txq_id];
  2812. struct iwl3945_queue *q = &txq->q;
  2813. int nfreed = 0;
  2814. if ((index >= q->n_bd) || (iwl3945_x2_queue_used(q, index) == 0)) {
  2815. IWL_ERROR("Read index for DMA queue txq id (%d), index %d, "
  2816. "is out of range [0-%d] %d %d.\n", txq_id,
  2817. index, q->n_bd, q->write_ptr, q->read_ptr);
  2818. return;
  2819. }
  2820. for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index;
  2821. q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
  2822. if (nfreed > 1) {
  2823. IWL_ERROR("HCMD skipped: index (%d) %d %d\n", index,
  2824. q->write_ptr, q->read_ptr);
  2825. queue_work(priv->workqueue, &priv->restart);
  2826. break;
  2827. }
  2828. nfreed++;
  2829. }
  2830. }
  2831. /**
  2832. * iwl3945_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
  2833. * @rxb: Rx buffer to reclaim
  2834. *
  2835. * If an Rx buffer has an async callback associated with it the callback
  2836. * will be executed. The attached skb (if present) will only be freed
  2837. * if the callback returns 1
  2838. */
  2839. static void iwl3945_tx_cmd_complete(struct iwl3945_priv *priv,
  2840. struct iwl3945_rx_mem_buffer *rxb)
  2841. {
  2842. struct iwl3945_rx_packet *pkt = (struct iwl3945_rx_packet *)rxb->skb->data;
  2843. u16 sequence = le16_to_cpu(pkt->hdr.sequence);
  2844. int txq_id = SEQ_TO_QUEUE(sequence);
  2845. int index = SEQ_TO_INDEX(sequence);
  2846. int huge = sequence & SEQ_HUGE_FRAME;
  2847. int cmd_index;
  2848. struct iwl3945_cmd *cmd;
  2849. BUG_ON(txq_id != IWL_CMD_QUEUE_NUM);
  2850. cmd_index = get_cmd_index(&priv->txq[IWL_CMD_QUEUE_NUM].q, index, huge);
  2851. cmd = &priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_index];
  2852. /* Input error checking is done when commands are added to queue. */
  2853. if (cmd->meta.flags & CMD_WANT_SKB) {
  2854. cmd->meta.source->u.skb = rxb->skb;
  2855. rxb->skb = NULL;
  2856. } else if (cmd->meta.u.callback &&
  2857. !cmd->meta.u.callback(priv, cmd, rxb->skb))
  2858. rxb->skb = NULL;
  2859. iwl3945_cmd_queue_reclaim(priv, txq_id, index);
  2860. if (!(cmd->meta.flags & CMD_ASYNC)) {
  2861. clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
  2862. wake_up_interruptible(&priv->wait_command_queue);
  2863. }
  2864. }
  2865. /************************** RX-FUNCTIONS ****************************/
  2866. /*
  2867. * Rx theory of operation
  2868. *
  2869. * The host allocates 32 DMA target addresses and passes the host address
  2870. * to the firmware at register IWL_RFDS_TABLE_LOWER + N * RFD_SIZE where N is
  2871. * 0 to 31
  2872. *
  2873. * Rx Queue Indexes
  2874. * The host/firmware share two index registers for managing the Rx buffers.
  2875. *
  2876. * The READ index maps to the first position that the firmware may be writing
  2877. * to -- the driver can read up to (but not including) this position and get
  2878. * good data.
  2879. * The READ index is managed by the firmware once the card is enabled.
  2880. *
  2881. * The WRITE index maps to the last position the driver has read from -- the
  2882. * position preceding WRITE is the last slot the firmware can place a packet.
  2883. *
  2884. * The queue is empty (no good data) if WRITE = READ - 1, and is full if
  2885. * WRITE = READ.
  2886. *
  2887. * During initialization, the host sets up the READ queue position to the first
  2888. * INDEX position, and WRITE to the last (READ - 1 wrapped)
  2889. *
  2890. * When the firmware places a packet in a buffer, it will advance the READ index
  2891. * and fire the RX interrupt. The driver can then query the READ index and
  2892. * process as many packets as possible, moving the WRITE index forward as it
  2893. * resets the Rx queue buffers with new memory.
  2894. *
  2895. * The management in the driver is as follows:
  2896. * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
  2897. * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
  2898. * to replenish the iwl->rxq->rx_free.
  2899. * + In iwl3945_rx_replenish (scheduled) if 'processed' != 'read' then the
  2900. * iwl->rxq is replenished and the READ INDEX is updated (updating the
  2901. * 'processed' and 'read' driver indexes as well)
  2902. * + A received packet is processed and handed to the kernel network stack,
  2903. * detached from the iwl->rxq. The driver 'processed' index is updated.
  2904. * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
  2905. * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
  2906. * INDEX is not incremented and iwl->status(RX_STALLED) is set. If there
  2907. * were enough free buffers and RX_STALLED is set it is cleared.
  2908. *
  2909. *
  2910. * Driver sequence:
  2911. *
  2912. * iwl3945_rx_queue_alloc() Allocates rx_free
  2913. * iwl3945_rx_replenish() Replenishes rx_free list from rx_used, and calls
  2914. * iwl3945_rx_queue_restock
  2915. * iwl3945_rx_queue_restock() Moves available buffers from rx_free into Rx
  2916. * queue, updates firmware pointers, and updates
  2917. * the WRITE index. If insufficient rx_free buffers
  2918. * are available, schedules iwl3945_rx_replenish
  2919. *
  2920. * -- enable interrupts --
  2921. * ISR - iwl3945_rx() Detach iwl3945_rx_mem_buffers from pool up to the
  2922. * READ INDEX, detaching the SKB from the pool.
  2923. * Moves the packet buffer from queue to rx_used.
  2924. * Calls iwl3945_rx_queue_restock to refill any empty
  2925. * slots.
  2926. * ...
  2927. *
  2928. */
  2929. /**
  2930. * iwl3945_rx_queue_space - Return number of free slots available in queue.
  2931. */
  2932. static int iwl3945_rx_queue_space(const struct iwl3945_rx_queue *q)
  2933. {
  2934. int s = q->read - q->write;
  2935. if (s <= 0)
  2936. s += RX_QUEUE_SIZE;
  2937. /* keep some buffer to not confuse full and empty queue */
  2938. s -= 2;
  2939. if (s < 0)
  2940. s = 0;
  2941. return s;
  2942. }
  2943. /**
  2944. * iwl3945_rx_queue_update_write_ptr - Update the write pointer for the RX queue
  2945. */
  2946. int iwl3945_rx_queue_update_write_ptr(struct iwl3945_priv *priv, struct iwl3945_rx_queue *q)
  2947. {
  2948. u32 reg = 0;
  2949. int rc = 0;
  2950. unsigned long flags;
  2951. spin_lock_irqsave(&q->lock, flags);
  2952. if (q->need_update == 0)
  2953. goto exit_unlock;
  2954. /* If power-saving is in use, make sure device is awake */
  2955. if (test_bit(STATUS_POWER_PMI, &priv->status)) {
  2956. reg = iwl3945_read32(priv, CSR_UCODE_DRV_GP1);
  2957. if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
  2958. iwl3945_set_bit(priv, CSR_GP_CNTRL,
  2959. CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  2960. goto exit_unlock;
  2961. }
  2962. rc = iwl3945_grab_nic_access(priv);
  2963. if (rc)
  2964. goto exit_unlock;
  2965. /* Device expects a multiple of 8 */
  2966. iwl3945_write_direct32(priv, FH_RSCSR_CHNL0_WPTR,
  2967. q->write & ~0x7);
  2968. iwl3945_release_nic_access(priv);
  2969. /* Else device is assumed to be awake */
  2970. } else
  2971. /* Device expects a multiple of 8 */
  2972. iwl3945_write32(priv, FH_RSCSR_CHNL0_WPTR, q->write & ~0x7);
  2973. q->need_update = 0;
  2974. exit_unlock:
  2975. spin_unlock_irqrestore(&q->lock, flags);
  2976. return rc;
  2977. }
  2978. /**
  2979. * iwl3945_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
  2980. */
  2981. static inline __le32 iwl3945_dma_addr2rbd_ptr(struct iwl3945_priv *priv,
  2982. dma_addr_t dma_addr)
  2983. {
  2984. return cpu_to_le32((u32)dma_addr);
  2985. }
  2986. /**
  2987. * iwl3945_rx_queue_restock - refill RX queue from pre-allocated pool
  2988. *
  2989. * If there are slots in the RX queue that need to be restocked,
  2990. * and we have free pre-allocated buffers, fill the ranks as much
  2991. * as we can, pulling from rx_free.
  2992. *
  2993. * This moves the 'write' index forward to catch up with 'processed', and
  2994. * also updates the memory address in the firmware to reference the new
  2995. * target buffer.
  2996. */
  2997. static int iwl3945_rx_queue_restock(struct iwl3945_priv *priv)
  2998. {
  2999. struct iwl3945_rx_queue *rxq = &priv->rxq;
  3000. struct list_head *element;
  3001. struct iwl3945_rx_mem_buffer *rxb;
  3002. unsigned long flags;
  3003. int write, rc;
  3004. spin_lock_irqsave(&rxq->lock, flags);
  3005. write = rxq->write & ~0x7;
  3006. while ((iwl3945_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
  3007. /* Get next free Rx buffer, remove from free list */
  3008. element = rxq->rx_free.next;
  3009. rxb = list_entry(element, struct iwl3945_rx_mem_buffer, list);
  3010. list_del(element);
  3011. /* Point to Rx buffer via next RBD in circular buffer */
  3012. rxq->bd[rxq->write] = iwl3945_dma_addr2rbd_ptr(priv, rxb->dma_addr);
  3013. rxq->queue[rxq->write] = rxb;
  3014. rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
  3015. rxq->free_count--;
  3016. }
  3017. spin_unlock_irqrestore(&rxq->lock, flags);
  3018. /* If the pre-allocated buffer pool is dropping low, schedule to
  3019. * refill it */
  3020. if (rxq->free_count <= RX_LOW_WATERMARK)
  3021. queue_work(priv->workqueue, &priv->rx_replenish);
  3022. /* If we've added more space for the firmware to place data, tell it.
  3023. * Increment device's write pointer in multiples of 8. */
  3024. if ((write != (rxq->write & ~0x7))
  3025. || (abs(rxq->write - rxq->read) > 7)) {
  3026. spin_lock_irqsave(&rxq->lock, flags);
  3027. rxq->need_update = 1;
  3028. spin_unlock_irqrestore(&rxq->lock, flags);
  3029. rc = iwl3945_rx_queue_update_write_ptr(priv, rxq);
  3030. if (rc)
  3031. return rc;
  3032. }
  3033. return 0;
  3034. }
  3035. /**
  3036. * iwl3945_rx_replenish - Move all used packet from rx_used to rx_free
  3037. *
  3038. * When moving to rx_free an SKB is allocated for the slot.
  3039. *
  3040. * Also restock the Rx queue via iwl3945_rx_queue_restock.
  3041. * This is called as a scheduled work item (except for during initialization)
  3042. */
  3043. static void iwl3945_rx_allocate(struct iwl3945_priv *priv)
  3044. {
  3045. struct iwl3945_rx_queue *rxq = &priv->rxq;
  3046. struct list_head *element;
  3047. struct iwl3945_rx_mem_buffer *rxb;
  3048. unsigned long flags;
  3049. spin_lock_irqsave(&rxq->lock, flags);
  3050. while (!list_empty(&rxq->rx_used)) {
  3051. element = rxq->rx_used.next;
  3052. rxb = list_entry(element, struct iwl3945_rx_mem_buffer, list);
  3053. /* Alloc a new receive buffer */
  3054. rxb->skb =
  3055. alloc_skb(IWL_RX_BUF_SIZE, __GFP_NOWARN | GFP_ATOMIC);
  3056. if (!rxb->skb) {
  3057. if (net_ratelimit())
  3058. printk(KERN_CRIT DRV_NAME
  3059. ": Can not allocate SKB buffers\n");
  3060. /* We don't reschedule replenish work here -- we will
  3061. * call the restock method and if it still needs
  3062. * more buffers it will schedule replenish */
  3063. break;
  3064. }
  3065. /* If radiotap head is required, reserve some headroom here.
  3066. * The physical head count is a variable rx_stats->phy_count.
  3067. * We reserve 4 bytes here. Plus these extra bytes, the
  3068. * headroom of the physical head should be enough for the
  3069. * radiotap head that iwl3945 supported. See iwl3945_rt.
  3070. */
  3071. skb_reserve(rxb->skb, 4);
  3072. priv->alloc_rxb_skb++;
  3073. list_del(element);
  3074. /* Get physical address of RB/SKB */
  3075. rxb->dma_addr =
  3076. pci_map_single(priv->pci_dev, rxb->skb->data,
  3077. IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
  3078. list_add_tail(&rxb->list, &rxq->rx_free);
  3079. rxq->free_count++;
  3080. }
  3081. spin_unlock_irqrestore(&rxq->lock, flags);
  3082. }
  3083. /*
  3084. * this should be called while priv->lock is locked
  3085. */
  3086. static void __iwl3945_rx_replenish(void *data)
  3087. {
  3088. struct iwl3945_priv *priv = data;
  3089. iwl3945_rx_allocate(priv);
  3090. iwl3945_rx_queue_restock(priv);
  3091. }
  3092. void iwl3945_rx_replenish(void *data)
  3093. {
  3094. struct iwl3945_priv *priv = data;
  3095. unsigned long flags;
  3096. iwl3945_rx_allocate(priv);
  3097. spin_lock_irqsave(&priv->lock, flags);
  3098. iwl3945_rx_queue_restock(priv);
  3099. spin_unlock_irqrestore(&priv->lock, flags);
  3100. }
  3101. /* Assumes that the skb field of the buffers in 'pool' is kept accurate.
  3102. * If an SKB has been detached, the POOL needs to have its SKB set to NULL
  3103. * This free routine walks the list of POOL entries and if SKB is set to
  3104. * non NULL it is unmapped and freed
  3105. */
  3106. static void iwl3945_rx_queue_free(struct iwl3945_priv *priv, struct iwl3945_rx_queue *rxq)
  3107. {
  3108. int i;
  3109. for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
  3110. if (rxq->pool[i].skb != NULL) {
  3111. pci_unmap_single(priv->pci_dev,
  3112. rxq->pool[i].dma_addr,
  3113. IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
  3114. dev_kfree_skb(rxq->pool[i].skb);
  3115. }
  3116. }
  3117. pci_free_consistent(priv->pci_dev, 4 * RX_QUEUE_SIZE, rxq->bd,
  3118. rxq->dma_addr);
  3119. rxq->bd = NULL;
  3120. }
  3121. int iwl3945_rx_queue_alloc(struct iwl3945_priv *priv)
  3122. {
  3123. struct iwl3945_rx_queue *rxq = &priv->rxq;
  3124. struct pci_dev *dev = priv->pci_dev;
  3125. int i;
  3126. spin_lock_init(&rxq->lock);
  3127. INIT_LIST_HEAD(&rxq->rx_free);
  3128. INIT_LIST_HEAD(&rxq->rx_used);
  3129. /* Alloc the circular buffer of Read Buffer Descriptors (RBDs) */
  3130. rxq->bd = pci_alloc_consistent(dev, 4 * RX_QUEUE_SIZE, &rxq->dma_addr);
  3131. if (!rxq->bd)
  3132. return -ENOMEM;
  3133. /* Fill the rx_used queue with _all_ of the Rx buffers */
  3134. for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++)
  3135. list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
  3136. /* Set us so that we have processed and used all buffers, but have
  3137. * not restocked the Rx queue with fresh buffers */
  3138. rxq->read = rxq->write = 0;
  3139. rxq->free_count = 0;
  3140. rxq->need_update = 0;
  3141. return 0;
  3142. }
  3143. void iwl3945_rx_queue_reset(struct iwl3945_priv *priv, struct iwl3945_rx_queue *rxq)
  3144. {
  3145. unsigned long flags;
  3146. int i;
  3147. spin_lock_irqsave(&rxq->lock, flags);
  3148. INIT_LIST_HEAD(&rxq->rx_free);
  3149. INIT_LIST_HEAD(&rxq->rx_used);
  3150. /* Fill the rx_used queue with _all_ of the Rx buffers */
  3151. for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
  3152. /* In the reset function, these buffers may have been allocated
  3153. * to an SKB, so we need to unmap and free potential storage */
  3154. if (rxq->pool[i].skb != NULL) {
  3155. pci_unmap_single(priv->pci_dev,
  3156. rxq->pool[i].dma_addr,
  3157. IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
  3158. priv->alloc_rxb_skb--;
  3159. dev_kfree_skb(rxq->pool[i].skb);
  3160. rxq->pool[i].skb = NULL;
  3161. }
  3162. list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
  3163. }
  3164. /* Set us so that we have processed and used all buffers, but have
  3165. * not restocked the Rx queue with fresh buffers */
  3166. rxq->read = rxq->write = 0;
  3167. rxq->free_count = 0;
  3168. spin_unlock_irqrestore(&rxq->lock, flags);
  3169. }
  3170. /* Convert linear signal-to-noise ratio into dB */
  3171. static u8 ratio2dB[100] = {
  3172. /* 0 1 2 3 4 5 6 7 8 9 */
  3173. 0, 0, 6, 10, 12, 14, 16, 17, 18, 19, /* 00 - 09 */
  3174. 20, 21, 22, 22, 23, 23, 24, 25, 26, 26, /* 10 - 19 */
  3175. 26, 26, 26, 27, 27, 28, 28, 28, 29, 29, /* 20 - 29 */
  3176. 29, 30, 30, 30, 31, 31, 31, 31, 32, 32, /* 30 - 39 */
  3177. 32, 32, 32, 33, 33, 33, 33, 33, 34, 34, /* 40 - 49 */
  3178. 34, 34, 34, 34, 35, 35, 35, 35, 35, 35, /* 50 - 59 */
  3179. 36, 36, 36, 36, 36, 36, 36, 37, 37, 37, /* 60 - 69 */
  3180. 37, 37, 37, 37, 37, 38, 38, 38, 38, 38, /* 70 - 79 */
  3181. 38, 38, 38, 38, 38, 39, 39, 39, 39, 39, /* 80 - 89 */
  3182. 39, 39, 39, 39, 39, 40, 40, 40, 40, 40 /* 90 - 99 */
  3183. };
  3184. /* Calculates a relative dB value from a ratio of linear
  3185. * (i.e. not dB) signal levels.
  3186. * Conversion assumes that levels are voltages (20*log), not powers (10*log). */
  3187. int iwl3945_calc_db_from_ratio(int sig_ratio)
  3188. {
  3189. /* 1000:1 or higher just report as 60 dB */
  3190. if (sig_ratio >= 1000)
  3191. return 60;
  3192. /* 100:1 or higher, divide by 10 and use table,
  3193. * add 20 dB to make up for divide by 10 */
  3194. if (sig_ratio >= 100)
  3195. return 20 + (int)ratio2dB[sig_ratio/10];
  3196. /* We shouldn't see this */
  3197. if (sig_ratio < 1)
  3198. return 0;
  3199. /* Use table for ratios 1:1 - 99:1 */
  3200. return (int)ratio2dB[sig_ratio];
  3201. }
  3202. #define PERFECT_RSSI (-20) /* dBm */
  3203. #define WORST_RSSI (-95) /* dBm */
  3204. #define RSSI_RANGE (PERFECT_RSSI - WORST_RSSI)
  3205. /* Calculate an indication of rx signal quality (a percentage, not dBm!).
  3206. * See http://www.ces.clemson.edu/linux/signal_quality.shtml for info
  3207. * about formulas used below. */
  3208. int iwl3945_calc_sig_qual(int rssi_dbm, int noise_dbm)
  3209. {
  3210. int sig_qual;
  3211. int degradation = PERFECT_RSSI - rssi_dbm;
  3212. /* If we get a noise measurement, use signal-to-noise ratio (SNR)
  3213. * as indicator; formula is (signal dbm - noise dbm).
  3214. * SNR at or above 40 is a great signal (100%).
  3215. * Below that, scale to fit SNR of 0 - 40 dB within 0 - 100% indicator.
  3216. * Weakest usable signal is usually 10 - 15 dB SNR. */
  3217. if (noise_dbm) {
  3218. if (rssi_dbm - noise_dbm >= 40)
  3219. return 100;
  3220. else if (rssi_dbm < noise_dbm)
  3221. return 0;
  3222. sig_qual = ((rssi_dbm - noise_dbm) * 5) / 2;
  3223. /* Else use just the signal level.
  3224. * This formula is a least squares fit of data points collected and
  3225. * compared with a reference system that had a percentage (%) display
  3226. * for signal quality. */
  3227. } else
  3228. sig_qual = (100 * (RSSI_RANGE * RSSI_RANGE) - degradation *
  3229. (15 * RSSI_RANGE + 62 * degradation)) /
  3230. (RSSI_RANGE * RSSI_RANGE);
  3231. if (sig_qual > 100)
  3232. sig_qual = 100;
  3233. else if (sig_qual < 1)
  3234. sig_qual = 0;
  3235. return sig_qual;
  3236. }
  3237. /**
  3238. * iwl3945_rx_handle - Main entry function for receiving responses from uCode
  3239. *
  3240. * Uses the priv->rx_handlers callback function array to invoke
  3241. * the appropriate handlers, including command responses,
  3242. * frame-received notifications, and other notifications.
  3243. */
  3244. static void iwl3945_rx_handle(struct iwl3945_priv *priv)
  3245. {
  3246. struct iwl3945_rx_mem_buffer *rxb;
  3247. struct iwl3945_rx_packet *pkt;
  3248. struct iwl3945_rx_queue *rxq = &priv->rxq;
  3249. u32 r, i;
  3250. int reclaim;
  3251. unsigned long flags;
  3252. u8 fill_rx = 0;
  3253. u32 count = 8;
  3254. /* uCode's read index (stored in shared DRAM) indicates the last Rx
  3255. * buffer that the driver may process (last buffer filled by ucode). */
  3256. r = iwl3945_hw_get_rx_read(priv);
  3257. i = rxq->read;
  3258. if (iwl3945_rx_queue_space(rxq) > (RX_QUEUE_SIZE / 2))
  3259. fill_rx = 1;
  3260. /* Rx interrupt, but nothing sent from uCode */
  3261. if (i == r)
  3262. IWL_DEBUG(IWL_DL_RX | IWL_DL_ISR, "r = %d, i = %d\n", r, i);
  3263. while (i != r) {
  3264. rxb = rxq->queue[i];
  3265. /* If an RXB doesn't have a Rx queue slot associated with it,
  3266. * then a bug has been introduced in the queue refilling
  3267. * routines -- catch it here */
  3268. BUG_ON(rxb == NULL);
  3269. rxq->queue[i] = NULL;
  3270. pci_dma_sync_single_for_cpu(priv->pci_dev, rxb->dma_addr,
  3271. IWL_RX_BUF_SIZE,
  3272. PCI_DMA_FROMDEVICE);
  3273. pkt = (struct iwl3945_rx_packet *)rxb->skb->data;
  3274. /* Reclaim a command buffer only if this packet is a response
  3275. * to a (driver-originated) command.
  3276. * If the packet (e.g. Rx frame) originated from uCode,
  3277. * there is no command buffer to reclaim.
  3278. * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
  3279. * but apparently a few don't get set; catch them here. */
  3280. reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
  3281. (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
  3282. (pkt->hdr.cmd != REPLY_TX);
  3283. /* Based on type of command response or notification,
  3284. * handle those that need handling via function in
  3285. * rx_handlers table. See iwl3945_setup_rx_handlers() */
  3286. if (priv->rx_handlers[pkt->hdr.cmd]) {
  3287. IWL_DEBUG(IWL_DL_HOST_COMMAND | IWL_DL_RX | IWL_DL_ISR,
  3288. "r = %d, i = %d, %s, 0x%02x\n", r, i,
  3289. get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
  3290. priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
  3291. } else {
  3292. /* No handling needed */
  3293. IWL_DEBUG(IWL_DL_HOST_COMMAND | IWL_DL_RX | IWL_DL_ISR,
  3294. "r %d i %d No handler needed for %s, 0x%02x\n",
  3295. r, i, get_cmd_string(pkt->hdr.cmd),
  3296. pkt->hdr.cmd);
  3297. }
  3298. if (reclaim) {
  3299. /* Invoke any callbacks, transfer the skb to caller, and
  3300. * fire off the (possibly) blocking iwl3945_send_cmd()
  3301. * as we reclaim the driver command queue */
  3302. if (rxb && rxb->skb)
  3303. iwl3945_tx_cmd_complete(priv, rxb);
  3304. else
  3305. IWL_WARNING("Claim null rxb?\n");
  3306. }
  3307. /* For now we just don't re-use anything. We can tweak this
  3308. * later to try and re-use notification packets and SKBs that
  3309. * fail to Rx correctly */
  3310. if (rxb->skb != NULL) {
  3311. priv->alloc_rxb_skb--;
  3312. dev_kfree_skb_any(rxb->skb);
  3313. rxb->skb = NULL;
  3314. }
  3315. pci_unmap_single(priv->pci_dev, rxb->dma_addr,
  3316. IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
  3317. spin_lock_irqsave(&rxq->lock, flags);
  3318. list_add_tail(&rxb->list, &priv->rxq.rx_used);
  3319. spin_unlock_irqrestore(&rxq->lock, flags);
  3320. i = (i + 1) & RX_QUEUE_MASK;
  3321. /* If there are a lot of unused frames,
  3322. * restock the Rx queue so ucode won't assert. */
  3323. if (fill_rx) {
  3324. count++;
  3325. if (count >= 8) {
  3326. priv->rxq.read = i;
  3327. __iwl3945_rx_replenish(priv);
  3328. count = 0;
  3329. }
  3330. }
  3331. }
  3332. /* Backtrack one entry */
  3333. priv->rxq.read = i;
  3334. iwl3945_rx_queue_restock(priv);
  3335. }
  3336. /**
  3337. * iwl3945_tx_queue_update_write_ptr - Send new write index to hardware
  3338. */
  3339. static int iwl3945_tx_queue_update_write_ptr(struct iwl3945_priv *priv,
  3340. struct iwl3945_tx_queue *txq)
  3341. {
  3342. u32 reg = 0;
  3343. int rc = 0;
  3344. int txq_id = txq->q.id;
  3345. if (txq->need_update == 0)
  3346. return rc;
  3347. /* if we're trying to save power */
  3348. if (test_bit(STATUS_POWER_PMI, &priv->status)) {
  3349. /* wake up nic if it's powered down ...
  3350. * uCode will wake up, and interrupt us again, so next
  3351. * time we'll skip this part. */
  3352. reg = iwl3945_read32(priv, CSR_UCODE_DRV_GP1);
  3353. if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
  3354. IWL_DEBUG_INFO("Requesting wakeup, GP1 = 0x%x\n", reg);
  3355. iwl3945_set_bit(priv, CSR_GP_CNTRL,
  3356. CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  3357. return rc;
  3358. }
  3359. /* restore this queue's parameters in nic hardware. */
  3360. rc = iwl3945_grab_nic_access(priv);
  3361. if (rc)
  3362. return rc;
  3363. iwl3945_write_direct32(priv, HBUS_TARG_WRPTR,
  3364. txq->q.write_ptr | (txq_id << 8));
  3365. iwl3945_release_nic_access(priv);
  3366. /* else not in power-save mode, uCode will never sleep when we're
  3367. * trying to tx (during RFKILL, we're not trying to tx). */
  3368. } else
  3369. iwl3945_write32(priv, HBUS_TARG_WRPTR,
  3370. txq->q.write_ptr | (txq_id << 8));
  3371. txq->need_update = 0;
  3372. return rc;
  3373. }
  3374. #ifdef CONFIG_IWL3945_DEBUG
  3375. static void iwl3945_print_rx_config_cmd(struct iwl3945_rxon_cmd *rxon)
  3376. {
  3377. DECLARE_MAC_BUF(mac);
  3378. IWL_DEBUG_RADIO("RX CONFIG:\n");
  3379. iwl3945_print_hex_dump(IWL_DL_RADIO, (u8 *) rxon, sizeof(*rxon));
  3380. IWL_DEBUG_RADIO("u16 channel: 0x%x\n", le16_to_cpu(rxon->channel));
  3381. IWL_DEBUG_RADIO("u32 flags: 0x%08X\n", le32_to_cpu(rxon->flags));
  3382. IWL_DEBUG_RADIO("u32 filter_flags: 0x%08x\n",
  3383. le32_to_cpu(rxon->filter_flags));
  3384. IWL_DEBUG_RADIO("u8 dev_type: 0x%x\n", rxon->dev_type);
  3385. IWL_DEBUG_RADIO("u8 ofdm_basic_rates: 0x%02x\n",
  3386. rxon->ofdm_basic_rates);
  3387. IWL_DEBUG_RADIO("u8 cck_basic_rates: 0x%02x\n", rxon->cck_basic_rates);
  3388. IWL_DEBUG_RADIO("u8[6] node_addr: %s\n",
  3389. print_mac(mac, rxon->node_addr));
  3390. IWL_DEBUG_RADIO("u8[6] bssid_addr: %s\n",
  3391. print_mac(mac, rxon->bssid_addr));
  3392. IWL_DEBUG_RADIO("u16 assoc_id: 0x%x\n", le16_to_cpu(rxon->assoc_id));
  3393. }
  3394. #endif
  3395. static void iwl3945_enable_interrupts(struct iwl3945_priv *priv)
  3396. {
  3397. IWL_DEBUG_ISR("Enabling interrupts\n");
  3398. set_bit(STATUS_INT_ENABLED, &priv->status);
  3399. iwl3945_write32(priv, CSR_INT_MASK, CSR_INI_SET_MASK);
  3400. }
  3401. /* call this function to flush any scheduled tasklet */
  3402. static inline void iwl_synchronize_irq(struct iwl3945_priv *priv)
  3403. {
  3404. /* wait to make sure we flush pedding tasklet*/
  3405. synchronize_irq(priv->pci_dev->irq);
  3406. tasklet_kill(&priv->irq_tasklet);
  3407. }
  3408. static inline void iwl3945_disable_interrupts(struct iwl3945_priv *priv)
  3409. {
  3410. clear_bit(STATUS_INT_ENABLED, &priv->status);
  3411. /* disable interrupts from uCode/NIC to host */
  3412. iwl3945_write32(priv, CSR_INT_MASK, 0x00000000);
  3413. /* acknowledge/clear/reset any interrupts still pending
  3414. * from uCode or flow handler (Rx/Tx DMA) */
  3415. iwl3945_write32(priv, CSR_INT, 0xffffffff);
  3416. iwl3945_write32(priv, CSR_FH_INT_STATUS, 0xffffffff);
  3417. IWL_DEBUG_ISR("Disabled interrupts\n");
  3418. }
  3419. static const char *desc_lookup(int i)
  3420. {
  3421. switch (i) {
  3422. case 1:
  3423. return "FAIL";
  3424. case 2:
  3425. return "BAD_PARAM";
  3426. case 3:
  3427. return "BAD_CHECKSUM";
  3428. case 4:
  3429. return "NMI_INTERRUPT";
  3430. case 5:
  3431. return "SYSASSERT";
  3432. case 6:
  3433. return "FATAL_ERROR";
  3434. }
  3435. return "UNKNOWN";
  3436. }
  3437. #define ERROR_START_OFFSET (1 * sizeof(u32))
  3438. #define ERROR_ELEM_SIZE (7 * sizeof(u32))
  3439. static void iwl3945_dump_nic_error_log(struct iwl3945_priv *priv)
  3440. {
  3441. u32 i;
  3442. u32 desc, time, count, base, data1;
  3443. u32 blink1, blink2, ilink1, ilink2;
  3444. int rc;
  3445. base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
  3446. if (!iwl3945_hw_valid_rtc_data_addr(base)) {
  3447. IWL_ERROR("Not valid error log pointer 0x%08X\n", base);
  3448. return;
  3449. }
  3450. rc = iwl3945_grab_nic_access(priv);
  3451. if (rc) {
  3452. IWL_WARNING("Can not read from adapter at this time.\n");
  3453. return;
  3454. }
  3455. count = iwl3945_read_targ_mem(priv, base);
  3456. if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
  3457. IWL_ERROR("Start IWL Error Log Dump:\n");
  3458. IWL_ERROR("Status: 0x%08lX, count: %d\n", priv->status, count);
  3459. }
  3460. IWL_ERROR("Desc Time asrtPC blink2 "
  3461. "ilink1 nmiPC Line\n");
  3462. for (i = ERROR_START_OFFSET;
  3463. i < (count * ERROR_ELEM_SIZE) + ERROR_START_OFFSET;
  3464. i += ERROR_ELEM_SIZE) {
  3465. desc = iwl3945_read_targ_mem(priv, base + i);
  3466. time =
  3467. iwl3945_read_targ_mem(priv, base + i + 1 * sizeof(u32));
  3468. blink1 =
  3469. iwl3945_read_targ_mem(priv, base + i + 2 * sizeof(u32));
  3470. blink2 =
  3471. iwl3945_read_targ_mem(priv, base + i + 3 * sizeof(u32));
  3472. ilink1 =
  3473. iwl3945_read_targ_mem(priv, base + i + 4 * sizeof(u32));
  3474. ilink2 =
  3475. iwl3945_read_targ_mem(priv, base + i + 5 * sizeof(u32));
  3476. data1 =
  3477. iwl3945_read_targ_mem(priv, base + i + 6 * sizeof(u32));
  3478. IWL_ERROR
  3479. ("%-13s (#%d) %010u 0x%05X 0x%05X 0x%05X 0x%05X %u\n\n",
  3480. desc_lookup(desc), desc, time, blink1, blink2,
  3481. ilink1, ilink2, data1);
  3482. }
  3483. iwl3945_release_nic_access(priv);
  3484. }
  3485. #define EVENT_START_OFFSET (6 * sizeof(u32))
  3486. /**
  3487. * iwl3945_print_event_log - Dump error event log to syslog
  3488. *
  3489. * NOTE: Must be called with iwl3945_grab_nic_access() already obtained!
  3490. */
  3491. static void iwl3945_print_event_log(struct iwl3945_priv *priv, u32 start_idx,
  3492. u32 num_events, u32 mode)
  3493. {
  3494. u32 i;
  3495. u32 base; /* SRAM byte address of event log header */
  3496. u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
  3497. u32 ptr; /* SRAM byte address of log data */
  3498. u32 ev, time, data; /* event log data */
  3499. if (num_events == 0)
  3500. return;
  3501. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  3502. if (mode == 0)
  3503. event_size = 2 * sizeof(u32);
  3504. else
  3505. event_size = 3 * sizeof(u32);
  3506. ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
  3507. /* "time" is actually "data" for mode 0 (no timestamp).
  3508. * place event id # at far right for easier visual parsing. */
  3509. for (i = 0; i < num_events; i++) {
  3510. ev = iwl3945_read_targ_mem(priv, ptr);
  3511. ptr += sizeof(u32);
  3512. time = iwl3945_read_targ_mem(priv, ptr);
  3513. ptr += sizeof(u32);
  3514. if (mode == 0)
  3515. IWL_ERROR("0x%08x\t%04u\n", time, ev); /* data, ev */
  3516. else {
  3517. data = iwl3945_read_targ_mem(priv, ptr);
  3518. ptr += sizeof(u32);
  3519. IWL_ERROR("%010u\t0x%08x\t%04u\n", time, data, ev);
  3520. }
  3521. }
  3522. }
  3523. static void iwl3945_dump_nic_event_log(struct iwl3945_priv *priv)
  3524. {
  3525. int rc;
  3526. u32 base; /* SRAM byte address of event log header */
  3527. u32 capacity; /* event log capacity in # entries */
  3528. u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
  3529. u32 num_wraps; /* # times uCode wrapped to top of log */
  3530. u32 next_entry; /* index of next entry to be written by uCode */
  3531. u32 size; /* # entries that we'll print */
  3532. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  3533. if (!iwl3945_hw_valid_rtc_data_addr(base)) {
  3534. IWL_ERROR("Invalid event log pointer 0x%08X\n", base);
  3535. return;
  3536. }
  3537. rc = iwl3945_grab_nic_access(priv);
  3538. if (rc) {
  3539. IWL_WARNING("Can not read from adapter at this time.\n");
  3540. return;
  3541. }
  3542. /* event log header */
  3543. capacity = iwl3945_read_targ_mem(priv, base);
  3544. mode = iwl3945_read_targ_mem(priv, base + (1 * sizeof(u32)));
  3545. num_wraps = iwl3945_read_targ_mem(priv, base + (2 * sizeof(u32)));
  3546. next_entry = iwl3945_read_targ_mem(priv, base + (3 * sizeof(u32)));
  3547. size = num_wraps ? capacity : next_entry;
  3548. /* bail out if nothing in log */
  3549. if (size == 0) {
  3550. IWL_ERROR("Start IWL Event Log Dump: nothing in log\n");
  3551. iwl3945_release_nic_access(priv);
  3552. return;
  3553. }
  3554. IWL_ERROR("Start IWL Event Log Dump: display count %d, wraps %d\n",
  3555. size, num_wraps);
  3556. /* if uCode has wrapped back to top of log, start at the oldest entry,
  3557. * i.e the next one that uCode would fill. */
  3558. if (num_wraps)
  3559. iwl3945_print_event_log(priv, next_entry,
  3560. capacity - next_entry, mode);
  3561. /* (then/else) start at top of log */
  3562. iwl3945_print_event_log(priv, 0, next_entry, mode);
  3563. iwl3945_release_nic_access(priv);
  3564. }
  3565. /**
  3566. * iwl3945_irq_handle_error - called for HW or SW error interrupt from card
  3567. */
  3568. static void iwl3945_irq_handle_error(struct iwl3945_priv *priv)
  3569. {
  3570. /* Set the FW error flag -- cleared on iwl3945_down */
  3571. set_bit(STATUS_FW_ERROR, &priv->status);
  3572. /* Cancel currently queued command. */
  3573. clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
  3574. #ifdef CONFIG_IWL3945_DEBUG
  3575. if (iwl3945_debug_level & IWL_DL_FW_ERRORS) {
  3576. iwl3945_dump_nic_error_log(priv);
  3577. iwl3945_dump_nic_event_log(priv);
  3578. iwl3945_print_rx_config_cmd(&priv->staging_rxon);
  3579. }
  3580. #endif
  3581. wake_up_interruptible(&priv->wait_command_queue);
  3582. /* Keep the restart process from trying to send host
  3583. * commands by clearing the INIT status bit */
  3584. clear_bit(STATUS_READY, &priv->status);
  3585. if (!test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  3586. IWL_DEBUG(IWL_DL_INFO | IWL_DL_FW_ERRORS,
  3587. "Restarting adapter due to uCode error.\n");
  3588. if (iwl3945_is_associated(priv)) {
  3589. memcpy(&priv->recovery_rxon, &priv->active_rxon,
  3590. sizeof(priv->recovery_rxon));
  3591. priv->error_recovering = 1;
  3592. }
  3593. queue_work(priv->workqueue, &priv->restart);
  3594. }
  3595. }
  3596. static void iwl3945_error_recovery(struct iwl3945_priv *priv)
  3597. {
  3598. unsigned long flags;
  3599. memcpy(&priv->staging_rxon, &priv->recovery_rxon,
  3600. sizeof(priv->staging_rxon));
  3601. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  3602. iwl3945_commit_rxon(priv);
  3603. iwl3945_add_station(priv, priv->bssid, 1, 0);
  3604. spin_lock_irqsave(&priv->lock, flags);
  3605. priv->assoc_id = le16_to_cpu(priv->staging_rxon.assoc_id);
  3606. priv->error_recovering = 0;
  3607. spin_unlock_irqrestore(&priv->lock, flags);
  3608. }
  3609. static void iwl3945_irq_tasklet(struct iwl3945_priv *priv)
  3610. {
  3611. u32 inta, handled = 0;
  3612. u32 inta_fh;
  3613. unsigned long flags;
  3614. #ifdef CONFIG_IWL3945_DEBUG
  3615. u32 inta_mask;
  3616. #endif
  3617. spin_lock_irqsave(&priv->lock, flags);
  3618. /* Ack/clear/reset pending uCode interrupts.
  3619. * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
  3620. * and will clear only when CSR_FH_INT_STATUS gets cleared. */
  3621. inta = iwl3945_read32(priv, CSR_INT);
  3622. iwl3945_write32(priv, CSR_INT, inta);
  3623. /* Ack/clear/reset pending flow-handler (DMA) interrupts.
  3624. * Any new interrupts that happen after this, either while we're
  3625. * in this tasklet, or later, will show up in next ISR/tasklet. */
  3626. inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS);
  3627. iwl3945_write32(priv, CSR_FH_INT_STATUS, inta_fh);
  3628. #ifdef CONFIG_IWL3945_DEBUG
  3629. if (iwl3945_debug_level & IWL_DL_ISR) {
  3630. /* just for debug */
  3631. inta_mask = iwl3945_read32(priv, CSR_INT_MASK);
  3632. IWL_DEBUG_ISR("inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
  3633. inta, inta_mask, inta_fh);
  3634. }
  3635. #endif
  3636. /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
  3637. * atomic, make sure that inta covers all the interrupts that
  3638. * we've discovered, even if FH interrupt came in just after
  3639. * reading CSR_INT. */
  3640. if (inta_fh & CSR39_FH_INT_RX_MASK)
  3641. inta |= CSR_INT_BIT_FH_RX;
  3642. if (inta_fh & CSR39_FH_INT_TX_MASK)
  3643. inta |= CSR_INT_BIT_FH_TX;
  3644. /* Now service all interrupt bits discovered above. */
  3645. if (inta & CSR_INT_BIT_HW_ERR) {
  3646. IWL_ERROR("Microcode HW error detected. Restarting.\n");
  3647. /* Tell the device to stop sending interrupts */
  3648. iwl3945_disable_interrupts(priv);
  3649. iwl3945_irq_handle_error(priv);
  3650. handled |= CSR_INT_BIT_HW_ERR;
  3651. spin_unlock_irqrestore(&priv->lock, flags);
  3652. return;
  3653. }
  3654. #ifdef CONFIG_IWL3945_DEBUG
  3655. if (iwl3945_debug_level & (IWL_DL_ISR)) {
  3656. /* NIC fires this, but we don't use it, redundant with WAKEUP */
  3657. if (inta & CSR_INT_BIT_SCD)
  3658. IWL_DEBUG_ISR("Scheduler finished to transmit "
  3659. "the frame/frames.\n");
  3660. /* Alive notification via Rx interrupt will do the real work */
  3661. if (inta & CSR_INT_BIT_ALIVE)
  3662. IWL_DEBUG_ISR("Alive interrupt\n");
  3663. }
  3664. #endif
  3665. /* Safely ignore these bits for debug checks below */
  3666. inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
  3667. /* HW RF KILL switch toggled (4965 only) */
  3668. if (inta & CSR_INT_BIT_RF_KILL) {
  3669. int hw_rf_kill = 0;
  3670. if (!(iwl3945_read32(priv, CSR_GP_CNTRL) &
  3671. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
  3672. hw_rf_kill = 1;
  3673. IWL_DEBUG(IWL_DL_INFO | IWL_DL_RF_KILL | IWL_DL_ISR,
  3674. "RF_KILL bit toggled to %s.\n",
  3675. hw_rf_kill ? "disable radio":"enable radio");
  3676. /* Queue restart only if RF_KILL switch was set to "kill"
  3677. * when we loaded driver, and is now set to "enable".
  3678. * After we're Alive, RF_KILL gets handled by
  3679. * iwl3945_rx_card_state_notif() */
  3680. if (!hw_rf_kill && !test_bit(STATUS_ALIVE, &priv->status)) {
  3681. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  3682. queue_work(priv->workqueue, &priv->restart);
  3683. }
  3684. handled |= CSR_INT_BIT_RF_KILL;
  3685. }
  3686. /* Chip got too hot and stopped itself (4965 only) */
  3687. if (inta & CSR_INT_BIT_CT_KILL) {
  3688. IWL_ERROR("Microcode CT kill error detected.\n");
  3689. handled |= CSR_INT_BIT_CT_KILL;
  3690. }
  3691. /* Error detected by uCode */
  3692. if (inta & CSR_INT_BIT_SW_ERR) {
  3693. IWL_ERROR("Microcode SW error detected. Restarting 0x%X.\n",
  3694. inta);
  3695. iwl3945_irq_handle_error(priv);
  3696. handled |= CSR_INT_BIT_SW_ERR;
  3697. }
  3698. /* uCode wakes up after power-down sleep */
  3699. if (inta & CSR_INT_BIT_WAKEUP) {
  3700. IWL_DEBUG_ISR("Wakeup interrupt\n");
  3701. iwl3945_rx_queue_update_write_ptr(priv, &priv->rxq);
  3702. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[0]);
  3703. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[1]);
  3704. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[2]);
  3705. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[3]);
  3706. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[4]);
  3707. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[5]);
  3708. handled |= CSR_INT_BIT_WAKEUP;
  3709. }
  3710. /* All uCode command responses, including Tx command responses,
  3711. * Rx "responses" (frame-received notification), and other
  3712. * notifications from uCode come through here*/
  3713. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
  3714. iwl3945_rx_handle(priv);
  3715. handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
  3716. }
  3717. if (inta & CSR_INT_BIT_FH_TX) {
  3718. IWL_DEBUG_ISR("Tx interrupt\n");
  3719. iwl3945_write32(priv, CSR_FH_INT_STATUS, (1 << 6));
  3720. if (!iwl3945_grab_nic_access(priv)) {
  3721. iwl3945_write_direct32(priv,
  3722. FH_TCSR_CREDIT
  3723. (ALM_FH_SRVC_CHNL), 0x0);
  3724. iwl3945_release_nic_access(priv);
  3725. }
  3726. handled |= CSR_INT_BIT_FH_TX;
  3727. }
  3728. if (inta & ~handled)
  3729. IWL_ERROR("Unhandled INTA bits 0x%08x\n", inta & ~handled);
  3730. if (inta & ~CSR_INI_SET_MASK) {
  3731. IWL_WARNING("Disabled INTA bits 0x%08x were pending\n",
  3732. inta & ~CSR_INI_SET_MASK);
  3733. IWL_WARNING(" with FH_INT = 0x%08x\n", inta_fh);
  3734. }
  3735. /* Re-enable all interrupts */
  3736. /* only Re-enable if disabled by irq */
  3737. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  3738. iwl3945_enable_interrupts(priv);
  3739. #ifdef CONFIG_IWL3945_DEBUG
  3740. if (iwl3945_debug_level & (IWL_DL_ISR)) {
  3741. inta = iwl3945_read32(priv, CSR_INT);
  3742. inta_mask = iwl3945_read32(priv, CSR_INT_MASK);
  3743. inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS);
  3744. IWL_DEBUG_ISR("End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
  3745. "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
  3746. }
  3747. #endif
  3748. spin_unlock_irqrestore(&priv->lock, flags);
  3749. }
  3750. static irqreturn_t iwl3945_isr(int irq, void *data)
  3751. {
  3752. struct iwl3945_priv *priv = data;
  3753. u32 inta, inta_mask;
  3754. u32 inta_fh;
  3755. if (!priv)
  3756. return IRQ_NONE;
  3757. spin_lock(&priv->lock);
  3758. /* Disable (but don't clear!) interrupts here to avoid
  3759. * back-to-back ISRs and sporadic interrupts from our NIC.
  3760. * If we have something to service, the tasklet will re-enable ints.
  3761. * If we *don't* have something, we'll re-enable before leaving here. */
  3762. inta_mask = iwl3945_read32(priv, CSR_INT_MASK); /* just for debug */
  3763. iwl3945_write32(priv, CSR_INT_MASK, 0x00000000);
  3764. /* Discover which interrupts are active/pending */
  3765. inta = iwl3945_read32(priv, CSR_INT);
  3766. inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS);
  3767. /* Ignore interrupt if there's nothing in NIC to service.
  3768. * This may be due to IRQ shared with another device,
  3769. * or due to sporadic interrupts thrown from our NIC. */
  3770. if (!inta && !inta_fh) {
  3771. IWL_DEBUG_ISR("Ignore interrupt, inta == 0, inta_fh == 0\n");
  3772. goto none;
  3773. }
  3774. if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
  3775. /* Hardware disappeared */
  3776. IWL_WARNING("HARDWARE GONE?? INTA == 0x%080x\n", inta);
  3777. goto unplugged;
  3778. }
  3779. IWL_DEBUG_ISR("ISR inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
  3780. inta, inta_mask, inta_fh);
  3781. inta &= ~CSR_INT_BIT_SCD;
  3782. /* iwl3945_irq_tasklet() will service interrupts and re-enable them */
  3783. if (likely(inta || inta_fh))
  3784. tasklet_schedule(&priv->irq_tasklet);
  3785. unplugged:
  3786. spin_unlock(&priv->lock);
  3787. return IRQ_HANDLED;
  3788. none:
  3789. /* re-enable interrupts here since we don't have anything to service. */
  3790. /* only Re-enable if disabled by irq */
  3791. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  3792. iwl3945_enable_interrupts(priv);
  3793. spin_unlock(&priv->lock);
  3794. return IRQ_NONE;
  3795. }
  3796. /************************** EEPROM BANDS ****************************
  3797. *
  3798. * The iwl3945_eeprom_band definitions below provide the mapping from the
  3799. * EEPROM contents to the specific channel number supported for each
  3800. * band.
  3801. *
  3802. * For example, iwl3945_priv->eeprom.band_3_channels[4] from the band_3
  3803. * definition below maps to physical channel 42 in the 5.2GHz spectrum.
  3804. * The specific geography and calibration information for that channel
  3805. * is contained in the eeprom map itself.
  3806. *
  3807. * During init, we copy the eeprom information and channel map
  3808. * information into priv->channel_info_24/52 and priv->channel_map_24/52
  3809. *
  3810. * channel_map_24/52 provides the index in the channel_info array for a
  3811. * given channel. We have to have two separate maps as there is channel
  3812. * overlap with the 2.4GHz and 5.2GHz spectrum as seen in band_1 and
  3813. * band_2
  3814. *
  3815. * A value of 0xff stored in the channel_map indicates that the channel
  3816. * is not supported by the hardware at all.
  3817. *
  3818. * A value of 0xfe in the channel_map indicates that the channel is not
  3819. * valid for Tx with the current hardware. This means that
  3820. * while the system can tune and receive on a given channel, it may not
  3821. * be able to associate or transmit any frames on that
  3822. * channel. There is no corresponding channel information for that
  3823. * entry.
  3824. *
  3825. *********************************************************************/
  3826. /* 2.4 GHz */
  3827. static const u8 iwl3945_eeprom_band_1[14] = {
  3828. 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
  3829. };
  3830. /* 5.2 GHz bands */
  3831. static const u8 iwl3945_eeprom_band_2[] = { /* 4915-5080MHz */
  3832. 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16
  3833. };
  3834. static const u8 iwl3945_eeprom_band_3[] = { /* 5170-5320MHz */
  3835. 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64
  3836. };
  3837. static const u8 iwl3945_eeprom_band_4[] = { /* 5500-5700MHz */
  3838. 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140
  3839. };
  3840. static const u8 iwl3945_eeprom_band_5[] = { /* 5725-5825MHz */
  3841. 145, 149, 153, 157, 161, 165
  3842. };
  3843. static void iwl3945_init_band_reference(const struct iwl3945_priv *priv, int band,
  3844. int *eeprom_ch_count,
  3845. const struct iwl3945_eeprom_channel
  3846. **eeprom_ch_info,
  3847. const u8 **eeprom_ch_index)
  3848. {
  3849. switch (band) {
  3850. case 1: /* 2.4GHz band */
  3851. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_1);
  3852. *eeprom_ch_info = priv->eeprom.band_1_channels;
  3853. *eeprom_ch_index = iwl3945_eeprom_band_1;
  3854. break;
  3855. case 2: /* 4.9GHz band */
  3856. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_2);
  3857. *eeprom_ch_info = priv->eeprom.band_2_channels;
  3858. *eeprom_ch_index = iwl3945_eeprom_band_2;
  3859. break;
  3860. case 3: /* 5.2GHz band */
  3861. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_3);
  3862. *eeprom_ch_info = priv->eeprom.band_3_channels;
  3863. *eeprom_ch_index = iwl3945_eeprom_band_3;
  3864. break;
  3865. case 4: /* 5.5GHz band */
  3866. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_4);
  3867. *eeprom_ch_info = priv->eeprom.band_4_channels;
  3868. *eeprom_ch_index = iwl3945_eeprom_band_4;
  3869. break;
  3870. case 5: /* 5.7GHz band */
  3871. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_5);
  3872. *eeprom_ch_info = priv->eeprom.band_5_channels;
  3873. *eeprom_ch_index = iwl3945_eeprom_band_5;
  3874. break;
  3875. default:
  3876. BUG();
  3877. return;
  3878. }
  3879. }
  3880. /**
  3881. * iwl3945_get_channel_info - Find driver's private channel info
  3882. *
  3883. * Based on band and channel number.
  3884. */
  3885. const struct iwl3945_channel_info *iwl3945_get_channel_info(const struct iwl3945_priv *priv,
  3886. enum ieee80211_band band, u16 channel)
  3887. {
  3888. int i;
  3889. switch (band) {
  3890. case IEEE80211_BAND_5GHZ:
  3891. for (i = 14; i < priv->channel_count; i++) {
  3892. if (priv->channel_info[i].channel == channel)
  3893. return &priv->channel_info[i];
  3894. }
  3895. break;
  3896. case IEEE80211_BAND_2GHZ:
  3897. if (channel >= 1 && channel <= 14)
  3898. return &priv->channel_info[channel - 1];
  3899. break;
  3900. case IEEE80211_NUM_BANDS:
  3901. WARN_ON(1);
  3902. }
  3903. return NULL;
  3904. }
  3905. #define CHECK_AND_PRINT(x) ((eeprom_ch_info[ch].flags & EEPROM_CHANNEL_##x) \
  3906. ? # x " " : "")
  3907. /**
  3908. * iwl3945_init_channel_map - Set up driver's info for all possible channels
  3909. */
  3910. static int iwl3945_init_channel_map(struct iwl3945_priv *priv)
  3911. {
  3912. int eeprom_ch_count = 0;
  3913. const u8 *eeprom_ch_index = NULL;
  3914. const struct iwl3945_eeprom_channel *eeprom_ch_info = NULL;
  3915. int band, ch;
  3916. struct iwl3945_channel_info *ch_info;
  3917. if (priv->channel_count) {
  3918. IWL_DEBUG_INFO("Channel map already initialized.\n");
  3919. return 0;
  3920. }
  3921. if (priv->eeprom.version < 0x2f) {
  3922. IWL_WARNING("Unsupported EEPROM version: 0x%04X\n",
  3923. priv->eeprom.version);
  3924. return -EINVAL;
  3925. }
  3926. IWL_DEBUG_INFO("Initializing regulatory info from EEPROM\n");
  3927. priv->channel_count =
  3928. ARRAY_SIZE(iwl3945_eeprom_band_1) +
  3929. ARRAY_SIZE(iwl3945_eeprom_band_2) +
  3930. ARRAY_SIZE(iwl3945_eeprom_band_3) +
  3931. ARRAY_SIZE(iwl3945_eeprom_band_4) +
  3932. ARRAY_SIZE(iwl3945_eeprom_band_5);
  3933. IWL_DEBUG_INFO("Parsing data for %d channels.\n", priv->channel_count);
  3934. priv->channel_info = kzalloc(sizeof(struct iwl3945_channel_info) *
  3935. priv->channel_count, GFP_KERNEL);
  3936. if (!priv->channel_info) {
  3937. IWL_ERROR("Could not allocate channel_info\n");
  3938. priv->channel_count = 0;
  3939. return -ENOMEM;
  3940. }
  3941. ch_info = priv->channel_info;
  3942. /* Loop through the 5 EEPROM bands adding them in order to the
  3943. * channel map we maintain (that contains additional information than
  3944. * what just in the EEPROM) */
  3945. for (band = 1; band <= 5; band++) {
  3946. iwl3945_init_band_reference(priv, band, &eeprom_ch_count,
  3947. &eeprom_ch_info, &eeprom_ch_index);
  3948. /* Loop through each band adding each of the channels */
  3949. for (ch = 0; ch < eeprom_ch_count; ch++) {
  3950. ch_info->channel = eeprom_ch_index[ch];
  3951. ch_info->band = (band == 1) ? IEEE80211_BAND_2GHZ :
  3952. IEEE80211_BAND_5GHZ;
  3953. /* permanently store EEPROM's channel regulatory flags
  3954. * and max power in channel info database. */
  3955. ch_info->eeprom = eeprom_ch_info[ch];
  3956. /* Copy the run-time flags so they are there even on
  3957. * invalid channels */
  3958. ch_info->flags = eeprom_ch_info[ch].flags;
  3959. if (!(is_channel_valid(ch_info))) {
  3960. IWL_DEBUG_INFO("Ch. %d Flags %x [%sGHz] - "
  3961. "No traffic\n",
  3962. ch_info->channel,
  3963. ch_info->flags,
  3964. is_channel_a_band(ch_info) ?
  3965. "5.2" : "2.4");
  3966. ch_info++;
  3967. continue;
  3968. }
  3969. /* Initialize regulatory-based run-time data */
  3970. ch_info->max_power_avg = ch_info->curr_txpow =
  3971. eeprom_ch_info[ch].max_power_avg;
  3972. ch_info->scan_power = eeprom_ch_info[ch].max_power_avg;
  3973. ch_info->min_power = 0;
  3974. IWL_DEBUG_INFO("Ch. %d [%sGHz] %s%s%s%s%s%s(0x%02x"
  3975. " %ddBm): Ad-Hoc %ssupported\n",
  3976. ch_info->channel,
  3977. is_channel_a_band(ch_info) ?
  3978. "5.2" : "2.4",
  3979. CHECK_AND_PRINT(VALID),
  3980. CHECK_AND_PRINT(IBSS),
  3981. CHECK_AND_PRINT(ACTIVE),
  3982. CHECK_AND_PRINT(RADAR),
  3983. CHECK_AND_PRINT(WIDE),
  3984. CHECK_AND_PRINT(DFS),
  3985. eeprom_ch_info[ch].flags,
  3986. eeprom_ch_info[ch].max_power_avg,
  3987. ((eeprom_ch_info[ch].
  3988. flags & EEPROM_CHANNEL_IBSS)
  3989. && !(eeprom_ch_info[ch].
  3990. flags & EEPROM_CHANNEL_RADAR))
  3991. ? "" : "not ");
  3992. /* Set the user_txpower_limit to the highest power
  3993. * supported by any channel */
  3994. if (eeprom_ch_info[ch].max_power_avg >
  3995. priv->user_txpower_limit)
  3996. priv->user_txpower_limit =
  3997. eeprom_ch_info[ch].max_power_avg;
  3998. ch_info++;
  3999. }
  4000. }
  4001. /* Set up txpower settings in driver for all channels */
  4002. if (iwl3945_txpower_set_from_eeprom(priv))
  4003. return -EIO;
  4004. return 0;
  4005. }
  4006. /*
  4007. * iwl3945_free_channel_map - undo allocations in iwl3945_init_channel_map
  4008. */
  4009. static void iwl3945_free_channel_map(struct iwl3945_priv *priv)
  4010. {
  4011. kfree(priv->channel_info);
  4012. priv->channel_count = 0;
  4013. }
  4014. /* For active scan, listen ACTIVE_DWELL_TIME (msec) on each channel after
  4015. * sending probe req. This should be set long enough to hear probe responses
  4016. * from more than one AP. */
  4017. #define IWL_ACTIVE_DWELL_TIME_24 (20) /* all times in msec */
  4018. #define IWL_ACTIVE_DWELL_TIME_52 (10)
  4019. /* For faster active scanning, scan will move to the next channel if fewer than
  4020. * PLCP_QUIET_THRESH packets are heard on this channel within
  4021. * ACTIVE_QUIET_TIME after sending probe request. This shortens the dwell
  4022. * time if it's a quiet channel (nothing responded to our probe, and there's
  4023. * no other traffic).
  4024. * Disable "quiet" feature by setting PLCP_QUIET_THRESH to 0. */
  4025. #define IWL_PLCP_QUIET_THRESH __constant_cpu_to_le16(1) /* packets */
  4026. #define IWL_ACTIVE_QUIET_TIME __constant_cpu_to_le16(5) /* msec */
  4027. /* For passive scan, listen PASSIVE_DWELL_TIME (msec) on each channel.
  4028. * Must be set longer than active dwell time.
  4029. * For the most reliable scan, set > AP beacon interval (typically 100msec). */
  4030. #define IWL_PASSIVE_DWELL_TIME_24 (20) /* all times in msec */
  4031. #define IWL_PASSIVE_DWELL_TIME_52 (10)
  4032. #define IWL_PASSIVE_DWELL_BASE (100)
  4033. #define IWL_CHANNEL_TUNE_TIME 5
  4034. static inline u16 iwl3945_get_active_dwell_time(struct iwl3945_priv *priv,
  4035. enum ieee80211_band band)
  4036. {
  4037. if (band == IEEE80211_BAND_5GHZ)
  4038. return IWL_ACTIVE_DWELL_TIME_52;
  4039. else
  4040. return IWL_ACTIVE_DWELL_TIME_24;
  4041. }
  4042. static u16 iwl3945_get_passive_dwell_time(struct iwl3945_priv *priv,
  4043. enum ieee80211_band band)
  4044. {
  4045. u16 active = iwl3945_get_active_dwell_time(priv, band);
  4046. u16 passive = (band == IEEE80211_BAND_2GHZ) ?
  4047. IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_24 :
  4048. IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_52;
  4049. if (iwl3945_is_associated(priv)) {
  4050. /* If we're associated, we clamp the maximum passive
  4051. * dwell time to be 98% of the beacon interval (minus
  4052. * 2 * channel tune time) */
  4053. passive = priv->beacon_int;
  4054. if ((passive > IWL_PASSIVE_DWELL_BASE) || !passive)
  4055. passive = IWL_PASSIVE_DWELL_BASE;
  4056. passive = (passive * 98) / 100 - IWL_CHANNEL_TUNE_TIME * 2;
  4057. }
  4058. if (passive <= active)
  4059. passive = active + 1;
  4060. return passive;
  4061. }
  4062. static int iwl3945_get_channels_for_scan(struct iwl3945_priv *priv,
  4063. enum ieee80211_band band,
  4064. u8 is_active, u8 direct_mask,
  4065. struct iwl3945_scan_channel *scan_ch)
  4066. {
  4067. const struct ieee80211_channel *channels = NULL;
  4068. const struct ieee80211_supported_band *sband;
  4069. const struct iwl3945_channel_info *ch_info;
  4070. u16 passive_dwell = 0;
  4071. u16 active_dwell = 0;
  4072. int added, i;
  4073. sband = iwl3945_get_band(priv, band);
  4074. if (!sband)
  4075. return 0;
  4076. channels = sband->channels;
  4077. active_dwell = iwl3945_get_active_dwell_time(priv, band);
  4078. passive_dwell = iwl3945_get_passive_dwell_time(priv, band);
  4079. for (i = 0, added = 0; i < sband->n_channels; i++) {
  4080. if (channels[i].flags & IEEE80211_CHAN_DISABLED)
  4081. continue;
  4082. scan_ch->channel = channels[i].hw_value;
  4083. ch_info = iwl3945_get_channel_info(priv, band, scan_ch->channel);
  4084. if (!is_channel_valid(ch_info)) {
  4085. IWL_DEBUG_SCAN("Channel %d is INVALID for this band.\n",
  4086. scan_ch->channel);
  4087. continue;
  4088. }
  4089. if (!is_active || is_channel_passive(ch_info) ||
  4090. (channels[i].flags & IEEE80211_CHAN_PASSIVE_SCAN))
  4091. scan_ch->type = 0; /* passive */
  4092. else
  4093. scan_ch->type = 1; /* active */
  4094. if (scan_ch->type & 1)
  4095. scan_ch->type |= (direct_mask << 1);
  4096. scan_ch->active_dwell = cpu_to_le16(active_dwell);
  4097. scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
  4098. /* Set txpower levels to defaults */
  4099. scan_ch->tpc.dsp_atten = 110;
  4100. /* scan_pwr_info->tpc.dsp_atten; */
  4101. /*scan_pwr_info->tpc.tx_gain; */
  4102. if (band == IEEE80211_BAND_5GHZ)
  4103. scan_ch->tpc.tx_gain = ((1 << 5) | (3 << 3)) | 3;
  4104. else {
  4105. scan_ch->tpc.tx_gain = ((1 << 5) | (5 << 3));
  4106. /* NOTE: if we were doing 6Mb OFDM for scans we'd use
  4107. * power level:
  4108. * scan_ch->tpc.tx_gain = ((1 << 5) | (2 << 3)) | 3;
  4109. */
  4110. }
  4111. IWL_DEBUG_SCAN("Scanning %d [%s %d]\n",
  4112. scan_ch->channel,
  4113. (scan_ch->type & 1) ? "ACTIVE" : "PASSIVE",
  4114. (scan_ch->type & 1) ?
  4115. active_dwell : passive_dwell);
  4116. scan_ch++;
  4117. added++;
  4118. }
  4119. IWL_DEBUG_SCAN("total channels to scan %d \n", added);
  4120. return added;
  4121. }
  4122. static void iwl3945_init_hw_rates(struct iwl3945_priv *priv,
  4123. struct ieee80211_rate *rates)
  4124. {
  4125. int i;
  4126. for (i = 0; i < IWL_RATE_COUNT; i++) {
  4127. rates[i].bitrate = iwl3945_rates[i].ieee * 5;
  4128. rates[i].hw_value = i; /* Rate scaling will work on indexes */
  4129. rates[i].hw_value_short = i;
  4130. rates[i].flags = 0;
  4131. if ((i > IWL_LAST_OFDM_RATE) || (i < IWL_FIRST_OFDM_RATE)) {
  4132. /*
  4133. * If CCK != 1M then set short preamble rate flag.
  4134. */
  4135. rates[i].flags |= (iwl3945_rates[i].plcp == 10) ?
  4136. 0 : IEEE80211_RATE_SHORT_PREAMBLE;
  4137. }
  4138. }
  4139. }
  4140. /**
  4141. * iwl3945_init_geos - Initialize mac80211's geo/channel info based from eeprom
  4142. */
  4143. static int iwl3945_init_geos(struct iwl3945_priv *priv)
  4144. {
  4145. struct iwl3945_channel_info *ch;
  4146. struct ieee80211_supported_band *sband;
  4147. struct ieee80211_channel *channels;
  4148. struct ieee80211_channel *geo_ch;
  4149. struct ieee80211_rate *rates;
  4150. int i = 0;
  4151. if (priv->bands[IEEE80211_BAND_2GHZ].n_bitrates ||
  4152. priv->bands[IEEE80211_BAND_5GHZ].n_bitrates) {
  4153. IWL_DEBUG_INFO("Geography modes already initialized.\n");
  4154. set_bit(STATUS_GEO_CONFIGURED, &priv->status);
  4155. return 0;
  4156. }
  4157. channels = kzalloc(sizeof(struct ieee80211_channel) *
  4158. priv->channel_count, GFP_KERNEL);
  4159. if (!channels)
  4160. return -ENOMEM;
  4161. rates = kzalloc((sizeof(struct ieee80211_rate) * (IWL_RATE_COUNT + 1)),
  4162. GFP_KERNEL);
  4163. if (!rates) {
  4164. kfree(channels);
  4165. return -ENOMEM;
  4166. }
  4167. /* 5.2GHz channels start after the 2.4GHz channels */
  4168. sband = &priv->bands[IEEE80211_BAND_5GHZ];
  4169. sband->channels = &channels[ARRAY_SIZE(iwl3945_eeprom_band_1)];
  4170. /* just OFDM */
  4171. sband->bitrates = &rates[IWL_FIRST_OFDM_RATE];
  4172. sband->n_bitrates = IWL_RATE_COUNT - IWL_FIRST_OFDM_RATE;
  4173. sband = &priv->bands[IEEE80211_BAND_2GHZ];
  4174. sband->channels = channels;
  4175. /* OFDM & CCK */
  4176. sband->bitrates = rates;
  4177. sband->n_bitrates = IWL_RATE_COUNT;
  4178. priv->ieee_channels = channels;
  4179. priv->ieee_rates = rates;
  4180. iwl3945_init_hw_rates(priv, rates);
  4181. for (i = 0; i < priv->channel_count; i++) {
  4182. ch = &priv->channel_info[i];
  4183. /* FIXME: might be removed if scan is OK*/
  4184. if (!is_channel_valid(ch))
  4185. continue;
  4186. if (is_channel_a_band(ch))
  4187. sband = &priv->bands[IEEE80211_BAND_5GHZ];
  4188. else
  4189. sband = &priv->bands[IEEE80211_BAND_2GHZ];
  4190. geo_ch = &sband->channels[sband->n_channels++];
  4191. geo_ch->center_freq = ieee80211_channel_to_frequency(ch->channel);
  4192. geo_ch->max_power = ch->max_power_avg;
  4193. geo_ch->max_antenna_gain = 0xff;
  4194. geo_ch->hw_value = ch->channel;
  4195. if (is_channel_valid(ch)) {
  4196. if (!(ch->flags & EEPROM_CHANNEL_IBSS))
  4197. geo_ch->flags |= IEEE80211_CHAN_NO_IBSS;
  4198. if (!(ch->flags & EEPROM_CHANNEL_ACTIVE))
  4199. geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
  4200. if (ch->flags & EEPROM_CHANNEL_RADAR)
  4201. geo_ch->flags |= IEEE80211_CHAN_RADAR;
  4202. if (ch->max_power_avg > priv->max_channel_txpower_limit)
  4203. priv->max_channel_txpower_limit =
  4204. ch->max_power_avg;
  4205. } else {
  4206. geo_ch->flags |= IEEE80211_CHAN_DISABLED;
  4207. }
  4208. /* Save flags for reg domain usage */
  4209. geo_ch->orig_flags = geo_ch->flags;
  4210. IWL_DEBUG_INFO("Channel %d Freq=%d[%sGHz] %s flag=0%X\n",
  4211. ch->channel, geo_ch->center_freq,
  4212. is_channel_a_band(ch) ? "5.2" : "2.4",
  4213. geo_ch->flags & IEEE80211_CHAN_DISABLED ?
  4214. "restricted" : "valid",
  4215. geo_ch->flags);
  4216. }
  4217. if ((priv->bands[IEEE80211_BAND_5GHZ].n_channels == 0) &&
  4218. priv->cfg->sku & IWL_SKU_A) {
  4219. printk(KERN_INFO DRV_NAME
  4220. ": Incorrectly detected BG card as ABG. Please send "
  4221. "your PCI ID 0x%04X:0x%04X to maintainer.\n",
  4222. priv->pci_dev->device, priv->pci_dev->subsystem_device);
  4223. priv->cfg->sku &= ~IWL_SKU_A;
  4224. }
  4225. printk(KERN_INFO DRV_NAME
  4226. ": Tunable channels: %d 802.11bg, %d 802.11a channels\n",
  4227. priv->bands[IEEE80211_BAND_2GHZ].n_channels,
  4228. priv->bands[IEEE80211_BAND_5GHZ].n_channels);
  4229. if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
  4230. priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
  4231. &priv->bands[IEEE80211_BAND_2GHZ];
  4232. if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
  4233. priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
  4234. &priv->bands[IEEE80211_BAND_5GHZ];
  4235. set_bit(STATUS_GEO_CONFIGURED, &priv->status);
  4236. return 0;
  4237. }
  4238. /*
  4239. * iwl3945_free_geos - undo allocations in iwl3945_init_geos
  4240. */
  4241. static void iwl3945_free_geos(struct iwl3945_priv *priv)
  4242. {
  4243. kfree(priv->ieee_channels);
  4244. kfree(priv->ieee_rates);
  4245. clear_bit(STATUS_GEO_CONFIGURED, &priv->status);
  4246. }
  4247. /******************************************************************************
  4248. *
  4249. * uCode download functions
  4250. *
  4251. ******************************************************************************/
  4252. static void iwl3945_dealloc_ucode_pci(struct iwl3945_priv *priv)
  4253. {
  4254. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
  4255. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
  4256. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  4257. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
  4258. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  4259. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
  4260. }
  4261. /**
  4262. * iwl3945_verify_inst_full - verify runtime uCode image in card vs. host,
  4263. * looking at all data.
  4264. */
  4265. static int iwl3945_verify_inst_full(struct iwl3945_priv *priv, __le32 *image, u32 len)
  4266. {
  4267. u32 val;
  4268. u32 save_len = len;
  4269. int rc = 0;
  4270. u32 errcnt;
  4271. IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
  4272. rc = iwl3945_grab_nic_access(priv);
  4273. if (rc)
  4274. return rc;
  4275. iwl3945_write_direct32(priv, HBUS_TARG_MEM_RADDR, RTC_INST_LOWER_BOUND);
  4276. errcnt = 0;
  4277. for (; len > 0; len -= sizeof(u32), image++) {
  4278. /* read data comes through single port, auto-incr addr */
  4279. /* NOTE: Use the debugless read so we don't flood kernel log
  4280. * if IWL_DL_IO is set */
  4281. val = _iwl3945_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  4282. if (val != le32_to_cpu(*image)) {
  4283. IWL_ERROR("uCode INST section is invalid at "
  4284. "offset 0x%x, is 0x%x, s/b 0x%x\n",
  4285. save_len - len, val, le32_to_cpu(*image));
  4286. rc = -EIO;
  4287. errcnt++;
  4288. if (errcnt >= 20)
  4289. break;
  4290. }
  4291. }
  4292. iwl3945_release_nic_access(priv);
  4293. if (!errcnt)
  4294. IWL_DEBUG_INFO("ucode image in INSTRUCTION memory is good\n");
  4295. return rc;
  4296. }
  4297. /**
  4298. * iwl3945_verify_inst_sparse - verify runtime uCode image in card vs. host,
  4299. * using sample data 100 bytes apart. If these sample points are good,
  4300. * it's a pretty good bet that everything between them is good, too.
  4301. */
  4302. static int iwl3945_verify_inst_sparse(struct iwl3945_priv *priv, __le32 *image, u32 len)
  4303. {
  4304. u32 val;
  4305. int rc = 0;
  4306. u32 errcnt = 0;
  4307. u32 i;
  4308. IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
  4309. rc = iwl3945_grab_nic_access(priv);
  4310. if (rc)
  4311. return rc;
  4312. for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
  4313. /* read data comes through single port, auto-incr addr */
  4314. /* NOTE: Use the debugless read so we don't flood kernel log
  4315. * if IWL_DL_IO is set */
  4316. iwl3945_write_direct32(priv, HBUS_TARG_MEM_RADDR,
  4317. i + RTC_INST_LOWER_BOUND);
  4318. val = _iwl3945_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  4319. if (val != le32_to_cpu(*image)) {
  4320. #if 0 /* Enable this if you want to see details */
  4321. IWL_ERROR("uCode INST section is invalid at "
  4322. "offset 0x%x, is 0x%x, s/b 0x%x\n",
  4323. i, val, *image);
  4324. #endif
  4325. rc = -EIO;
  4326. errcnt++;
  4327. if (errcnt >= 3)
  4328. break;
  4329. }
  4330. }
  4331. iwl3945_release_nic_access(priv);
  4332. return rc;
  4333. }
  4334. /**
  4335. * iwl3945_verify_ucode - determine which instruction image is in SRAM,
  4336. * and verify its contents
  4337. */
  4338. static int iwl3945_verify_ucode(struct iwl3945_priv *priv)
  4339. {
  4340. __le32 *image;
  4341. u32 len;
  4342. int rc = 0;
  4343. /* Try bootstrap */
  4344. image = (__le32 *)priv->ucode_boot.v_addr;
  4345. len = priv->ucode_boot.len;
  4346. rc = iwl3945_verify_inst_sparse(priv, image, len);
  4347. if (rc == 0) {
  4348. IWL_DEBUG_INFO("Bootstrap uCode is good in inst SRAM\n");
  4349. return 0;
  4350. }
  4351. /* Try initialize */
  4352. image = (__le32 *)priv->ucode_init.v_addr;
  4353. len = priv->ucode_init.len;
  4354. rc = iwl3945_verify_inst_sparse(priv, image, len);
  4355. if (rc == 0) {
  4356. IWL_DEBUG_INFO("Initialize uCode is good in inst SRAM\n");
  4357. return 0;
  4358. }
  4359. /* Try runtime/protocol */
  4360. image = (__le32 *)priv->ucode_code.v_addr;
  4361. len = priv->ucode_code.len;
  4362. rc = iwl3945_verify_inst_sparse(priv, image, len);
  4363. if (rc == 0) {
  4364. IWL_DEBUG_INFO("Runtime uCode is good in inst SRAM\n");
  4365. return 0;
  4366. }
  4367. IWL_ERROR("NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
  4368. /* Since nothing seems to match, show first several data entries in
  4369. * instruction SRAM, so maybe visual inspection will give a clue.
  4370. * Selection of bootstrap image (vs. other images) is arbitrary. */
  4371. image = (__le32 *)priv->ucode_boot.v_addr;
  4372. len = priv->ucode_boot.len;
  4373. rc = iwl3945_verify_inst_full(priv, image, len);
  4374. return rc;
  4375. }
  4376. /* check contents of special bootstrap uCode SRAM */
  4377. static int iwl3945_verify_bsm(struct iwl3945_priv *priv)
  4378. {
  4379. __le32 *image = priv->ucode_boot.v_addr;
  4380. u32 len = priv->ucode_boot.len;
  4381. u32 reg;
  4382. u32 val;
  4383. IWL_DEBUG_INFO("Begin verify bsm\n");
  4384. /* verify BSM SRAM contents */
  4385. val = iwl3945_read_prph(priv, BSM_WR_DWCOUNT_REG);
  4386. for (reg = BSM_SRAM_LOWER_BOUND;
  4387. reg < BSM_SRAM_LOWER_BOUND + len;
  4388. reg += sizeof(u32), image++) {
  4389. val = iwl3945_read_prph(priv, reg);
  4390. if (val != le32_to_cpu(*image)) {
  4391. IWL_ERROR("BSM uCode verification failed at "
  4392. "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
  4393. BSM_SRAM_LOWER_BOUND,
  4394. reg - BSM_SRAM_LOWER_BOUND, len,
  4395. val, le32_to_cpu(*image));
  4396. return -EIO;
  4397. }
  4398. }
  4399. IWL_DEBUG_INFO("BSM bootstrap uCode image OK\n");
  4400. return 0;
  4401. }
  4402. /**
  4403. * iwl3945_load_bsm - Load bootstrap instructions
  4404. *
  4405. * BSM operation:
  4406. *
  4407. * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
  4408. * in special SRAM that does not power down during RFKILL. When powering back
  4409. * up after power-saving sleeps (or during initial uCode load), the BSM loads
  4410. * the bootstrap program into the on-board processor, and starts it.
  4411. *
  4412. * The bootstrap program loads (via DMA) instructions and data for a new
  4413. * program from host DRAM locations indicated by the host driver in the
  4414. * BSM_DRAM_* registers. Once the new program is loaded, it starts
  4415. * automatically.
  4416. *
  4417. * When initializing the NIC, the host driver points the BSM to the
  4418. * "initialize" uCode image. This uCode sets up some internal data, then
  4419. * notifies host via "initialize alive" that it is complete.
  4420. *
  4421. * The host then replaces the BSM_DRAM_* pointer values to point to the
  4422. * normal runtime uCode instructions and a backup uCode data cache buffer
  4423. * (filled initially with starting data values for the on-board processor),
  4424. * then triggers the "initialize" uCode to load and launch the runtime uCode,
  4425. * which begins normal operation.
  4426. *
  4427. * When doing a power-save shutdown, runtime uCode saves data SRAM into
  4428. * the backup data cache in DRAM before SRAM is powered down.
  4429. *
  4430. * When powering back up, the BSM loads the bootstrap program. This reloads
  4431. * the runtime uCode instructions and the backup data cache into SRAM,
  4432. * and re-launches the runtime uCode from where it left off.
  4433. */
  4434. static int iwl3945_load_bsm(struct iwl3945_priv *priv)
  4435. {
  4436. __le32 *image = priv->ucode_boot.v_addr;
  4437. u32 len = priv->ucode_boot.len;
  4438. dma_addr_t pinst;
  4439. dma_addr_t pdata;
  4440. u32 inst_len;
  4441. u32 data_len;
  4442. int rc;
  4443. int i;
  4444. u32 done;
  4445. u32 reg_offset;
  4446. IWL_DEBUG_INFO("Begin load bsm\n");
  4447. /* make sure bootstrap program is no larger than BSM's SRAM size */
  4448. if (len > IWL_MAX_BSM_SIZE)
  4449. return -EINVAL;
  4450. /* Tell bootstrap uCode where to find the "Initialize" uCode
  4451. * in host DRAM ... host DRAM physical address bits 31:0 for 3945.
  4452. * NOTE: iwl3945_initialize_alive_start() will replace these values,
  4453. * after the "initialize" uCode has run, to point to
  4454. * runtime/protocol instructions and backup data cache. */
  4455. pinst = priv->ucode_init.p_addr;
  4456. pdata = priv->ucode_init_data.p_addr;
  4457. inst_len = priv->ucode_init.len;
  4458. data_len = priv->ucode_init_data.len;
  4459. rc = iwl3945_grab_nic_access(priv);
  4460. if (rc)
  4461. return rc;
  4462. iwl3945_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
  4463. iwl3945_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
  4464. iwl3945_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
  4465. iwl3945_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
  4466. /* Fill BSM memory with bootstrap instructions */
  4467. for (reg_offset = BSM_SRAM_LOWER_BOUND;
  4468. reg_offset < BSM_SRAM_LOWER_BOUND + len;
  4469. reg_offset += sizeof(u32), image++)
  4470. _iwl3945_write_prph(priv, reg_offset,
  4471. le32_to_cpu(*image));
  4472. rc = iwl3945_verify_bsm(priv);
  4473. if (rc) {
  4474. iwl3945_release_nic_access(priv);
  4475. return rc;
  4476. }
  4477. /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
  4478. iwl3945_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
  4479. iwl3945_write_prph(priv, BSM_WR_MEM_DST_REG,
  4480. RTC_INST_LOWER_BOUND);
  4481. iwl3945_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
  4482. /* Load bootstrap code into instruction SRAM now,
  4483. * to prepare to load "initialize" uCode */
  4484. iwl3945_write_prph(priv, BSM_WR_CTRL_REG,
  4485. BSM_WR_CTRL_REG_BIT_START);
  4486. /* Wait for load of bootstrap uCode to finish */
  4487. for (i = 0; i < 100; i++) {
  4488. done = iwl3945_read_prph(priv, BSM_WR_CTRL_REG);
  4489. if (!(done & BSM_WR_CTRL_REG_BIT_START))
  4490. break;
  4491. udelay(10);
  4492. }
  4493. if (i < 100)
  4494. IWL_DEBUG_INFO("BSM write complete, poll %d iterations\n", i);
  4495. else {
  4496. IWL_ERROR("BSM write did not complete!\n");
  4497. return -EIO;
  4498. }
  4499. /* Enable future boot loads whenever power management unit triggers it
  4500. * (e.g. when powering back up after power-save shutdown) */
  4501. iwl3945_write_prph(priv, BSM_WR_CTRL_REG,
  4502. BSM_WR_CTRL_REG_BIT_START_EN);
  4503. iwl3945_release_nic_access(priv);
  4504. return 0;
  4505. }
  4506. static void iwl3945_nic_start(struct iwl3945_priv *priv)
  4507. {
  4508. /* Remove all resets to allow NIC to operate */
  4509. iwl3945_write32(priv, CSR_RESET, 0);
  4510. }
  4511. /**
  4512. * iwl3945_read_ucode - Read uCode images from disk file.
  4513. *
  4514. * Copy into buffers for card to fetch via bus-mastering
  4515. */
  4516. static int iwl3945_read_ucode(struct iwl3945_priv *priv)
  4517. {
  4518. struct iwl3945_ucode *ucode;
  4519. int ret = 0;
  4520. const struct firmware *ucode_raw;
  4521. /* firmware file name contains uCode/driver compatibility version */
  4522. const char *name = priv->cfg->fw_name;
  4523. u8 *src;
  4524. size_t len;
  4525. u32 ver, inst_size, data_size, init_size, init_data_size, boot_size;
  4526. /* Ask kernel firmware_class module to get the boot firmware off disk.
  4527. * request_firmware() is synchronous, file is in memory on return. */
  4528. ret = request_firmware(&ucode_raw, name, &priv->pci_dev->dev);
  4529. if (ret < 0) {
  4530. IWL_ERROR("%s firmware file req failed: Reason %d\n",
  4531. name, ret);
  4532. goto error;
  4533. }
  4534. IWL_DEBUG_INFO("Got firmware '%s' file (%zd bytes) from disk\n",
  4535. name, ucode_raw->size);
  4536. /* Make sure that we got at least our header! */
  4537. if (ucode_raw->size < sizeof(*ucode)) {
  4538. IWL_ERROR("File size way too small!\n");
  4539. ret = -EINVAL;
  4540. goto err_release;
  4541. }
  4542. /* Data from ucode file: header followed by uCode images */
  4543. ucode = (void *)ucode_raw->data;
  4544. ver = le32_to_cpu(ucode->ver);
  4545. inst_size = le32_to_cpu(ucode->inst_size);
  4546. data_size = le32_to_cpu(ucode->data_size);
  4547. init_size = le32_to_cpu(ucode->init_size);
  4548. init_data_size = le32_to_cpu(ucode->init_data_size);
  4549. boot_size = le32_to_cpu(ucode->boot_size);
  4550. IWL_DEBUG_INFO("f/w package hdr ucode version = 0x%x\n", ver);
  4551. IWL_DEBUG_INFO("f/w package hdr runtime inst size = %u\n", inst_size);
  4552. IWL_DEBUG_INFO("f/w package hdr runtime data size = %u\n", data_size);
  4553. IWL_DEBUG_INFO("f/w package hdr init inst size = %u\n", init_size);
  4554. IWL_DEBUG_INFO("f/w package hdr init data size = %u\n", init_data_size);
  4555. IWL_DEBUG_INFO("f/w package hdr boot inst size = %u\n", boot_size);
  4556. /* Verify size of file vs. image size info in file's header */
  4557. if (ucode_raw->size < sizeof(*ucode) +
  4558. inst_size + data_size + init_size +
  4559. init_data_size + boot_size) {
  4560. IWL_DEBUG_INFO("uCode file size %d too small\n",
  4561. (int)ucode_raw->size);
  4562. ret = -EINVAL;
  4563. goto err_release;
  4564. }
  4565. /* Verify that uCode images will fit in card's SRAM */
  4566. if (inst_size > IWL_MAX_INST_SIZE) {
  4567. IWL_DEBUG_INFO("uCode instr len %d too large to fit in\n",
  4568. inst_size);
  4569. ret = -EINVAL;
  4570. goto err_release;
  4571. }
  4572. if (data_size > IWL_MAX_DATA_SIZE) {
  4573. IWL_DEBUG_INFO("uCode data len %d too large to fit in\n",
  4574. data_size);
  4575. ret = -EINVAL;
  4576. goto err_release;
  4577. }
  4578. if (init_size > IWL_MAX_INST_SIZE) {
  4579. IWL_DEBUG_INFO("uCode init instr len %d too large to fit in\n",
  4580. init_size);
  4581. ret = -EINVAL;
  4582. goto err_release;
  4583. }
  4584. if (init_data_size > IWL_MAX_DATA_SIZE) {
  4585. IWL_DEBUG_INFO("uCode init data len %d too large to fit in\n",
  4586. init_data_size);
  4587. ret = -EINVAL;
  4588. goto err_release;
  4589. }
  4590. if (boot_size > IWL_MAX_BSM_SIZE) {
  4591. IWL_DEBUG_INFO("uCode boot instr len %d too large to fit in\n",
  4592. boot_size);
  4593. ret = -EINVAL;
  4594. goto err_release;
  4595. }
  4596. /* Allocate ucode buffers for card's bus-master loading ... */
  4597. /* Runtime instructions and 2 copies of data:
  4598. * 1) unmodified from disk
  4599. * 2) backup cache for save/restore during power-downs */
  4600. priv->ucode_code.len = inst_size;
  4601. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
  4602. priv->ucode_data.len = data_size;
  4603. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
  4604. priv->ucode_data_backup.len = data_size;
  4605. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  4606. if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
  4607. !priv->ucode_data_backup.v_addr)
  4608. goto err_pci_alloc;
  4609. /* Initialization instructions and data */
  4610. if (init_size && init_data_size) {
  4611. priv->ucode_init.len = init_size;
  4612. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
  4613. priv->ucode_init_data.len = init_data_size;
  4614. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  4615. if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
  4616. goto err_pci_alloc;
  4617. }
  4618. /* Bootstrap (instructions only, no data) */
  4619. if (boot_size) {
  4620. priv->ucode_boot.len = boot_size;
  4621. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
  4622. if (!priv->ucode_boot.v_addr)
  4623. goto err_pci_alloc;
  4624. }
  4625. /* Copy images into buffers for card's bus-master reads ... */
  4626. /* Runtime instructions (first block of data in file) */
  4627. src = &ucode->data[0];
  4628. len = priv->ucode_code.len;
  4629. IWL_DEBUG_INFO("Copying (but not loading) uCode instr len %Zd\n", len);
  4630. memcpy(priv->ucode_code.v_addr, src, len);
  4631. IWL_DEBUG_INFO("uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
  4632. priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
  4633. /* Runtime data (2nd block)
  4634. * NOTE: Copy into backup buffer will be done in iwl3945_up() */
  4635. src = &ucode->data[inst_size];
  4636. len = priv->ucode_data.len;
  4637. IWL_DEBUG_INFO("Copying (but not loading) uCode data len %Zd\n", len);
  4638. memcpy(priv->ucode_data.v_addr, src, len);
  4639. memcpy(priv->ucode_data_backup.v_addr, src, len);
  4640. /* Initialization instructions (3rd block) */
  4641. if (init_size) {
  4642. src = &ucode->data[inst_size + data_size];
  4643. len = priv->ucode_init.len;
  4644. IWL_DEBUG_INFO("Copying (but not loading) init instr len %Zd\n",
  4645. len);
  4646. memcpy(priv->ucode_init.v_addr, src, len);
  4647. }
  4648. /* Initialization data (4th block) */
  4649. if (init_data_size) {
  4650. src = &ucode->data[inst_size + data_size + init_size];
  4651. len = priv->ucode_init_data.len;
  4652. IWL_DEBUG_INFO("Copying (but not loading) init data len %d\n",
  4653. (int)len);
  4654. memcpy(priv->ucode_init_data.v_addr, src, len);
  4655. }
  4656. /* Bootstrap instructions (5th block) */
  4657. src = &ucode->data[inst_size + data_size + init_size + init_data_size];
  4658. len = priv->ucode_boot.len;
  4659. IWL_DEBUG_INFO("Copying (but not loading) boot instr len %d\n",
  4660. (int)len);
  4661. memcpy(priv->ucode_boot.v_addr, src, len);
  4662. /* We have our copies now, allow OS release its copies */
  4663. release_firmware(ucode_raw);
  4664. return 0;
  4665. err_pci_alloc:
  4666. IWL_ERROR("failed to allocate pci memory\n");
  4667. ret = -ENOMEM;
  4668. iwl3945_dealloc_ucode_pci(priv);
  4669. err_release:
  4670. release_firmware(ucode_raw);
  4671. error:
  4672. return ret;
  4673. }
  4674. /**
  4675. * iwl3945_set_ucode_ptrs - Set uCode address location
  4676. *
  4677. * Tell initialization uCode where to find runtime uCode.
  4678. *
  4679. * BSM registers initially contain pointers to initialization uCode.
  4680. * We need to replace them to load runtime uCode inst and data,
  4681. * and to save runtime data when powering down.
  4682. */
  4683. static int iwl3945_set_ucode_ptrs(struct iwl3945_priv *priv)
  4684. {
  4685. dma_addr_t pinst;
  4686. dma_addr_t pdata;
  4687. int rc = 0;
  4688. unsigned long flags;
  4689. /* bits 31:0 for 3945 */
  4690. pinst = priv->ucode_code.p_addr;
  4691. pdata = priv->ucode_data_backup.p_addr;
  4692. spin_lock_irqsave(&priv->lock, flags);
  4693. rc = iwl3945_grab_nic_access(priv);
  4694. if (rc) {
  4695. spin_unlock_irqrestore(&priv->lock, flags);
  4696. return rc;
  4697. }
  4698. /* Tell bootstrap uCode where to find image to load */
  4699. iwl3945_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
  4700. iwl3945_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
  4701. iwl3945_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG,
  4702. priv->ucode_data.len);
  4703. /* Inst bytecount must be last to set up, bit 31 signals uCode
  4704. * that all new ptr/size info is in place */
  4705. iwl3945_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG,
  4706. priv->ucode_code.len | BSM_DRAM_INST_LOAD);
  4707. iwl3945_release_nic_access(priv);
  4708. spin_unlock_irqrestore(&priv->lock, flags);
  4709. IWL_DEBUG_INFO("Runtime uCode pointers are set.\n");
  4710. return rc;
  4711. }
  4712. /**
  4713. * iwl3945_init_alive_start - Called after REPLY_ALIVE notification received
  4714. *
  4715. * Called after REPLY_ALIVE notification received from "initialize" uCode.
  4716. *
  4717. * Tell "initialize" uCode to go ahead and load the runtime uCode.
  4718. */
  4719. static void iwl3945_init_alive_start(struct iwl3945_priv *priv)
  4720. {
  4721. /* Check alive response for "valid" sign from uCode */
  4722. if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
  4723. /* We had an error bringing up the hardware, so take it
  4724. * all the way back down so we can try again */
  4725. IWL_DEBUG_INFO("Initialize Alive failed.\n");
  4726. goto restart;
  4727. }
  4728. /* Bootstrap uCode has loaded initialize uCode ... verify inst image.
  4729. * This is a paranoid check, because we would not have gotten the
  4730. * "initialize" alive if code weren't properly loaded. */
  4731. if (iwl3945_verify_ucode(priv)) {
  4732. /* Runtime instruction load was bad;
  4733. * take it all the way back down so we can try again */
  4734. IWL_DEBUG_INFO("Bad \"initialize\" uCode load.\n");
  4735. goto restart;
  4736. }
  4737. /* Send pointers to protocol/runtime uCode image ... init code will
  4738. * load and launch runtime uCode, which will send us another "Alive"
  4739. * notification. */
  4740. IWL_DEBUG_INFO("Initialization Alive received.\n");
  4741. if (iwl3945_set_ucode_ptrs(priv)) {
  4742. /* Runtime instruction load won't happen;
  4743. * take it all the way back down so we can try again */
  4744. IWL_DEBUG_INFO("Couldn't set up uCode pointers.\n");
  4745. goto restart;
  4746. }
  4747. return;
  4748. restart:
  4749. queue_work(priv->workqueue, &priv->restart);
  4750. }
  4751. /**
  4752. * iwl3945_alive_start - called after REPLY_ALIVE notification received
  4753. * from protocol/runtime uCode (initialization uCode's
  4754. * Alive gets handled by iwl3945_init_alive_start()).
  4755. */
  4756. static void iwl3945_alive_start(struct iwl3945_priv *priv)
  4757. {
  4758. int rc = 0;
  4759. int thermal_spin = 0;
  4760. u32 rfkill;
  4761. IWL_DEBUG_INFO("Runtime Alive received.\n");
  4762. if (priv->card_alive.is_valid != UCODE_VALID_OK) {
  4763. /* We had an error bringing up the hardware, so take it
  4764. * all the way back down so we can try again */
  4765. IWL_DEBUG_INFO("Alive failed.\n");
  4766. goto restart;
  4767. }
  4768. /* Initialize uCode has loaded Runtime uCode ... verify inst image.
  4769. * This is a paranoid check, because we would not have gotten the
  4770. * "runtime" alive if code weren't properly loaded. */
  4771. if (iwl3945_verify_ucode(priv)) {
  4772. /* Runtime instruction load was bad;
  4773. * take it all the way back down so we can try again */
  4774. IWL_DEBUG_INFO("Bad runtime uCode load.\n");
  4775. goto restart;
  4776. }
  4777. iwl3945_clear_stations_table(priv);
  4778. rc = iwl3945_grab_nic_access(priv);
  4779. if (rc) {
  4780. IWL_WARNING("Can not read rfkill status from adapter\n");
  4781. return;
  4782. }
  4783. rfkill = iwl3945_read_prph(priv, APMG_RFKILL_REG);
  4784. IWL_DEBUG_INFO("RFKILL status: 0x%x\n", rfkill);
  4785. iwl3945_release_nic_access(priv);
  4786. if (rfkill & 0x1) {
  4787. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  4788. /* if rfkill is not on, then wait for thermal
  4789. * sensor in adapter to kick in */
  4790. while (iwl3945_hw_get_temperature(priv) == 0) {
  4791. thermal_spin++;
  4792. udelay(10);
  4793. }
  4794. if (thermal_spin)
  4795. IWL_DEBUG_INFO("Thermal calibration took %dus\n",
  4796. thermal_spin * 10);
  4797. } else
  4798. set_bit(STATUS_RF_KILL_HW, &priv->status);
  4799. /* After the ALIVE response, we can send commands to 3945 uCode */
  4800. set_bit(STATUS_ALIVE, &priv->status);
  4801. /* Clear out the uCode error bit if it is set */
  4802. clear_bit(STATUS_FW_ERROR, &priv->status);
  4803. if (iwl3945_is_rfkill(priv))
  4804. return;
  4805. ieee80211_wake_queues(priv->hw);
  4806. priv->active_rate = priv->rates_mask;
  4807. priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
  4808. iwl3945_send_power_mode(priv, IWL_POWER_LEVEL(priv->power_mode));
  4809. if (iwl3945_is_associated(priv)) {
  4810. struct iwl3945_rxon_cmd *active_rxon =
  4811. (struct iwl3945_rxon_cmd *)(&priv->active_rxon);
  4812. memcpy(&priv->staging_rxon, &priv->active_rxon,
  4813. sizeof(priv->staging_rxon));
  4814. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  4815. } else {
  4816. /* Initialize our rx_config data */
  4817. iwl3945_connection_init_rx_config(priv);
  4818. memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
  4819. }
  4820. /* Configure Bluetooth device coexistence support */
  4821. iwl3945_send_bt_config(priv);
  4822. /* Configure the adapter for unassociated operation */
  4823. iwl3945_commit_rxon(priv);
  4824. iwl3945_reg_txpower_periodic(priv);
  4825. iwl3945_led_register(priv);
  4826. IWL_DEBUG_INFO("ALIVE processing complete.\n");
  4827. set_bit(STATUS_READY, &priv->status);
  4828. wake_up_interruptible(&priv->wait_command_queue);
  4829. if (priv->error_recovering)
  4830. iwl3945_error_recovery(priv);
  4831. ieee80211_notify_mac(priv->hw, IEEE80211_NOTIFY_RE_ASSOC);
  4832. return;
  4833. restart:
  4834. queue_work(priv->workqueue, &priv->restart);
  4835. }
  4836. static void iwl3945_cancel_deferred_work(struct iwl3945_priv *priv);
  4837. static void __iwl3945_down(struct iwl3945_priv *priv)
  4838. {
  4839. unsigned long flags;
  4840. int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
  4841. struct ieee80211_conf *conf = NULL;
  4842. IWL_DEBUG_INFO(DRV_NAME " is going down\n");
  4843. conf = ieee80211_get_hw_conf(priv->hw);
  4844. if (!exit_pending)
  4845. set_bit(STATUS_EXIT_PENDING, &priv->status);
  4846. iwl3945_led_unregister(priv);
  4847. iwl3945_clear_stations_table(priv);
  4848. /* Unblock any waiting calls */
  4849. wake_up_interruptible_all(&priv->wait_command_queue);
  4850. /* Wipe out the EXIT_PENDING status bit if we are not actually
  4851. * exiting the module */
  4852. if (!exit_pending)
  4853. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  4854. /* stop and reset the on-board processor */
  4855. iwl3945_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
  4856. /* tell the device to stop sending interrupts */
  4857. spin_lock_irqsave(&priv->lock, flags);
  4858. iwl3945_disable_interrupts(priv);
  4859. spin_unlock_irqrestore(&priv->lock, flags);
  4860. iwl_synchronize_irq(priv);
  4861. if (priv->mac80211_registered)
  4862. ieee80211_stop_queues(priv->hw);
  4863. /* If we have not previously called iwl3945_init() then
  4864. * clear all bits but the RF Kill and SUSPEND bits and return */
  4865. if (!iwl3945_is_init(priv)) {
  4866. priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  4867. STATUS_RF_KILL_HW |
  4868. test_bit(STATUS_RF_KILL_SW, &priv->status) <<
  4869. STATUS_RF_KILL_SW |
  4870. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  4871. STATUS_GEO_CONFIGURED |
  4872. test_bit(STATUS_IN_SUSPEND, &priv->status) <<
  4873. STATUS_IN_SUSPEND |
  4874. test_bit(STATUS_EXIT_PENDING, &priv->status) <<
  4875. STATUS_EXIT_PENDING;
  4876. goto exit;
  4877. }
  4878. /* ...otherwise clear out all the status bits but the RF Kill and
  4879. * SUSPEND bits and continue taking the NIC down. */
  4880. priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  4881. STATUS_RF_KILL_HW |
  4882. test_bit(STATUS_RF_KILL_SW, &priv->status) <<
  4883. STATUS_RF_KILL_SW |
  4884. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  4885. STATUS_GEO_CONFIGURED |
  4886. test_bit(STATUS_IN_SUSPEND, &priv->status) <<
  4887. STATUS_IN_SUSPEND |
  4888. test_bit(STATUS_FW_ERROR, &priv->status) <<
  4889. STATUS_FW_ERROR |
  4890. test_bit(STATUS_EXIT_PENDING, &priv->status) <<
  4891. STATUS_EXIT_PENDING;
  4892. spin_lock_irqsave(&priv->lock, flags);
  4893. iwl3945_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  4894. spin_unlock_irqrestore(&priv->lock, flags);
  4895. iwl3945_hw_txq_ctx_stop(priv);
  4896. iwl3945_hw_rxq_stop(priv);
  4897. spin_lock_irqsave(&priv->lock, flags);
  4898. if (!iwl3945_grab_nic_access(priv)) {
  4899. iwl3945_write_prph(priv, APMG_CLK_DIS_REG,
  4900. APMG_CLK_VAL_DMA_CLK_RQT);
  4901. iwl3945_release_nic_access(priv);
  4902. }
  4903. spin_unlock_irqrestore(&priv->lock, flags);
  4904. udelay(5);
  4905. iwl3945_hw_nic_stop_master(priv);
  4906. iwl3945_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
  4907. iwl3945_hw_nic_reset(priv);
  4908. exit:
  4909. memset(&priv->card_alive, 0, sizeof(struct iwl3945_alive_resp));
  4910. if (priv->ibss_beacon)
  4911. dev_kfree_skb(priv->ibss_beacon);
  4912. priv->ibss_beacon = NULL;
  4913. /* clear out any free frames */
  4914. iwl3945_clear_free_frames(priv);
  4915. }
  4916. static void iwl3945_down(struct iwl3945_priv *priv)
  4917. {
  4918. mutex_lock(&priv->mutex);
  4919. __iwl3945_down(priv);
  4920. mutex_unlock(&priv->mutex);
  4921. iwl3945_cancel_deferred_work(priv);
  4922. }
  4923. #define MAX_HW_RESTARTS 5
  4924. static int __iwl3945_up(struct iwl3945_priv *priv)
  4925. {
  4926. int rc, i;
  4927. if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  4928. IWL_WARNING("Exit pending; will not bring the NIC up\n");
  4929. return -EIO;
  4930. }
  4931. if (test_bit(STATUS_RF_KILL_SW, &priv->status)) {
  4932. IWL_WARNING("Radio disabled by SW RF kill (module "
  4933. "parameter)\n");
  4934. return -ENODEV;
  4935. }
  4936. if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
  4937. IWL_ERROR("ucode not available for device bringup\n");
  4938. return -EIO;
  4939. }
  4940. /* If platform's RF_KILL switch is NOT set to KILL */
  4941. if (iwl3945_read32(priv, CSR_GP_CNTRL) &
  4942. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
  4943. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  4944. else {
  4945. set_bit(STATUS_RF_KILL_HW, &priv->status);
  4946. if (!test_bit(STATUS_IN_SUSPEND, &priv->status)) {
  4947. IWL_WARNING("Radio disabled by HW RF Kill switch\n");
  4948. return -ENODEV;
  4949. }
  4950. }
  4951. iwl3945_write32(priv, CSR_INT, 0xFFFFFFFF);
  4952. rc = iwl3945_hw_nic_init(priv);
  4953. if (rc) {
  4954. IWL_ERROR("Unable to int nic\n");
  4955. return rc;
  4956. }
  4957. /* make sure rfkill handshake bits are cleared */
  4958. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  4959. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  4960. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  4961. /* clear (again), then enable host interrupts */
  4962. iwl3945_write32(priv, CSR_INT, 0xFFFFFFFF);
  4963. iwl3945_enable_interrupts(priv);
  4964. /* really make sure rfkill handshake bits are cleared */
  4965. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  4966. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  4967. /* Copy original ucode data image from disk into backup cache.
  4968. * This will be used to initialize the on-board processor's
  4969. * data SRAM for a clean start when the runtime program first loads. */
  4970. memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
  4971. priv->ucode_data.len);
  4972. /* We return success when we resume from suspend and rf_kill is on. */
  4973. if (test_bit(STATUS_RF_KILL_HW, &priv->status))
  4974. return 0;
  4975. for (i = 0; i < MAX_HW_RESTARTS; i++) {
  4976. iwl3945_clear_stations_table(priv);
  4977. /* load bootstrap state machine,
  4978. * load bootstrap program into processor's memory,
  4979. * prepare to load the "initialize" uCode */
  4980. rc = iwl3945_load_bsm(priv);
  4981. if (rc) {
  4982. IWL_ERROR("Unable to set up bootstrap uCode: %d\n", rc);
  4983. continue;
  4984. }
  4985. /* start card; "initialize" will load runtime ucode */
  4986. iwl3945_nic_start(priv);
  4987. IWL_DEBUG_INFO(DRV_NAME " is coming up\n");
  4988. return 0;
  4989. }
  4990. set_bit(STATUS_EXIT_PENDING, &priv->status);
  4991. __iwl3945_down(priv);
  4992. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  4993. /* tried to restart and config the device for as long as our
  4994. * patience could withstand */
  4995. IWL_ERROR("Unable to initialize device after %d attempts.\n", i);
  4996. return -EIO;
  4997. }
  4998. /*****************************************************************************
  4999. *
  5000. * Workqueue callbacks
  5001. *
  5002. *****************************************************************************/
  5003. static void iwl3945_bg_init_alive_start(struct work_struct *data)
  5004. {
  5005. struct iwl3945_priv *priv =
  5006. container_of(data, struct iwl3945_priv, init_alive_start.work);
  5007. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5008. return;
  5009. mutex_lock(&priv->mutex);
  5010. iwl3945_init_alive_start(priv);
  5011. mutex_unlock(&priv->mutex);
  5012. }
  5013. static void iwl3945_bg_alive_start(struct work_struct *data)
  5014. {
  5015. struct iwl3945_priv *priv =
  5016. container_of(data, struct iwl3945_priv, alive_start.work);
  5017. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5018. return;
  5019. mutex_lock(&priv->mutex);
  5020. iwl3945_alive_start(priv);
  5021. mutex_unlock(&priv->mutex);
  5022. }
  5023. static void iwl3945_bg_rf_kill(struct work_struct *work)
  5024. {
  5025. struct iwl3945_priv *priv = container_of(work, struct iwl3945_priv, rf_kill);
  5026. wake_up_interruptible(&priv->wait_command_queue);
  5027. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5028. return;
  5029. mutex_lock(&priv->mutex);
  5030. if (!iwl3945_is_rfkill(priv)) {
  5031. IWL_DEBUG(IWL_DL_INFO | IWL_DL_RF_KILL,
  5032. "HW and/or SW RF Kill no longer active, restarting "
  5033. "device\n");
  5034. if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
  5035. queue_work(priv->workqueue, &priv->restart);
  5036. } else {
  5037. if (!test_bit(STATUS_RF_KILL_HW, &priv->status))
  5038. IWL_DEBUG_RF_KILL("Can not turn radio back on - "
  5039. "disabled by SW switch\n");
  5040. else
  5041. IWL_WARNING("Radio Frequency Kill Switch is On:\n"
  5042. "Kill switch must be turned off for "
  5043. "wireless networking to work.\n");
  5044. }
  5045. mutex_unlock(&priv->mutex);
  5046. iwl3945_rfkill_set_hw_state(priv);
  5047. }
  5048. static void iwl3945_bg_set_monitor(struct work_struct *work)
  5049. {
  5050. struct iwl3945_priv *priv = container_of(work,
  5051. struct iwl3945_priv, set_monitor);
  5052. IWL_DEBUG(IWL_DL_STATE, "setting monitor mode\n");
  5053. mutex_lock(&priv->mutex);
  5054. if (!iwl3945_is_ready(priv))
  5055. IWL_DEBUG(IWL_DL_STATE, "leave - not ready\n");
  5056. else
  5057. if (iwl3945_set_mode(priv, IEEE80211_IF_TYPE_MNTR) != 0)
  5058. IWL_ERROR("iwl3945_set_mode() failed\n");
  5059. mutex_unlock(&priv->mutex);
  5060. }
  5061. #define IWL_SCAN_CHECK_WATCHDOG (7 * HZ)
  5062. static void iwl3945_bg_scan_check(struct work_struct *data)
  5063. {
  5064. struct iwl3945_priv *priv =
  5065. container_of(data, struct iwl3945_priv, scan_check.work);
  5066. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5067. return;
  5068. mutex_lock(&priv->mutex);
  5069. if (test_bit(STATUS_SCANNING, &priv->status) ||
  5070. test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  5071. IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN,
  5072. "Scan completion watchdog resetting adapter (%dms)\n",
  5073. jiffies_to_msecs(IWL_SCAN_CHECK_WATCHDOG));
  5074. if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
  5075. iwl3945_send_scan_abort(priv);
  5076. }
  5077. mutex_unlock(&priv->mutex);
  5078. }
  5079. static void iwl3945_bg_request_scan(struct work_struct *data)
  5080. {
  5081. struct iwl3945_priv *priv =
  5082. container_of(data, struct iwl3945_priv, request_scan);
  5083. struct iwl3945_host_cmd cmd = {
  5084. .id = REPLY_SCAN_CMD,
  5085. .len = sizeof(struct iwl3945_scan_cmd),
  5086. .meta.flags = CMD_SIZE_HUGE,
  5087. };
  5088. int rc = 0;
  5089. struct iwl3945_scan_cmd *scan;
  5090. struct ieee80211_conf *conf = NULL;
  5091. u8 direct_mask;
  5092. enum ieee80211_band band;
  5093. conf = ieee80211_get_hw_conf(priv->hw);
  5094. mutex_lock(&priv->mutex);
  5095. if (!iwl3945_is_ready(priv)) {
  5096. IWL_WARNING("request scan called when driver not ready.\n");
  5097. goto done;
  5098. }
  5099. /* Make sure the scan wasn't cancelled before this queued work
  5100. * was given the chance to run... */
  5101. if (!test_bit(STATUS_SCANNING, &priv->status))
  5102. goto done;
  5103. /* This should never be called or scheduled if there is currently
  5104. * a scan active in the hardware. */
  5105. if (test_bit(STATUS_SCAN_HW, &priv->status)) {
  5106. IWL_DEBUG_INFO("Multiple concurrent scan requests in parallel. "
  5107. "Ignoring second request.\n");
  5108. rc = -EIO;
  5109. goto done;
  5110. }
  5111. if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  5112. IWL_DEBUG_SCAN("Aborting scan due to device shutdown\n");
  5113. goto done;
  5114. }
  5115. if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  5116. IWL_DEBUG_HC("Scan request while abort pending. Queuing.\n");
  5117. goto done;
  5118. }
  5119. if (iwl3945_is_rfkill(priv)) {
  5120. IWL_DEBUG_HC("Aborting scan due to RF Kill activation\n");
  5121. goto done;
  5122. }
  5123. if (!test_bit(STATUS_READY, &priv->status)) {
  5124. IWL_DEBUG_HC("Scan request while uninitialized. Queuing.\n");
  5125. goto done;
  5126. }
  5127. if (!priv->scan_bands) {
  5128. IWL_DEBUG_HC("Aborting scan due to no requested bands\n");
  5129. goto done;
  5130. }
  5131. if (!priv->scan) {
  5132. priv->scan = kmalloc(sizeof(struct iwl3945_scan_cmd) +
  5133. IWL_MAX_SCAN_SIZE, GFP_KERNEL);
  5134. if (!priv->scan) {
  5135. rc = -ENOMEM;
  5136. goto done;
  5137. }
  5138. }
  5139. scan = priv->scan;
  5140. memset(scan, 0, sizeof(struct iwl3945_scan_cmd) + IWL_MAX_SCAN_SIZE);
  5141. scan->quiet_plcp_th = IWL_PLCP_QUIET_THRESH;
  5142. scan->quiet_time = IWL_ACTIVE_QUIET_TIME;
  5143. if (iwl3945_is_associated(priv)) {
  5144. u16 interval = 0;
  5145. u32 extra;
  5146. u32 suspend_time = 100;
  5147. u32 scan_suspend_time = 100;
  5148. unsigned long flags;
  5149. IWL_DEBUG_INFO("Scanning while associated...\n");
  5150. spin_lock_irqsave(&priv->lock, flags);
  5151. interval = priv->beacon_int;
  5152. spin_unlock_irqrestore(&priv->lock, flags);
  5153. scan->suspend_time = 0;
  5154. scan->max_out_time = cpu_to_le32(200 * 1024);
  5155. if (!interval)
  5156. interval = suspend_time;
  5157. /*
  5158. * suspend time format:
  5159. * 0-19: beacon interval in usec (time before exec.)
  5160. * 20-23: 0
  5161. * 24-31: number of beacons (suspend between channels)
  5162. */
  5163. extra = (suspend_time / interval) << 24;
  5164. scan_suspend_time = 0xFF0FFFFF &
  5165. (extra | ((suspend_time % interval) * 1024));
  5166. scan->suspend_time = cpu_to_le32(scan_suspend_time);
  5167. IWL_DEBUG_SCAN("suspend_time 0x%X beacon interval %d\n",
  5168. scan_suspend_time, interval);
  5169. }
  5170. /* We should add the ability for user to lock to PASSIVE ONLY */
  5171. if (priv->one_direct_scan) {
  5172. IWL_DEBUG_SCAN
  5173. ("Kicking off one direct scan for '%s'\n",
  5174. iwl3945_escape_essid(priv->direct_ssid,
  5175. priv->direct_ssid_len));
  5176. scan->direct_scan[0].id = WLAN_EID_SSID;
  5177. scan->direct_scan[0].len = priv->direct_ssid_len;
  5178. memcpy(scan->direct_scan[0].ssid,
  5179. priv->direct_ssid, priv->direct_ssid_len);
  5180. direct_mask = 1;
  5181. } else if (!iwl3945_is_associated(priv) && priv->essid_len) {
  5182. IWL_DEBUG_SCAN
  5183. ("Kicking off one direct scan for '%s' when not associated\n",
  5184. iwl3945_escape_essid(priv->essid, priv->essid_len));
  5185. scan->direct_scan[0].id = WLAN_EID_SSID;
  5186. scan->direct_scan[0].len = priv->essid_len;
  5187. memcpy(scan->direct_scan[0].ssid, priv->essid, priv->essid_len);
  5188. direct_mask = 1;
  5189. } else {
  5190. IWL_DEBUG_SCAN("Kicking off one indirect scan.\n");
  5191. direct_mask = 0;
  5192. }
  5193. /* We don't build a direct scan probe request; the uCode will do
  5194. * that based on the direct_mask added to each channel entry */
  5195. scan->tx_cmd.len = cpu_to_le16(
  5196. iwl3945_fill_probe_req(priv, (struct ieee80211_mgmt *)scan->data,
  5197. IWL_MAX_SCAN_SIZE - sizeof(*scan), 0));
  5198. scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
  5199. scan->tx_cmd.sta_id = priv->hw_setting.bcast_sta_id;
  5200. scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  5201. /* flags + rate selection */
  5202. if (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ)) {
  5203. scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
  5204. scan->tx_cmd.rate = IWL_RATE_1M_PLCP;
  5205. scan->good_CRC_th = 0;
  5206. band = IEEE80211_BAND_2GHZ;
  5207. } else if (priv->scan_bands & BIT(IEEE80211_BAND_5GHZ)) {
  5208. scan->tx_cmd.rate = IWL_RATE_6M_PLCP;
  5209. scan->good_CRC_th = IWL_GOOD_CRC_TH;
  5210. band = IEEE80211_BAND_5GHZ;
  5211. } else {
  5212. IWL_WARNING("Invalid scan band count\n");
  5213. goto done;
  5214. }
  5215. /* select Rx antennas */
  5216. scan->flags |= iwl3945_get_antenna_flags(priv);
  5217. if (priv->iw_mode == IEEE80211_IF_TYPE_MNTR)
  5218. scan->filter_flags = RXON_FILTER_PROMISC_MSK;
  5219. if (direct_mask)
  5220. scan->channel_count =
  5221. iwl3945_get_channels_for_scan(
  5222. priv, band, 1, /* active */
  5223. direct_mask,
  5224. (void *)&scan->data[le16_to_cpu(scan->tx_cmd.len)]);
  5225. else
  5226. scan->channel_count =
  5227. iwl3945_get_channels_for_scan(
  5228. priv, band, 0, /* passive */
  5229. direct_mask,
  5230. (void *)&scan->data[le16_to_cpu(scan->tx_cmd.len)]);
  5231. cmd.len += le16_to_cpu(scan->tx_cmd.len) +
  5232. scan->channel_count * sizeof(struct iwl3945_scan_channel);
  5233. cmd.data = scan;
  5234. scan->len = cpu_to_le16(cmd.len);
  5235. set_bit(STATUS_SCAN_HW, &priv->status);
  5236. rc = iwl3945_send_cmd_sync(priv, &cmd);
  5237. if (rc)
  5238. goto done;
  5239. queue_delayed_work(priv->workqueue, &priv->scan_check,
  5240. IWL_SCAN_CHECK_WATCHDOG);
  5241. mutex_unlock(&priv->mutex);
  5242. return;
  5243. done:
  5244. /* inform mac80211 scan aborted */
  5245. queue_work(priv->workqueue, &priv->scan_completed);
  5246. mutex_unlock(&priv->mutex);
  5247. }
  5248. static void iwl3945_bg_up(struct work_struct *data)
  5249. {
  5250. struct iwl3945_priv *priv = container_of(data, struct iwl3945_priv, up);
  5251. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5252. return;
  5253. mutex_lock(&priv->mutex);
  5254. __iwl3945_up(priv);
  5255. mutex_unlock(&priv->mutex);
  5256. iwl3945_rfkill_set_hw_state(priv);
  5257. }
  5258. static void iwl3945_bg_restart(struct work_struct *data)
  5259. {
  5260. struct iwl3945_priv *priv = container_of(data, struct iwl3945_priv, restart);
  5261. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5262. return;
  5263. iwl3945_down(priv);
  5264. queue_work(priv->workqueue, &priv->up);
  5265. }
  5266. static void iwl3945_bg_rx_replenish(struct work_struct *data)
  5267. {
  5268. struct iwl3945_priv *priv =
  5269. container_of(data, struct iwl3945_priv, rx_replenish);
  5270. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5271. return;
  5272. mutex_lock(&priv->mutex);
  5273. iwl3945_rx_replenish(priv);
  5274. mutex_unlock(&priv->mutex);
  5275. }
  5276. #define IWL_DELAY_NEXT_SCAN (HZ*2)
  5277. static void iwl3945_bg_post_associate(struct work_struct *data)
  5278. {
  5279. struct iwl3945_priv *priv = container_of(data, struct iwl3945_priv,
  5280. post_associate.work);
  5281. int rc = 0;
  5282. struct ieee80211_conf *conf = NULL;
  5283. DECLARE_MAC_BUF(mac);
  5284. if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
  5285. IWL_ERROR("%s Should not be called in AP mode\n", __func__);
  5286. return;
  5287. }
  5288. IWL_DEBUG_ASSOC("Associated as %d to: %s\n",
  5289. priv->assoc_id,
  5290. print_mac(mac, priv->active_rxon.bssid_addr));
  5291. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5292. return;
  5293. mutex_lock(&priv->mutex);
  5294. if (!priv->vif || !priv->is_open) {
  5295. mutex_unlock(&priv->mutex);
  5296. return;
  5297. }
  5298. iwl3945_scan_cancel_timeout(priv, 200);
  5299. conf = ieee80211_get_hw_conf(priv->hw);
  5300. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  5301. iwl3945_commit_rxon(priv);
  5302. memset(&priv->rxon_timing, 0, sizeof(struct iwl3945_rxon_time_cmd));
  5303. iwl3945_setup_rxon_timing(priv);
  5304. rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  5305. sizeof(priv->rxon_timing), &priv->rxon_timing);
  5306. if (rc)
  5307. IWL_WARNING("REPLY_RXON_TIMING failed - "
  5308. "Attempting to continue.\n");
  5309. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  5310. priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
  5311. IWL_DEBUG_ASSOC("assoc id %d beacon interval %d\n",
  5312. priv->assoc_id, priv->beacon_int);
  5313. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
  5314. priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  5315. else
  5316. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  5317. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  5318. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
  5319. priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  5320. else
  5321. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  5322. if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS)
  5323. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  5324. }
  5325. iwl3945_commit_rxon(priv);
  5326. switch (priv->iw_mode) {
  5327. case IEEE80211_IF_TYPE_STA:
  5328. iwl3945_rate_scale_init(priv->hw, IWL_AP_ID);
  5329. break;
  5330. case IEEE80211_IF_TYPE_IBSS:
  5331. /* clear out the station table */
  5332. iwl3945_clear_stations_table(priv);
  5333. iwl3945_add_station(priv, iwl3945_broadcast_addr, 0, 0);
  5334. iwl3945_add_station(priv, priv->bssid, 0, 0);
  5335. iwl3945_sync_sta(priv, IWL_STA_ID,
  5336. (priv->band == IEEE80211_BAND_5GHZ) ?
  5337. IWL_RATE_6M_PLCP : IWL_RATE_1M_PLCP,
  5338. CMD_ASYNC);
  5339. iwl3945_rate_scale_init(priv->hw, IWL_STA_ID);
  5340. iwl3945_send_beacon_cmd(priv);
  5341. break;
  5342. default:
  5343. IWL_ERROR("%s Should not be called in %d mode\n",
  5344. __func__, priv->iw_mode);
  5345. break;
  5346. }
  5347. iwl3945_activate_qos(priv, 0);
  5348. /* we have just associated, don't start scan too early */
  5349. priv->next_scan_jiffies = jiffies + IWL_DELAY_NEXT_SCAN;
  5350. mutex_unlock(&priv->mutex);
  5351. }
  5352. static void iwl3945_bg_abort_scan(struct work_struct *work)
  5353. {
  5354. struct iwl3945_priv *priv = container_of(work, struct iwl3945_priv, abort_scan);
  5355. if (!iwl3945_is_ready(priv))
  5356. return;
  5357. mutex_lock(&priv->mutex);
  5358. set_bit(STATUS_SCAN_ABORTING, &priv->status);
  5359. iwl3945_send_scan_abort(priv);
  5360. mutex_unlock(&priv->mutex);
  5361. }
  5362. static int iwl3945_mac_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf);
  5363. static void iwl3945_bg_scan_completed(struct work_struct *work)
  5364. {
  5365. struct iwl3945_priv *priv =
  5366. container_of(work, struct iwl3945_priv, scan_completed);
  5367. IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN, "SCAN complete scan\n");
  5368. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5369. return;
  5370. if (test_bit(STATUS_CONF_PENDING, &priv->status))
  5371. iwl3945_mac_config(priv->hw, ieee80211_get_hw_conf(priv->hw));
  5372. ieee80211_scan_completed(priv->hw);
  5373. /* Since setting the TXPOWER may have been deferred while
  5374. * performing the scan, fire one off */
  5375. mutex_lock(&priv->mutex);
  5376. iwl3945_hw_reg_send_txpower(priv);
  5377. mutex_unlock(&priv->mutex);
  5378. }
  5379. /*****************************************************************************
  5380. *
  5381. * mac80211 entry point functions
  5382. *
  5383. *****************************************************************************/
  5384. #define UCODE_READY_TIMEOUT (2 * HZ)
  5385. static int iwl3945_mac_start(struct ieee80211_hw *hw)
  5386. {
  5387. struct iwl3945_priv *priv = hw->priv;
  5388. int ret;
  5389. IWL_DEBUG_MAC80211("enter\n");
  5390. if (pci_enable_device(priv->pci_dev)) {
  5391. IWL_ERROR("Fail to pci_enable_device\n");
  5392. return -ENODEV;
  5393. }
  5394. pci_restore_state(priv->pci_dev);
  5395. pci_enable_msi(priv->pci_dev);
  5396. ret = request_irq(priv->pci_dev->irq, iwl3945_isr, IRQF_SHARED,
  5397. DRV_NAME, priv);
  5398. if (ret) {
  5399. IWL_ERROR("Error allocating IRQ %d\n", priv->pci_dev->irq);
  5400. goto out_disable_msi;
  5401. }
  5402. /* we should be verifying the device is ready to be opened */
  5403. mutex_lock(&priv->mutex);
  5404. memset(&priv->staging_rxon, 0, sizeof(struct iwl3945_rxon_cmd));
  5405. /* fetch ucode file from disk, alloc and copy to bus-master buffers ...
  5406. * ucode filename and max sizes are card-specific. */
  5407. if (!priv->ucode_code.len) {
  5408. ret = iwl3945_read_ucode(priv);
  5409. if (ret) {
  5410. IWL_ERROR("Could not read microcode: %d\n", ret);
  5411. mutex_unlock(&priv->mutex);
  5412. goto out_release_irq;
  5413. }
  5414. }
  5415. ret = __iwl3945_up(priv);
  5416. mutex_unlock(&priv->mutex);
  5417. iwl3945_rfkill_set_hw_state(priv);
  5418. if (ret)
  5419. goto out_release_irq;
  5420. IWL_DEBUG_INFO("Start UP work.\n");
  5421. if (test_bit(STATUS_IN_SUSPEND, &priv->status))
  5422. return 0;
  5423. /* Wait for START_ALIVE from ucode. Otherwise callbacks from
  5424. * mac80211 will not be run successfully. */
  5425. ret = wait_event_interruptible_timeout(priv->wait_command_queue,
  5426. test_bit(STATUS_READY, &priv->status),
  5427. UCODE_READY_TIMEOUT);
  5428. if (!ret) {
  5429. if (!test_bit(STATUS_READY, &priv->status)) {
  5430. IWL_ERROR("Wait for START_ALIVE timeout after %dms.\n",
  5431. jiffies_to_msecs(UCODE_READY_TIMEOUT));
  5432. ret = -ETIMEDOUT;
  5433. goto out_release_irq;
  5434. }
  5435. }
  5436. priv->is_open = 1;
  5437. IWL_DEBUG_MAC80211("leave\n");
  5438. return 0;
  5439. out_release_irq:
  5440. free_irq(priv->pci_dev->irq, priv);
  5441. out_disable_msi:
  5442. pci_disable_msi(priv->pci_dev);
  5443. pci_disable_device(priv->pci_dev);
  5444. priv->is_open = 0;
  5445. IWL_DEBUG_MAC80211("leave - failed\n");
  5446. return ret;
  5447. }
  5448. static void iwl3945_mac_stop(struct ieee80211_hw *hw)
  5449. {
  5450. struct iwl3945_priv *priv = hw->priv;
  5451. IWL_DEBUG_MAC80211("enter\n");
  5452. if (!priv->is_open) {
  5453. IWL_DEBUG_MAC80211("leave - skip\n");
  5454. return;
  5455. }
  5456. priv->is_open = 0;
  5457. if (iwl3945_is_ready_rf(priv)) {
  5458. /* stop mac, cancel any scan request and clear
  5459. * RXON_FILTER_ASSOC_MSK BIT
  5460. */
  5461. mutex_lock(&priv->mutex);
  5462. iwl3945_scan_cancel_timeout(priv, 100);
  5463. cancel_delayed_work(&priv->post_associate);
  5464. mutex_unlock(&priv->mutex);
  5465. }
  5466. iwl3945_down(priv);
  5467. flush_workqueue(priv->workqueue);
  5468. free_irq(priv->pci_dev->irq, priv);
  5469. pci_disable_msi(priv->pci_dev);
  5470. pci_save_state(priv->pci_dev);
  5471. pci_disable_device(priv->pci_dev);
  5472. IWL_DEBUG_MAC80211("leave\n");
  5473. }
  5474. static int iwl3945_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
  5475. {
  5476. struct iwl3945_priv *priv = hw->priv;
  5477. IWL_DEBUG_MAC80211("enter\n");
  5478. IWL_DEBUG_TX("dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
  5479. ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
  5480. if (iwl3945_tx_skb(priv, skb))
  5481. dev_kfree_skb_any(skb);
  5482. IWL_DEBUG_MAC80211("leave\n");
  5483. return 0;
  5484. }
  5485. static int iwl3945_mac_add_interface(struct ieee80211_hw *hw,
  5486. struct ieee80211_if_init_conf *conf)
  5487. {
  5488. struct iwl3945_priv *priv = hw->priv;
  5489. unsigned long flags;
  5490. DECLARE_MAC_BUF(mac);
  5491. IWL_DEBUG_MAC80211("enter: type %d\n", conf->type);
  5492. if (priv->vif) {
  5493. IWL_DEBUG_MAC80211("leave - vif != NULL\n");
  5494. return -EOPNOTSUPP;
  5495. }
  5496. spin_lock_irqsave(&priv->lock, flags);
  5497. priv->vif = conf->vif;
  5498. spin_unlock_irqrestore(&priv->lock, flags);
  5499. mutex_lock(&priv->mutex);
  5500. if (conf->mac_addr) {
  5501. IWL_DEBUG_MAC80211("Set: %s\n", print_mac(mac, conf->mac_addr));
  5502. memcpy(priv->mac_addr, conf->mac_addr, ETH_ALEN);
  5503. }
  5504. if (iwl3945_is_ready(priv))
  5505. iwl3945_set_mode(priv, conf->type);
  5506. mutex_unlock(&priv->mutex);
  5507. IWL_DEBUG_MAC80211("leave\n");
  5508. return 0;
  5509. }
  5510. /**
  5511. * iwl3945_mac_config - mac80211 config callback
  5512. *
  5513. * We ignore conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME since it seems to
  5514. * be set inappropriately and the driver currently sets the hardware up to
  5515. * use it whenever needed.
  5516. */
  5517. static int iwl3945_mac_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf)
  5518. {
  5519. struct iwl3945_priv *priv = hw->priv;
  5520. const struct iwl3945_channel_info *ch_info;
  5521. unsigned long flags;
  5522. int ret = 0;
  5523. mutex_lock(&priv->mutex);
  5524. IWL_DEBUG_MAC80211("enter to channel %d\n", conf->channel->hw_value);
  5525. priv->add_radiotap = !!(conf->flags & IEEE80211_CONF_RADIOTAP);
  5526. if (!iwl3945_is_ready(priv)) {
  5527. IWL_DEBUG_MAC80211("leave - not ready\n");
  5528. ret = -EIO;
  5529. goto out;
  5530. }
  5531. if (unlikely(!iwl3945_param_disable_hw_scan &&
  5532. test_bit(STATUS_SCANNING, &priv->status))) {
  5533. IWL_DEBUG_MAC80211("leave - scanning\n");
  5534. set_bit(STATUS_CONF_PENDING, &priv->status);
  5535. mutex_unlock(&priv->mutex);
  5536. return 0;
  5537. }
  5538. spin_lock_irqsave(&priv->lock, flags);
  5539. ch_info = iwl3945_get_channel_info(priv, conf->channel->band,
  5540. conf->channel->hw_value);
  5541. if (!is_channel_valid(ch_info)) {
  5542. IWL_DEBUG_SCAN("Channel %d [%d] is INVALID for this band.\n",
  5543. conf->channel->hw_value, conf->channel->band);
  5544. IWL_DEBUG_MAC80211("leave - invalid channel\n");
  5545. spin_unlock_irqrestore(&priv->lock, flags);
  5546. ret = -EINVAL;
  5547. goto out;
  5548. }
  5549. iwl3945_set_rxon_channel(priv, conf->channel->band, conf->channel->hw_value);
  5550. iwl3945_set_flags_for_phymode(priv, conf->channel->band);
  5551. /* The list of supported rates and rate mask can be different
  5552. * for each phymode; since the phymode may have changed, reset
  5553. * the rate mask to what mac80211 lists */
  5554. iwl3945_set_rate(priv);
  5555. spin_unlock_irqrestore(&priv->lock, flags);
  5556. #ifdef IEEE80211_CONF_CHANNEL_SWITCH
  5557. if (conf->flags & IEEE80211_CONF_CHANNEL_SWITCH) {
  5558. iwl3945_hw_channel_switch(priv, conf->channel);
  5559. goto out;
  5560. }
  5561. #endif
  5562. iwl3945_radio_kill_sw(priv, !conf->radio_enabled);
  5563. if (!conf->radio_enabled) {
  5564. IWL_DEBUG_MAC80211("leave - radio disabled\n");
  5565. goto out;
  5566. }
  5567. if (iwl3945_is_rfkill(priv)) {
  5568. IWL_DEBUG_MAC80211("leave - RF kill\n");
  5569. ret = -EIO;
  5570. goto out;
  5571. }
  5572. iwl3945_set_rate(priv);
  5573. if (memcmp(&priv->active_rxon,
  5574. &priv->staging_rxon, sizeof(priv->staging_rxon)))
  5575. iwl3945_commit_rxon(priv);
  5576. else
  5577. IWL_DEBUG_INFO("No re-sending same RXON configuration.\n");
  5578. IWL_DEBUG_MAC80211("leave\n");
  5579. out:
  5580. clear_bit(STATUS_CONF_PENDING, &priv->status);
  5581. mutex_unlock(&priv->mutex);
  5582. return ret;
  5583. }
  5584. static void iwl3945_config_ap(struct iwl3945_priv *priv)
  5585. {
  5586. int rc = 0;
  5587. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5588. return;
  5589. /* The following should be done only at AP bring up */
  5590. if (!(iwl3945_is_associated(priv))) {
  5591. /* RXON - unassoc (to set timing command) */
  5592. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  5593. iwl3945_commit_rxon(priv);
  5594. /* RXON Timing */
  5595. memset(&priv->rxon_timing, 0, sizeof(struct iwl3945_rxon_time_cmd));
  5596. iwl3945_setup_rxon_timing(priv);
  5597. rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  5598. sizeof(priv->rxon_timing), &priv->rxon_timing);
  5599. if (rc)
  5600. IWL_WARNING("REPLY_RXON_TIMING failed - "
  5601. "Attempting to continue.\n");
  5602. /* FIXME: what should be the assoc_id for AP? */
  5603. priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
  5604. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
  5605. priv->staging_rxon.flags |=
  5606. RXON_FLG_SHORT_PREAMBLE_MSK;
  5607. else
  5608. priv->staging_rxon.flags &=
  5609. ~RXON_FLG_SHORT_PREAMBLE_MSK;
  5610. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  5611. if (priv->assoc_capability &
  5612. WLAN_CAPABILITY_SHORT_SLOT_TIME)
  5613. priv->staging_rxon.flags |=
  5614. RXON_FLG_SHORT_SLOT_MSK;
  5615. else
  5616. priv->staging_rxon.flags &=
  5617. ~RXON_FLG_SHORT_SLOT_MSK;
  5618. if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS)
  5619. priv->staging_rxon.flags &=
  5620. ~RXON_FLG_SHORT_SLOT_MSK;
  5621. }
  5622. /* restore RXON assoc */
  5623. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  5624. iwl3945_commit_rxon(priv);
  5625. iwl3945_add_station(priv, iwl3945_broadcast_addr, 0, 0);
  5626. }
  5627. iwl3945_send_beacon_cmd(priv);
  5628. /* FIXME - we need to add code here to detect a totally new
  5629. * configuration, reset the AP, unassoc, rxon timing, assoc,
  5630. * clear sta table, add BCAST sta... */
  5631. }
  5632. /* temporary */
  5633. static int iwl3945_mac_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb);
  5634. static int iwl3945_mac_config_interface(struct ieee80211_hw *hw,
  5635. struct ieee80211_vif *vif,
  5636. struct ieee80211_if_conf *conf)
  5637. {
  5638. struct iwl3945_priv *priv = hw->priv;
  5639. DECLARE_MAC_BUF(mac);
  5640. unsigned long flags;
  5641. int rc;
  5642. if (conf == NULL)
  5643. return -EIO;
  5644. if (priv->vif != vif) {
  5645. IWL_DEBUG_MAC80211("leave - priv->vif != vif\n");
  5646. return 0;
  5647. }
  5648. /* handle this temporarily here */
  5649. if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS &&
  5650. conf->changed & IEEE80211_IFCC_BEACON) {
  5651. struct sk_buff *beacon = ieee80211_beacon_get(hw, vif);
  5652. if (!beacon)
  5653. return -ENOMEM;
  5654. rc = iwl3945_mac_beacon_update(hw, beacon);
  5655. if (rc)
  5656. return rc;
  5657. }
  5658. /* XXX: this MUST use conf->mac_addr */
  5659. if ((priv->iw_mode == IEEE80211_IF_TYPE_AP) &&
  5660. (!conf->ssid_len)) {
  5661. IWL_DEBUG_MAC80211
  5662. ("Leaving in AP mode because HostAPD is not ready.\n");
  5663. return 0;
  5664. }
  5665. if (!iwl3945_is_alive(priv))
  5666. return -EAGAIN;
  5667. mutex_lock(&priv->mutex);
  5668. if (conf->bssid)
  5669. IWL_DEBUG_MAC80211("bssid: %s\n",
  5670. print_mac(mac, conf->bssid));
  5671. /*
  5672. * very dubious code was here; the probe filtering flag is never set:
  5673. *
  5674. if (unlikely(test_bit(STATUS_SCANNING, &priv->status)) &&
  5675. !(priv->hw->flags & IEEE80211_HW_NO_PROBE_FILTERING)) {
  5676. */
  5677. if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
  5678. if (!conf->bssid) {
  5679. conf->bssid = priv->mac_addr;
  5680. memcpy(priv->bssid, priv->mac_addr, ETH_ALEN);
  5681. IWL_DEBUG_MAC80211("bssid was set to: %s\n",
  5682. print_mac(mac, conf->bssid));
  5683. }
  5684. if (priv->ibss_beacon)
  5685. dev_kfree_skb(priv->ibss_beacon);
  5686. priv->ibss_beacon = ieee80211_beacon_get(hw, vif);
  5687. }
  5688. if (iwl3945_is_rfkill(priv))
  5689. goto done;
  5690. if (conf->bssid && !is_zero_ether_addr(conf->bssid) &&
  5691. !is_multicast_ether_addr(conf->bssid)) {
  5692. /* If there is currently a HW scan going on in the background
  5693. * then we need to cancel it else the RXON below will fail. */
  5694. if (iwl3945_scan_cancel_timeout(priv, 100)) {
  5695. IWL_WARNING("Aborted scan still in progress "
  5696. "after 100ms\n");
  5697. IWL_DEBUG_MAC80211("leaving - scan abort failed.\n");
  5698. mutex_unlock(&priv->mutex);
  5699. return -EAGAIN;
  5700. }
  5701. memcpy(priv->staging_rxon.bssid_addr, conf->bssid, ETH_ALEN);
  5702. /* TODO: Audit driver for usage of these members and see
  5703. * if mac80211 deprecates them (priv->bssid looks like it
  5704. * shouldn't be there, but I haven't scanned the IBSS code
  5705. * to verify) - jpk */
  5706. memcpy(priv->bssid, conf->bssid, ETH_ALEN);
  5707. if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
  5708. iwl3945_config_ap(priv);
  5709. else {
  5710. rc = iwl3945_commit_rxon(priv);
  5711. if ((priv->iw_mode == IEEE80211_IF_TYPE_STA) && rc)
  5712. iwl3945_add_station(priv,
  5713. priv->active_rxon.bssid_addr, 1, 0);
  5714. }
  5715. } else {
  5716. iwl3945_scan_cancel_timeout(priv, 100);
  5717. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  5718. iwl3945_commit_rxon(priv);
  5719. }
  5720. done:
  5721. spin_lock_irqsave(&priv->lock, flags);
  5722. if (!conf->ssid_len)
  5723. memset(priv->essid, 0, IW_ESSID_MAX_SIZE);
  5724. else
  5725. memcpy(priv->essid, conf->ssid, conf->ssid_len);
  5726. priv->essid_len = conf->ssid_len;
  5727. spin_unlock_irqrestore(&priv->lock, flags);
  5728. IWL_DEBUG_MAC80211("leave\n");
  5729. mutex_unlock(&priv->mutex);
  5730. return 0;
  5731. }
  5732. static void iwl3945_configure_filter(struct ieee80211_hw *hw,
  5733. unsigned int changed_flags,
  5734. unsigned int *total_flags,
  5735. int mc_count, struct dev_addr_list *mc_list)
  5736. {
  5737. struct iwl3945_priv *priv = hw->priv;
  5738. if (changed_flags & (*total_flags) & FIF_OTHER_BSS) {
  5739. IWL_DEBUG_MAC80211("Enter: type %d (0x%x, 0x%x)\n",
  5740. IEEE80211_IF_TYPE_MNTR,
  5741. changed_flags, *total_flags);
  5742. /* queue work 'cuz mac80211 is holding a lock which
  5743. * prevents us from issuing (synchronous) f/w cmds */
  5744. queue_work(priv->workqueue, &priv->set_monitor);
  5745. }
  5746. *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI |
  5747. FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
  5748. }
  5749. static void iwl3945_mac_remove_interface(struct ieee80211_hw *hw,
  5750. struct ieee80211_if_init_conf *conf)
  5751. {
  5752. struct iwl3945_priv *priv = hw->priv;
  5753. IWL_DEBUG_MAC80211("enter\n");
  5754. mutex_lock(&priv->mutex);
  5755. if (iwl3945_is_ready_rf(priv)) {
  5756. iwl3945_scan_cancel_timeout(priv, 100);
  5757. cancel_delayed_work(&priv->post_associate);
  5758. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  5759. iwl3945_commit_rxon(priv);
  5760. }
  5761. if (priv->vif == conf->vif) {
  5762. priv->vif = NULL;
  5763. memset(priv->bssid, 0, ETH_ALEN);
  5764. memset(priv->essid, 0, IW_ESSID_MAX_SIZE);
  5765. priv->essid_len = 0;
  5766. }
  5767. mutex_unlock(&priv->mutex);
  5768. IWL_DEBUG_MAC80211("leave\n");
  5769. }
  5770. static int iwl3945_mac_hw_scan(struct ieee80211_hw *hw, u8 *ssid, size_t len)
  5771. {
  5772. int rc = 0;
  5773. unsigned long flags;
  5774. struct iwl3945_priv *priv = hw->priv;
  5775. IWL_DEBUG_MAC80211("enter\n");
  5776. mutex_lock(&priv->mutex);
  5777. spin_lock_irqsave(&priv->lock, flags);
  5778. if (!iwl3945_is_ready_rf(priv)) {
  5779. rc = -EIO;
  5780. IWL_DEBUG_MAC80211("leave - not ready or exit pending\n");
  5781. goto out_unlock;
  5782. }
  5783. if (priv->iw_mode == IEEE80211_IF_TYPE_AP) { /* APs don't scan */
  5784. rc = -EIO;
  5785. IWL_ERROR("ERROR: APs don't scan\n");
  5786. goto out_unlock;
  5787. }
  5788. /* we don't schedule scan within next_scan_jiffies period */
  5789. if (priv->next_scan_jiffies &&
  5790. time_after(priv->next_scan_jiffies, jiffies)) {
  5791. rc = -EAGAIN;
  5792. goto out_unlock;
  5793. }
  5794. /* if we just finished scan ask for delay for a broadcast scan */
  5795. if ((len == 0) && priv->last_scan_jiffies &&
  5796. time_after(priv->last_scan_jiffies + IWL_DELAY_NEXT_SCAN,
  5797. jiffies)) {
  5798. rc = -EAGAIN;
  5799. goto out_unlock;
  5800. }
  5801. if (len) {
  5802. IWL_DEBUG_SCAN("direct scan for %s [%d]\n ",
  5803. iwl3945_escape_essid(ssid, len), (int)len);
  5804. priv->one_direct_scan = 1;
  5805. priv->direct_ssid_len = (u8)
  5806. min((u8) len, (u8) IW_ESSID_MAX_SIZE);
  5807. memcpy(priv->direct_ssid, ssid, priv->direct_ssid_len);
  5808. } else
  5809. priv->one_direct_scan = 0;
  5810. rc = iwl3945_scan_initiate(priv);
  5811. IWL_DEBUG_MAC80211("leave\n");
  5812. out_unlock:
  5813. spin_unlock_irqrestore(&priv->lock, flags);
  5814. mutex_unlock(&priv->mutex);
  5815. return rc;
  5816. }
  5817. static int iwl3945_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
  5818. const u8 *local_addr, const u8 *addr,
  5819. struct ieee80211_key_conf *key)
  5820. {
  5821. struct iwl3945_priv *priv = hw->priv;
  5822. int rc = 0;
  5823. u8 sta_id;
  5824. IWL_DEBUG_MAC80211("enter\n");
  5825. if (!iwl3945_param_hwcrypto) {
  5826. IWL_DEBUG_MAC80211("leave - hwcrypto disabled\n");
  5827. return -EOPNOTSUPP;
  5828. }
  5829. if (is_zero_ether_addr(addr))
  5830. /* only support pairwise keys */
  5831. return -EOPNOTSUPP;
  5832. sta_id = iwl3945_hw_find_station(priv, addr);
  5833. if (sta_id == IWL_INVALID_STATION) {
  5834. DECLARE_MAC_BUF(mac);
  5835. IWL_DEBUG_MAC80211("leave - %s not in station map.\n",
  5836. print_mac(mac, addr));
  5837. return -EINVAL;
  5838. }
  5839. mutex_lock(&priv->mutex);
  5840. iwl3945_scan_cancel_timeout(priv, 100);
  5841. switch (cmd) {
  5842. case SET_KEY:
  5843. rc = iwl3945_update_sta_key_info(priv, key, sta_id);
  5844. if (!rc) {
  5845. iwl3945_set_rxon_hwcrypto(priv, 1);
  5846. iwl3945_commit_rxon(priv);
  5847. key->hw_key_idx = sta_id;
  5848. IWL_DEBUG_MAC80211("set_key success, using hwcrypto\n");
  5849. key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
  5850. }
  5851. break;
  5852. case DISABLE_KEY:
  5853. rc = iwl3945_clear_sta_key_info(priv, sta_id);
  5854. if (!rc) {
  5855. iwl3945_set_rxon_hwcrypto(priv, 0);
  5856. iwl3945_commit_rxon(priv);
  5857. IWL_DEBUG_MAC80211("disable hwcrypto key\n");
  5858. }
  5859. break;
  5860. default:
  5861. rc = -EINVAL;
  5862. }
  5863. IWL_DEBUG_MAC80211("leave\n");
  5864. mutex_unlock(&priv->mutex);
  5865. return rc;
  5866. }
  5867. static int iwl3945_mac_conf_tx(struct ieee80211_hw *hw, u16 queue,
  5868. const struct ieee80211_tx_queue_params *params)
  5869. {
  5870. struct iwl3945_priv *priv = hw->priv;
  5871. unsigned long flags;
  5872. int q;
  5873. IWL_DEBUG_MAC80211("enter\n");
  5874. if (!iwl3945_is_ready_rf(priv)) {
  5875. IWL_DEBUG_MAC80211("leave - RF not ready\n");
  5876. return -EIO;
  5877. }
  5878. if (queue >= AC_NUM) {
  5879. IWL_DEBUG_MAC80211("leave - queue >= AC_NUM %d\n", queue);
  5880. return 0;
  5881. }
  5882. if (!priv->qos_data.qos_enable) {
  5883. priv->qos_data.qos_active = 0;
  5884. IWL_DEBUG_MAC80211("leave - qos not enabled\n");
  5885. return 0;
  5886. }
  5887. q = AC_NUM - 1 - queue;
  5888. spin_lock_irqsave(&priv->lock, flags);
  5889. priv->qos_data.def_qos_parm.ac[q].cw_min = cpu_to_le16(params->cw_min);
  5890. priv->qos_data.def_qos_parm.ac[q].cw_max = cpu_to_le16(params->cw_max);
  5891. priv->qos_data.def_qos_parm.ac[q].aifsn = params->aifs;
  5892. priv->qos_data.def_qos_parm.ac[q].edca_txop =
  5893. cpu_to_le16((params->txop * 32));
  5894. priv->qos_data.def_qos_parm.ac[q].reserved1 = 0;
  5895. priv->qos_data.qos_active = 1;
  5896. spin_unlock_irqrestore(&priv->lock, flags);
  5897. mutex_lock(&priv->mutex);
  5898. if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
  5899. iwl3945_activate_qos(priv, 1);
  5900. else if (priv->assoc_id && iwl3945_is_associated(priv))
  5901. iwl3945_activate_qos(priv, 0);
  5902. mutex_unlock(&priv->mutex);
  5903. IWL_DEBUG_MAC80211("leave\n");
  5904. return 0;
  5905. }
  5906. static int iwl3945_mac_get_tx_stats(struct ieee80211_hw *hw,
  5907. struct ieee80211_tx_queue_stats *stats)
  5908. {
  5909. struct iwl3945_priv *priv = hw->priv;
  5910. int i, avail;
  5911. struct iwl3945_tx_queue *txq;
  5912. struct iwl3945_queue *q;
  5913. unsigned long flags;
  5914. IWL_DEBUG_MAC80211("enter\n");
  5915. if (!iwl3945_is_ready_rf(priv)) {
  5916. IWL_DEBUG_MAC80211("leave - RF not ready\n");
  5917. return -EIO;
  5918. }
  5919. spin_lock_irqsave(&priv->lock, flags);
  5920. for (i = 0; i < AC_NUM; i++) {
  5921. txq = &priv->txq[i];
  5922. q = &txq->q;
  5923. avail = iwl3945_queue_space(q);
  5924. stats[i].len = q->n_window - avail;
  5925. stats[i].limit = q->n_window - q->high_mark;
  5926. stats[i].count = q->n_window;
  5927. }
  5928. spin_unlock_irqrestore(&priv->lock, flags);
  5929. IWL_DEBUG_MAC80211("leave\n");
  5930. return 0;
  5931. }
  5932. static int iwl3945_mac_get_stats(struct ieee80211_hw *hw,
  5933. struct ieee80211_low_level_stats *stats)
  5934. {
  5935. IWL_DEBUG_MAC80211("enter\n");
  5936. IWL_DEBUG_MAC80211("leave\n");
  5937. return 0;
  5938. }
  5939. static u64 iwl3945_mac_get_tsf(struct ieee80211_hw *hw)
  5940. {
  5941. IWL_DEBUG_MAC80211("enter\n");
  5942. IWL_DEBUG_MAC80211("leave\n");
  5943. return 0;
  5944. }
  5945. static void iwl3945_mac_reset_tsf(struct ieee80211_hw *hw)
  5946. {
  5947. struct iwl3945_priv *priv = hw->priv;
  5948. unsigned long flags;
  5949. mutex_lock(&priv->mutex);
  5950. IWL_DEBUG_MAC80211("enter\n");
  5951. iwl3945_reset_qos(priv);
  5952. cancel_delayed_work(&priv->post_associate);
  5953. spin_lock_irqsave(&priv->lock, flags);
  5954. priv->assoc_id = 0;
  5955. priv->assoc_capability = 0;
  5956. priv->call_post_assoc_from_beacon = 0;
  5957. /* new association get rid of ibss beacon skb */
  5958. if (priv->ibss_beacon)
  5959. dev_kfree_skb(priv->ibss_beacon);
  5960. priv->ibss_beacon = NULL;
  5961. priv->beacon_int = priv->hw->conf.beacon_int;
  5962. priv->timestamp1 = 0;
  5963. priv->timestamp0 = 0;
  5964. if ((priv->iw_mode == IEEE80211_IF_TYPE_STA))
  5965. priv->beacon_int = 0;
  5966. spin_unlock_irqrestore(&priv->lock, flags);
  5967. if (!iwl3945_is_ready_rf(priv)) {
  5968. IWL_DEBUG_MAC80211("leave - not ready\n");
  5969. mutex_unlock(&priv->mutex);
  5970. return;
  5971. }
  5972. /* we are restarting association process
  5973. * clear RXON_FILTER_ASSOC_MSK bit
  5974. */
  5975. if (priv->iw_mode != IEEE80211_IF_TYPE_AP) {
  5976. iwl3945_scan_cancel_timeout(priv, 100);
  5977. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  5978. iwl3945_commit_rxon(priv);
  5979. }
  5980. /* Per mac80211.h: This is only used in IBSS mode... */
  5981. if (priv->iw_mode != IEEE80211_IF_TYPE_IBSS) {
  5982. IWL_DEBUG_MAC80211("leave - not in IBSS\n");
  5983. mutex_unlock(&priv->mutex);
  5984. return;
  5985. }
  5986. iwl3945_set_rate(priv);
  5987. mutex_unlock(&priv->mutex);
  5988. IWL_DEBUG_MAC80211("leave\n");
  5989. }
  5990. static int iwl3945_mac_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb)
  5991. {
  5992. struct iwl3945_priv *priv = hw->priv;
  5993. unsigned long flags;
  5994. mutex_lock(&priv->mutex);
  5995. IWL_DEBUG_MAC80211("enter\n");
  5996. if (!iwl3945_is_ready_rf(priv)) {
  5997. IWL_DEBUG_MAC80211("leave - RF not ready\n");
  5998. mutex_unlock(&priv->mutex);
  5999. return -EIO;
  6000. }
  6001. if (priv->iw_mode != IEEE80211_IF_TYPE_IBSS) {
  6002. IWL_DEBUG_MAC80211("leave - not IBSS\n");
  6003. mutex_unlock(&priv->mutex);
  6004. return -EIO;
  6005. }
  6006. spin_lock_irqsave(&priv->lock, flags);
  6007. if (priv->ibss_beacon)
  6008. dev_kfree_skb(priv->ibss_beacon);
  6009. priv->ibss_beacon = skb;
  6010. priv->assoc_id = 0;
  6011. IWL_DEBUG_MAC80211("leave\n");
  6012. spin_unlock_irqrestore(&priv->lock, flags);
  6013. iwl3945_reset_qos(priv);
  6014. queue_work(priv->workqueue, &priv->post_associate.work);
  6015. mutex_unlock(&priv->mutex);
  6016. return 0;
  6017. }
  6018. /*****************************************************************************
  6019. *
  6020. * sysfs attributes
  6021. *
  6022. *****************************************************************************/
  6023. #ifdef CONFIG_IWL3945_DEBUG
  6024. /*
  6025. * The following adds a new attribute to the sysfs representation
  6026. * of this device driver (i.e. a new file in /sys/bus/pci/drivers/iwl/)
  6027. * used for controlling the debug level.
  6028. *
  6029. * See the level definitions in iwl for details.
  6030. */
  6031. static ssize_t show_debug_level(struct device_driver *d, char *buf)
  6032. {
  6033. return sprintf(buf, "0x%08X\n", iwl3945_debug_level);
  6034. }
  6035. static ssize_t store_debug_level(struct device_driver *d,
  6036. const char *buf, size_t count)
  6037. {
  6038. char *p = (char *)buf;
  6039. u32 val;
  6040. val = simple_strtoul(p, &p, 0);
  6041. if (p == buf)
  6042. printk(KERN_INFO DRV_NAME
  6043. ": %s is not in hex or decimal form.\n", buf);
  6044. else
  6045. iwl3945_debug_level = val;
  6046. return strnlen(buf, count);
  6047. }
  6048. static DRIVER_ATTR(debug_level, S_IWUSR | S_IRUGO,
  6049. show_debug_level, store_debug_level);
  6050. #endif /* CONFIG_IWL3945_DEBUG */
  6051. static ssize_t show_temperature(struct device *d,
  6052. struct device_attribute *attr, char *buf)
  6053. {
  6054. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6055. if (!iwl3945_is_alive(priv))
  6056. return -EAGAIN;
  6057. return sprintf(buf, "%d\n", iwl3945_hw_get_temperature(priv));
  6058. }
  6059. static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
  6060. static ssize_t show_rs_window(struct device *d,
  6061. struct device_attribute *attr,
  6062. char *buf)
  6063. {
  6064. struct iwl3945_priv *priv = d->driver_data;
  6065. return iwl3945_fill_rs_info(priv->hw, buf, IWL_AP_ID);
  6066. }
  6067. static DEVICE_ATTR(rs_window, S_IRUGO, show_rs_window, NULL);
  6068. static ssize_t show_tx_power(struct device *d,
  6069. struct device_attribute *attr, char *buf)
  6070. {
  6071. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6072. return sprintf(buf, "%d\n", priv->user_txpower_limit);
  6073. }
  6074. static ssize_t store_tx_power(struct device *d,
  6075. struct device_attribute *attr,
  6076. const char *buf, size_t count)
  6077. {
  6078. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6079. char *p = (char *)buf;
  6080. u32 val;
  6081. val = simple_strtoul(p, &p, 10);
  6082. if (p == buf)
  6083. printk(KERN_INFO DRV_NAME
  6084. ": %s is not in decimal form.\n", buf);
  6085. else
  6086. iwl3945_hw_reg_set_txpower(priv, val);
  6087. return count;
  6088. }
  6089. static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
  6090. static ssize_t show_flags(struct device *d,
  6091. struct device_attribute *attr, char *buf)
  6092. {
  6093. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6094. return sprintf(buf, "0x%04X\n", priv->active_rxon.flags);
  6095. }
  6096. static ssize_t store_flags(struct device *d,
  6097. struct device_attribute *attr,
  6098. const char *buf, size_t count)
  6099. {
  6100. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6101. u32 flags = simple_strtoul(buf, NULL, 0);
  6102. mutex_lock(&priv->mutex);
  6103. if (le32_to_cpu(priv->staging_rxon.flags) != flags) {
  6104. /* Cancel any currently running scans... */
  6105. if (iwl3945_scan_cancel_timeout(priv, 100))
  6106. IWL_WARNING("Could not cancel scan.\n");
  6107. else {
  6108. IWL_DEBUG_INFO("Committing rxon.flags = 0x%04X\n",
  6109. flags);
  6110. priv->staging_rxon.flags = cpu_to_le32(flags);
  6111. iwl3945_commit_rxon(priv);
  6112. }
  6113. }
  6114. mutex_unlock(&priv->mutex);
  6115. return count;
  6116. }
  6117. static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags);
  6118. static ssize_t show_filter_flags(struct device *d,
  6119. struct device_attribute *attr, char *buf)
  6120. {
  6121. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6122. return sprintf(buf, "0x%04X\n",
  6123. le32_to_cpu(priv->active_rxon.filter_flags));
  6124. }
  6125. static ssize_t store_filter_flags(struct device *d,
  6126. struct device_attribute *attr,
  6127. const char *buf, size_t count)
  6128. {
  6129. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6130. u32 filter_flags = simple_strtoul(buf, NULL, 0);
  6131. mutex_lock(&priv->mutex);
  6132. if (le32_to_cpu(priv->staging_rxon.filter_flags) != filter_flags) {
  6133. /* Cancel any currently running scans... */
  6134. if (iwl3945_scan_cancel_timeout(priv, 100))
  6135. IWL_WARNING("Could not cancel scan.\n");
  6136. else {
  6137. IWL_DEBUG_INFO("Committing rxon.filter_flags = "
  6138. "0x%04X\n", filter_flags);
  6139. priv->staging_rxon.filter_flags =
  6140. cpu_to_le32(filter_flags);
  6141. iwl3945_commit_rxon(priv);
  6142. }
  6143. }
  6144. mutex_unlock(&priv->mutex);
  6145. return count;
  6146. }
  6147. static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags,
  6148. store_filter_flags);
  6149. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  6150. static ssize_t show_measurement(struct device *d,
  6151. struct device_attribute *attr, char *buf)
  6152. {
  6153. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6154. struct iwl3945_spectrum_notification measure_report;
  6155. u32 size = sizeof(measure_report), len = 0, ofs = 0;
  6156. u8 *data = (u8 *)&measure_report;
  6157. unsigned long flags;
  6158. spin_lock_irqsave(&priv->lock, flags);
  6159. if (!(priv->measurement_status & MEASUREMENT_READY)) {
  6160. spin_unlock_irqrestore(&priv->lock, flags);
  6161. return 0;
  6162. }
  6163. memcpy(&measure_report, &priv->measure_report, size);
  6164. priv->measurement_status = 0;
  6165. spin_unlock_irqrestore(&priv->lock, flags);
  6166. while (size && (PAGE_SIZE - len)) {
  6167. hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
  6168. PAGE_SIZE - len, 1);
  6169. len = strlen(buf);
  6170. if (PAGE_SIZE - len)
  6171. buf[len++] = '\n';
  6172. ofs += 16;
  6173. size -= min(size, 16U);
  6174. }
  6175. return len;
  6176. }
  6177. static ssize_t store_measurement(struct device *d,
  6178. struct device_attribute *attr,
  6179. const char *buf, size_t count)
  6180. {
  6181. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6182. struct ieee80211_measurement_params params = {
  6183. .channel = le16_to_cpu(priv->active_rxon.channel),
  6184. .start_time = cpu_to_le64(priv->last_tsf),
  6185. .duration = cpu_to_le16(1),
  6186. };
  6187. u8 type = IWL_MEASURE_BASIC;
  6188. u8 buffer[32];
  6189. u8 channel;
  6190. if (count) {
  6191. char *p = buffer;
  6192. strncpy(buffer, buf, min(sizeof(buffer), count));
  6193. channel = simple_strtoul(p, NULL, 0);
  6194. if (channel)
  6195. params.channel = channel;
  6196. p = buffer;
  6197. while (*p && *p != ' ')
  6198. p++;
  6199. if (*p)
  6200. type = simple_strtoul(p + 1, NULL, 0);
  6201. }
  6202. IWL_DEBUG_INFO("Invoking measurement of type %d on "
  6203. "channel %d (for '%s')\n", type, params.channel, buf);
  6204. iwl3945_get_measurement(priv, &params, type);
  6205. return count;
  6206. }
  6207. static DEVICE_ATTR(measurement, S_IRUSR | S_IWUSR,
  6208. show_measurement, store_measurement);
  6209. #endif /* CONFIG_IWL3945_SPECTRUM_MEASUREMENT */
  6210. static ssize_t store_retry_rate(struct device *d,
  6211. struct device_attribute *attr,
  6212. const char *buf, size_t count)
  6213. {
  6214. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6215. priv->retry_rate = simple_strtoul(buf, NULL, 0);
  6216. if (priv->retry_rate <= 0)
  6217. priv->retry_rate = 1;
  6218. return count;
  6219. }
  6220. static ssize_t show_retry_rate(struct device *d,
  6221. struct device_attribute *attr, char *buf)
  6222. {
  6223. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6224. return sprintf(buf, "%d", priv->retry_rate);
  6225. }
  6226. static DEVICE_ATTR(retry_rate, S_IWUSR | S_IRUSR, show_retry_rate,
  6227. store_retry_rate);
  6228. static ssize_t store_power_level(struct device *d,
  6229. struct device_attribute *attr,
  6230. const char *buf, size_t count)
  6231. {
  6232. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6233. int rc;
  6234. int mode;
  6235. mode = simple_strtoul(buf, NULL, 0);
  6236. mutex_lock(&priv->mutex);
  6237. if (!iwl3945_is_ready(priv)) {
  6238. rc = -EAGAIN;
  6239. goto out;
  6240. }
  6241. if ((mode < 1) || (mode > IWL_POWER_LIMIT) || (mode == IWL_POWER_AC))
  6242. mode = IWL_POWER_AC;
  6243. else
  6244. mode |= IWL_POWER_ENABLED;
  6245. if (mode != priv->power_mode) {
  6246. rc = iwl3945_send_power_mode(priv, IWL_POWER_LEVEL(mode));
  6247. if (rc) {
  6248. IWL_DEBUG_MAC80211("failed setting power mode.\n");
  6249. goto out;
  6250. }
  6251. priv->power_mode = mode;
  6252. }
  6253. rc = count;
  6254. out:
  6255. mutex_unlock(&priv->mutex);
  6256. return rc;
  6257. }
  6258. #define MAX_WX_STRING 80
  6259. /* Values are in microsecond */
  6260. static const s32 timeout_duration[] = {
  6261. 350000,
  6262. 250000,
  6263. 75000,
  6264. 37000,
  6265. 25000,
  6266. };
  6267. static const s32 period_duration[] = {
  6268. 400000,
  6269. 700000,
  6270. 1000000,
  6271. 1000000,
  6272. 1000000
  6273. };
  6274. static ssize_t show_power_level(struct device *d,
  6275. struct device_attribute *attr, char *buf)
  6276. {
  6277. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6278. int level = IWL_POWER_LEVEL(priv->power_mode);
  6279. char *p = buf;
  6280. p += sprintf(p, "%d ", level);
  6281. switch (level) {
  6282. case IWL_POWER_MODE_CAM:
  6283. case IWL_POWER_AC:
  6284. p += sprintf(p, "(AC)");
  6285. break;
  6286. case IWL_POWER_BATTERY:
  6287. p += sprintf(p, "(BATTERY)");
  6288. break;
  6289. default:
  6290. p += sprintf(p,
  6291. "(Timeout %dms, Period %dms)",
  6292. timeout_duration[level - 1] / 1000,
  6293. period_duration[level - 1] / 1000);
  6294. }
  6295. if (!(priv->power_mode & IWL_POWER_ENABLED))
  6296. p += sprintf(p, " OFF\n");
  6297. else
  6298. p += sprintf(p, " \n");
  6299. return p - buf + 1;
  6300. }
  6301. static DEVICE_ATTR(power_level, S_IWUSR | S_IRUSR, show_power_level,
  6302. store_power_level);
  6303. static ssize_t show_channels(struct device *d,
  6304. struct device_attribute *attr, char *buf)
  6305. {
  6306. /* all this shit doesn't belong into sysfs anyway */
  6307. return 0;
  6308. }
  6309. static DEVICE_ATTR(channels, S_IRUSR, show_channels, NULL);
  6310. static ssize_t show_statistics(struct device *d,
  6311. struct device_attribute *attr, char *buf)
  6312. {
  6313. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6314. u32 size = sizeof(struct iwl3945_notif_statistics);
  6315. u32 len = 0, ofs = 0;
  6316. u8 *data = (u8 *)&priv->statistics;
  6317. int rc = 0;
  6318. if (!iwl3945_is_alive(priv))
  6319. return -EAGAIN;
  6320. mutex_lock(&priv->mutex);
  6321. rc = iwl3945_send_statistics_request(priv);
  6322. mutex_unlock(&priv->mutex);
  6323. if (rc) {
  6324. len = sprintf(buf,
  6325. "Error sending statistics request: 0x%08X\n", rc);
  6326. return len;
  6327. }
  6328. while (size && (PAGE_SIZE - len)) {
  6329. hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
  6330. PAGE_SIZE - len, 1);
  6331. len = strlen(buf);
  6332. if (PAGE_SIZE - len)
  6333. buf[len++] = '\n';
  6334. ofs += 16;
  6335. size -= min(size, 16U);
  6336. }
  6337. return len;
  6338. }
  6339. static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL);
  6340. static ssize_t show_antenna(struct device *d,
  6341. struct device_attribute *attr, char *buf)
  6342. {
  6343. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6344. if (!iwl3945_is_alive(priv))
  6345. return -EAGAIN;
  6346. return sprintf(buf, "%d\n", priv->antenna);
  6347. }
  6348. static ssize_t store_antenna(struct device *d,
  6349. struct device_attribute *attr,
  6350. const char *buf, size_t count)
  6351. {
  6352. int ant;
  6353. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6354. if (count == 0)
  6355. return 0;
  6356. if (sscanf(buf, "%1i", &ant) != 1) {
  6357. IWL_DEBUG_INFO("not in hex or decimal form.\n");
  6358. return count;
  6359. }
  6360. if ((ant >= 0) && (ant <= 2)) {
  6361. IWL_DEBUG_INFO("Setting antenna select to %d.\n", ant);
  6362. priv->antenna = (enum iwl3945_antenna)ant;
  6363. } else
  6364. IWL_DEBUG_INFO("Bad antenna select value %d.\n", ant);
  6365. return count;
  6366. }
  6367. static DEVICE_ATTR(antenna, S_IWUSR | S_IRUGO, show_antenna, store_antenna);
  6368. static ssize_t show_status(struct device *d,
  6369. struct device_attribute *attr, char *buf)
  6370. {
  6371. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6372. if (!iwl3945_is_alive(priv))
  6373. return -EAGAIN;
  6374. return sprintf(buf, "0x%08x\n", (int)priv->status);
  6375. }
  6376. static DEVICE_ATTR(status, S_IRUGO, show_status, NULL);
  6377. static ssize_t dump_error_log(struct device *d,
  6378. struct device_attribute *attr,
  6379. const char *buf, size_t count)
  6380. {
  6381. char *p = (char *)buf;
  6382. if (p[0] == '1')
  6383. iwl3945_dump_nic_error_log((struct iwl3945_priv *)d->driver_data);
  6384. return strnlen(buf, count);
  6385. }
  6386. static DEVICE_ATTR(dump_errors, S_IWUSR, NULL, dump_error_log);
  6387. static ssize_t dump_event_log(struct device *d,
  6388. struct device_attribute *attr,
  6389. const char *buf, size_t count)
  6390. {
  6391. char *p = (char *)buf;
  6392. if (p[0] == '1')
  6393. iwl3945_dump_nic_event_log((struct iwl3945_priv *)d->driver_data);
  6394. return strnlen(buf, count);
  6395. }
  6396. static DEVICE_ATTR(dump_events, S_IWUSR, NULL, dump_event_log);
  6397. /*****************************************************************************
  6398. *
  6399. * driver setup and teardown
  6400. *
  6401. *****************************************************************************/
  6402. static void iwl3945_setup_deferred_work(struct iwl3945_priv *priv)
  6403. {
  6404. priv->workqueue = create_workqueue(DRV_NAME);
  6405. init_waitqueue_head(&priv->wait_command_queue);
  6406. INIT_WORK(&priv->up, iwl3945_bg_up);
  6407. INIT_WORK(&priv->restart, iwl3945_bg_restart);
  6408. INIT_WORK(&priv->rx_replenish, iwl3945_bg_rx_replenish);
  6409. INIT_WORK(&priv->scan_completed, iwl3945_bg_scan_completed);
  6410. INIT_WORK(&priv->request_scan, iwl3945_bg_request_scan);
  6411. INIT_WORK(&priv->abort_scan, iwl3945_bg_abort_scan);
  6412. INIT_WORK(&priv->rf_kill, iwl3945_bg_rf_kill);
  6413. INIT_WORK(&priv->beacon_update, iwl3945_bg_beacon_update);
  6414. INIT_WORK(&priv->set_monitor, iwl3945_bg_set_monitor);
  6415. INIT_DELAYED_WORK(&priv->post_associate, iwl3945_bg_post_associate);
  6416. INIT_DELAYED_WORK(&priv->init_alive_start, iwl3945_bg_init_alive_start);
  6417. INIT_DELAYED_WORK(&priv->alive_start, iwl3945_bg_alive_start);
  6418. INIT_DELAYED_WORK(&priv->scan_check, iwl3945_bg_scan_check);
  6419. iwl3945_hw_setup_deferred_work(priv);
  6420. tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
  6421. iwl3945_irq_tasklet, (unsigned long)priv);
  6422. }
  6423. static void iwl3945_cancel_deferred_work(struct iwl3945_priv *priv)
  6424. {
  6425. iwl3945_hw_cancel_deferred_work(priv);
  6426. cancel_delayed_work_sync(&priv->init_alive_start);
  6427. cancel_delayed_work(&priv->scan_check);
  6428. cancel_delayed_work(&priv->alive_start);
  6429. cancel_delayed_work(&priv->post_associate);
  6430. cancel_work_sync(&priv->beacon_update);
  6431. }
  6432. static struct attribute *iwl3945_sysfs_entries[] = {
  6433. &dev_attr_antenna.attr,
  6434. &dev_attr_channels.attr,
  6435. &dev_attr_dump_errors.attr,
  6436. &dev_attr_dump_events.attr,
  6437. &dev_attr_flags.attr,
  6438. &dev_attr_filter_flags.attr,
  6439. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  6440. &dev_attr_measurement.attr,
  6441. #endif
  6442. &dev_attr_power_level.attr,
  6443. &dev_attr_retry_rate.attr,
  6444. &dev_attr_rs_window.attr,
  6445. &dev_attr_statistics.attr,
  6446. &dev_attr_status.attr,
  6447. &dev_attr_temperature.attr,
  6448. &dev_attr_tx_power.attr,
  6449. NULL
  6450. };
  6451. static struct attribute_group iwl3945_attribute_group = {
  6452. .name = NULL, /* put in device directory */
  6453. .attrs = iwl3945_sysfs_entries,
  6454. };
  6455. static struct ieee80211_ops iwl3945_hw_ops = {
  6456. .tx = iwl3945_mac_tx,
  6457. .start = iwl3945_mac_start,
  6458. .stop = iwl3945_mac_stop,
  6459. .add_interface = iwl3945_mac_add_interface,
  6460. .remove_interface = iwl3945_mac_remove_interface,
  6461. .config = iwl3945_mac_config,
  6462. .config_interface = iwl3945_mac_config_interface,
  6463. .configure_filter = iwl3945_configure_filter,
  6464. .set_key = iwl3945_mac_set_key,
  6465. .get_stats = iwl3945_mac_get_stats,
  6466. .get_tx_stats = iwl3945_mac_get_tx_stats,
  6467. .conf_tx = iwl3945_mac_conf_tx,
  6468. .get_tsf = iwl3945_mac_get_tsf,
  6469. .reset_tsf = iwl3945_mac_reset_tsf,
  6470. .hw_scan = iwl3945_mac_hw_scan
  6471. };
  6472. static int iwl3945_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  6473. {
  6474. int err = 0;
  6475. struct iwl3945_priv *priv;
  6476. struct ieee80211_hw *hw;
  6477. struct iwl_3945_cfg *cfg = (struct iwl_3945_cfg *)(ent->driver_data);
  6478. unsigned long flags;
  6479. DECLARE_MAC_BUF(mac);
  6480. /* Disabling hardware scan means that mac80211 will perform scans
  6481. * "the hard way", rather than using device's scan. */
  6482. if (iwl3945_param_disable_hw_scan) {
  6483. IWL_DEBUG_INFO("Disabling hw_scan\n");
  6484. iwl3945_hw_ops.hw_scan = NULL;
  6485. }
  6486. if ((iwl3945_param_queues_num > IWL39_MAX_NUM_QUEUES) ||
  6487. (iwl3945_param_queues_num < IWL_MIN_NUM_QUEUES)) {
  6488. IWL_ERROR("invalid queues_num, should be between %d and %d\n",
  6489. IWL_MIN_NUM_QUEUES, IWL39_MAX_NUM_QUEUES);
  6490. err = -EINVAL;
  6491. goto out;
  6492. }
  6493. /* mac80211 allocates memory for this device instance, including
  6494. * space for this driver's private structure */
  6495. hw = ieee80211_alloc_hw(sizeof(struct iwl3945_priv), &iwl3945_hw_ops);
  6496. if (hw == NULL) {
  6497. IWL_ERROR("Can not allocate network device\n");
  6498. err = -ENOMEM;
  6499. goto out;
  6500. }
  6501. SET_IEEE80211_DEV(hw, &pdev->dev);
  6502. hw->rate_control_algorithm = "iwl-3945-rs";
  6503. IWL_DEBUG_INFO("*** LOAD DRIVER ***\n");
  6504. priv = hw->priv;
  6505. priv->hw = hw;
  6506. priv->pci_dev = pdev;
  6507. priv->cfg = cfg;
  6508. /* Select antenna (may be helpful if only one antenna is connected) */
  6509. priv->antenna = (enum iwl3945_antenna)iwl3945_param_antenna;
  6510. #ifdef CONFIG_IWL3945_DEBUG
  6511. iwl3945_debug_level = iwl3945_param_debug;
  6512. atomic_set(&priv->restrict_refcnt, 0);
  6513. #endif
  6514. priv->retry_rate = 1;
  6515. priv->ibss_beacon = NULL;
  6516. /* Tell mac80211 our characteristics */
  6517. hw->flags = IEEE80211_HW_SIGNAL_DBM |
  6518. IEEE80211_HW_NOISE_DBM;
  6519. /* 4 EDCA QOS priorities */
  6520. hw->queues = 4;
  6521. spin_lock_init(&priv->lock);
  6522. spin_lock_init(&priv->power_data.lock);
  6523. spin_lock_init(&priv->sta_lock);
  6524. spin_lock_init(&priv->hcmd_lock);
  6525. INIT_LIST_HEAD(&priv->free_frames);
  6526. mutex_init(&priv->mutex);
  6527. if (pci_enable_device(pdev)) {
  6528. err = -ENODEV;
  6529. goto out_ieee80211_free_hw;
  6530. }
  6531. pci_set_master(pdev);
  6532. /* Clear the driver's (not device's) station table */
  6533. iwl3945_clear_stations_table(priv);
  6534. priv->data_retry_limit = -1;
  6535. priv->ieee_channels = NULL;
  6536. priv->ieee_rates = NULL;
  6537. priv->band = IEEE80211_BAND_2GHZ;
  6538. err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
  6539. if (!err)
  6540. err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
  6541. if (err) {
  6542. printk(KERN_WARNING DRV_NAME ": No suitable DMA available.\n");
  6543. goto out_pci_disable_device;
  6544. }
  6545. pci_set_drvdata(pdev, priv);
  6546. err = pci_request_regions(pdev, DRV_NAME);
  6547. if (err)
  6548. goto out_pci_disable_device;
  6549. /* We disable the RETRY_TIMEOUT register (0x41) to keep
  6550. * PCI Tx retries from interfering with C3 CPU state */
  6551. pci_write_config_byte(pdev, 0x41, 0x00);
  6552. priv->hw_base = pci_iomap(pdev, 0, 0);
  6553. if (!priv->hw_base) {
  6554. err = -ENODEV;
  6555. goto out_pci_release_regions;
  6556. }
  6557. IWL_DEBUG_INFO("pci_resource_len = 0x%08llx\n",
  6558. (unsigned long long) pci_resource_len(pdev, 0));
  6559. IWL_DEBUG_INFO("pci_resource_base = %p\n", priv->hw_base);
  6560. /* Initialize module parameter values here */
  6561. /* Disable radio (SW RF KILL) via parameter when loading driver */
  6562. if (iwl3945_param_disable) {
  6563. set_bit(STATUS_RF_KILL_SW, &priv->status);
  6564. IWL_DEBUG_INFO("Radio disabled.\n");
  6565. }
  6566. priv->iw_mode = IEEE80211_IF_TYPE_STA;
  6567. printk(KERN_INFO DRV_NAME
  6568. ": Detected Intel Wireless WiFi Link %s\n", priv->cfg->name);
  6569. /* Device-specific setup */
  6570. if (iwl3945_hw_set_hw_setting(priv)) {
  6571. IWL_ERROR("failed to set hw settings\n");
  6572. goto out_iounmap;
  6573. }
  6574. if (iwl3945_param_qos_enable)
  6575. priv->qos_data.qos_enable = 1;
  6576. iwl3945_reset_qos(priv);
  6577. priv->qos_data.qos_active = 0;
  6578. priv->qos_data.qos_cap.val = 0;
  6579. iwl3945_set_rxon_channel(priv, IEEE80211_BAND_2GHZ, 6);
  6580. iwl3945_setup_deferred_work(priv);
  6581. iwl3945_setup_rx_handlers(priv);
  6582. priv->rates_mask = IWL_RATES_MASK;
  6583. /* If power management is turned on, default to AC mode */
  6584. priv->power_mode = IWL_POWER_AC;
  6585. priv->user_txpower_limit = IWL_DEFAULT_TX_POWER;
  6586. spin_lock_irqsave(&priv->lock, flags);
  6587. iwl3945_disable_interrupts(priv);
  6588. spin_unlock_irqrestore(&priv->lock, flags);
  6589. err = sysfs_create_group(&pdev->dev.kobj, &iwl3945_attribute_group);
  6590. if (err) {
  6591. IWL_ERROR("failed to create sysfs device attributes\n");
  6592. goto out_release_irq;
  6593. }
  6594. /* nic init */
  6595. iwl3945_set_bit(priv, CSR_GIO_CHICKEN_BITS,
  6596. CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
  6597. iwl3945_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
  6598. err = iwl3945_poll_bit(priv, CSR_GP_CNTRL,
  6599. CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
  6600. CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
  6601. if (err < 0) {
  6602. IWL_DEBUG_INFO("Failed to init the card\n");
  6603. goto out_remove_sysfs;
  6604. }
  6605. /* Read the EEPROM */
  6606. err = iwl3945_eeprom_init(priv);
  6607. if (err) {
  6608. IWL_ERROR("Unable to init EEPROM\n");
  6609. goto out_remove_sysfs;
  6610. }
  6611. /* MAC Address location in EEPROM same for 3945/4965 */
  6612. get_eeprom_mac(priv, priv->mac_addr);
  6613. IWL_DEBUG_INFO("MAC address: %s\n", print_mac(mac, priv->mac_addr));
  6614. SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
  6615. err = iwl3945_init_channel_map(priv);
  6616. if (err) {
  6617. IWL_ERROR("initializing regulatory failed: %d\n", err);
  6618. goto out_remove_sysfs;
  6619. }
  6620. err = iwl3945_init_geos(priv);
  6621. if (err) {
  6622. IWL_ERROR("initializing geos failed: %d\n", err);
  6623. goto out_free_channel_map;
  6624. }
  6625. err = ieee80211_register_hw(priv->hw);
  6626. if (err) {
  6627. IWL_ERROR("Failed to register network device (error %d)\n", err);
  6628. goto out_free_geos;
  6629. }
  6630. priv->hw->conf.beacon_int = 100;
  6631. priv->mac80211_registered = 1;
  6632. pci_save_state(pdev);
  6633. pci_disable_device(pdev);
  6634. err = iwl3945_rfkill_init(priv);
  6635. if (err)
  6636. IWL_ERROR("Unable to initialize RFKILL system. "
  6637. "Ignoring error: %d\n", err);
  6638. return 0;
  6639. out_free_geos:
  6640. iwl3945_free_geos(priv);
  6641. out_free_channel_map:
  6642. iwl3945_free_channel_map(priv);
  6643. out_remove_sysfs:
  6644. sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
  6645. out_release_irq:
  6646. destroy_workqueue(priv->workqueue);
  6647. priv->workqueue = NULL;
  6648. iwl3945_unset_hw_setting(priv);
  6649. out_iounmap:
  6650. pci_iounmap(pdev, priv->hw_base);
  6651. out_pci_release_regions:
  6652. pci_release_regions(pdev);
  6653. out_pci_disable_device:
  6654. pci_disable_device(pdev);
  6655. pci_set_drvdata(pdev, NULL);
  6656. out_ieee80211_free_hw:
  6657. ieee80211_free_hw(priv->hw);
  6658. out:
  6659. return err;
  6660. }
  6661. static void __devexit iwl3945_pci_remove(struct pci_dev *pdev)
  6662. {
  6663. struct iwl3945_priv *priv = pci_get_drvdata(pdev);
  6664. unsigned long flags;
  6665. if (!priv)
  6666. return;
  6667. IWL_DEBUG_INFO("*** UNLOAD DRIVER ***\n");
  6668. set_bit(STATUS_EXIT_PENDING, &priv->status);
  6669. iwl3945_down(priv);
  6670. /* make sure we flush any pending irq or
  6671. * tasklet for the driver
  6672. */
  6673. spin_lock_irqsave(&priv->lock, flags);
  6674. iwl3945_disable_interrupts(priv);
  6675. spin_unlock_irqrestore(&priv->lock, flags);
  6676. iwl_synchronize_irq(priv);
  6677. sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
  6678. iwl3945_rfkill_unregister(priv);
  6679. iwl3945_dealloc_ucode_pci(priv);
  6680. if (priv->rxq.bd)
  6681. iwl3945_rx_queue_free(priv, &priv->rxq);
  6682. iwl3945_hw_txq_ctx_free(priv);
  6683. iwl3945_unset_hw_setting(priv);
  6684. iwl3945_clear_stations_table(priv);
  6685. if (priv->mac80211_registered)
  6686. ieee80211_unregister_hw(priv->hw);
  6687. /*netif_stop_queue(dev); */
  6688. flush_workqueue(priv->workqueue);
  6689. /* ieee80211_unregister_hw calls iwl3945_mac_stop, which flushes
  6690. * priv->workqueue... so we can't take down the workqueue
  6691. * until now... */
  6692. destroy_workqueue(priv->workqueue);
  6693. priv->workqueue = NULL;
  6694. pci_iounmap(pdev, priv->hw_base);
  6695. pci_release_regions(pdev);
  6696. pci_disable_device(pdev);
  6697. pci_set_drvdata(pdev, NULL);
  6698. iwl3945_free_channel_map(priv);
  6699. iwl3945_free_geos(priv);
  6700. kfree(priv->scan);
  6701. if (priv->ibss_beacon)
  6702. dev_kfree_skb(priv->ibss_beacon);
  6703. ieee80211_free_hw(priv->hw);
  6704. }
  6705. #ifdef CONFIG_PM
  6706. static int iwl3945_pci_suspend(struct pci_dev *pdev, pm_message_t state)
  6707. {
  6708. struct iwl3945_priv *priv = pci_get_drvdata(pdev);
  6709. if (priv->is_open) {
  6710. set_bit(STATUS_IN_SUSPEND, &priv->status);
  6711. iwl3945_mac_stop(priv->hw);
  6712. priv->is_open = 1;
  6713. }
  6714. pci_set_power_state(pdev, PCI_D3hot);
  6715. return 0;
  6716. }
  6717. static int iwl3945_pci_resume(struct pci_dev *pdev)
  6718. {
  6719. struct iwl3945_priv *priv = pci_get_drvdata(pdev);
  6720. pci_set_power_state(pdev, PCI_D0);
  6721. if (priv->is_open)
  6722. iwl3945_mac_start(priv->hw);
  6723. clear_bit(STATUS_IN_SUSPEND, &priv->status);
  6724. return 0;
  6725. }
  6726. #endif /* CONFIG_PM */
  6727. /*************** RFKILL FUNCTIONS **********/
  6728. #ifdef CONFIG_IWL3945_RFKILL
  6729. /* software rf-kill from user */
  6730. static int iwl3945_rfkill_soft_rf_kill(void *data, enum rfkill_state state)
  6731. {
  6732. struct iwl3945_priv *priv = data;
  6733. int err = 0;
  6734. if (!priv->rfkill)
  6735. return 0;
  6736. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  6737. return 0;
  6738. IWL_DEBUG_RF_KILL("we recieved soft RFKILL set to state %d\n", state);
  6739. mutex_lock(&priv->mutex);
  6740. switch (state) {
  6741. case RFKILL_STATE_UNBLOCKED:
  6742. if (iwl3945_is_rfkill_hw(priv)) {
  6743. err = -EBUSY;
  6744. goto out_unlock;
  6745. }
  6746. iwl3945_radio_kill_sw(priv, 0);
  6747. break;
  6748. case RFKILL_STATE_SOFT_BLOCKED:
  6749. iwl3945_radio_kill_sw(priv, 1);
  6750. break;
  6751. default:
  6752. IWL_WARNING("we recieved unexpected RFKILL state %d\n", state);
  6753. break;
  6754. }
  6755. out_unlock:
  6756. mutex_unlock(&priv->mutex);
  6757. return err;
  6758. }
  6759. int iwl3945_rfkill_init(struct iwl3945_priv *priv)
  6760. {
  6761. struct device *device = wiphy_dev(priv->hw->wiphy);
  6762. int ret = 0;
  6763. BUG_ON(device == NULL);
  6764. IWL_DEBUG_RF_KILL("Initializing RFKILL.\n");
  6765. priv->rfkill = rfkill_allocate(device, RFKILL_TYPE_WLAN);
  6766. if (!priv->rfkill) {
  6767. IWL_ERROR("Unable to allocate rfkill device.\n");
  6768. ret = -ENOMEM;
  6769. goto error;
  6770. }
  6771. priv->rfkill->name = priv->cfg->name;
  6772. priv->rfkill->data = priv;
  6773. priv->rfkill->state = RFKILL_STATE_UNBLOCKED;
  6774. priv->rfkill->toggle_radio = iwl3945_rfkill_soft_rf_kill;
  6775. priv->rfkill->user_claim_unsupported = 1;
  6776. priv->rfkill->dev.class->suspend = NULL;
  6777. priv->rfkill->dev.class->resume = NULL;
  6778. ret = rfkill_register(priv->rfkill);
  6779. if (ret) {
  6780. IWL_ERROR("Unable to register rfkill: %d\n", ret);
  6781. goto freed_rfkill;
  6782. }
  6783. IWL_DEBUG_RF_KILL("RFKILL initialization complete.\n");
  6784. return ret;
  6785. freed_rfkill:
  6786. if (priv->rfkill != NULL)
  6787. rfkill_free(priv->rfkill);
  6788. priv->rfkill = NULL;
  6789. error:
  6790. IWL_DEBUG_RF_KILL("RFKILL initialization complete.\n");
  6791. return ret;
  6792. }
  6793. void iwl3945_rfkill_unregister(struct iwl3945_priv *priv)
  6794. {
  6795. if (priv->rfkill)
  6796. rfkill_unregister(priv->rfkill);
  6797. priv->rfkill = NULL;
  6798. }
  6799. /* set rf-kill to the right state. */
  6800. void iwl3945_rfkill_set_hw_state(struct iwl3945_priv *priv)
  6801. {
  6802. if (!priv->rfkill)
  6803. return;
  6804. if (iwl3945_is_rfkill_hw(priv)) {
  6805. rfkill_force_state(priv->rfkill, RFKILL_STATE_HARD_BLOCKED);
  6806. return;
  6807. }
  6808. if (!iwl3945_is_rfkill_sw(priv))
  6809. rfkill_force_state(priv->rfkill, RFKILL_STATE_UNBLOCKED);
  6810. else
  6811. rfkill_force_state(priv->rfkill, RFKILL_STATE_SOFT_BLOCKED);
  6812. }
  6813. #endif
  6814. /*****************************************************************************
  6815. *
  6816. * driver and module entry point
  6817. *
  6818. *****************************************************************************/
  6819. static struct pci_driver iwl3945_driver = {
  6820. .name = DRV_NAME,
  6821. .id_table = iwl3945_hw_card_ids,
  6822. .probe = iwl3945_pci_probe,
  6823. .remove = __devexit_p(iwl3945_pci_remove),
  6824. #ifdef CONFIG_PM
  6825. .suspend = iwl3945_pci_suspend,
  6826. .resume = iwl3945_pci_resume,
  6827. #endif
  6828. };
  6829. static int __init iwl3945_init(void)
  6830. {
  6831. int ret;
  6832. printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
  6833. printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
  6834. ret = iwl3945_rate_control_register();
  6835. if (ret) {
  6836. IWL_ERROR("Unable to register rate control algorithm: %d\n", ret);
  6837. return ret;
  6838. }
  6839. ret = pci_register_driver(&iwl3945_driver);
  6840. if (ret) {
  6841. IWL_ERROR("Unable to initialize PCI module\n");
  6842. goto error_register;
  6843. }
  6844. #ifdef CONFIG_IWL3945_DEBUG
  6845. ret = driver_create_file(&iwl3945_driver.driver, &driver_attr_debug_level);
  6846. if (ret) {
  6847. IWL_ERROR("Unable to create driver sysfs file\n");
  6848. goto error_debug;
  6849. }
  6850. #endif
  6851. return ret;
  6852. #ifdef CONFIG_IWL3945_DEBUG
  6853. error_debug:
  6854. pci_unregister_driver(&iwl3945_driver);
  6855. #endif
  6856. error_register:
  6857. iwl3945_rate_control_unregister();
  6858. return ret;
  6859. }
  6860. static void __exit iwl3945_exit(void)
  6861. {
  6862. #ifdef CONFIG_IWL3945_DEBUG
  6863. driver_remove_file(&iwl3945_driver.driver, &driver_attr_debug_level);
  6864. #endif
  6865. pci_unregister_driver(&iwl3945_driver);
  6866. iwl3945_rate_control_unregister();
  6867. }
  6868. module_param_named(antenna, iwl3945_param_antenna, int, 0444);
  6869. MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
  6870. module_param_named(disable, iwl3945_param_disable, int, 0444);
  6871. MODULE_PARM_DESC(disable, "manually disable the radio (default 0 [radio on])");
  6872. module_param_named(hwcrypto, iwl3945_param_hwcrypto, int, 0444);
  6873. MODULE_PARM_DESC(hwcrypto,
  6874. "using hardware crypto engine (default 0 [software])\n");
  6875. module_param_named(debug, iwl3945_param_debug, int, 0444);
  6876. MODULE_PARM_DESC(debug, "debug output mask");
  6877. module_param_named(disable_hw_scan, iwl3945_param_disable_hw_scan, int, 0444);
  6878. MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
  6879. module_param_named(queues_num, iwl3945_param_queues_num, int, 0444);
  6880. MODULE_PARM_DESC(queues_num, "number of hw queues.");
  6881. /* QoS */
  6882. module_param_named(qos_enable, iwl3945_param_qos_enable, int, 0444);
  6883. MODULE_PARM_DESC(qos_enable, "enable all QoS functionality");
  6884. module_exit(iwl3945_exit);
  6885. module_init(iwl3945_init);