devs.c 39 KB

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  1. /* linux/arch/arm/plat-samsung/devs.c
  2. *
  3. * Copyright (c) 2011 Samsung Electronics Co., Ltd.
  4. * http://www.samsung.com
  5. *
  6. * Base SAMSUNG platform device definitions
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. */
  12. #include <linux/kernel.h>
  13. #include <linux/types.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/list.h>
  16. #include <linux/timer.h>
  17. #include <linux/init.h>
  18. #include <linux/serial_core.h>
  19. #include <linux/platform_device.h>
  20. #include <linux/io.h>
  21. #include <linux/slab.h>
  22. #include <linux/string.h>
  23. #include <linux/dma-mapping.h>
  24. #include <linux/fb.h>
  25. #include <linux/gfp.h>
  26. #include <linux/mtd/mtd.h>
  27. #include <linux/mtd/onenand.h>
  28. #include <linux/mtd/partitions.h>
  29. #include <linux/mmc/host.h>
  30. #include <linux/ioport.h>
  31. #include <linux/platform_data/s3c-hsudc.h>
  32. #include <linux/platform_data/s3c-hsotg.h>
  33. #include <media/s5p_hdmi.h>
  34. #include <asm/irq.h>
  35. #include <asm/mach/arch.h>
  36. #include <asm/mach/map.h>
  37. #include <asm/mach/irq.h>
  38. #include <mach/hardware.h>
  39. #include <mach/dma.h>
  40. #include <mach/irqs.h>
  41. #include <mach/map.h>
  42. #include <plat/cpu.h>
  43. #include <plat/devs.h>
  44. #include <plat/adc.h>
  45. #include <linux/platform_data/ata-samsung_cf.h>
  46. #include <linux/platform_data/usb-ehci-s5p.h>
  47. #include <plat/fb.h>
  48. #include <plat/fb-s3c2410.h>
  49. #include <plat/hdmi.h>
  50. #include <linux/platform_data/hwmon-s3c.h>
  51. #include <linux/platform_data/i2c-s3c2410.h>
  52. #include <plat/keypad.h>
  53. #include <linux/platform_data/mmc-s3cmci.h>
  54. #include <linux/platform_data/mtd-nand-s3c2410.h>
  55. #include <plat/sdhci.h>
  56. #include <linux/platform_data/touchscreen-s3c2410.h>
  57. #include <linux/platform_data/usb-s3c2410_udc.h>
  58. #include <linux/platform_data/usb-ohci-s3c2410.h>
  59. #include <plat/usb-phy.h>
  60. #include <plat/regs-serial.h>
  61. #include <plat/regs-spi.h>
  62. #include <linux/platform_data/spi-s3c64xx.h>
  63. static u64 samsung_device_dma_mask = DMA_BIT_MASK(32);
  64. /* AC97 */
  65. #ifdef CONFIG_CPU_S3C2440
  66. static struct resource s3c_ac97_resource[] = {
  67. [0] = DEFINE_RES_MEM(S3C2440_PA_AC97, S3C2440_SZ_AC97),
  68. [1] = DEFINE_RES_IRQ(IRQ_S3C244X_AC97),
  69. [2] = DEFINE_RES_DMA_NAMED(DMACH_PCM_OUT, "PCM out"),
  70. [3] = DEFINE_RES_DMA_NAMED(DMACH_PCM_IN, "PCM in"),
  71. [4] = DEFINE_RES_DMA_NAMED(DMACH_MIC_IN, "Mic in"),
  72. };
  73. struct platform_device s3c_device_ac97 = {
  74. .name = "samsung-ac97",
  75. .id = -1,
  76. .num_resources = ARRAY_SIZE(s3c_ac97_resource),
  77. .resource = s3c_ac97_resource,
  78. .dev = {
  79. .dma_mask = &samsung_device_dma_mask,
  80. .coherent_dma_mask = DMA_BIT_MASK(32),
  81. }
  82. };
  83. #endif /* CONFIG_CPU_S3C2440 */
  84. /* ADC */
  85. #ifdef CONFIG_PLAT_S3C24XX
  86. static struct resource s3c_adc_resource[] = {
  87. [0] = DEFINE_RES_MEM(S3C24XX_PA_ADC, S3C24XX_SZ_ADC),
  88. [1] = DEFINE_RES_IRQ(IRQ_TC),
  89. [2] = DEFINE_RES_IRQ(IRQ_ADC),
  90. };
  91. struct platform_device s3c_device_adc = {
  92. .name = "s3c24xx-adc",
  93. .id = -1,
  94. .num_resources = ARRAY_SIZE(s3c_adc_resource),
  95. .resource = s3c_adc_resource,
  96. };
  97. #endif /* CONFIG_PLAT_S3C24XX */
  98. #if defined(CONFIG_SAMSUNG_DEV_ADC)
  99. static struct resource s3c_adc_resource[] = {
  100. [0] = DEFINE_RES_MEM(SAMSUNG_PA_ADC, SZ_256),
  101. [1] = DEFINE_RES_IRQ(IRQ_TC),
  102. [2] = DEFINE_RES_IRQ(IRQ_ADC),
  103. };
  104. struct platform_device s3c_device_adc = {
  105. .name = "samsung-adc",
  106. .id = -1,
  107. .num_resources = ARRAY_SIZE(s3c_adc_resource),
  108. .resource = s3c_adc_resource,
  109. };
  110. #endif /* CONFIG_SAMSUNG_DEV_ADC */
  111. /* Camif Controller */
  112. #ifdef CONFIG_CPU_S3C2440
  113. static struct resource s3c_camif_resource[] = {
  114. [0] = DEFINE_RES_MEM(S3C2440_PA_CAMIF, S3C2440_SZ_CAMIF),
  115. [1] = DEFINE_RES_IRQ(IRQ_S3C2440_CAM_C),
  116. [2] = DEFINE_RES_IRQ(IRQ_S3C2440_CAM_P),
  117. };
  118. struct platform_device s3c_device_camif = {
  119. .name = "s3c2440-camif",
  120. .id = -1,
  121. .num_resources = ARRAY_SIZE(s3c_camif_resource),
  122. .resource = s3c_camif_resource,
  123. .dev = {
  124. .dma_mask = &samsung_device_dma_mask,
  125. .coherent_dma_mask = DMA_BIT_MASK(32),
  126. }
  127. };
  128. #endif /* CONFIG_CPU_S3C2440 */
  129. /* ASOC DMA */
  130. struct platform_device samsung_asoc_idma = {
  131. .name = "samsung-idma",
  132. .id = -1,
  133. .dev = {
  134. .dma_mask = &samsung_device_dma_mask,
  135. .coherent_dma_mask = DMA_BIT_MASK(32),
  136. }
  137. };
  138. /* FB */
  139. #ifdef CONFIG_S3C_DEV_FB
  140. static struct resource s3c_fb_resource[] = {
  141. [0] = DEFINE_RES_MEM(S3C_PA_FB, SZ_16K),
  142. [1] = DEFINE_RES_IRQ(IRQ_LCD_VSYNC),
  143. [2] = DEFINE_RES_IRQ(IRQ_LCD_FIFO),
  144. [3] = DEFINE_RES_IRQ(IRQ_LCD_SYSTEM),
  145. };
  146. struct platform_device s3c_device_fb = {
  147. .name = "s3c-fb",
  148. .id = -1,
  149. .num_resources = ARRAY_SIZE(s3c_fb_resource),
  150. .resource = s3c_fb_resource,
  151. .dev = {
  152. .dma_mask = &samsung_device_dma_mask,
  153. .coherent_dma_mask = DMA_BIT_MASK(32),
  154. },
  155. };
  156. void __init s3c_fb_set_platdata(struct s3c_fb_platdata *pd)
  157. {
  158. s3c_set_platdata(pd, sizeof(struct s3c_fb_platdata),
  159. &s3c_device_fb);
  160. }
  161. #endif /* CONFIG_S3C_DEV_FB */
  162. /* FIMC */
  163. #ifdef CONFIG_S5P_DEV_FIMC0
  164. static struct resource s5p_fimc0_resource[] = {
  165. [0] = DEFINE_RES_MEM(S5P_PA_FIMC0, SZ_4K),
  166. [1] = DEFINE_RES_IRQ(IRQ_FIMC0),
  167. };
  168. struct platform_device s5p_device_fimc0 = {
  169. .name = "s5p-fimc",
  170. .id = 0,
  171. .num_resources = ARRAY_SIZE(s5p_fimc0_resource),
  172. .resource = s5p_fimc0_resource,
  173. .dev = {
  174. .dma_mask = &samsung_device_dma_mask,
  175. .coherent_dma_mask = DMA_BIT_MASK(32),
  176. },
  177. };
  178. struct platform_device s5p_device_fimc_md = {
  179. .name = "s5p-fimc-md",
  180. .id = -1,
  181. };
  182. #endif /* CONFIG_S5P_DEV_FIMC0 */
  183. #ifdef CONFIG_S5P_DEV_FIMC1
  184. static struct resource s5p_fimc1_resource[] = {
  185. [0] = DEFINE_RES_MEM(S5P_PA_FIMC1, SZ_4K),
  186. [1] = DEFINE_RES_IRQ(IRQ_FIMC1),
  187. };
  188. struct platform_device s5p_device_fimc1 = {
  189. .name = "s5p-fimc",
  190. .id = 1,
  191. .num_resources = ARRAY_SIZE(s5p_fimc1_resource),
  192. .resource = s5p_fimc1_resource,
  193. .dev = {
  194. .dma_mask = &samsung_device_dma_mask,
  195. .coherent_dma_mask = DMA_BIT_MASK(32),
  196. },
  197. };
  198. #endif /* CONFIG_S5P_DEV_FIMC1 */
  199. #ifdef CONFIG_S5P_DEV_FIMC2
  200. static struct resource s5p_fimc2_resource[] = {
  201. [0] = DEFINE_RES_MEM(S5P_PA_FIMC2, SZ_4K),
  202. [1] = DEFINE_RES_IRQ(IRQ_FIMC2),
  203. };
  204. struct platform_device s5p_device_fimc2 = {
  205. .name = "s5p-fimc",
  206. .id = 2,
  207. .num_resources = ARRAY_SIZE(s5p_fimc2_resource),
  208. .resource = s5p_fimc2_resource,
  209. .dev = {
  210. .dma_mask = &samsung_device_dma_mask,
  211. .coherent_dma_mask = DMA_BIT_MASK(32),
  212. },
  213. };
  214. #endif /* CONFIG_S5P_DEV_FIMC2 */
  215. #ifdef CONFIG_S5P_DEV_FIMC3
  216. static struct resource s5p_fimc3_resource[] = {
  217. [0] = DEFINE_RES_MEM(S5P_PA_FIMC3, SZ_4K),
  218. [1] = DEFINE_RES_IRQ(IRQ_FIMC3),
  219. };
  220. struct platform_device s5p_device_fimc3 = {
  221. .name = "s5p-fimc",
  222. .id = 3,
  223. .num_resources = ARRAY_SIZE(s5p_fimc3_resource),
  224. .resource = s5p_fimc3_resource,
  225. .dev = {
  226. .dma_mask = &samsung_device_dma_mask,
  227. .coherent_dma_mask = DMA_BIT_MASK(32),
  228. },
  229. };
  230. #endif /* CONFIG_S5P_DEV_FIMC3 */
  231. /* G2D */
  232. #ifdef CONFIG_S5P_DEV_G2D
  233. static struct resource s5p_g2d_resource[] = {
  234. [0] = DEFINE_RES_MEM(S5P_PA_G2D, SZ_4K),
  235. [1] = DEFINE_RES_IRQ(IRQ_2D),
  236. };
  237. struct platform_device s5p_device_g2d = {
  238. .name = "s5p-g2d",
  239. .id = 0,
  240. .num_resources = ARRAY_SIZE(s5p_g2d_resource),
  241. .resource = s5p_g2d_resource,
  242. .dev = {
  243. .dma_mask = &samsung_device_dma_mask,
  244. .coherent_dma_mask = DMA_BIT_MASK(32),
  245. },
  246. };
  247. #endif /* CONFIG_S5P_DEV_G2D */
  248. #ifdef CONFIG_S5P_DEV_JPEG
  249. static struct resource s5p_jpeg_resource[] = {
  250. [0] = DEFINE_RES_MEM(S5P_PA_JPEG, SZ_4K),
  251. [1] = DEFINE_RES_IRQ(IRQ_JPEG),
  252. };
  253. struct platform_device s5p_device_jpeg = {
  254. .name = "s5p-jpeg",
  255. .id = 0,
  256. .num_resources = ARRAY_SIZE(s5p_jpeg_resource),
  257. .resource = s5p_jpeg_resource,
  258. .dev = {
  259. .dma_mask = &samsung_device_dma_mask,
  260. .coherent_dma_mask = DMA_BIT_MASK(32),
  261. },
  262. };
  263. #endif /* CONFIG_S5P_DEV_JPEG */
  264. /* FIMD0 */
  265. #ifdef CONFIG_S5P_DEV_FIMD0
  266. static struct resource s5p_fimd0_resource[] = {
  267. [0] = DEFINE_RES_MEM(S5P_PA_FIMD0, SZ_32K),
  268. [1] = DEFINE_RES_IRQ(IRQ_FIMD0_VSYNC),
  269. [2] = DEFINE_RES_IRQ(IRQ_FIMD0_FIFO),
  270. [3] = DEFINE_RES_IRQ(IRQ_FIMD0_SYSTEM),
  271. };
  272. struct platform_device s5p_device_fimd0 = {
  273. .name = "s5p-fb",
  274. .id = 0,
  275. .num_resources = ARRAY_SIZE(s5p_fimd0_resource),
  276. .resource = s5p_fimd0_resource,
  277. .dev = {
  278. .dma_mask = &samsung_device_dma_mask,
  279. .coherent_dma_mask = DMA_BIT_MASK(32),
  280. },
  281. };
  282. void __init s5p_fimd0_set_platdata(struct s3c_fb_platdata *pd)
  283. {
  284. s3c_set_platdata(pd, sizeof(struct s3c_fb_platdata),
  285. &s5p_device_fimd0);
  286. }
  287. #endif /* CONFIG_S5P_DEV_FIMD0 */
  288. /* HWMON */
  289. #ifdef CONFIG_S3C_DEV_HWMON
  290. struct platform_device s3c_device_hwmon = {
  291. .name = "s3c-hwmon",
  292. .id = -1,
  293. .dev.parent = &s3c_device_adc.dev,
  294. };
  295. void __init s3c_hwmon_set_platdata(struct s3c_hwmon_pdata *pd)
  296. {
  297. s3c_set_platdata(pd, sizeof(struct s3c_hwmon_pdata),
  298. &s3c_device_hwmon);
  299. }
  300. #endif /* CONFIG_S3C_DEV_HWMON */
  301. /* HSMMC */
  302. #ifdef CONFIG_S3C_DEV_HSMMC
  303. static struct resource s3c_hsmmc_resource[] = {
  304. [0] = DEFINE_RES_MEM(S3C_PA_HSMMC0, SZ_4K),
  305. [1] = DEFINE_RES_IRQ(IRQ_HSMMC0),
  306. };
  307. struct s3c_sdhci_platdata s3c_hsmmc0_def_platdata = {
  308. .max_width = 4,
  309. .host_caps = (MMC_CAP_4_BIT_DATA |
  310. MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
  311. };
  312. struct platform_device s3c_device_hsmmc0 = {
  313. .name = "s3c-sdhci",
  314. .id = 0,
  315. .num_resources = ARRAY_SIZE(s3c_hsmmc_resource),
  316. .resource = s3c_hsmmc_resource,
  317. .dev = {
  318. .dma_mask = &samsung_device_dma_mask,
  319. .coherent_dma_mask = DMA_BIT_MASK(32),
  320. .platform_data = &s3c_hsmmc0_def_platdata,
  321. },
  322. };
  323. void s3c_sdhci0_set_platdata(struct s3c_sdhci_platdata *pd)
  324. {
  325. s3c_sdhci_set_platdata(pd, &s3c_hsmmc0_def_platdata);
  326. }
  327. #endif /* CONFIG_S3C_DEV_HSMMC */
  328. #ifdef CONFIG_S3C_DEV_HSMMC1
  329. static struct resource s3c_hsmmc1_resource[] = {
  330. [0] = DEFINE_RES_MEM(S3C_PA_HSMMC1, SZ_4K),
  331. [1] = DEFINE_RES_IRQ(IRQ_HSMMC1),
  332. };
  333. struct s3c_sdhci_platdata s3c_hsmmc1_def_platdata = {
  334. .max_width = 4,
  335. .host_caps = (MMC_CAP_4_BIT_DATA |
  336. MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
  337. };
  338. struct platform_device s3c_device_hsmmc1 = {
  339. .name = "s3c-sdhci",
  340. .id = 1,
  341. .num_resources = ARRAY_SIZE(s3c_hsmmc1_resource),
  342. .resource = s3c_hsmmc1_resource,
  343. .dev = {
  344. .dma_mask = &samsung_device_dma_mask,
  345. .coherent_dma_mask = DMA_BIT_MASK(32),
  346. .platform_data = &s3c_hsmmc1_def_platdata,
  347. },
  348. };
  349. void s3c_sdhci1_set_platdata(struct s3c_sdhci_platdata *pd)
  350. {
  351. s3c_sdhci_set_platdata(pd, &s3c_hsmmc1_def_platdata);
  352. }
  353. #endif /* CONFIG_S3C_DEV_HSMMC1 */
  354. /* HSMMC2 */
  355. #ifdef CONFIG_S3C_DEV_HSMMC2
  356. static struct resource s3c_hsmmc2_resource[] = {
  357. [0] = DEFINE_RES_MEM(S3C_PA_HSMMC2, SZ_4K),
  358. [1] = DEFINE_RES_IRQ(IRQ_HSMMC2),
  359. };
  360. struct s3c_sdhci_platdata s3c_hsmmc2_def_platdata = {
  361. .max_width = 4,
  362. .host_caps = (MMC_CAP_4_BIT_DATA |
  363. MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
  364. };
  365. struct platform_device s3c_device_hsmmc2 = {
  366. .name = "s3c-sdhci",
  367. .id = 2,
  368. .num_resources = ARRAY_SIZE(s3c_hsmmc2_resource),
  369. .resource = s3c_hsmmc2_resource,
  370. .dev = {
  371. .dma_mask = &samsung_device_dma_mask,
  372. .coherent_dma_mask = DMA_BIT_MASK(32),
  373. .platform_data = &s3c_hsmmc2_def_platdata,
  374. },
  375. };
  376. void s3c_sdhci2_set_platdata(struct s3c_sdhci_platdata *pd)
  377. {
  378. s3c_sdhci_set_platdata(pd, &s3c_hsmmc2_def_platdata);
  379. }
  380. #endif /* CONFIG_S3C_DEV_HSMMC2 */
  381. #ifdef CONFIG_S3C_DEV_HSMMC3
  382. static struct resource s3c_hsmmc3_resource[] = {
  383. [0] = DEFINE_RES_MEM(S3C_PA_HSMMC3, SZ_4K),
  384. [1] = DEFINE_RES_IRQ(IRQ_HSMMC3),
  385. };
  386. struct s3c_sdhci_platdata s3c_hsmmc3_def_platdata = {
  387. .max_width = 4,
  388. .host_caps = (MMC_CAP_4_BIT_DATA |
  389. MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
  390. };
  391. struct platform_device s3c_device_hsmmc3 = {
  392. .name = "s3c-sdhci",
  393. .id = 3,
  394. .num_resources = ARRAY_SIZE(s3c_hsmmc3_resource),
  395. .resource = s3c_hsmmc3_resource,
  396. .dev = {
  397. .dma_mask = &samsung_device_dma_mask,
  398. .coherent_dma_mask = DMA_BIT_MASK(32),
  399. .platform_data = &s3c_hsmmc3_def_platdata,
  400. },
  401. };
  402. void s3c_sdhci3_set_platdata(struct s3c_sdhci_platdata *pd)
  403. {
  404. s3c_sdhci_set_platdata(pd, &s3c_hsmmc3_def_platdata);
  405. }
  406. #endif /* CONFIG_S3C_DEV_HSMMC3 */
  407. /* I2C */
  408. static struct resource s3c_i2c0_resource[] = {
  409. [0] = DEFINE_RES_MEM(S3C_PA_IIC, SZ_4K),
  410. [1] = DEFINE_RES_IRQ(IRQ_IIC),
  411. };
  412. struct platform_device s3c_device_i2c0 = {
  413. .name = "s3c2410-i2c",
  414. .id = 0,
  415. .num_resources = ARRAY_SIZE(s3c_i2c0_resource),
  416. .resource = s3c_i2c0_resource,
  417. };
  418. struct s3c2410_platform_i2c default_i2c_data __initdata = {
  419. .flags = 0,
  420. .slave_addr = 0x10,
  421. .frequency = 100*1000,
  422. .sda_delay = 100,
  423. };
  424. void __init s3c_i2c0_set_platdata(struct s3c2410_platform_i2c *pd)
  425. {
  426. struct s3c2410_platform_i2c *npd;
  427. if (!pd) {
  428. pd = &default_i2c_data;
  429. pd->bus_num = 0;
  430. }
  431. npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
  432. &s3c_device_i2c0);
  433. if (!npd->cfg_gpio)
  434. npd->cfg_gpio = s3c_i2c0_cfg_gpio;
  435. }
  436. #ifdef CONFIG_S3C_DEV_I2C1
  437. static struct resource s3c_i2c1_resource[] = {
  438. [0] = DEFINE_RES_MEM(S3C_PA_IIC1, SZ_4K),
  439. [1] = DEFINE_RES_IRQ(IRQ_IIC1),
  440. };
  441. struct platform_device s3c_device_i2c1 = {
  442. .name = "s3c2410-i2c",
  443. .id = 1,
  444. .num_resources = ARRAY_SIZE(s3c_i2c1_resource),
  445. .resource = s3c_i2c1_resource,
  446. };
  447. void __init s3c_i2c1_set_platdata(struct s3c2410_platform_i2c *pd)
  448. {
  449. struct s3c2410_platform_i2c *npd;
  450. if (!pd) {
  451. pd = &default_i2c_data;
  452. pd->bus_num = 1;
  453. }
  454. npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
  455. &s3c_device_i2c1);
  456. if (!npd->cfg_gpio)
  457. npd->cfg_gpio = s3c_i2c1_cfg_gpio;
  458. }
  459. #endif /* CONFIG_S3C_DEV_I2C1 */
  460. #ifdef CONFIG_S3C_DEV_I2C2
  461. static struct resource s3c_i2c2_resource[] = {
  462. [0] = DEFINE_RES_MEM(S3C_PA_IIC2, SZ_4K),
  463. [1] = DEFINE_RES_IRQ(IRQ_IIC2),
  464. };
  465. struct platform_device s3c_device_i2c2 = {
  466. .name = "s3c2410-i2c",
  467. .id = 2,
  468. .num_resources = ARRAY_SIZE(s3c_i2c2_resource),
  469. .resource = s3c_i2c2_resource,
  470. };
  471. void __init s3c_i2c2_set_platdata(struct s3c2410_platform_i2c *pd)
  472. {
  473. struct s3c2410_platform_i2c *npd;
  474. if (!pd) {
  475. pd = &default_i2c_data;
  476. pd->bus_num = 2;
  477. }
  478. npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
  479. &s3c_device_i2c2);
  480. if (!npd->cfg_gpio)
  481. npd->cfg_gpio = s3c_i2c2_cfg_gpio;
  482. }
  483. #endif /* CONFIG_S3C_DEV_I2C2 */
  484. #ifdef CONFIG_S3C_DEV_I2C3
  485. static struct resource s3c_i2c3_resource[] = {
  486. [0] = DEFINE_RES_MEM(S3C_PA_IIC3, SZ_4K),
  487. [1] = DEFINE_RES_IRQ(IRQ_IIC3),
  488. };
  489. struct platform_device s3c_device_i2c3 = {
  490. .name = "s3c2440-i2c",
  491. .id = 3,
  492. .num_resources = ARRAY_SIZE(s3c_i2c3_resource),
  493. .resource = s3c_i2c3_resource,
  494. };
  495. void __init s3c_i2c3_set_platdata(struct s3c2410_platform_i2c *pd)
  496. {
  497. struct s3c2410_platform_i2c *npd;
  498. if (!pd) {
  499. pd = &default_i2c_data;
  500. pd->bus_num = 3;
  501. }
  502. npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
  503. &s3c_device_i2c3);
  504. if (!npd->cfg_gpio)
  505. npd->cfg_gpio = s3c_i2c3_cfg_gpio;
  506. }
  507. #endif /*CONFIG_S3C_DEV_I2C3 */
  508. #ifdef CONFIG_S3C_DEV_I2C4
  509. static struct resource s3c_i2c4_resource[] = {
  510. [0] = DEFINE_RES_MEM(S3C_PA_IIC4, SZ_4K),
  511. [1] = DEFINE_RES_IRQ(IRQ_IIC4),
  512. };
  513. struct platform_device s3c_device_i2c4 = {
  514. .name = "s3c2440-i2c",
  515. .id = 4,
  516. .num_resources = ARRAY_SIZE(s3c_i2c4_resource),
  517. .resource = s3c_i2c4_resource,
  518. };
  519. void __init s3c_i2c4_set_platdata(struct s3c2410_platform_i2c *pd)
  520. {
  521. struct s3c2410_platform_i2c *npd;
  522. if (!pd) {
  523. pd = &default_i2c_data;
  524. pd->bus_num = 4;
  525. }
  526. npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
  527. &s3c_device_i2c4);
  528. if (!npd->cfg_gpio)
  529. npd->cfg_gpio = s3c_i2c4_cfg_gpio;
  530. }
  531. #endif /*CONFIG_S3C_DEV_I2C4 */
  532. #ifdef CONFIG_S3C_DEV_I2C5
  533. static struct resource s3c_i2c5_resource[] = {
  534. [0] = DEFINE_RES_MEM(S3C_PA_IIC5, SZ_4K),
  535. [1] = DEFINE_RES_IRQ(IRQ_IIC5),
  536. };
  537. struct platform_device s3c_device_i2c5 = {
  538. .name = "s3c2440-i2c",
  539. .id = 5,
  540. .num_resources = ARRAY_SIZE(s3c_i2c5_resource),
  541. .resource = s3c_i2c5_resource,
  542. };
  543. void __init s3c_i2c5_set_platdata(struct s3c2410_platform_i2c *pd)
  544. {
  545. struct s3c2410_platform_i2c *npd;
  546. if (!pd) {
  547. pd = &default_i2c_data;
  548. pd->bus_num = 5;
  549. }
  550. npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
  551. &s3c_device_i2c5);
  552. if (!npd->cfg_gpio)
  553. npd->cfg_gpio = s3c_i2c5_cfg_gpio;
  554. }
  555. #endif /*CONFIG_S3C_DEV_I2C5 */
  556. #ifdef CONFIG_S3C_DEV_I2C6
  557. static struct resource s3c_i2c6_resource[] = {
  558. [0] = DEFINE_RES_MEM(S3C_PA_IIC6, SZ_4K),
  559. [1] = DEFINE_RES_IRQ(IRQ_IIC6),
  560. };
  561. struct platform_device s3c_device_i2c6 = {
  562. .name = "s3c2440-i2c",
  563. .id = 6,
  564. .num_resources = ARRAY_SIZE(s3c_i2c6_resource),
  565. .resource = s3c_i2c6_resource,
  566. };
  567. void __init s3c_i2c6_set_platdata(struct s3c2410_platform_i2c *pd)
  568. {
  569. struct s3c2410_platform_i2c *npd;
  570. if (!pd) {
  571. pd = &default_i2c_data;
  572. pd->bus_num = 6;
  573. }
  574. npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
  575. &s3c_device_i2c6);
  576. if (!npd->cfg_gpio)
  577. npd->cfg_gpio = s3c_i2c6_cfg_gpio;
  578. }
  579. #endif /* CONFIG_S3C_DEV_I2C6 */
  580. #ifdef CONFIG_S3C_DEV_I2C7
  581. static struct resource s3c_i2c7_resource[] = {
  582. [0] = DEFINE_RES_MEM(S3C_PA_IIC7, SZ_4K),
  583. [1] = DEFINE_RES_IRQ(IRQ_IIC7),
  584. };
  585. struct platform_device s3c_device_i2c7 = {
  586. .name = "s3c2440-i2c",
  587. .id = 7,
  588. .num_resources = ARRAY_SIZE(s3c_i2c7_resource),
  589. .resource = s3c_i2c7_resource,
  590. };
  591. void __init s3c_i2c7_set_platdata(struct s3c2410_platform_i2c *pd)
  592. {
  593. struct s3c2410_platform_i2c *npd;
  594. if (!pd) {
  595. pd = &default_i2c_data;
  596. pd->bus_num = 7;
  597. }
  598. npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
  599. &s3c_device_i2c7);
  600. if (!npd->cfg_gpio)
  601. npd->cfg_gpio = s3c_i2c7_cfg_gpio;
  602. }
  603. #endif /* CONFIG_S3C_DEV_I2C7 */
  604. /* I2C HDMIPHY */
  605. #ifdef CONFIG_S5P_DEV_I2C_HDMIPHY
  606. static struct resource s5p_i2c_resource[] = {
  607. [0] = DEFINE_RES_MEM(S5P_PA_IIC_HDMIPHY, SZ_4K),
  608. [1] = DEFINE_RES_IRQ(IRQ_IIC_HDMIPHY),
  609. };
  610. struct platform_device s5p_device_i2c_hdmiphy = {
  611. .name = "s3c2440-hdmiphy-i2c",
  612. .id = -1,
  613. .num_resources = ARRAY_SIZE(s5p_i2c_resource),
  614. .resource = s5p_i2c_resource,
  615. };
  616. void __init s5p_i2c_hdmiphy_set_platdata(struct s3c2410_platform_i2c *pd)
  617. {
  618. struct s3c2410_platform_i2c *npd;
  619. if (!pd) {
  620. pd = &default_i2c_data;
  621. if (soc_is_exynos4210() ||
  622. soc_is_exynos4212() || soc_is_exynos4412())
  623. pd->bus_num = 8;
  624. else if (soc_is_s5pv210())
  625. pd->bus_num = 3;
  626. else
  627. pd->bus_num = 0;
  628. }
  629. npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
  630. &s5p_device_i2c_hdmiphy);
  631. }
  632. static struct s5p_hdmi_platform_data s5p_hdmi_def_platdata;
  633. void __init s5p_hdmi_set_platdata(struct i2c_board_info *hdmiphy_info,
  634. struct i2c_board_info *mhl_info, int mhl_bus)
  635. {
  636. struct s5p_hdmi_platform_data *pd = &s5p_hdmi_def_platdata;
  637. if (soc_is_exynos4210() ||
  638. soc_is_exynos4212() || soc_is_exynos4412())
  639. pd->hdmiphy_bus = 8;
  640. else if (soc_is_s5pv210())
  641. pd->hdmiphy_bus = 3;
  642. else
  643. pd->hdmiphy_bus = 0;
  644. pd->hdmiphy_info = hdmiphy_info;
  645. pd->mhl_info = mhl_info;
  646. pd->mhl_bus = mhl_bus;
  647. s3c_set_platdata(pd, sizeof(struct s5p_hdmi_platform_data),
  648. &s5p_device_hdmi);
  649. }
  650. #endif /* CONFIG_S5P_DEV_I2C_HDMIPHY */
  651. /* I2S */
  652. #ifdef CONFIG_PLAT_S3C24XX
  653. static struct resource s3c_iis_resource[] = {
  654. [0] = DEFINE_RES_MEM(S3C24XX_PA_IIS, S3C24XX_SZ_IIS),
  655. };
  656. struct platform_device s3c_device_iis = {
  657. .name = "s3c24xx-iis",
  658. .id = -1,
  659. .num_resources = ARRAY_SIZE(s3c_iis_resource),
  660. .resource = s3c_iis_resource,
  661. .dev = {
  662. .dma_mask = &samsung_device_dma_mask,
  663. .coherent_dma_mask = DMA_BIT_MASK(32),
  664. }
  665. };
  666. #endif /* CONFIG_PLAT_S3C24XX */
  667. /* IDE CFCON */
  668. #ifdef CONFIG_SAMSUNG_DEV_IDE
  669. static struct resource s3c_cfcon_resource[] = {
  670. [0] = DEFINE_RES_MEM(SAMSUNG_PA_CFCON, SZ_16K),
  671. [1] = DEFINE_RES_IRQ(IRQ_CFCON),
  672. };
  673. struct platform_device s3c_device_cfcon = {
  674. .id = 0,
  675. .num_resources = ARRAY_SIZE(s3c_cfcon_resource),
  676. .resource = s3c_cfcon_resource,
  677. };
  678. void __init s3c_ide_set_platdata(struct s3c_ide_platdata *pdata)
  679. {
  680. s3c_set_platdata(pdata, sizeof(struct s3c_ide_platdata),
  681. &s3c_device_cfcon);
  682. }
  683. #endif /* CONFIG_SAMSUNG_DEV_IDE */
  684. /* KEYPAD */
  685. #ifdef CONFIG_SAMSUNG_DEV_KEYPAD
  686. static struct resource samsung_keypad_resources[] = {
  687. [0] = DEFINE_RES_MEM(SAMSUNG_PA_KEYPAD, SZ_32),
  688. [1] = DEFINE_RES_IRQ(IRQ_KEYPAD),
  689. };
  690. struct platform_device samsung_device_keypad = {
  691. .name = "samsung-keypad",
  692. .id = -1,
  693. .num_resources = ARRAY_SIZE(samsung_keypad_resources),
  694. .resource = samsung_keypad_resources,
  695. };
  696. void __init samsung_keypad_set_platdata(struct samsung_keypad_platdata *pd)
  697. {
  698. struct samsung_keypad_platdata *npd;
  699. npd = s3c_set_platdata(pd, sizeof(struct samsung_keypad_platdata),
  700. &samsung_device_keypad);
  701. if (!npd->cfg_gpio)
  702. npd->cfg_gpio = samsung_keypad_cfg_gpio;
  703. }
  704. #endif /* CONFIG_SAMSUNG_DEV_KEYPAD */
  705. /* LCD Controller */
  706. #ifdef CONFIG_PLAT_S3C24XX
  707. static struct resource s3c_lcd_resource[] = {
  708. [0] = DEFINE_RES_MEM(S3C24XX_PA_LCD, S3C24XX_SZ_LCD),
  709. [1] = DEFINE_RES_IRQ(IRQ_LCD),
  710. };
  711. struct platform_device s3c_device_lcd = {
  712. .name = "s3c2410-lcd",
  713. .id = -1,
  714. .num_resources = ARRAY_SIZE(s3c_lcd_resource),
  715. .resource = s3c_lcd_resource,
  716. .dev = {
  717. .dma_mask = &samsung_device_dma_mask,
  718. .coherent_dma_mask = DMA_BIT_MASK(32),
  719. }
  720. };
  721. void __init s3c24xx_fb_set_platdata(struct s3c2410fb_mach_info *pd)
  722. {
  723. struct s3c2410fb_mach_info *npd;
  724. npd = s3c_set_platdata(pd, sizeof(*npd), &s3c_device_lcd);
  725. if (npd) {
  726. npd->displays = kmemdup(pd->displays,
  727. sizeof(struct s3c2410fb_display) * npd->num_displays,
  728. GFP_KERNEL);
  729. if (!npd->displays)
  730. printk(KERN_ERR "no memory for LCD display data\n");
  731. } else {
  732. printk(KERN_ERR "no memory for LCD platform data\n");
  733. }
  734. }
  735. #endif /* CONFIG_PLAT_S3C24XX */
  736. /* MFC */
  737. #ifdef CONFIG_S5P_DEV_MFC
  738. static struct resource s5p_mfc_resource[] = {
  739. [0] = DEFINE_RES_MEM(S5P_PA_MFC, SZ_64K),
  740. [1] = DEFINE_RES_IRQ(IRQ_MFC),
  741. };
  742. struct platform_device s5p_device_mfc = {
  743. .name = "s5p-mfc",
  744. .id = -1,
  745. .num_resources = ARRAY_SIZE(s5p_mfc_resource),
  746. .resource = s5p_mfc_resource,
  747. };
  748. /*
  749. * MFC hardware has 2 memory interfaces which are modelled as two separate
  750. * platform devices to let dma-mapping distinguish between them.
  751. *
  752. * MFC parent device (s5p_device_mfc) must be registered before memory
  753. * interface specific devices (s5p_device_mfc_l and s5p_device_mfc_r).
  754. */
  755. struct platform_device s5p_device_mfc_l = {
  756. .name = "s5p-mfc-l",
  757. .id = -1,
  758. .dev = {
  759. .parent = &s5p_device_mfc.dev,
  760. .dma_mask = &samsung_device_dma_mask,
  761. .coherent_dma_mask = DMA_BIT_MASK(32),
  762. },
  763. };
  764. struct platform_device s5p_device_mfc_r = {
  765. .name = "s5p-mfc-r",
  766. .id = -1,
  767. .dev = {
  768. .parent = &s5p_device_mfc.dev,
  769. .dma_mask = &samsung_device_dma_mask,
  770. .coherent_dma_mask = DMA_BIT_MASK(32),
  771. },
  772. };
  773. #endif /* CONFIG_S5P_DEV_MFC */
  774. /* MIPI CSIS */
  775. #ifdef CONFIG_S5P_DEV_CSIS0
  776. static struct resource s5p_mipi_csis0_resource[] = {
  777. [0] = DEFINE_RES_MEM(S5P_PA_MIPI_CSIS0, SZ_16K),
  778. [1] = DEFINE_RES_IRQ(IRQ_MIPI_CSIS0),
  779. };
  780. struct platform_device s5p_device_mipi_csis0 = {
  781. .name = "s5p-mipi-csis",
  782. .id = 0,
  783. .num_resources = ARRAY_SIZE(s5p_mipi_csis0_resource),
  784. .resource = s5p_mipi_csis0_resource,
  785. };
  786. #endif /* CONFIG_S5P_DEV_CSIS0 */
  787. #ifdef CONFIG_S5P_DEV_CSIS1
  788. static struct resource s5p_mipi_csis1_resource[] = {
  789. [0] = DEFINE_RES_MEM(S5P_PA_MIPI_CSIS1, SZ_16K),
  790. [1] = DEFINE_RES_IRQ(IRQ_MIPI_CSIS1),
  791. };
  792. struct platform_device s5p_device_mipi_csis1 = {
  793. .name = "s5p-mipi-csis",
  794. .id = 1,
  795. .num_resources = ARRAY_SIZE(s5p_mipi_csis1_resource),
  796. .resource = s5p_mipi_csis1_resource,
  797. };
  798. #endif
  799. /* NAND */
  800. #ifdef CONFIG_S3C_DEV_NAND
  801. static struct resource s3c_nand_resource[] = {
  802. [0] = DEFINE_RES_MEM(S3C_PA_NAND, SZ_1M),
  803. };
  804. struct platform_device s3c_device_nand = {
  805. .name = "s3c2410-nand",
  806. .id = -1,
  807. .num_resources = ARRAY_SIZE(s3c_nand_resource),
  808. .resource = s3c_nand_resource,
  809. };
  810. /*
  811. * s3c_nand_copy_set() - copy nand set data
  812. * @set: The new structure, directly copied from the old.
  813. *
  814. * Copy all the fields from the NAND set field from what is probably __initdata
  815. * to new kernel memory. The code returns 0 if the copy happened correctly or
  816. * an error code for the calling function to display.
  817. *
  818. * Note, we currently do not try and look to see if we've already copied the
  819. * data in a previous set.
  820. */
  821. static int __init s3c_nand_copy_set(struct s3c2410_nand_set *set)
  822. {
  823. void *ptr;
  824. int size;
  825. size = sizeof(struct mtd_partition) * set->nr_partitions;
  826. if (size) {
  827. ptr = kmemdup(set->partitions, size, GFP_KERNEL);
  828. set->partitions = ptr;
  829. if (!ptr)
  830. return -ENOMEM;
  831. }
  832. if (set->nr_map && set->nr_chips) {
  833. size = sizeof(int) * set->nr_chips;
  834. ptr = kmemdup(set->nr_map, size, GFP_KERNEL);
  835. set->nr_map = ptr;
  836. if (!ptr)
  837. return -ENOMEM;
  838. }
  839. if (set->ecc_layout) {
  840. ptr = kmemdup(set->ecc_layout,
  841. sizeof(struct nand_ecclayout), GFP_KERNEL);
  842. set->ecc_layout = ptr;
  843. if (!ptr)
  844. return -ENOMEM;
  845. }
  846. return 0;
  847. }
  848. void __init s3c_nand_set_platdata(struct s3c2410_platform_nand *nand)
  849. {
  850. struct s3c2410_platform_nand *npd;
  851. int size;
  852. int ret;
  853. /* note, if we get a failure in allocation, we simply drop out of the
  854. * function. If there is so little memory available at initialisation
  855. * time then there is little chance the system is going to run.
  856. */
  857. npd = s3c_set_platdata(nand, sizeof(struct s3c2410_platform_nand),
  858. &s3c_device_nand);
  859. if (!npd)
  860. return;
  861. /* now see if we need to copy any of the nand set data */
  862. size = sizeof(struct s3c2410_nand_set) * npd->nr_sets;
  863. if (size) {
  864. struct s3c2410_nand_set *from = npd->sets;
  865. struct s3c2410_nand_set *to;
  866. int i;
  867. to = kmemdup(from, size, GFP_KERNEL);
  868. npd->sets = to; /* set, even if we failed */
  869. if (!to) {
  870. printk(KERN_ERR "%s: no memory for sets\n", __func__);
  871. return;
  872. }
  873. for (i = 0; i < npd->nr_sets; i++) {
  874. ret = s3c_nand_copy_set(to);
  875. if (ret) {
  876. printk(KERN_ERR "%s: failed to copy set %d\n",
  877. __func__, i);
  878. return;
  879. }
  880. to++;
  881. }
  882. }
  883. }
  884. #endif /* CONFIG_S3C_DEV_NAND */
  885. /* ONENAND */
  886. #ifdef CONFIG_S3C_DEV_ONENAND
  887. static struct resource s3c_onenand_resources[] = {
  888. [0] = DEFINE_RES_MEM(S3C_PA_ONENAND, SZ_1K),
  889. [1] = DEFINE_RES_MEM(S3C_PA_ONENAND_BUF, S3C_SZ_ONENAND_BUF),
  890. [2] = DEFINE_RES_IRQ(IRQ_ONENAND),
  891. };
  892. struct platform_device s3c_device_onenand = {
  893. .name = "samsung-onenand",
  894. .id = 0,
  895. .num_resources = ARRAY_SIZE(s3c_onenand_resources),
  896. .resource = s3c_onenand_resources,
  897. };
  898. #endif /* CONFIG_S3C_DEV_ONENAND */
  899. #ifdef CONFIG_S3C64XX_DEV_ONENAND1
  900. static struct resource s3c64xx_onenand1_resources[] = {
  901. [0] = DEFINE_RES_MEM(S3C64XX_PA_ONENAND1, SZ_1K),
  902. [1] = DEFINE_RES_MEM(S3C64XX_PA_ONENAND1_BUF, S3C64XX_SZ_ONENAND1_BUF),
  903. [2] = DEFINE_RES_IRQ(IRQ_ONENAND1),
  904. };
  905. struct platform_device s3c64xx_device_onenand1 = {
  906. .name = "samsung-onenand",
  907. .id = 1,
  908. .num_resources = ARRAY_SIZE(s3c64xx_onenand1_resources),
  909. .resource = s3c64xx_onenand1_resources,
  910. };
  911. void __init s3c64xx_onenand1_set_platdata(struct onenand_platform_data *pdata)
  912. {
  913. s3c_set_platdata(pdata, sizeof(struct onenand_platform_data),
  914. &s3c64xx_device_onenand1);
  915. }
  916. #endif /* CONFIG_S3C64XX_DEV_ONENAND1 */
  917. #ifdef CONFIG_S5P_DEV_ONENAND
  918. static struct resource s5p_onenand_resources[] = {
  919. [0] = DEFINE_RES_MEM(S5P_PA_ONENAND, SZ_128K),
  920. [1] = DEFINE_RES_MEM(S5P_PA_ONENAND_DMA, SZ_8K),
  921. [2] = DEFINE_RES_IRQ(IRQ_ONENAND_AUDI),
  922. };
  923. struct platform_device s5p_device_onenand = {
  924. .name = "s5pc110-onenand",
  925. .id = -1,
  926. .num_resources = ARRAY_SIZE(s5p_onenand_resources),
  927. .resource = s5p_onenand_resources,
  928. };
  929. #endif /* CONFIG_S5P_DEV_ONENAND */
  930. /* PMU */
  931. #ifdef CONFIG_PLAT_S5P
  932. static struct resource s5p_pmu_resource[] = {
  933. DEFINE_RES_IRQ(IRQ_PMU)
  934. };
  935. static struct platform_device s5p_device_pmu = {
  936. .name = "arm-pmu",
  937. .id = -1,
  938. .num_resources = ARRAY_SIZE(s5p_pmu_resource),
  939. .resource = s5p_pmu_resource,
  940. };
  941. static int __init s5p_pmu_init(void)
  942. {
  943. platform_device_register(&s5p_device_pmu);
  944. return 0;
  945. }
  946. arch_initcall(s5p_pmu_init);
  947. #endif /* CONFIG_PLAT_S5P */
  948. /* PWM Timer */
  949. #ifdef CONFIG_SAMSUNG_DEV_PWM
  950. #define TIMER_RESOURCE_SIZE (1)
  951. #define TIMER_RESOURCE(_tmr, _irq) \
  952. (struct resource [TIMER_RESOURCE_SIZE]) { \
  953. [0] = { \
  954. .start = _irq, \
  955. .end = _irq, \
  956. .flags = IORESOURCE_IRQ \
  957. } \
  958. }
  959. #define DEFINE_S3C_TIMER(_tmr_no, _irq) \
  960. .name = "s3c24xx-pwm", \
  961. .id = _tmr_no, \
  962. .num_resources = TIMER_RESOURCE_SIZE, \
  963. .resource = TIMER_RESOURCE(_tmr_no, _irq), \
  964. /*
  965. * since we already have an static mapping for the timer,
  966. * we do not bother setting any IO resource for the base.
  967. */
  968. struct platform_device s3c_device_timer[] = {
  969. [0] = { DEFINE_S3C_TIMER(0, IRQ_TIMER0) },
  970. [1] = { DEFINE_S3C_TIMER(1, IRQ_TIMER1) },
  971. [2] = { DEFINE_S3C_TIMER(2, IRQ_TIMER2) },
  972. [3] = { DEFINE_S3C_TIMER(3, IRQ_TIMER3) },
  973. [4] = { DEFINE_S3C_TIMER(4, IRQ_TIMER4) },
  974. };
  975. #endif /* CONFIG_SAMSUNG_DEV_PWM */
  976. /* RTC */
  977. #ifdef CONFIG_PLAT_S3C24XX
  978. static struct resource s3c_rtc_resource[] = {
  979. [0] = DEFINE_RES_MEM(S3C24XX_PA_RTC, SZ_256),
  980. [1] = DEFINE_RES_IRQ(IRQ_RTC),
  981. [2] = DEFINE_RES_IRQ(IRQ_TICK),
  982. };
  983. struct platform_device s3c_device_rtc = {
  984. .name = "s3c2410-rtc",
  985. .id = -1,
  986. .num_resources = ARRAY_SIZE(s3c_rtc_resource),
  987. .resource = s3c_rtc_resource,
  988. };
  989. #endif /* CONFIG_PLAT_S3C24XX */
  990. #ifdef CONFIG_S3C_DEV_RTC
  991. static struct resource s3c_rtc_resource[] = {
  992. [0] = DEFINE_RES_MEM(S3C_PA_RTC, SZ_256),
  993. [1] = DEFINE_RES_IRQ(IRQ_RTC_ALARM),
  994. [2] = DEFINE_RES_IRQ(IRQ_RTC_TIC),
  995. };
  996. struct platform_device s3c_device_rtc = {
  997. .name = "s3c64xx-rtc",
  998. .id = -1,
  999. .num_resources = ARRAY_SIZE(s3c_rtc_resource),
  1000. .resource = s3c_rtc_resource,
  1001. };
  1002. #endif /* CONFIG_S3C_DEV_RTC */
  1003. /* SDI */
  1004. #ifdef CONFIG_PLAT_S3C24XX
  1005. static struct resource s3c_sdi_resource[] = {
  1006. [0] = DEFINE_RES_MEM(S3C24XX_PA_SDI, S3C24XX_SZ_SDI),
  1007. [1] = DEFINE_RES_IRQ(IRQ_SDI),
  1008. };
  1009. struct platform_device s3c_device_sdi = {
  1010. .name = "s3c2410-sdi",
  1011. .id = -1,
  1012. .num_resources = ARRAY_SIZE(s3c_sdi_resource),
  1013. .resource = s3c_sdi_resource,
  1014. };
  1015. void __init s3c24xx_mci_set_platdata(struct s3c24xx_mci_pdata *pdata)
  1016. {
  1017. s3c_set_platdata(pdata, sizeof(struct s3c24xx_mci_pdata),
  1018. &s3c_device_sdi);
  1019. }
  1020. #endif /* CONFIG_PLAT_S3C24XX */
  1021. /* SPI */
  1022. #ifdef CONFIG_PLAT_S3C24XX
  1023. static struct resource s3c_spi0_resource[] = {
  1024. [0] = DEFINE_RES_MEM(S3C24XX_PA_SPI, SZ_32),
  1025. [1] = DEFINE_RES_IRQ(IRQ_SPI0),
  1026. };
  1027. struct platform_device s3c_device_spi0 = {
  1028. .name = "s3c2410-spi",
  1029. .id = 0,
  1030. .num_resources = ARRAY_SIZE(s3c_spi0_resource),
  1031. .resource = s3c_spi0_resource,
  1032. .dev = {
  1033. .dma_mask = &samsung_device_dma_mask,
  1034. .coherent_dma_mask = DMA_BIT_MASK(32),
  1035. }
  1036. };
  1037. static struct resource s3c_spi1_resource[] = {
  1038. [0] = DEFINE_RES_MEM(S3C24XX_PA_SPI1, SZ_32),
  1039. [1] = DEFINE_RES_IRQ(IRQ_SPI1),
  1040. };
  1041. struct platform_device s3c_device_spi1 = {
  1042. .name = "s3c2410-spi",
  1043. .id = 1,
  1044. .num_resources = ARRAY_SIZE(s3c_spi1_resource),
  1045. .resource = s3c_spi1_resource,
  1046. .dev = {
  1047. .dma_mask = &samsung_device_dma_mask,
  1048. .coherent_dma_mask = DMA_BIT_MASK(32),
  1049. }
  1050. };
  1051. #endif /* CONFIG_PLAT_S3C24XX */
  1052. /* Touchscreen */
  1053. #ifdef CONFIG_PLAT_S3C24XX
  1054. static struct resource s3c_ts_resource[] = {
  1055. [0] = DEFINE_RES_MEM(S3C24XX_PA_ADC, S3C24XX_SZ_ADC),
  1056. [1] = DEFINE_RES_IRQ(IRQ_TC),
  1057. };
  1058. struct platform_device s3c_device_ts = {
  1059. .name = "s3c2410-ts",
  1060. .id = -1,
  1061. .dev.parent = &s3c_device_adc.dev,
  1062. .num_resources = ARRAY_SIZE(s3c_ts_resource),
  1063. .resource = s3c_ts_resource,
  1064. };
  1065. void __init s3c24xx_ts_set_platdata(struct s3c2410_ts_mach_info *hard_s3c2410ts_info)
  1066. {
  1067. s3c_set_platdata(hard_s3c2410ts_info,
  1068. sizeof(struct s3c2410_ts_mach_info), &s3c_device_ts);
  1069. }
  1070. #endif /* CONFIG_PLAT_S3C24XX */
  1071. #ifdef CONFIG_SAMSUNG_DEV_TS
  1072. static struct resource s3c_ts_resource[] = {
  1073. [0] = DEFINE_RES_MEM(SAMSUNG_PA_ADC, SZ_256),
  1074. [1] = DEFINE_RES_IRQ(IRQ_TC),
  1075. };
  1076. static struct s3c2410_ts_mach_info default_ts_data __initdata = {
  1077. .delay = 10000,
  1078. .presc = 49,
  1079. .oversampling_shift = 2,
  1080. };
  1081. struct platform_device s3c_device_ts = {
  1082. .name = "s3c64xx-ts",
  1083. .id = -1,
  1084. .num_resources = ARRAY_SIZE(s3c_ts_resource),
  1085. .resource = s3c_ts_resource,
  1086. };
  1087. void __init s3c24xx_ts_set_platdata(struct s3c2410_ts_mach_info *pd)
  1088. {
  1089. if (!pd)
  1090. pd = &default_ts_data;
  1091. s3c_set_platdata(pd, sizeof(struct s3c2410_ts_mach_info),
  1092. &s3c_device_ts);
  1093. }
  1094. #endif /* CONFIG_SAMSUNG_DEV_TS */
  1095. /* TV */
  1096. #ifdef CONFIG_S5P_DEV_TV
  1097. static struct resource s5p_hdmi_resources[] = {
  1098. [0] = DEFINE_RES_MEM(S5P_PA_HDMI, SZ_1M),
  1099. [1] = DEFINE_RES_IRQ(IRQ_HDMI),
  1100. };
  1101. struct platform_device s5p_device_hdmi = {
  1102. .name = "s5p-hdmi",
  1103. .id = -1,
  1104. .num_resources = ARRAY_SIZE(s5p_hdmi_resources),
  1105. .resource = s5p_hdmi_resources,
  1106. };
  1107. static struct resource s5p_sdo_resources[] = {
  1108. [0] = DEFINE_RES_MEM(S5P_PA_SDO, SZ_64K),
  1109. [1] = DEFINE_RES_IRQ(IRQ_SDO),
  1110. };
  1111. struct platform_device s5p_device_sdo = {
  1112. .name = "s5p-sdo",
  1113. .id = -1,
  1114. .num_resources = ARRAY_SIZE(s5p_sdo_resources),
  1115. .resource = s5p_sdo_resources,
  1116. };
  1117. static struct resource s5p_mixer_resources[] = {
  1118. [0] = DEFINE_RES_MEM_NAMED(S5P_PA_MIXER, SZ_64K, "mxr"),
  1119. [1] = DEFINE_RES_MEM_NAMED(S5P_PA_VP, SZ_64K, "vp"),
  1120. [2] = DEFINE_RES_IRQ_NAMED(IRQ_MIXER, "irq"),
  1121. };
  1122. struct platform_device s5p_device_mixer = {
  1123. .name = "s5p-mixer",
  1124. .id = -1,
  1125. .num_resources = ARRAY_SIZE(s5p_mixer_resources),
  1126. .resource = s5p_mixer_resources,
  1127. .dev = {
  1128. .dma_mask = &samsung_device_dma_mask,
  1129. .coherent_dma_mask = DMA_BIT_MASK(32),
  1130. }
  1131. };
  1132. #endif /* CONFIG_S5P_DEV_TV */
  1133. /* USB */
  1134. #ifdef CONFIG_S3C_DEV_USB_HOST
  1135. static struct resource s3c_usb_resource[] = {
  1136. [0] = DEFINE_RES_MEM(S3C_PA_USBHOST, SZ_256),
  1137. [1] = DEFINE_RES_IRQ(IRQ_USBH),
  1138. };
  1139. struct platform_device s3c_device_ohci = {
  1140. .name = "s3c2410-ohci",
  1141. .id = -1,
  1142. .num_resources = ARRAY_SIZE(s3c_usb_resource),
  1143. .resource = s3c_usb_resource,
  1144. .dev = {
  1145. .dma_mask = &samsung_device_dma_mask,
  1146. .coherent_dma_mask = DMA_BIT_MASK(32),
  1147. }
  1148. };
  1149. /*
  1150. * s3c_ohci_set_platdata - initialise OHCI device platform data
  1151. * @info: The platform data.
  1152. *
  1153. * This call copies the @info passed in and sets the device .platform_data
  1154. * field to that copy. The @info is copied so that the original can be marked
  1155. * __initdata.
  1156. */
  1157. void __init s3c_ohci_set_platdata(struct s3c2410_hcd_info *info)
  1158. {
  1159. s3c_set_platdata(info, sizeof(struct s3c2410_hcd_info),
  1160. &s3c_device_ohci);
  1161. }
  1162. #endif /* CONFIG_S3C_DEV_USB_HOST */
  1163. /* USB Device (Gadget) */
  1164. #ifdef CONFIG_PLAT_S3C24XX
  1165. static struct resource s3c_usbgadget_resource[] = {
  1166. [0] = DEFINE_RES_MEM(S3C24XX_PA_USBDEV, S3C24XX_SZ_USBDEV),
  1167. [1] = DEFINE_RES_IRQ(IRQ_USBD),
  1168. };
  1169. struct platform_device s3c_device_usbgadget = {
  1170. .name = "s3c2410-usbgadget",
  1171. .id = -1,
  1172. .num_resources = ARRAY_SIZE(s3c_usbgadget_resource),
  1173. .resource = s3c_usbgadget_resource,
  1174. };
  1175. void __init s3c24xx_udc_set_platdata(struct s3c2410_udc_mach_info *pd)
  1176. {
  1177. s3c_set_platdata(pd, sizeof(*pd), &s3c_device_usbgadget);
  1178. }
  1179. #endif /* CONFIG_PLAT_S3C24XX */
  1180. /* USB EHCI Host Controller */
  1181. #ifdef CONFIG_S5P_DEV_USB_EHCI
  1182. static struct resource s5p_ehci_resource[] = {
  1183. [0] = DEFINE_RES_MEM(S5P_PA_EHCI, SZ_256),
  1184. [1] = DEFINE_RES_IRQ(IRQ_USB_HOST),
  1185. };
  1186. struct platform_device s5p_device_ehci = {
  1187. .name = "s5p-ehci",
  1188. .id = -1,
  1189. .num_resources = ARRAY_SIZE(s5p_ehci_resource),
  1190. .resource = s5p_ehci_resource,
  1191. .dev = {
  1192. .dma_mask = &samsung_device_dma_mask,
  1193. .coherent_dma_mask = DMA_BIT_MASK(32),
  1194. }
  1195. };
  1196. void __init s5p_ehci_set_platdata(struct s5p_ehci_platdata *pd)
  1197. {
  1198. struct s5p_ehci_platdata *npd;
  1199. npd = s3c_set_platdata(pd, sizeof(struct s5p_ehci_platdata),
  1200. &s5p_device_ehci);
  1201. if (!npd->phy_init)
  1202. npd->phy_init = s5p_usb_phy_init;
  1203. if (!npd->phy_exit)
  1204. npd->phy_exit = s5p_usb_phy_exit;
  1205. }
  1206. #endif /* CONFIG_S5P_DEV_USB_EHCI */
  1207. /* USB HSOTG */
  1208. #ifdef CONFIG_S3C_DEV_USB_HSOTG
  1209. static struct resource s3c_usb_hsotg_resources[] = {
  1210. [0] = DEFINE_RES_MEM(S3C_PA_USB_HSOTG, SZ_128K),
  1211. [1] = DEFINE_RES_IRQ(IRQ_OTG),
  1212. };
  1213. struct platform_device s3c_device_usb_hsotg = {
  1214. .name = "s3c-hsotg",
  1215. .id = -1,
  1216. .num_resources = ARRAY_SIZE(s3c_usb_hsotg_resources),
  1217. .resource = s3c_usb_hsotg_resources,
  1218. .dev = {
  1219. .dma_mask = &samsung_device_dma_mask,
  1220. .coherent_dma_mask = DMA_BIT_MASK(32),
  1221. },
  1222. };
  1223. void __init s3c_hsotg_set_platdata(struct s3c_hsotg_plat *pd)
  1224. {
  1225. struct s3c_hsotg_plat *npd;
  1226. npd = s3c_set_platdata(pd, sizeof(struct s3c_hsotg_plat),
  1227. &s3c_device_usb_hsotg);
  1228. if (!npd->phy_init)
  1229. npd->phy_init = s5p_usb_phy_init;
  1230. if (!npd->phy_exit)
  1231. npd->phy_exit = s5p_usb_phy_exit;
  1232. }
  1233. #endif /* CONFIG_S3C_DEV_USB_HSOTG */
  1234. /* USB High Spped 2.0 Device (Gadget) */
  1235. #ifdef CONFIG_PLAT_S3C24XX
  1236. static struct resource s3c_hsudc_resource[] = {
  1237. [0] = DEFINE_RES_MEM(S3C2416_PA_HSUDC, S3C2416_SZ_HSUDC),
  1238. [1] = DEFINE_RES_IRQ(IRQ_USBD),
  1239. };
  1240. struct platform_device s3c_device_usb_hsudc = {
  1241. .name = "s3c-hsudc",
  1242. .id = -1,
  1243. .num_resources = ARRAY_SIZE(s3c_hsudc_resource),
  1244. .resource = s3c_hsudc_resource,
  1245. .dev = {
  1246. .dma_mask = &samsung_device_dma_mask,
  1247. .coherent_dma_mask = DMA_BIT_MASK(32),
  1248. },
  1249. };
  1250. void __init s3c24xx_hsudc_set_platdata(struct s3c24xx_hsudc_platdata *pd)
  1251. {
  1252. s3c_set_platdata(pd, sizeof(*pd), &s3c_device_usb_hsudc);
  1253. }
  1254. #endif /* CONFIG_PLAT_S3C24XX */
  1255. /* WDT */
  1256. #ifdef CONFIG_S3C_DEV_WDT
  1257. static struct resource s3c_wdt_resource[] = {
  1258. [0] = DEFINE_RES_MEM(S3C_PA_WDT, SZ_1K),
  1259. [1] = DEFINE_RES_IRQ(IRQ_WDT),
  1260. };
  1261. struct platform_device s3c_device_wdt = {
  1262. .name = "s3c2410-wdt",
  1263. .id = -1,
  1264. .num_resources = ARRAY_SIZE(s3c_wdt_resource),
  1265. .resource = s3c_wdt_resource,
  1266. };
  1267. #endif /* CONFIG_S3C_DEV_WDT */
  1268. #ifdef CONFIG_S3C64XX_DEV_SPI0
  1269. static struct resource s3c64xx_spi0_resource[] = {
  1270. [0] = DEFINE_RES_MEM(S3C_PA_SPI0, SZ_256),
  1271. [1] = DEFINE_RES_DMA(DMACH_SPI0_TX),
  1272. [2] = DEFINE_RES_DMA(DMACH_SPI0_RX),
  1273. [3] = DEFINE_RES_IRQ(IRQ_SPI0),
  1274. };
  1275. struct platform_device s3c64xx_device_spi0 = {
  1276. .name = "s3c6410-spi",
  1277. .id = 0,
  1278. .num_resources = ARRAY_SIZE(s3c64xx_spi0_resource),
  1279. .resource = s3c64xx_spi0_resource,
  1280. .dev = {
  1281. .dma_mask = &samsung_device_dma_mask,
  1282. .coherent_dma_mask = DMA_BIT_MASK(32),
  1283. },
  1284. };
  1285. void __init s3c64xx_spi0_set_platdata(int (*cfg_gpio)(void), int src_clk_nr,
  1286. int num_cs)
  1287. {
  1288. struct s3c64xx_spi_info pd;
  1289. /* Reject invalid configuration */
  1290. if (!num_cs || src_clk_nr < 0) {
  1291. pr_err("%s: Invalid SPI configuration\n", __func__);
  1292. return;
  1293. }
  1294. pd.num_cs = num_cs;
  1295. pd.src_clk_nr = src_clk_nr;
  1296. pd.cfg_gpio = (cfg_gpio) ? cfg_gpio : s3c64xx_spi0_cfg_gpio;
  1297. s3c_set_platdata(&pd, sizeof(pd), &s3c64xx_device_spi0);
  1298. }
  1299. #endif /* CONFIG_S3C64XX_DEV_SPI0 */
  1300. #ifdef CONFIG_S3C64XX_DEV_SPI1
  1301. static struct resource s3c64xx_spi1_resource[] = {
  1302. [0] = DEFINE_RES_MEM(S3C_PA_SPI1, SZ_256),
  1303. [1] = DEFINE_RES_DMA(DMACH_SPI1_TX),
  1304. [2] = DEFINE_RES_DMA(DMACH_SPI1_RX),
  1305. [3] = DEFINE_RES_IRQ(IRQ_SPI1),
  1306. };
  1307. struct platform_device s3c64xx_device_spi1 = {
  1308. .name = "s3c6410-spi",
  1309. .id = 1,
  1310. .num_resources = ARRAY_SIZE(s3c64xx_spi1_resource),
  1311. .resource = s3c64xx_spi1_resource,
  1312. .dev = {
  1313. .dma_mask = &samsung_device_dma_mask,
  1314. .coherent_dma_mask = DMA_BIT_MASK(32),
  1315. },
  1316. };
  1317. void __init s3c64xx_spi1_set_platdata(int (*cfg_gpio)(void), int src_clk_nr,
  1318. int num_cs)
  1319. {
  1320. struct s3c64xx_spi_info pd;
  1321. /* Reject invalid configuration */
  1322. if (!num_cs || src_clk_nr < 0) {
  1323. pr_err("%s: Invalid SPI configuration\n", __func__);
  1324. return;
  1325. }
  1326. pd.num_cs = num_cs;
  1327. pd.src_clk_nr = src_clk_nr;
  1328. pd.cfg_gpio = (cfg_gpio) ? cfg_gpio : s3c64xx_spi1_cfg_gpio;
  1329. s3c_set_platdata(&pd, sizeof(pd), &s3c64xx_device_spi1);
  1330. }
  1331. #endif /* CONFIG_S3C64XX_DEV_SPI1 */
  1332. #ifdef CONFIG_S3C64XX_DEV_SPI2
  1333. static struct resource s3c64xx_spi2_resource[] = {
  1334. [0] = DEFINE_RES_MEM(S3C_PA_SPI2, SZ_256),
  1335. [1] = DEFINE_RES_DMA(DMACH_SPI2_TX),
  1336. [2] = DEFINE_RES_DMA(DMACH_SPI2_RX),
  1337. [3] = DEFINE_RES_IRQ(IRQ_SPI2),
  1338. };
  1339. struct platform_device s3c64xx_device_spi2 = {
  1340. .name = "s3c6410-spi",
  1341. .id = 2,
  1342. .num_resources = ARRAY_SIZE(s3c64xx_spi2_resource),
  1343. .resource = s3c64xx_spi2_resource,
  1344. .dev = {
  1345. .dma_mask = &samsung_device_dma_mask,
  1346. .coherent_dma_mask = DMA_BIT_MASK(32),
  1347. },
  1348. };
  1349. void __init s3c64xx_spi2_set_platdata(int (*cfg_gpio)(void), int src_clk_nr,
  1350. int num_cs)
  1351. {
  1352. struct s3c64xx_spi_info pd;
  1353. /* Reject invalid configuration */
  1354. if (!num_cs || src_clk_nr < 0) {
  1355. pr_err("%s: Invalid SPI configuration\n", __func__);
  1356. return;
  1357. }
  1358. pd.num_cs = num_cs;
  1359. pd.src_clk_nr = src_clk_nr;
  1360. pd.cfg_gpio = (cfg_gpio) ? cfg_gpio : s3c64xx_spi2_cfg_gpio;
  1361. s3c_set_platdata(&pd, sizeof(pd), &s3c64xx_device_spi2);
  1362. }
  1363. #endif /* CONFIG_S3C64XX_DEV_SPI2 */