Home Explore Help
Register Sign In
phyus
/
linux-vybrid_public
8
0
Fork 0
Files Issues 0 Pull Requests 0 Wiki
Tree: e631227f69
Branches Tags
linux-vybrid_pu...
/
drivers
/
gpu
/
drm
/
radeon
/
radeon_asic.h

radeon_asic.h 35 KB
History Raw

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746 
  1. /*
    2. 

  2.  * Copyright 2008 Advanced Micro Devices, Inc.
    3. 

  3.  * Copyright 2008 Red Hat Inc.
    4. 

  4.  * Copyright 2009 Jerome Glisse.
    5. 

  5.  *
    6. 

  6.  * Permission is hereby granted, free of charge, to any person obtaining a
    7. 

  7.  * copy of this software and associated documentation files (the "Software"),
    8. 

  8.  * to deal in the Software without restriction, including without limitation
    9. 

  9.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
    10. 

  10.  * and/or sell copies of the Software, and to permit persons to whom the
    11. 

  11.  * Software is furnished to do so, subject to the following conditions:
    12. 

  12.  *
    13. 

  13.  * The above copyright notice and this permission notice shall be included in
    14. 

  14.  * all copies or substantial portions of the Software.
    15. 

  15.  *
    16. 

  16.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
    17. 

  17.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
    18. 

  18.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
    19. 

  19.  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
    20. 

  20.  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
    21. 

  21.  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
    22. 

  22.  * OTHER DEALINGS IN THE SOFTWARE.
    23. 

  23.  *
    24. 

  24.  * Authors: Dave Airlie
    25. 

  25.  *          Alex Deucher
    26. 

  26.  *          Jerome Glisse
    27. 

  27.  */
    28. 

  28. #ifndef __RADEON_ASIC_H__
    29. 

  29. #define __RADEON_ASIC_H__
    30. 

  30. 

  31. /*
    32. 

  32.  * common functions
    33. 

  33.  */
    34. 

  34. uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev);
    35. 

  35. void radeon_legacy_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock);
    36. 

  36. uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev);
    37. 

  37. void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
    38. 

  38. 

  39. uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev);
    40. 

  40. void radeon_atom_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock);
    41. 

  41. uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev);
    42. 

  42. void radeon_atom_set_memory_clock(struct radeon_device *rdev, uint32_t mem_clock);
    43. 

  43. void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
    44. 

  44. 

  45. void atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level);
    46. 

  46. u8 atombios_get_backlight_level(struct radeon_encoder *radeon_encoder);
    47. 

  47. void radeon_legacy_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level);
    48. 

  48. u8 radeon_legacy_get_backlight_level(struct radeon_encoder *radeon_encoder);
    49. 

  49. 

  50. u32 radeon_ring_generic_get_rptr(struct radeon_device *rdev,
    51. 

  51. 				 struct radeon_ring *ring);
    52. 

  52. u32 radeon_ring_generic_get_wptr(struct radeon_device *rdev,
    53. 

  53. 				 struct radeon_ring *ring);
    54. 

  54. void radeon_ring_generic_set_wptr(struct radeon_device *rdev,
    55. 

  55. 				  struct radeon_ring *ring);
    56. 

  56. 

  57. /*
    58. 

  58.  * r100,rv100,rs100,rv200,rs200
    59. 

  59.  */
    60. 

  60. struct r100_mc_save {
    61. 

  61. 	u32	GENMO_WT;
    62. 

  62. 	u32	CRTC_EXT_CNTL;
    63. 

  63. 	u32	CRTC_GEN_CNTL;
    64. 

  64. 	u32	CRTC2_GEN_CNTL;
    65. 

  65. 	u32	CUR_OFFSET;
    66. 

  66. 	u32	CUR2_OFFSET;
    67. 

  67. };
    68. 

  68. int r100_init(struct radeon_device *rdev);
    69. 

  69. void r100_fini(struct radeon_device *rdev);
    70. 

  70. int r100_suspend(struct radeon_device *rdev);
    71. 

  71. int r100_resume(struct radeon_device *rdev);
    72. 

  72. void r100_vga_set_state(struct radeon_device *rdev, bool state);
    73. 

  73. bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
    74. 

  74. int r100_asic_reset(struct radeon_device *rdev);
    75. 

  75. u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc);
    76. 

  76. void r100_pci_gart_tlb_flush(struct radeon_device *rdev);
    77. 

  77. int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
    78. 

  78. void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring);
    79. 

  79. int r100_irq_set(struct radeon_device *rdev);
    80. 

  80. int r100_irq_process(struct radeon_device *rdev);
    81. 

  81. void r100_fence_ring_emit(struct radeon_device *rdev,
    82. 

  82. 			  struct radeon_fence *fence);
    83. 

  83. void r100_semaphore_ring_emit(struct radeon_device *rdev,
    84. 

  84. 			      struct radeon_ring *cp,
    85. 

  85. 			      struct radeon_semaphore *semaphore,
    86. 

  86. 			      bool emit_wait);
    87. 

  87. int r100_cs_parse(struct radeon_cs_parser *p);
    88. 

  88. void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
    89. 

  89. uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg);
    90. 

  90. int r100_copy_blit(struct radeon_device *rdev,
    91. 

  91. 		   uint64_t src_offset,
    92. 

  92. 		   uint64_t dst_offset,
    93. 

  93. 		   unsigned num_gpu_pages,
    94. 

  94. 		   struct radeon_fence **fence);
    95. 

  95. int r100_set_surface_reg(struct radeon_device *rdev, int reg,
    96. 

  96. 			 uint32_t tiling_flags, uint32_t pitch,
    97. 

  97. 			 uint32_t offset, uint32_t obj_size);
    98. 

  98. void r100_clear_surface_reg(struct radeon_device *rdev, int reg);
    99. 

  99. void r100_bandwidth_update(struct radeon_device *rdev);
    100. 

  100. void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
    101. 

  101. int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
    102. 

  102. void r100_hpd_init(struct radeon_device *rdev);
    103. 

  103. void r100_hpd_fini(struct radeon_device *rdev);
    104. 

  104. bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
    105. 

  105. void r100_hpd_set_polarity(struct radeon_device *rdev,
    106. 

  106. 			   enum radeon_hpd_id hpd);
    107. 

  107. int r100_debugfs_rbbm_init(struct radeon_device *rdev);
    108. 

  108. int r100_debugfs_cp_init(struct radeon_device *rdev);
    109. 

  109. void r100_cp_disable(struct radeon_device *rdev);
    110. 

  110. int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
    111. 

  111. void r100_cp_fini(struct radeon_device *rdev);
    112. 

  112. int r100_pci_gart_init(struct radeon_device *rdev);
    113. 

  113. void r100_pci_gart_fini(struct radeon_device *rdev);
    114. 

  114. int r100_pci_gart_enable(struct radeon_device *rdev);
    115. 

  115. void r100_pci_gart_disable(struct radeon_device *rdev);
    116. 

  116. int r100_debugfs_mc_info_init(struct radeon_device *rdev);
    117. 

  117. int r100_gui_wait_for_idle(struct radeon_device *rdev);
    118. 

  118. int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
    119. 

  119. void r100_irq_disable(struct radeon_device *rdev);
    120. 

  120. void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save);
    121. 

  121. void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save);
    122. 

  122. void r100_vram_init_sizes(struct radeon_device *rdev);
    123. 

  123. int r100_cp_reset(struct radeon_device *rdev);
    124. 

  124. void r100_vga_render_disable(struct radeon_device *rdev);
    125. 

  125. void r100_restore_sanity(struct radeon_device *rdev);
    126. 

  126. int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
    127. 

  127. 					 struct radeon_cs_packet *pkt,
    128. 

  128. 					 struct radeon_bo *robj);
    129. 

  129. int r100_cs_parse_packet0(struct radeon_cs_parser *p,
    130. 

  130. 			  struct radeon_cs_packet *pkt,
    131. 

  131. 			  const unsigned *auth, unsigned n,
    132. 

  132. 			  radeon_packet0_check_t check);
    133. 

  133. int r100_cs_packet_parse(struct radeon_cs_parser *p,
    134. 

  134. 			 struct radeon_cs_packet *pkt,
    135. 

  135. 			 unsigned idx);
    136. 

  136. void r100_enable_bm(struct radeon_device *rdev);
    137. 

  137. void r100_set_common_regs(struct radeon_device *rdev);
    138. 

  138. void r100_bm_disable(struct radeon_device *rdev);
    139. 

  139. extern bool r100_gui_idle(struct radeon_device *rdev);
    140. 

  140. extern void r100_pm_misc(struct radeon_device *rdev);
    141. 

  141. extern void r100_pm_prepare(struct radeon_device *rdev);
    142. 

  142. extern void r100_pm_finish(struct radeon_device *rdev);
    143. 

  143. extern void r100_pm_init_profile(struct radeon_device *rdev);
    144. 

  144. extern void r100_pm_get_dynpm_state(struct radeon_device *rdev);
    145. 

  145. extern void r100_pre_page_flip(struct radeon_device *rdev, int crtc);
    146. 

  146. extern u32 r100_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base);
    147. 

  147. extern void r100_post_page_flip(struct radeon_device *rdev, int crtc);
    148. 

  148. extern void r100_wait_for_vblank(struct radeon_device *rdev, int crtc);
    149. 

  149. extern int r100_mc_wait_for_idle(struct radeon_device *rdev);
    150. 

  150. 

  151. /*
    152. 

  152.  * r200,rv250,rs300,rv280
    153. 

  153.  */
    154. 

  154. extern int r200_copy_dma(struct radeon_device *rdev,
    155. 

  155. 			 uint64_t src_offset,
    156. 

  156. 			 uint64_t dst_offset,
    157. 

  157. 			 unsigned num_gpu_pages,
    158. 

  158. 			 struct radeon_fence **fence);
    159. 

  159. void r200_set_safe_registers(struct radeon_device *rdev);
    160. 

  160. 

  161. /*
    162. 

  162.  * r300,r350,rv350,rv380
    163. 

  163.  */
    164. 

  164. extern int r300_init(struct radeon_device *rdev);
    165. 

  165. extern void r300_fini(struct radeon_device *rdev);
    166. 

  166. extern int r300_suspend(struct radeon_device *rdev);
    167. 

  167. extern int r300_resume(struct radeon_device *rdev);
    168. 

  168. extern int r300_asic_reset(struct radeon_device *rdev);
    169. 

  169. extern void r300_ring_start(struct radeon_device *rdev, struct radeon_ring *ring);
    170. 

  170. extern void r300_fence_ring_emit(struct radeon_device *rdev,
    171. 

  171. 				struct radeon_fence *fence);
    172. 

  172. extern int r300_cs_parse(struct radeon_cs_parser *p);
    173. 

  173. extern void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev);
    174. 

  174. extern int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
    175. 

  175. extern void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes);
    176. 

  176. extern int rv370_get_pcie_lanes(struct radeon_device *rdev);
    177. 

  177. extern void r300_set_reg_safe(struct radeon_device *rdev);
    178. 

  178. extern void r300_mc_program(struct radeon_device *rdev);
    179. 

  179. extern void r300_mc_init(struct radeon_device *rdev);
    180. 

  180. extern void r300_clock_startup(struct radeon_device *rdev);
    181. 

  181. extern int r300_mc_wait_for_idle(struct radeon_device *rdev);
    182. 

  182. extern int rv370_pcie_gart_init(struct radeon_device *rdev);
    183. 

  183. extern void rv370_pcie_gart_fini(struct radeon_device *rdev);
    184. 

  184. extern int rv370_pcie_gart_enable(struct radeon_device *rdev);
    185. 

  185. extern void rv370_pcie_gart_disable(struct radeon_device *rdev);
    186. 

  186. extern int r300_mc_wait_for_idle(struct radeon_device *rdev);
    187. 

  187. 

  188. /*
    189. 

  189.  * r420,r423,rv410
    190. 

  190.  */
    191. 

  191. extern int r420_init(struct radeon_device *rdev);
    192. 

  192. extern void r420_fini(struct radeon_device *rdev);
    193. 

  193. extern int r420_suspend(struct radeon_device *rdev);
    194. 

  194. extern int r420_resume(struct radeon_device *rdev);
    195. 

  195. extern void r420_pm_init_profile(struct radeon_device *rdev);
    196. 

  196. extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg);
    197. 

  197. extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
    198. 

  198. extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev);
    199. 

  199. extern void r420_pipes_init(struct radeon_device *rdev);
    200. 

  200. 

  201. /*
    202. 

  202.  * rs400,rs480
    203. 

  203.  */
    204. 

  204. extern int rs400_init(struct radeon_device *rdev);
    205. 

  205. extern void rs400_fini(struct radeon_device *rdev);
    206. 

  206. extern int rs400_suspend(struct radeon_device *rdev);
    207. 

  207. extern int rs400_resume(struct radeon_device *rdev);
    208. 

  208. void rs400_gart_tlb_flush(struct radeon_device *rdev);
    209. 

  209. int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
    210. 

  210. uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg);
    211. 

  211. void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
    212. 

  212. int rs400_gart_init(struct radeon_device *rdev);
    213. 

  213. int rs400_gart_enable(struct radeon_device *rdev);
    214. 

  214. void rs400_gart_adjust_size(struct radeon_device *rdev);
    215. 

  215. void rs400_gart_disable(struct radeon_device *rdev);
    216. 

  216. void rs400_gart_fini(struct radeon_device *rdev);
    217. 

  217. extern int rs400_mc_wait_for_idle(struct radeon_device *rdev);
    218. 

  218. 

  219. /*
    220. 

  220.  * rs600.
    221. 

  221.  */
    222. 

  222. extern int rs600_asic_reset(struct radeon_device *rdev);
    223. 

  223. extern int rs600_init(struct radeon_device *rdev);
    224. 

  224. extern void rs600_fini(struct radeon_device *rdev);
    225. 

  225. extern int rs600_suspend(struct radeon_device *rdev);
    226. 

  226. extern int rs600_resume(struct radeon_device *rdev);
    227. 

  227. int rs600_irq_set(struct radeon_device *rdev);
    228. 

  228. int rs600_irq_process(struct radeon_device *rdev);
    229. 

  229. void rs600_irq_disable(struct radeon_device *rdev);
    230. 

  230. u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc);
    231. 

  231. void rs600_gart_tlb_flush(struct radeon_device *rdev);
    232. 

  232. int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
    233. 

  233. uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg);
    234. 

  234. void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
    235. 

  235. void rs600_bandwidth_update(struct radeon_device *rdev);
    236. 

  236. void rs600_hpd_init(struct radeon_device *rdev);
    237. 

  237. void rs600_hpd_fini(struct radeon_device *rdev);
    238. 

  238. bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
    239. 

  239. void rs600_hpd_set_polarity(struct radeon_device *rdev,
    240. 

  240. 			    enum radeon_hpd_id hpd);
    241. 

  241. extern void rs600_pm_misc(struct radeon_device *rdev);
    242. 

  242. extern void rs600_pm_prepare(struct radeon_device *rdev);
    243. 

  243. extern void rs600_pm_finish(struct radeon_device *rdev);
    244. 

  244. extern void rs600_pre_page_flip(struct radeon_device *rdev, int crtc);
    245. 

  245. extern u32 rs600_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base);
    246. 

  246. extern void rs600_post_page_flip(struct radeon_device *rdev, int crtc);
    247. 

  247. void rs600_set_safe_registers(struct radeon_device *rdev);
    248. 

  248. extern void avivo_wait_for_vblank(struct radeon_device *rdev, int crtc);
    249. 

  249. extern int rs600_mc_wait_for_idle(struct radeon_device *rdev);
    250. 

  250. 

  251. /*
    252. 

  252.  * rs690,rs740
    253. 

  253.  */
    254. 

  254. int rs690_init(struct radeon_device *rdev);
    255. 

  255. void rs690_fini(struct radeon_device *rdev);
    256. 

  256. int rs690_resume(struct radeon_device *rdev);
    257. 

  257. int rs690_suspend(struct radeon_device *rdev);
    258. 

  258. uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg);
    259. 

  259. void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
    260. 

  260. void rs690_bandwidth_update(struct radeon_device *rdev);
    261. 

  261. void rs690_line_buffer_adjust(struct radeon_device *rdev,
    262. 

  262. 					struct drm_display_mode *mode1,
    263. 

  263. 					struct drm_display_mode *mode2);
    264. 

  264. extern int rs690_mc_wait_for_idle(struct radeon_device *rdev);
    265. 

  265. 

  266. /*
    267. 

  267.  * rv515
    268. 

  268.  */
    269. 

  269. struct rv515_mc_save {
    270. 

  270. 	u32 vga_render_control;
    271. 

  271. 	u32 vga_hdp_control;
    272. 

  272. 	bool crtc_enabled[2];
    273. 

  273. };
    274. 

  274. 

  275. int rv515_init(struct radeon_device *rdev);
    276. 

  276. void rv515_fini(struct radeon_device *rdev);
    277. 

  277. uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg);
    278. 

  278. void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
    279. 

  279. void rv515_ring_start(struct radeon_device *rdev, struct radeon_ring *ring);
    280. 

  280. void rv515_bandwidth_update(struct radeon_device *rdev);
    281. 

  281. int rv515_resume(struct radeon_device *rdev);
    282. 

  282. int rv515_suspend(struct radeon_device *rdev);
    283. 

  283. void rv515_bandwidth_avivo_update(struct radeon_device *rdev);
    284. 

  284. void rv515_vga_render_disable(struct radeon_device *rdev);
    285. 

  285. void rv515_set_safe_registers(struct radeon_device *rdev);
    286. 

  286. void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save);
    287. 

  287. void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save);
    288. 

  288. void rv515_clock_startup(struct radeon_device *rdev);
    289. 

  289. void rv515_debugfs(struct radeon_device *rdev);
    290. 

  290. int rv515_mc_wait_for_idle(struct radeon_device *rdev);
    291. 

  291. 

  292. /*
    293. 

  293.  * r520,rv530,rv560,rv570,r580
    294. 

  294.  */
    295. 

  295. int r520_init(struct radeon_device *rdev);
    296. 

  296. int r520_resume(struct radeon_device *rdev);
    297. 

  297. int r520_mc_wait_for_idle(struct radeon_device *rdev);
    298. 

  298. 

  299. /*
    300. 

  300.  * r600,rv610,rv630,rv620,rv635,rv670,rs780,rs880
    301. 

  301.  */
    302. 

  302. int r600_init(struct radeon_device *rdev);
    303. 

  303. void r600_fini(struct radeon_device *rdev);
    304. 

  304. int r600_suspend(struct radeon_device *rdev);
    305. 

  305. int r600_resume(struct radeon_device *rdev);
    306. 

  306. void r600_vga_set_state(struct radeon_device *rdev, bool state);
    307. 

  307. int r600_wb_init(struct radeon_device *rdev);
    308. 

  308. void r600_wb_fini(struct radeon_device *rdev);
    309. 

  309. void r600_pcie_gart_tlb_flush(struct radeon_device *rdev);
    310. 

  310. uint32_t r600_pciep_rreg(struct radeon_device *rdev, uint32_t reg);
    311. 

  311. void r600_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
    312. 

  312. int r600_cs_parse(struct radeon_cs_parser *p);
    313. 

  313. int r600_dma_cs_parse(struct radeon_cs_parser *p);
    314. 

  314. void r600_fence_ring_emit(struct radeon_device *rdev,
    315. 

  315. 			  struct radeon_fence *fence);
    316. 

  316. void r600_semaphore_ring_emit(struct radeon_device *rdev,
    317. 

  317. 			      struct radeon_ring *cp,
    318. 

  318. 			      struct radeon_semaphore *semaphore,
    319. 

  319. 			      bool emit_wait);
    320. 

  320. void r600_dma_fence_ring_emit(struct radeon_device *rdev,
    321. 

  321. 			      struct radeon_fence *fence);
    322. 

  322. void r600_dma_semaphore_ring_emit(struct radeon_device *rdev,
    323. 

  323. 				  struct radeon_ring *ring,
    324. 

  324. 				  struct radeon_semaphore *semaphore,
    325. 

  325. 				  bool emit_wait);
    326. 

  326. void r600_dma_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
    327. 

  327. bool r600_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
    328. 

  328. bool r600_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
    329. 

  329. int r600_asic_reset(struct radeon_device *rdev);
    330. 

  330. int r600_set_surface_reg(struct radeon_device *rdev, int reg,
    331. 

  331. 			 uint32_t tiling_flags, uint32_t pitch,
    332. 

  332. 			 uint32_t offset, uint32_t obj_size);
    333. 

  333. void r600_clear_surface_reg(struct radeon_device *rdev, int reg);
    334. 

  334. int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
    335. 

  335. int r600_dma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
    336. 

  336. void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
    337. 

  337. int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
    338. 

  338. int r600_dma_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
    339. 

  339. int r600_uvd_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
    340. 

  340. int r600_copy_blit(struct radeon_device *rdev,
    341. 

  341. 		   uint64_t src_offset, uint64_t dst_offset,
    342. 

  342. 		   unsigned num_gpu_pages, struct radeon_fence **fence);
    343. 

  343. int r600_copy_dma(struct radeon_device *rdev,
    344. 

  344. 		  uint64_t src_offset, uint64_t dst_offset,
    345. 

  345. 		  unsigned num_gpu_pages, struct radeon_fence **fence);
    346. 

  346. void r600_hpd_init(struct radeon_device *rdev);
    347. 

  347. void r600_hpd_fini(struct radeon_device *rdev);
    348. 

  348. bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
    349. 

  349. void r600_hpd_set_polarity(struct radeon_device *rdev,
    350. 

  350. 			   enum radeon_hpd_id hpd);
    351. 

  351. extern void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo);
    352. 

  352. extern bool r600_gui_idle(struct radeon_device *rdev);
    353. 

  353. extern void r600_pm_misc(struct radeon_device *rdev);
    354. 

  354. extern void r600_pm_init_profile(struct radeon_device *rdev);
    355. 

  355. extern void rs780_pm_init_profile(struct radeon_device *rdev);
    356. 

  356. extern uint32_t rs780_mc_rreg(struct radeon_device *rdev, uint32_t reg);
    357. 

  357. extern void rs780_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
    358. 

  358. extern void r600_pm_get_dynpm_state(struct radeon_device *rdev);
    359. 

  359. extern void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes);
    360. 

  360. extern int r600_get_pcie_lanes(struct radeon_device *rdev);
    361. 

  361. bool r600_card_posted(struct radeon_device *rdev);
    362. 

  362. void r600_cp_stop(struct radeon_device *rdev);
    363. 

  363. int r600_cp_start(struct radeon_device *rdev);
    364. 

  364. void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size);
    365. 

  365. int r600_cp_resume(struct radeon_device *rdev);
    366. 

  366. void r600_cp_fini(struct radeon_device *rdev);
    367. 

  367. int r600_count_pipe_bits(uint32_t val);
    368. 

  368. int r600_mc_wait_for_idle(struct radeon_device *rdev);
    369. 

  369. int r600_pcie_gart_init(struct radeon_device *rdev);
    370. 

  370. void r600_scratch_init(struct radeon_device *rdev);
    371. 

  371. int r600_blit_init(struct radeon_device *rdev);
    372. 

  372. void r600_blit_fini(struct radeon_device *rdev);
    373. 

  373. int r600_init_microcode(struct radeon_device *rdev);
    374. 

  374. /* r600 irq */
    375. 

  375. int r600_irq_process(struct radeon_device *rdev);
    376. 

  376. int r600_irq_init(struct radeon_device *rdev);
    377. 

  377. void r600_irq_fini(struct radeon_device *rdev);
    378. 

  378. void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size);
    379. 

  379. int r600_irq_set(struct radeon_device *rdev);
    380. 

  380. void r600_irq_suspend(struct radeon_device *rdev);
    381. 

  381. void r600_disable_interrupts(struct radeon_device *rdev);
    382. 

  382. void r600_rlc_stop(struct radeon_device *rdev);
    383. 

  383. /* r600 audio */
    384. 

  384. int r600_audio_init(struct radeon_device *rdev);
    385. 

  385. struct r600_audio r600_audio_status(struct radeon_device *rdev);
    386. 

  386. void r600_audio_fini(struct radeon_device *rdev);
    387. 

  387. int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder);
    388. 

  388. void r600_hdmi_update_audio_settings(struct drm_encoder *encoder);
    389. 

  389. void r600_hdmi_enable(struct drm_encoder *encoder, bool enable);
    390. 

  390. void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
    391. 

  391. /* r600 blit */
    392. 

  392. int r600_blit_prepare_copy(struct radeon_device *rdev, unsigned num_gpu_pages,
    393. 

  393. 			   struct radeon_fence **fence, struct radeon_sa_bo **vb,
    394. 

  394. 			   struct radeon_semaphore **sem);
    395. 

  395. void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence **fence,
    396. 

  396. 			 struct radeon_sa_bo *vb, struct radeon_semaphore *sem);
    397. 

  397. void r600_kms_blit_copy(struct radeon_device *rdev,
    398. 

  398. 			u64 src_gpu_addr, u64 dst_gpu_addr,
    399. 

  399. 			unsigned num_gpu_pages,
    400. 

  400. 			struct radeon_sa_bo *vb);
    401. 

  401. int r600_mc_wait_for_idle(struct radeon_device *rdev);
    402. 

  402. u32 r600_get_xclk(struct radeon_device *rdev);
    403. 

  403. uint64_t r600_get_gpu_clock_counter(struct radeon_device *rdev);
    404. 

  404. int rv6xx_get_temp(struct radeon_device *rdev);
    405. 

  405. int r600_dpm_pre_set_power_state(struct radeon_device *rdev);
    406. 

  406. void r600_dpm_post_set_power_state(struct radeon_device *rdev);
    407. 

  407. /* rv6xx dpm */
    408. 

  408. int rv6xx_dpm_init(struct radeon_device *rdev);
    409. 

  409. int rv6xx_dpm_enable(struct radeon_device *rdev);
    410. 

  410. void rv6xx_dpm_disable(struct radeon_device *rdev);
    411. 

  411. int rv6xx_dpm_set_power_state(struct radeon_device *rdev);
    412. 

  412. void rv6xx_setup_asic(struct radeon_device *rdev);
    413. 

  413. void rv6xx_dpm_display_configuration_changed(struct radeon_device *rdev);
    414. 

  414. void rv6xx_dpm_fini(struct radeon_device *rdev);
    415. 

  415. u32 rv6xx_dpm_get_sclk(struct radeon_device *rdev, bool low);
    416. 

  416. u32 rv6xx_dpm_get_mclk(struct radeon_device *rdev, bool low);
    417. 

  417. void rv6xx_dpm_print_power_state(struct radeon_device *rdev,
    418. 

  418. 				 struct radeon_ps *ps);
    419. 

  419. void rv6xx_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
    420. 

  420. 						       struct seq_file *m);
    421. 

  421. /* rs780 dpm */
    422. 

  422. int rs780_dpm_init(struct radeon_device *rdev);
    423. 

  423. int rs780_dpm_enable(struct radeon_device *rdev);
    424. 

  424. void rs780_dpm_disable(struct radeon_device *rdev);
    425. 

  425. int rs780_dpm_set_power_state(struct radeon_device *rdev);
    426. 

  426. void rs780_dpm_setup_asic(struct radeon_device *rdev);
    427. 

  427. void rs780_dpm_display_configuration_changed(struct radeon_device *rdev);
    428. 

  428. void rs780_dpm_fini(struct radeon_device *rdev);
    429. 

  429. u32 rs780_dpm_get_sclk(struct radeon_device *rdev, bool low);
    430. 

  430. u32 rs780_dpm_get_mclk(struct radeon_device *rdev, bool low);
    431. 

  431. void rs780_dpm_print_power_state(struct radeon_device *rdev,
    432. 

  432. 				 struct radeon_ps *ps);
    433. 

  433. 

  434. /* uvd */
    435. 

  435. int r600_uvd_init(struct radeon_device *rdev);
    436. 

  436. int r600_uvd_rbc_start(struct radeon_device *rdev);
    437. 

  437. void r600_uvd_rbc_stop(struct radeon_device *rdev);
    438. 

  438. int r600_uvd_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
    439. 

  439. void r600_uvd_fence_emit(struct radeon_device *rdev,
    440. 

  440. 			 struct radeon_fence *fence);
    441. 

  441. void r600_uvd_semaphore_emit(struct radeon_device *rdev,
    442. 

  442. 			     struct radeon_ring *ring,
    443. 

  443. 			     struct radeon_semaphore *semaphore,
    444. 

  444. 			     bool emit_wait);
    445. 

  445. void r600_uvd_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
    446. 

  446. 

  447. /*
    448. 

  448.  * rv770,rv730,rv710,rv740
    449. 

  449.  */
    450. 

  450. int rv770_init(struct radeon_device *rdev);
    451. 

  451. void rv770_fini(struct radeon_device *rdev);
    452. 

  452. int rv770_suspend(struct radeon_device *rdev);
    453. 

  453. int rv770_resume(struct radeon_device *rdev);
    454. 

  454. void rv770_pm_misc(struct radeon_device *rdev);
    455. 

  455. u32 rv770_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base);
    456. 

  456. void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
    457. 

  457. void r700_cp_stop(struct radeon_device *rdev);
    458. 

  458. void r700_cp_fini(struct radeon_device *rdev);
    459. 

  459. int rv770_copy_dma(struct radeon_device *rdev,
    460. 

  460. 		  uint64_t src_offset, uint64_t dst_offset,
    461. 

  461. 		  unsigned num_gpu_pages,
    462. 

  462. 		   struct radeon_fence **fence);
    463. 

  463. u32 rv770_get_xclk(struct radeon_device *rdev);
    464. 

  464. int rv770_uvd_resume(struct radeon_device *rdev);
    465. 

  465. int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
    466. 

  466. int rv770_get_temp(struct radeon_device *rdev);
    467. 

  467. /* rv7xx pm */
    468. 

  468. int rv770_dpm_init(struct radeon_device *rdev);
    469. 

  469. int rv770_dpm_enable(struct radeon_device *rdev);
    470. 

  470. void rv770_dpm_disable(struct radeon_device *rdev);
    471. 

  471. int rv770_dpm_set_power_state(struct radeon_device *rdev);
    472. 

  472. void rv770_dpm_setup_asic(struct radeon_device *rdev);
    473. 

  473. void rv770_dpm_display_configuration_changed(struct radeon_device *rdev);
    474. 

  474. void rv770_dpm_fini(struct radeon_device *rdev);
    475. 

  475. u32 rv770_dpm_get_sclk(struct radeon_device *rdev, bool low);
    476. 

  476. u32 rv770_dpm_get_mclk(struct radeon_device *rdev, bool low);
    477. 

  477. void rv770_dpm_print_power_state(struct radeon_device *rdev,
    478. 

  478. 				 struct radeon_ps *ps);
    479. 

  479. void rv770_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
    480. 

  480. 						       struct seq_file *m);
    481. 

  481. 

  482. /*
    483. 

  483.  * evergreen
    484. 

  484.  */
    485. 

  485. struct evergreen_mc_save {
    486. 

  486. 	u32 vga_render_control;
    487. 

  487. 	u32 vga_hdp_control;
    488. 

  488. 	bool crtc_enabled[RADEON_MAX_CRTCS];
    489. 

  489. };
    490. 

  490. 

  491. void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev);
    492. 

  492. int evergreen_init(struct radeon_device *rdev);
    493. 

  493. void evergreen_fini(struct radeon_device *rdev);
    494. 

  494. int evergreen_suspend(struct radeon_device *rdev);
    495. 

  495. int evergreen_resume(struct radeon_device *rdev);
    496. 

  496. bool evergreen_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
    497. 

  497. bool evergreen_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
    498. 

  498. int evergreen_asic_reset(struct radeon_device *rdev);
    499. 

  499. void evergreen_bandwidth_update(struct radeon_device *rdev);
    500. 

  500. void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
    501. 

  501. void evergreen_hpd_init(struct radeon_device *rdev);
    502. 

  502. void evergreen_hpd_fini(struct radeon_device *rdev);
    503. 

  503. bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
    504. 

  504. void evergreen_hpd_set_polarity(struct radeon_device *rdev,
    505. 

  505. 				enum radeon_hpd_id hpd);
    506. 

  506. u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc);
    507. 

  507. int evergreen_irq_set(struct radeon_device *rdev);
    508. 

  508. int evergreen_irq_process(struct radeon_device *rdev);
    509. 

  509. extern int evergreen_cs_parse(struct radeon_cs_parser *p);
    510. 

  510. extern int evergreen_dma_cs_parse(struct radeon_cs_parser *p);
    511. 

  511. extern void evergreen_pm_misc(struct radeon_device *rdev);
    512. 

  512. extern void evergreen_pm_prepare(struct radeon_device *rdev);
    513. 

  513. extern void evergreen_pm_finish(struct radeon_device *rdev);
    514. 

  514. extern void sumo_pm_init_profile(struct radeon_device *rdev);
    515. 

  515. extern void btc_pm_init_profile(struct radeon_device *rdev);
    516. 

  516. int sumo_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
    517. 

  517. int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
    518. 

  518. extern void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc);
    519. 

  519. extern u32 evergreen_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base);
    520. 

  520. extern void evergreen_post_page_flip(struct radeon_device *rdev, int crtc);
    521. 

  521. extern void dce4_wait_for_vblank(struct radeon_device *rdev, int crtc);
    522. 

  522. void evergreen_disable_interrupt_state(struct radeon_device *rdev);
    523. 

  523. int evergreen_blit_init(struct radeon_device *rdev);
    524. 

  524. int evergreen_mc_wait_for_idle(struct radeon_device *rdev);
    525. 

  525. void evergreen_dma_fence_ring_emit(struct radeon_device *rdev,
    526. 

  526. 				   struct radeon_fence *fence);
    527. 

  527. void evergreen_dma_ring_ib_execute(struct radeon_device *rdev,
    528. 

  528. 				   struct radeon_ib *ib);
    529. 

  529. int evergreen_copy_dma(struct radeon_device *rdev,
    530. 

  530. 		       uint64_t src_offset, uint64_t dst_offset,
    531. 

  531. 		       unsigned num_gpu_pages,
    532. 

  532. 		       struct radeon_fence **fence);
    533. 

  533. void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable);
    534. 

  534. void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
    535. 

  535. int evergreen_get_temp(struct radeon_device *rdev);
    536. 

  536. int sumo_get_temp(struct radeon_device *rdev);
    537. 

  537. int tn_get_temp(struct radeon_device *rdev);
    538. 

  538. int cypress_dpm_init(struct radeon_device *rdev);
    539. 

  539. void cypress_dpm_setup_asic(struct radeon_device *rdev);
    540. 

  540. int cypress_dpm_enable(struct radeon_device *rdev);
    541. 

  541. void cypress_dpm_disable(struct radeon_device *rdev);
    542. 

  542. int cypress_dpm_set_power_state(struct radeon_device *rdev);
    543. 

  543. void cypress_dpm_display_configuration_changed(struct radeon_device *rdev);
    544. 

  544. void cypress_dpm_fini(struct radeon_device *rdev);
    545. 

  545. int btc_dpm_init(struct radeon_device *rdev);
    546. 

  546. void btc_dpm_setup_asic(struct radeon_device *rdev);
    547. 

  547. int btc_dpm_enable(struct radeon_device *rdev);
    548. 

  548. void btc_dpm_disable(struct radeon_device *rdev);
    549. 

  549. int btc_dpm_pre_set_power_state(struct radeon_device *rdev);
    550. 

  550. int btc_dpm_set_power_state(struct radeon_device *rdev);
    551. 

  551. void btc_dpm_post_set_power_state(struct radeon_device *rdev);
    552. 

  552. void btc_dpm_fini(struct radeon_device *rdev);
    553. 

  553. u32 btc_dpm_get_sclk(struct radeon_device *rdev, bool low);
    554. 

  554. u32 btc_dpm_get_mclk(struct radeon_device *rdev, bool low);
    555. 

  555. int sumo_dpm_init(struct radeon_device *rdev);
    556. 

  556. int sumo_dpm_enable(struct radeon_device *rdev);
    557. 

  557. void sumo_dpm_disable(struct radeon_device *rdev);
    558. 

  558. int sumo_dpm_pre_set_power_state(struct radeon_device *rdev);
    559. 

  559. int sumo_dpm_set_power_state(struct radeon_device *rdev);
    560. 

  560. void sumo_dpm_post_set_power_state(struct radeon_device *rdev);
    561. 

  561. void sumo_dpm_setup_asic(struct radeon_device *rdev);
    562. 

  562. void sumo_dpm_display_configuration_changed(struct radeon_device *rdev);
    563. 

  563. void sumo_dpm_fini(struct radeon_device *rdev);
    564. 

  564. u32 sumo_dpm_get_sclk(struct radeon_device *rdev, bool low);
    565. 

  565. u32 sumo_dpm_get_mclk(struct radeon_device *rdev, bool low);
    566. 

  566. void sumo_dpm_print_power_state(struct radeon_device *rdev,
    567. 

  567. 				struct radeon_ps *ps);
    568. 

  568. void sumo_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
    569. 

  569. 						      struct seq_file *m);
    570. 

  570. 

  571. /*
    572. 

  572.  * cayman
    573. 

  573.  */
    574. 

  574. void cayman_fence_ring_emit(struct radeon_device *rdev,
    575. 

  575. 			    struct radeon_fence *fence);
    576. 

  576. void cayman_uvd_semaphore_emit(struct radeon_device *rdev,
    577. 

  577. 			       struct radeon_ring *ring,
    578. 

  578. 			       struct radeon_semaphore *semaphore,
    579. 

  579. 			       bool emit_wait);
    580. 

  580. void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev);
    581. 

  581. int cayman_init(struct radeon_device *rdev);
    582. 

  582. void cayman_fini(struct radeon_device *rdev);
    583. 

  583. int cayman_suspend(struct radeon_device *rdev);
    584. 

  584. int cayman_resume(struct radeon_device *rdev);
    585. 

  585. int cayman_asic_reset(struct radeon_device *rdev);
    586. 

  586. void cayman_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
    587. 

  587. int cayman_vm_init(struct radeon_device *rdev);
    588. 

  588. void cayman_vm_fini(struct radeon_device *rdev);
    589. 

  589. void cayman_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
    590. 

  590. uint32_t cayman_vm_page_flags(struct radeon_device *rdev, uint32_t flags);
    591. 

  591. void cayman_vm_set_page(struct radeon_device *rdev,
    592. 

  592. 			struct radeon_ib *ib,
    593. 

  593. 			uint64_t pe,
    594. 

  594. 			uint64_t addr, unsigned count,
    595. 

  595. 			uint32_t incr, uint32_t flags);
    596. 

  596. int evergreen_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib);
    597. 

  597. int evergreen_dma_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib);
    598. 

  598. void cayman_dma_ring_ib_execute(struct radeon_device *rdev,
    599. 

  599. 				struct radeon_ib *ib);
    600. 

  600. bool cayman_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
    601. 

  601. bool cayman_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
    602. 

  602. void cayman_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
    603. 

  603. 

  604. int ni_dpm_init(struct radeon_device *rdev);
    605. 

  605. void ni_dpm_setup_asic(struct radeon_device *rdev);
    606. 

  606. int ni_dpm_enable(struct radeon_device *rdev);
    607. 

  607. void ni_dpm_disable(struct radeon_device *rdev);
    608. 

  608. int ni_dpm_pre_set_power_state(struct radeon_device *rdev);
    609. 

  609. int ni_dpm_set_power_state(struct radeon_device *rdev);
    610. 

  610. void ni_dpm_post_set_power_state(struct radeon_device *rdev);
    611. 

  611. void ni_dpm_fini(struct radeon_device *rdev);
    612. 

  612. u32 ni_dpm_get_sclk(struct radeon_device *rdev, bool low);
    613. 

  613. u32 ni_dpm_get_mclk(struct radeon_device *rdev, bool low);
    614. 

  614. void ni_dpm_print_power_state(struct radeon_device *rdev,
    615. 

  615. 			      struct radeon_ps *ps);
    616. 

  616. void ni_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
    617. 

  617. 						    struct seq_file *m);
    618. 

  618. int trinity_dpm_init(struct radeon_device *rdev);
    619. 

  619. int trinity_dpm_enable(struct radeon_device *rdev);
    620. 

  620. void trinity_dpm_disable(struct radeon_device *rdev);
    621. 

  621. int trinity_dpm_pre_set_power_state(struct radeon_device *rdev);
    622. 

  622. int trinity_dpm_set_power_state(struct radeon_device *rdev);
    623. 

  623. void trinity_dpm_post_set_power_state(struct radeon_device *rdev);
    624. 

  624. void trinity_dpm_setup_asic(struct radeon_device *rdev);
    625. 

  625. void trinity_dpm_display_configuration_changed(struct radeon_device *rdev);
    626. 

  626. void trinity_dpm_fini(struct radeon_device *rdev);
    627. 

  627. u32 trinity_dpm_get_sclk(struct radeon_device *rdev, bool low);
    628. 

  628. u32 trinity_dpm_get_mclk(struct radeon_device *rdev, bool low);
    629. 

  629. void trinity_dpm_print_power_state(struct radeon_device *rdev,
    630. 

  630. 				   struct radeon_ps *ps);
    631. 

  631. void trinity_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
    632. 

  632. 							 struct seq_file *m);
    633. 

  633. 

  634. /* DCE6 - SI */
    635. 

  635. void dce6_bandwidth_update(struct radeon_device *rdev);
    636. 

  636. 

  637. /*
    638. 

  638.  * si
    639. 

  639.  */
    640. 

  640. void si_fence_ring_emit(struct radeon_device *rdev,
    641. 

  641. 			struct radeon_fence *fence);
    642. 

  642. void si_pcie_gart_tlb_flush(struct radeon_device *rdev);
    643. 

  643. int si_init(struct radeon_device *rdev);
    644. 

  644. void si_fini(struct radeon_device *rdev);
    645. 

  645. int si_suspend(struct radeon_device *rdev);
    646. 

  646. int si_resume(struct radeon_device *rdev);
    647. 

  647. bool si_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
    648. 

  648. bool si_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
    649. 

  649. int si_asic_reset(struct radeon_device *rdev);
    650. 

  650. void si_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
    651. 

  651. int si_irq_set(struct radeon_device *rdev);
    652. 

  652. int si_irq_process(struct radeon_device *rdev);
    653. 

  653. int si_vm_init(struct radeon_device *rdev);
    654. 

  654. void si_vm_fini(struct radeon_device *rdev);
    655. 

  655. void si_vm_set_page(struct radeon_device *rdev,
    656. 

  656. 		    struct radeon_ib *ib,
    657. 

  657. 		    uint64_t pe,
    658. 

  658. 		    uint64_t addr, unsigned count,
    659. 

  659. 		    uint32_t incr, uint32_t flags);
    660. 

  660. void si_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
    661. 

  661. int si_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib);
    662. 

  662. int si_copy_dma(struct radeon_device *rdev,
    663. 

  663. 		uint64_t src_offset, uint64_t dst_offset,
    664. 

  664. 		unsigned num_gpu_pages,
    665. 

  665. 		struct radeon_fence **fence);
    666. 

  666. void si_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
    667. 

  667. u32 si_get_xclk(struct radeon_device *rdev);
    668. 

  668. uint64_t si_get_gpu_clock_counter(struct radeon_device *rdev);
    669. 

  669. int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
    670. 

  670. int si_get_temp(struct radeon_device *rdev);
    671. 

  671. int si_dpm_init(struct radeon_device *rdev);
    672. 

  672. void si_dpm_setup_asic(struct radeon_device *rdev);
    673. 

  673. int si_dpm_enable(struct radeon_device *rdev);
    674. 

  674. void si_dpm_disable(struct radeon_device *rdev);
    675. 

  675. int si_dpm_pre_set_power_state(struct radeon_device *rdev);
    676. 

  676. int si_dpm_set_power_state(struct radeon_device *rdev);
    677. 

  677. void si_dpm_post_set_power_state(struct radeon_device *rdev);
    678. 

  678. void si_dpm_fini(struct radeon_device *rdev);
    679. 

  679. void si_dpm_display_configuration_changed(struct radeon_device *rdev);
    680. 

  680. void si_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
    681. 

  681. 						    struct seq_file *m);
    682. 

  682. 

  683. /* DCE8 - CIK */
    684. 

  684. void dce8_bandwidth_update(struct radeon_device *rdev);
    685. 

  685. 

  686. /*
    687. 

  687.  * cik
    688. 

  688.  */
    689. 

  689. uint64_t cik_get_gpu_clock_counter(struct radeon_device *rdev);
    690. 

  690. u32 cik_get_xclk(struct radeon_device *rdev);
    691. 

  691. uint32_t cik_pciep_rreg(struct radeon_device *rdev, uint32_t reg);
    692. 

  692. void cik_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
    693. 

  693. int cik_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
    694. 

  694. int cik_uvd_resume(struct radeon_device *rdev);
    695. 

  695. void cik_sdma_fence_ring_emit(struct radeon_device *rdev,
    696. 

  696. 			      struct radeon_fence *fence);
    697. 

  697. void cik_sdma_semaphore_ring_emit(struct radeon_device *rdev,
    698. 

  698. 				  struct radeon_ring *ring,
    699. 

  699. 				  struct radeon_semaphore *semaphore,
    700. 

  700. 				  bool emit_wait);
    701. 

  701. void cik_sdma_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
    702. 

  702. int cik_copy_dma(struct radeon_device *rdev,
    703. 

  703. 		 uint64_t src_offset, uint64_t dst_offset,
    704. 

  704. 		 unsigned num_gpu_pages,
    705. 

  705. 		 struct radeon_fence **fence);
    706. 

  706. int cik_sdma_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
    707. 

  707. int cik_sdma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
    708. 

  708. bool cik_sdma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
    709. 

  709. void cik_fence_gfx_ring_emit(struct radeon_device *rdev,
    710. 

  710. 			     struct radeon_fence *fence);
    711. 

  711. void cik_fence_compute_ring_emit(struct radeon_device *rdev,
    712. 

  712. 				 struct radeon_fence *fence);
    713. 

  713. void cik_semaphore_ring_emit(struct radeon_device *rdev,
    714. 

  714. 			     struct radeon_ring *cp,
    715. 

  715. 			     struct radeon_semaphore *semaphore,
    716. 

  716. 			     bool emit_wait);
    717. 

  717. void cik_pcie_gart_tlb_flush(struct radeon_device *rdev);
    718. 

  718. int cik_init(struct radeon_device *rdev);
    719. 

  719. void cik_fini(struct radeon_device *rdev);
    720. 

  720. int cik_suspend(struct radeon_device *rdev);
    721. 

  721. int cik_resume(struct radeon_device *rdev);
    722. 

  722. bool cik_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
    723. 

  723. int cik_asic_reset(struct radeon_device *rdev);
    724. 

  724. void cik_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
    725. 

  725. int cik_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
    726. 

  726. int cik_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
    727. 

  727. int cik_irq_set(struct radeon_device *rdev);
    728. 

  728. int cik_irq_process(struct radeon_device *rdev);
    729. 

  729. int cik_vm_init(struct radeon_device *rdev);
    730. 

  730. void cik_vm_fini(struct radeon_device *rdev);
    731. 

  731. void cik_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
    732. 

  732. void cik_vm_set_page(struct radeon_device *rdev,
    733. 

  733. 		     struct radeon_ib *ib,
    734. 

  734. 		     uint64_t pe,
    735. 

  735. 		     uint64_t addr, unsigned count,
    736. 

  736. 		     uint32_t incr, uint32_t flags);
    737. 

  737. void cik_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
    738. 

  738. int cik_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib);
    739. 

  739. u32 cik_compute_ring_get_rptr(struct radeon_device *rdev,
    740. 

  740. 			      struct radeon_ring *ring);
    741. 

  741. u32 cik_compute_ring_get_wptr(struct radeon_device *rdev,
    742. 

  742. 			      struct radeon_ring *ring);
    743. 

  743. void cik_compute_ring_set_wptr(struct radeon_device *rdev,
    744. 

  744. 			       struct radeon_ring *ring);
    745. 

  745. 

  746. #endif
    747.