intel_ddi.c 37 KB

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  1. /*
  2. * Copyright © 2012 Intel Corporation
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice (including the next
  12. * paragraph) shall be included in all copies or substantial portions of the
  13. * Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  18. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21. * IN THE SOFTWARE.
  22. *
  23. * Authors:
  24. * Eugeni Dodonov <eugeni.dodonov@intel.com>
  25. *
  26. */
  27. #include "i915_drv.h"
  28. #include "intel_drv.h"
  29. /* HDMI/DVI modes ignore everything but the last 2 items. So we share
  30. * them for both DP and FDI transports, allowing those ports to
  31. * automatically adapt to HDMI connections as well
  32. */
  33. static const u32 hsw_ddi_translations_dp[] = {
  34. 0x00FFFFFF, 0x0006000E, /* DP parameters */
  35. 0x00D75FFF, 0x0005000A,
  36. 0x00C30FFF, 0x00040006,
  37. 0x80AAAFFF, 0x000B0000,
  38. 0x00FFFFFF, 0x0005000A,
  39. 0x00D75FFF, 0x000C0004,
  40. 0x80C30FFF, 0x000B0000,
  41. 0x00FFFFFF, 0x00040006,
  42. 0x80D75FFF, 0x000B0000,
  43. 0x00FFFFFF, 0x00040006 /* HDMI parameters */
  44. };
  45. static const u32 hsw_ddi_translations_fdi[] = {
  46. 0x00FFFFFF, 0x0007000E, /* FDI parameters */
  47. 0x00D75FFF, 0x000F000A,
  48. 0x00C30FFF, 0x00060006,
  49. 0x00AAAFFF, 0x001E0000,
  50. 0x00FFFFFF, 0x000F000A,
  51. 0x00D75FFF, 0x00160004,
  52. 0x00C30FFF, 0x001E0000,
  53. 0x00FFFFFF, 0x00060006,
  54. 0x00D75FFF, 0x001E0000,
  55. 0x00FFFFFF, 0x00040006 /* HDMI parameters */
  56. };
  57. static enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder)
  58. {
  59. struct drm_encoder *encoder = &intel_encoder->base;
  60. int type = intel_encoder->type;
  61. if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP ||
  62. type == INTEL_OUTPUT_HDMI || type == INTEL_OUTPUT_UNKNOWN) {
  63. struct intel_digital_port *intel_dig_port =
  64. enc_to_dig_port(encoder);
  65. return intel_dig_port->port;
  66. } else if (type == INTEL_OUTPUT_ANALOG) {
  67. return PORT_E;
  68. } else {
  69. DRM_ERROR("Invalid DDI encoder type %d\n", type);
  70. BUG();
  71. }
  72. }
  73. /* On Haswell, DDI port buffers must be programmed with correct values
  74. * in advance. The buffer values are different for FDI and DP modes,
  75. * but the HDMI/DVI fields are shared among those. So we program the DDI
  76. * in either FDI or DP modes only, as HDMI connections will work with both
  77. * of those
  78. */
  79. static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port,
  80. bool use_fdi_mode)
  81. {
  82. struct drm_i915_private *dev_priv = dev->dev_private;
  83. u32 reg;
  84. int i;
  85. const u32 *ddi_translations = ((use_fdi_mode) ?
  86. hsw_ddi_translations_fdi :
  87. hsw_ddi_translations_dp);
  88. DRM_DEBUG_DRIVER("Initializing DDI buffers for port %c in %s mode\n",
  89. port_name(port),
  90. use_fdi_mode ? "FDI" : "DP");
  91. WARN((use_fdi_mode && (port != PORT_E)),
  92. "Programming port %c in FDI mode, this probably will not work.\n",
  93. port_name(port));
  94. for (i=0, reg=DDI_BUF_TRANS(port); i < ARRAY_SIZE(hsw_ddi_translations_fdi); i++) {
  95. I915_WRITE(reg, ddi_translations[i]);
  96. reg += 4;
  97. }
  98. }
  99. /* Program DDI buffers translations for DP. By default, program ports A-D in DP
  100. * mode and port E for FDI.
  101. */
  102. void intel_prepare_ddi(struct drm_device *dev)
  103. {
  104. int port;
  105. if (!HAS_DDI(dev))
  106. return;
  107. for (port = PORT_A; port < PORT_E; port++)
  108. intel_prepare_ddi_buffers(dev, port, false);
  109. /* DDI E is the suggested one to work in FDI mode, so program is as such
  110. * by default. It will have to be re-programmed in case a digital DP
  111. * output will be detected on it
  112. */
  113. intel_prepare_ddi_buffers(dev, PORT_E, true);
  114. }
  115. static const long hsw_ddi_buf_ctl_values[] = {
  116. DDI_BUF_EMP_400MV_0DB_HSW,
  117. DDI_BUF_EMP_400MV_3_5DB_HSW,
  118. DDI_BUF_EMP_400MV_6DB_HSW,
  119. DDI_BUF_EMP_400MV_9_5DB_HSW,
  120. DDI_BUF_EMP_600MV_0DB_HSW,
  121. DDI_BUF_EMP_600MV_3_5DB_HSW,
  122. DDI_BUF_EMP_600MV_6DB_HSW,
  123. DDI_BUF_EMP_800MV_0DB_HSW,
  124. DDI_BUF_EMP_800MV_3_5DB_HSW
  125. };
  126. static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
  127. enum port port)
  128. {
  129. uint32_t reg = DDI_BUF_CTL(port);
  130. int i;
  131. for (i = 0; i < 8; i++) {
  132. udelay(1);
  133. if (I915_READ(reg) & DDI_BUF_IS_IDLE)
  134. return;
  135. }
  136. DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
  137. }
  138. /* Starting with Haswell, different DDI ports can work in FDI mode for
  139. * connection to the PCH-located connectors. For this, it is necessary to train
  140. * both the DDI port and PCH receiver for the desired DDI buffer settings.
  141. *
  142. * The recommended port to work in FDI mode is DDI E, which we use here. Also,
  143. * please note that when FDI mode is active on DDI E, it shares 2 lines with
  144. * DDI A (which is used for eDP)
  145. */
  146. void hsw_fdi_link_train(struct drm_crtc *crtc)
  147. {
  148. struct drm_device *dev = crtc->dev;
  149. struct drm_i915_private *dev_priv = dev->dev_private;
  150. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  151. u32 temp, i, rx_ctl_val;
  152. /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
  153. * mode set "sequence for CRT port" document:
  154. * - TP1 to TP2 time with the default value
  155. * - FDI delay to 90h
  156. *
  157. * WaFDIAutoLinkSetTimingOverrride:hsw
  158. */
  159. I915_WRITE(_FDI_RXA_MISC, FDI_RX_PWRDN_LANE1_VAL(2) |
  160. FDI_RX_PWRDN_LANE0_VAL(2) |
  161. FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
  162. /* Enable the PCH Receiver FDI PLL */
  163. rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
  164. FDI_RX_PLL_ENABLE |
  165. FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
  166. I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
  167. POSTING_READ(_FDI_RXA_CTL);
  168. udelay(220);
  169. /* Switch from Rawclk to PCDclk */
  170. rx_ctl_val |= FDI_PCDCLK;
  171. I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
  172. /* Configure Port Clock Select */
  173. I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->ddi_pll_sel);
  174. /* Start the training iterating through available voltages and emphasis,
  175. * testing each value twice. */
  176. for (i = 0; i < ARRAY_SIZE(hsw_ddi_buf_ctl_values) * 2; i++) {
  177. /* Configure DP_TP_CTL with auto-training */
  178. I915_WRITE(DP_TP_CTL(PORT_E),
  179. DP_TP_CTL_FDI_AUTOTRAIN |
  180. DP_TP_CTL_ENHANCED_FRAME_ENABLE |
  181. DP_TP_CTL_LINK_TRAIN_PAT1 |
  182. DP_TP_CTL_ENABLE);
  183. /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
  184. * DDI E does not support port reversal, the functionality is
  185. * achieved on the PCH side in FDI_RX_CTL, so no need to set the
  186. * port reversal bit */
  187. I915_WRITE(DDI_BUF_CTL(PORT_E),
  188. DDI_BUF_CTL_ENABLE |
  189. ((intel_crtc->config.fdi_lanes - 1) << 1) |
  190. hsw_ddi_buf_ctl_values[i / 2]);
  191. POSTING_READ(DDI_BUF_CTL(PORT_E));
  192. udelay(600);
  193. /* Program PCH FDI Receiver TU */
  194. I915_WRITE(_FDI_RXA_TUSIZE1, TU_SIZE(64));
  195. /* Enable PCH FDI Receiver with auto-training */
  196. rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
  197. I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
  198. POSTING_READ(_FDI_RXA_CTL);
  199. /* Wait for FDI receiver lane calibration */
  200. udelay(30);
  201. /* Unset FDI_RX_MISC pwrdn lanes */
  202. temp = I915_READ(_FDI_RXA_MISC);
  203. temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
  204. I915_WRITE(_FDI_RXA_MISC, temp);
  205. POSTING_READ(_FDI_RXA_MISC);
  206. /* Wait for FDI auto training time */
  207. udelay(5);
  208. temp = I915_READ(DP_TP_STATUS(PORT_E));
  209. if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
  210. DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
  211. /* Enable normal pixel sending for FDI */
  212. I915_WRITE(DP_TP_CTL(PORT_E),
  213. DP_TP_CTL_FDI_AUTOTRAIN |
  214. DP_TP_CTL_LINK_TRAIN_NORMAL |
  215. DP_TP_CTL_ENHANCED_FRAME_ENABLE |
  216. DP_TP_CTL_ENABLE);
  217. return;
  218. }
  219. temp = I915_READ(DDI_BUF_CTL(PORT_E));
  220. temp &= ~DDI_BUF_CTL_ENABLE;
  221. I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
  222. POSTING_READ(DDI_BUF_CTL(PORT_E));
  223. /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
  224. temp = I915_READ(DP_TP_CTL(PORT_E));
  225. temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
  226. temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
  227. I915_WRITE(DP_TP_CTL(PORT_E), temp);
  228. POSTING_READ(DP_TP_CTL(PORT_E));
  229. intel_wait_ddi_buf_idle(dev_priv, PORT_E);
  230. rx_ctl_val &= ~FDI_RX_ENABLE;
  231. I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
  232. POSTING_READ(_FDI_RXA_CTL);
  233. /* Reset FDI_RX_MISC pwrdn lanes */
  234. temp = I915_READ(_FDI_RXA_MISC);
  235. temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
  236. temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
  237. I915_WRITE(_FDI_RXA_MISC, temp);
  238. POSTING_READ(_FDI_RXA_MISC);
  239. }
  240. DRM_ERROR("FDI link training failed!\n");
  241. }
  242. static void intel_ddi_mode_set(struct drm_encoder *encoder,
  243. struct drm_display_mode *mode,
  244. struct drm_display_mode *adjusted_mode)
  245. {
  246. struct drm_crtc *crtc = encoder->crtc;
  247. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  248. struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
  249. int port = intel_ddi_get_encoder_port(intel_encoder);
  250. int pipe = intel_crtc->pipe;
  251. int type = intel_encoder->type;
  252. DRM_DEBUG_KMS("Preparing DDI mode on port %c, pipe %c\n",
  253. port_name(port), pipe_name(pipe));
  254. intel_crtc->eld_vld = false;
  255. if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
  256. struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
  257. struct intel_digital_port *intel_dig_port =
  258. enc_to_dig_port(encoder);
  259. intel_dp->DP = intel_dig_port->port_reversal |
  260. DDI_BUF_CTL_ENABLE | DDI_BUF_EMP_400MV_0DB_HSW;
  261. intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
  262. if (intel_dp->has_audio) {
  263. DRM_DEBUG_DRIVER("DP audio on pipe %c on DDI\n",
  264. pipe_name(intel_crtc->pipe));
  265. /* write eld */
  266. DRM_DEBUG_DRIVER("DP audio: write eld information\n");
  267. intel_write_eld(encoder, adjusted_mode);
  268. }
  269. intel_dp_init_link_config(intel_dp);
  270. } else if (type == INTEL_OUTPUT_HDMI) {
  271. struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
  272. if (intel_hdmi->has_audio) {
  273. /* Proper support for digital audio needs a new logic
  274. * and a new set of registers, so we leave it for future
  275. * patch bombing.
  276. */
  277. DRM_DEBUG_DRIVER("HDMI audio on pipe %c on DDI\n",
  278. pipe_name(intel_crtc->pipe));
  279. /* write eld */
  280. DRM_DEBUG_DRIVER("HDMI audio: write eld information\n");
  281. intel_write_eld(encoder, adjusted_mode);
  282. }
  283. intel_hdmi->set_infoframes(encoder, adjusted_mode);
  284. }
  285. }
  286. static struct intel_encoder *
  287. intel_ddi_get_crtc_encoder(struct drm_crtc *crtc)
  288. {
  289. struct drm_device *dev = crtc->dev;
  290. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  291. struct intel_encoder *intel_encoder, *ret = NULL;
  292. int num_encoders = 0;
  293. for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
  294. ret = intel_encoder;
  295. num_encoders++;
  296. }
  297. if (num_encoders != 1)
  298. WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
  299. pipe_name(intel_crtc->pipe));
  300. BUG_ON(ret == NULL);
  301. return ret;
  302. }
  303. void intel_ddi_put_crtc_pll(struct drm_crtc *crtc)
  304. {
  305. struct drm_i915_private *dev_priv = crtc->dev->dev_private;
  306. struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
  307. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  308. uint32_t val;
  309. switch (intel_crtc->ddi_pll_sel) {
  310. case PORT_CLK_SEL_SPLL:
  311. plls->spll_refcount--;
  312. if (plls->spll_refcount == 0) {
  313. DRM_DEBUG_KMS("Disabling SPLL\n");
  314. val = I915_READ(SPLL_CTL);
  315. WARN_ON(!(val & SPLL_PLL_ENABLE));
  316. I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE);
  317. POSTING_READ(SPLL_CTL);
  318. }
  319. break;
  320. case PORT_CLK_SEL_WRPLL1:
  321. plls->wrpll1_refcount--;
  322. if (plls->wrpll1_refcount == 0) {
  323. DRM_DEBUG_KMS("Disabling WRPLL 1\n");
  324. val = I915_READ(WRPLL_CTL1);
  325. WARN_ON(!(val & WRPLL_PLL_ENABLE));
  326. I915_WRITE(WRPLL_CTL1, val & ~WRPLL_PLL_ENABLE);
  327. POSTING_READ(WRPLL_CTL1);
  328. }
  329. break;
  330. case PORT_CLK_SEL_WRPLL2:
  331. plls->wrpll2_refcount--;
  332. if (plls->wrpll2_refcount == 0) {
  333. DRM_DEBUG_KMS("Disabling WRPLL 2\n");
  334. val = I915_READ(WRPLL_CTL2);
  335. WARN_ON(!(val & WRPLL_PLL_ENABLE));
  336. I915_WRITE(WRPLL_CTL2, val & ~WRPLL_PLL_ENABLE);
  337. POSTING_READ(WRPLL_CTL2);
  338. }
  339. break;
  340. }
  341. WARN(plls->spll_refcount < 0, "Invalid SPLL refcount\n");
  342. WARN(plls->wrpll1_refcount < 0, "Invalid WRPLL1 refcount\n");
  343. WARN(plls->wrpll2_refcount < 0, "Invalid WRPLL2 refcount\n");
  344. intel_crtc->ddi_pll_sel = PORT_CLK_SEL_NONE;
  345. }
  346. #define LC_FREQ 2700
  347. #define LC_FREQ_2K (LC_FREQ * 2000)
  348. #define P_MIN 2
  349. #define P_MAX 64
  350. #define P_INC 2
  351. /* Constraints for PLL good behavior */
  352. #define REF_MIN 48
  353. #define REF_MAX 400
  354. #define VCO_MIN 2400
  355. #define VCO_MAX 4800
  356. #define ABS_DIFF(a, b) ((a > b) ? (a - b) : (b - a))
  357. struct wrpll_rnp {
  358. unsigned p, n2, r2;
  359. };
  360. static unsigned wrpll_get_budget_for_freq(int clock)
  361. {
  362. unsigned budget;
  363. switch (clock) {
  364. case 25175000:
  365. case 25200000:
  366. case 27000000:
  367. case 27027000:
  368. case 37762500:
  369. case 37800000:
  370. case 40500000:
  371. case 40541000:
  372. case 54000000:
  373. case 54054000:
  374. case 59341000:
  375. case 59400000:
  376. case 72000000:
  377. case 74176000:
  378. case 74250000:
  379. case 81000000:
  380. case 81081000:
  381. case 89012000:
  382. case 89100000:
  383. case 108000000:
  384. case 108108000:
  385. case 111264000:
  386. case 111375000:
  387. case 148352000:
  388. case 148500000:
  389. case 162000000:
  390. case 162162000:
  391. case 222525000:
  392. case 222750000:
  393. case 296703000:
  394. case 297000000:
  395. budget = 0;
  396. break;
  397. case 233500000:
  398. case 245250000:
  399. case 247750000:
  400. case 253250000:
  401. case 298000000:
  402. budget = 1500;
  403. break;
  404. case 169128000:
  405. case 169500000:
  406. case 179500000:
  407. case 202000000:
  408. budget = 2000;
  409. break;
  410. case 256250000:
  411. case 262500000:
  412. case 270000000:
  413. case 272500000:
  414. case 273750000:
  415. case 280750000:
  416. case 281250000:
  417. case 286000000:
  418. case 291750000:
  419. budget = 4000;
  420. break;
  421. case 267250000:
  422. case 268500000:
  423. budget = 5000;
  424. break;
  425. default:
  426. budget = 1000;
  427. break;
  428. }
  429. return budget;
  430. }
  431. static void wrpll_update_rnp(uint64_t freq2k, unsigned budget,
  432. unsigned r2, unsigned n2, unsigned p,
  433. struct wrpll_rnp *best)
  434. {
  435. uint64_t a, b, c, d, diff, diff_best;
  436. /* No best (r,n,p) yet */
  437. if (best->p == 0) {
  438. best->p = p;
  439. best->n2 = n2;
  440. best->r2 = r2;
  441. return;
  442. }
  443. /*
  444. * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to
  445. * freq2k.
  446. *
  447. * delta = 1e6 *
  448. * abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) /
  449. * freq2k;
  450. *
  451. * and we would like delta <= budget.
  452. *
  453. * If the discrepancy is above the PPM-based budget, always prefer to
  454. * improve upon the previous solution. However, if you're within the
  455. * budget, try to maximize Ref * VCO, that is N / (P * R^2).
  456. */
  457. a = freq2k * budget * p * r2;
  458. b = freq2k * budget * best->p * best->r2;
  459. diff = ABS_DIFF((freq2k * p * r2), (LC_FREQ_2K * n2));
  460. diff_best = ABS_DIFF((freq2k * best->p * best->r2),
  461. (LC_FREQ_2K * best->n2));
  462. c = 1000000 * diff;
  463. d = 1000000 * diff_best;
  464. if (a < c && b < d) {
  465. /* If both are above the budget, pick the closer */
  466. if (best->p * best->r2 * diff < p * r2 * diff_best) {
  467. best->p = p;
  468. best->n2 = n2;
  469. best->r2 = r2;
  470. }
  471. } else if (a >= c && b < d) {
  472. /* If A is below the threshold but B is above it? Update. */
  473. best->p = p;
  474. best->n2 = n2;
  475. best->r2 = r2;
  476. } else if (a >= c && b >= d) {
  477. /* Both are below the limit, so pick the higher n2/(r2*r2) */
  478. if (n2 * best->r2 * best->r2 > best->n2 * r2 * r2) {
  479. best->p = p;
  480. best->n2 = n2;
  481. best->r2 = r2;
  482. }
  483. }
  484. /* Otherwise a < c && b >= d, do nothing */
  485. }
  486. static void
  487. intel_ddi_calculate_wrpll(int clock /* in Hz */,
  488. unsigned *r2_out, unsigned *n2_out, unsigned *p_out)
  489. {
  490. uint64_t freq2k;
  491. unsigned p, n2, r2;
  492. struct wrpll_rnp best = { 0, 0, 0 };
  493. unsigned budget;
  494. freq2k = clock / 100;
  495. budget = wrpll_get_budget_for_freq(clock);
  496. /* Special case handling for 540 pixel clock: bypass WR PLL entirely
  497. * and directly pass the LC PLL to it. */
  498. if (freq2k == 5400000) {
  499. *n2_out = 2;
  500. *p_out = 1;
  501. *r2_out = 2;
  502. return;
  503. }
  504. /*
  505. * Ref = LC_FREQ / R, where Ref is the actual reference input seen by
  506. * the WR PLL.
  507. *
  508. * We want R so that REF_MIN <= Ref <= REF_MAX.
  509. * Injecting R2 = 2 * R gives:
  510. * REF_MAX * r2 > LC_FREQ * 2 and
  511. * REF_MIN * r2 < LC_FREQ * 2
  512. *
  513. * Which means the desired boundaries for r2 are:
  514. * LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN
  515. *
  516. */
  517. for (r2 = LC_FREQ * 2 / REF_MAX + 1;
  518. r2 <= LC_FREQ * 2 / REF_MIN;
  519. r2++) {
  520. /*
  521. * VCO = N * Ref, that is: VCO = N * LC_FREQ / R
  522. *
  523. * Once again we want VCO_MIN <= VCO <= VCO_MAX.
  524. * Injecting R2 = 2 * R and N2 = 2 * N, we get:
  525. * VCO_MAX * r2 > n2 * LC_FREQ and
  526. * VCO_MIN * r2 < n2 * LC_FREQ)
  527. *
  528. * Which means the desired boundaries for n2 are:
  529. * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ
  530. */
  531. for (n2 = VCO_MIN * r2 / LC_FREQ + 1;
  532. n2 <= VCO_MAX * r2 / LC_FREQ;
  533. n2++) {
  534. for (p = P_MIN; p <= P_MAX; p += P_INC)
  535. wrpll_update_rnp(freq2k, budget,
  536. r2, n2, p, &best);
  537. }
  538. }
  539. *n2_out = best.n2;
  540. *p_out = best.p;
  541. *r2_out = best.r2;
  542. DRM_DEBUG_KMS("WRPLL: %dHz refresh rate with p=%d, n2=%d r2=%d\n",
  543. clock, *p_out, *n2_out, *r2_out);
  544. }
  545. bool intel_ddi_pll_mode_set(struct drm_crtc *crtc)
  546. {
  547. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  548. struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
  549. struct drm_encoder *encoder = &intel_encoder->base;
  550. struct drm_i915_private *dev_priv = crtc->dev->dev_private;
  551. struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
  552. int type = intel_encoder->type;
  553. enum pipe pipe = intel_crtc->pipe;
  554. uint32_t reg, val;
  555. int clock = intel_crtc->config.port_clock;
  556. /* TODO: reuse PLLs when possible (compare values) */
  557. intel_ddi_put_crtc_pll(crtc);
  558. if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
  559. struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
  560. switch (intel_dp->link_bw) {
  561. case DP_LINK_BW_1_62:
  562. intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
  563. break;
  564. case DP_LINK_BW_2_7:
  565. intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
  566. break;
  567. case DP_LINK_BW_5_4:
  568. intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
  569. break;
  570. default:
  571. DRM_ERROR("Link bandwidth %d unsupported\n",
  572. intel_dp->link_bw);
  573. return false;
  574. }
  575. /* We don't need to turn any PLL on because we'll use LCPLL. */
  576. return true;
  577. } else if (type == INTEL_OUTPUT_HDMI) {
  578. unsigned p, n2, r2;
  579. if (plls->wrpll1_refcount == 0) {
  580. DRM_DEBUG_KMS("Using WRPLL 1 on pipe %c\n",
  581. pipe_name(pipe));
  582. plls->wrpll1_refcount++;
  583. reg = WRPLL_CTL1;
  584. intel_crtc->ddi_pll_sel = PORT_CLK_SEL_WRPLL1;
  585. } else if (plls->wrpll2_refcount == 0) {
  586. DRM_DEBUG_KMS("Using WRPLL 2 on pipe %c\n",
  587. pipe_name(pipe));
  588. plls->wrpll2_refcount++;
  589. reg = WRPLL_CTL2;
  590. intel_crtc->ddi_pll_sel = PORT_CLK_SEL_WRPLL2;
  591. } else {
  592. DRM_ERROR("No WRPLLs available!\n");
  593. return false;
  594. }
  595. WARN(I915_READ(reg) & WRPLL_PLL_ENABLE,
  596. "WRPLL already enabled\n");
  597. intel_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p);
  598. val = WRPLL_PLL_ENABLE | WRPLL_PLL_SELECT_LCPLL_2700 |
  599. WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
  600. WRPLL_DIVIDER_POST(p);
  601. } else if (type == INTEL_OUTPUT_ANALOG) {
  602. if (plls->spll_refcount == 0) {
  603. DRM_DEBUG_KMS("Using SPLL on pipe %c\n",
  604. pipe_name(pipe));
  605. plls->spll_refcount++;
  606. reg = SPLL_CTL;
  607. intel_crtc->ddi_pll_sel = PORT_CLK_SEL_SPLL;
  608. } else {
  609. DRM_ERROR("SPLL already in use\n");
  610. return false;
  611. }
  612. WARN(I915_READ(reg) & SPLL_PLL_ENABLE,
  613. "SPLL already enabled\n");
  614. val = SPLL_PLL_ENABLE | SPLL_PLL_FREQ_1350MHz | SPLL_PLL_SSC;
  615. } else {
  616. WARN(1, "Invalid DDI encoder type %d\n", type);
  617. return false;
  618. }
  619. I915_WRITE(reg, val);
  620. udelay(20);
  621. return true;
  622. }
  623. void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
  624. {
  625. struct drm_i915_private *dev_priv = crtc->dev->dev_private;
  626. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  627. struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
  628. enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
  629. int type = intel_encoder->type;
  630. uint32_t temp;
  631. if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
  632. temp = TRANS_MSA_SYNC_CLK;
  633. switch (intel_crtc->config.pipe_bpp) {
  634. case 18:
  635. temp |= TRANS_MSA_6_BPC;
  636. break;
  637. case 24:
  638. temp |= TRANS_MSA_8_BPC;
  639. break;
  640. case 30:
  641. temp |= TRANS_MSA_10_BPC;
  642. break;
  643. case 36:
  644. temp |= TRANS_MSA_12_BPC;
  645. break;
  646. default:
  647. BUG();
  648. }
  649. I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
  650. }
  651. }
  652. void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
  653. {
  654. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  655. struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
  656. struct drm_encoder *encoder = &intel_encoder->base;
  657. struct drm_i915_private *dev_priv = crtc->dev->dev_private;
  658. enum pipe pipe = intel_crtc->pipe;
  659. enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
  660. enum port port = intel_ddi_get_encoder_port(intel_encoder);
  661. int type = intel_encoder->type;
  662. uint32_t temp;
  663. /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
  664. temp = TRANS_DDI_FUNC_ENABLE;
  665. temp |= TRANS_DDI_SELECT_PORT(port);
  666. switch (intel_crtc->config.pipe_bpp) {
  667. case 18:
  668. temp |= TRANS_DDI_BPC_6;
  669. break;
  670. case 24:
  671. temp |= TRANS_DDI_BPC_8;
  672. break;
  673. case 30:
  674. temp |= TRANS_DDI_BPC_10;
  675. break;
  676. case 36:
  677. temp |= TRANS_DDI_BPC_12;
  678. break;
  679. default:
  680. BUG();
  681. }
  682. if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
  683. temp |= TRANS_DDI_PVSYNC;
  684. if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
  685. temp |= TRANS_DDI_PHSYNC;
  686. if (cpu_transcoder == TRANSCODER_EDP) {
  687. switch (pipe) {
  688. case PIPE_A:
  689. /* Can only use the always-on power well for eDP when
  690. * not using the panel fitter, and when not using motion
  691. * blur mitigation (which we don't support). */
  692. if (intel_crtc->config.pch_pfit.size)
  693. temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
  694. else
  695. temp |= TRANS_DDI_EDP_INPUT_A_ON;
  696. break;
  697. case PIPE_B:
  698. temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
  699. break;
  700. case PIPE_C:
  701. temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
  702. break;
  703. default:
  704. BUG();
  705. break;
  706. }
  707. }
  708. if (type == INTEL_OUTPUT_HDMI) {
  709. struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
  710. if (intel_hdmi->has_hdmi_sink)
  711. temp |= TRANS_DDI_MODE_SELECT_HDMI;
  712. else
  713. temp |= TRANS_DDI_MODE_SELECT_DVI;
  714. } else if (type == INTEL_OUTPUT_ANALOG) {
  715. temp |= TRANS_DDI_MODE_SELECT_FDI;
  716. temp |= (intel_crtc->config.fdi_lanes - 1) << 1;
  717. } else if (type == INTEL_OUTPUT_DISPLAYPORT ||
  718. type == INTEL_OUTPUT_EDP) {
  719. struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
  720. temp |= TRANS_DDI_MODE_SELECT_DP_SST;
  721. temp |= DDI_PORT_WIDTH(intel_dp->lane_count);
  722. } else {
  723. WARN(1, "Invalid encoder type %d for pipe %c\n",
  724. intel_encoder->type, pipe_name(pipe));
  725. }
  726. I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
  727. }
  728. void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
  729. enum transcoder cpu_transcoder)
  730. {
  731. uint32_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
  732. uint32_t val = I915_READ(reg);
  733. val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK);
  734. val |= TRANS_DDI_PORT_NONE;
  735. I915_WRITE(reg, val);
  736. }
  737. bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
  738. {
  739. struct drm_device *dev = intel_connector->base.dev;
  740. struct drm_i915_private *dev_priv = dev->dev_private;
  741. struct intel_encoder *intel_encoder = intel_connector->encoder;
  742. int type = intel_connector->base.connector_type;
  743. enum port port = intel_ddi_get_encoder_port(intel_encoder);
  744. enum pipe pipe = 0;
  745. enum transcoder cpu_transcoder;
  746. uint32_t tmp;
  747. if (!intel_encoder->get_hw_state(intel_encoder, &pipe))
  748. return false;
  749. if (port == PORT_A)
  750. cpu_transcoder = TRANSCODER_EDP;
  751. else
  752. cpu_transcoder = (enum transcoder) pipe;
  753. tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
  754. switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
  755. case TRANS_DDI_MODE_SELECT_HDMI:
  756. case TRANS_DDI_MODE_SELECT_DVI:
  757. return (type == DRM_MODE_CONNECTOR_HDMIA);
  758. case TRANS_DDI_MODE_SELECT_DP_SST:
  759. if (type == DRM_MODE_CONNECTOR_eDP)
  760. return true;
  761. case TRANS_DDI_MODE_SELECT_DP_MST:
  762. return (type == DRM_MODE_CONNECTOR_DisplayPort);
  763. case TRANS_DDI_MODE_SELECT_FDI:
  764. return (type == DRM_MODE_CONNECTOR_VGA);
  765. default:
  766. return false;
  767. }
  768. }
  769. bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
  770. enum pipe *pipe)
  771. {
  772. struct drm_device *dev = encoder->base.dev;
  773. struct drm_i915_private *dev_priv = dev->dev_private;
  774. enum port port = intel_ddi_get_encoder_port(encoder);
  775. u32 tmp;
  776. int i;
  777. tmp = I915_READ(DDI_BUF_CTL(port));
  778. if (!(tmp & DDI_BUF_CTL_ENABLE))
  779. return false;
  780. if (port == PORT_A) {
  781. tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
  782. switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
  783. case TRANS_DDI_EDP_INPUT_A_ON:
  784. case TRANS_DDI_EDP_INPUT_A_ONOFF:
  785. *pipe = PIPE_A;
  786. break;
  787. case TRANS_DDI_EDP_INPUT_B_ONOFF:
  788. *pipe = PIPE_B;
  789. break;
  790. case TRANS_DDI_EDP_INPUT_C_ONOFF:
  791. *pipe = PIPE_C;
  792. break;
  793. }
  794. return true;
  795. } else {
  796. for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) {
  797. tmp = I915_READ(TRANS_DDI_FUNC_CTL(i));
  798. if ((tmp & TRANS_DDI_PORT_MASK)
  799. == TRANS_DDI_SELECT_PORT(port)) {
  800. *pipe = i;
  801. return true;
  802. }
  803. }
  804. }
  805. DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
  806. return false;
  807. }
  808. static uint32_t intel_ddi_get_crtc_pll(struct drm_i915_private *dev_priv,
  809. enum pipe pipe)
  810. {
  811. uint32_t temp, ret;
  812. enum port port = I915_MAX_PORTS;
  813. enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
  814. pipe);
  815. int i;
  816. if (cpu_transcoder == TRANSCODER_EDP) {
  817. port = PORT_A;
  818. } else {
  819. temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
  820. temp &= TRANS_DDI_PORT_MASK;
  821. for (i = PORT_B; i <= PORT_E; i++)
  822. if (temp == TRANS_DDI_SELECT_PORT(i))
  823. port = i;
  824. }
  825. if (port == I915_MAX_PORTS) {
  826. WARN(1, "Pipe %c enabled on an unknown port\n",
  827. pipe_name(pipe));
  828. ret = PORT_CLK_SEL_NONE;
  829. } else {
  830. ret = I915_READ(PORT_CLK_SEL(port));
  831. DRM_DEBUG_KMS("Pipe %c connected to port %c using clock "
  832. "0x%08x\n", pipe_name(pipe), port_name(port),
  833. ret);
  834. }
  835. return ret;
  836. }
  837. void intel_ddi_setup_hw_pll_state(struct drm_device *dev)
  838. {
  839. struct drm_i915_private *dev_priv = dev->dev_private;
  840. enum pipe pipe;
  841. struct intel_crtc *intel_crtc;
  842. for_each_pipe(pipe) {
  843. intel_crtc =
  844. to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
  845. if (!intel_crtc->active)
  846. continue;
  847. intel_crtc->ddi_pll_sel = intel_ddi_get_crtc_pll(dev_priv,
  848. pipe);
  849. switch (intel_crtc->ddi_pll_sel) {
  850. case PORT_CLK_SEL_SPLL:
  851. dev_priv->ddi_plls.spll_refcount++;
  852. break;
  853. case PORT_CLK_SEL_WRPLL1:
  854. dev_priv->ddi_plls.wrpll1_refcount++;
  855. break;
  856. case PORT_CLK_SEL_WRPLL2:
  857. dev_priv->ddi_plls.wrpll2_refcount++;
  858. break;
  859. }
  860. }
  861. }
  862. void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
  863. {
  864. struct drm_crtc *crtc = &intel_crtc->base;
  865. struct drm_i915_private *dev_priv = crtc->dev->dev_private;
  866. struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
  867. enum port port = intel_ddi_get_encoder_port(intel_encoder);
  868. enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
  869. if (cpu_transcoder != TRANSCODER_EDP)
  870. I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
  871. TRANS_CLK_SEL_PORT(port));
  872. }
  873. void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc)
  874. {
  875. struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
  876. enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
  877. if (cpu_transcoder != TRANSCODER_EDP)
  878. I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
  879. TRANS_CLK_SEL_DISABLED);
  880. }
  881. static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
  882. {
  883. struct drm_encoder *encoder = &intel_encoder->base;
  884. struct drm_crtc *crtc = encoder->crtc;
  885. struct drm_i915_private *dev_priv = encoder->dev->dev_private;
  886. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  887. enum port port = intel_ddi_get_encoder_port(intel_encoder);
  888. int type = intel_encoder->type;
  889. if (type == INTEL_OUTPUT_EDP) {
  890. struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
  891. ironlake_edp_panel_vdd_on(intel_dp);
  892. ironlake_edp_panel_on(intel_dp);
  893. ironlake_edp_panel_vdd_off(intel_dp, true);
  894. }
  895. WARN_ON(intel_crtc->ddi_pll_sel == PORT_CLK_SEL_NONE);
  896. I915_WRITE(PORT_CLK_SEL(port), intel_crtc->ddi_pll_sel);
  897. if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
  898. struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
  899. intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
  900. intel_dp_start_link_train(intel_dp);
  901. intel_dp_complete_link_train(intel_dp);
  902. if (port != PORT_A)
  903. intel_dp_stop_link_train(intel_dp);
  904. }
  905. }
  906. static void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
  907. {
  908. struct drm_encoder *encoder = &intel_encoder->base;
  909. struct drm_i915_private *dev_priv = encoder->dev->dev_private;
  910. enum port port = intel_ddi_get_encoder_port(intel_encoder);
  911. int type = intel_encoder->type;
  912. uint32_t val;
  913. bool wait = false;
  914. val = I915_READ(DDI_BUF_CTL(port));
  915. if (val & DDI_BUF_CTL_ENABLE) {
  916. val &= ~DDI_BUF_CTL_ENABLE;
  917. I915_WRITE(DDI_BUF_CTL(port), val);
  918. wait = true;
  919. }
  920. val = I915_READ(DP_TP_CTL(port));
  921. val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
  922. val |= DP_TP_CTL_LINK_TRAIN_PAT1;
  923. I915_WRITE(DP_TP_CTL(port), val);
  924. if (wait)
  925. intel_wait_ddi_buf_idle(dev_priv, port);
  926. if (type == INTEL_OUTPUT_EDP) {
  927. struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
  928. ironlake_edp_panel_vdd_on(intel_dp);
  929. ironlake_edp_panel_off(intel_dp);
  930. }
  931. I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
  932. }
  933. static void intel_enable_ddi(struct intel_encoder *intel_encoder)
  934. {
  935. struct drm_encoder *encoder = &intel_encoder->base;
  936. struct drm_crtc *crtc = encoder->crtc;
  937. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  938. int pipe = intel_crtc->pipe;
  939. struct drm_device *dev = encoder->dev;
  940. struct drm_i915_private *dev_priv = dev->dev_private;
  941. enum port port = intel_ddi_get_encoder_port(intel_encoder);
  942. int type = intel_encoder->type;
  943. uint32_t tmp;
  944. if (type == INTEL_OUTPUT_HDMI) {
  945. struct intel_digital_port *intel_dig_port =
  946. enc_to_dig_port(encoder);
  947. /* In HDMI/DVI mode, the port width, and swing/emphasis values
  948. * are ignored so nothing special needs to be done besides
  949. * enabling the port.
  950. */
  951. I915_WRITE(DDI_BUF_CTL(port),
  952. intel_dig_port->port_reversal | DDI_BUF_CTL_ENABLE);
  953. } else if (type == INTEL_OUTPUT_EDP) {
  954. struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
  955. if (port == PORT_A)
  956. intel_dp_stop_link_train(intel_dp);
  957. ironlake_edp_backlight_on(intel_dp);
  958. }
  959. if (intel_crtc->eld_vld && type != INTEL_OUTPUT_EDP) {
  960. tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
  961. tmp |= ((AUDIO_OUTPUT_ENABLE_A | AUDIO_ELD_VALID_A) << (pipe * 4));
  962. I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
  963. }
  964. }
  965. static void intel_disable_ddi(struct intel_encoder *intel_encoder)
  966. {
  967. struct drm_encoder *encoder = &intel_encoder->base;
  968. struct drm_crtc *crtc = encoder->crtc;
  969. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  970. int pipe = intel_crtc->pipe;
  971. int type = intel_encoder->type;
  972. struct drm_device *dev = encoder->dev;
  973. struct drm_i915_private *dev_priv = dev->dev_private;
  974. uint32_t tmp;
  975. if (intel_crtc->eld_vld && type != INTEL_OUTPUT_EDP) {
  976. tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
  977. tmp &= ~((AUDIO_OUTPUT_ENABLE_A | AUDIO_ELD_VALID_A) <<
  978. (pipe * 4));
  979. I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
  980. }
  981. if (type == INTEL_OUTPUT_EDP) {
  982. struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
  983. ironlake_edp_backlight_off(intel_dp);
  984. }
  985. }
  986. int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv)
  987. {
  988. if (I915_READ(HSW_FUSE_STRAP) & HSW_CDCLK_LIMIT)
  989. return 450000;
  990. else if ((I915_READ(LCPLL_CTL) & LCPLL_CLK_FREQ_MASK) ==
  991. LCPLL_CLK_FREQ_450)
  992. return 450000;
  993. else if (IS_ULT(dev_priv->dev))
  994. return 337500;
  995. else
  996. return 540000;
  997. }
  998. void intel_ddi_pll_init(struct drm_device *dev)
  999. {
  1000. struct drm_i915_private *dev_priv = dev->dev_private;
  1001. uint32_t val = I915_READ(LCPLL_CTL);
  1002. /* The LCPLL register should be turned on by the BIOS. For now let's
  1003. * just check its state and print errors in case something is wrong.
  1004. * Don't even try to turn it on.
  1005. */
  1006. DRM_DEBUG_KMS("CDCLK running at %dKHz\n",
  1007. intel_ddi_get_cdclk_freq(dev_priv));
  1008. if (val & LCPLL_CD_SOURCE_FCLK)
  1009. DRM_ERROR("CDCLK source is not LCPLL\n");
  1010. if (val & LCPLL_PLL_DISABLE)
  1011. DRM_ERROR("LCPLL is disabled\n");
  1012. }
  1013. void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder)
  1014. {
  1015. struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
  1016. struct intel_dp *intel_dp = &intel_dig_port->dp;
  1017. struct drm_i915_private *dev_priv = encoder->dev->dev_private;
  1018. enum port port = intel_dig_port->port;
  1019. uint32_t val;
  1020. bool wait = false;
  1021. if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
  1022. val = I915_READ(DDI_BUF_CTL(port));
  1023. if (val & DDI_BUF_CTL_ENABLE) {
  1024. val &= ~DDI_BUF_CTL_ENABLE;
  1025. I915_WRITE(DDI_BUF_CTL(port), val);
  1026. wait = true;
  1027. }
  1028. val = I915_READ(DP_TP_CTL(port));
  1029. val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
  1030. val |= DP_TP_CTL_LINK_TRAIN_PAT1;
  1031. I915_WRITE(DP_TP_CTL(port), val);
  1032. POSTING_READ(DP_TP_CTL(port));
  1033. if (wait)
  1034. intel_wait_ddi_buf_idle(dev_priv, port);
  1035. }
  1036. val = DP_TP_CTL_ENABLE | DP_TP_CTL_MODE_SST |
  1037. DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
  1038. if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
  1039. val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
  1040. I915_WRITE(DP_TP_CTL(port), val);
  1041. POSTING_READ(DP_TP_CTL(port));
  1042. intel_dp->DP |= DDI_BUF_CTL_ENABLE;
  1043. I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
  1044. POSTING_READ(DDI_BUF_CTL(port));
  1045. udelay(600);
  1046. }
  1047. void intel_ddi_fdi_disable(struct drm_crtc *crtc)
  1048. {
  1049. struct drm_i915_private *dev_priv = crtc->dev->dev_private;
  1050. struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
  1051. uint32_t val;
  1052. intel_ddi_post_disable(intel_encoder);
  1053. val = I915_READ(_FDI_RXA_CTL);
  1054. val &= ~FDI_RX_ENABLE;
  1055. I915_WRITE(_FDI_RXA_CTL, val);
  1056. val = I915_READ(_FDI_RXA_MISC);
  1057. val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
  1058. val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
  1059. I915_WRITE(_FDI_RXA_MISC, val);
  1060. val = I915_READ(_FDI_RXA_CTL);
  1061. val &= ~FDI_PCDCLK;
  1062. I915_WRITE(_FDI_RXA_CTL, val);
  1063. val = I915_READ(_FDI_RXA_CTL);
  1064. val &= ~FDI_RX_PLL_ENABLE;
  1065. I915_WRITE(_FDI_RXA_CTL, val);
  1066. }
  1067. static void intel_ddi_hot_plug(struct intel_encoder *intel_encoder)
  1068. {
  1069. struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
  1070. int type = intel_encoder->type;
  1071. if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP)
  1072. intel_dp_check_link_status(intel_dp);
  1073. }
  1074. static void intel_ddi_get_config(struct intel_encoder *encoder,
  1075. struct intel_crtc_config *pipe_config)
  1076. {
  1077. struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
  1078. struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
  1079. enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
  1080. u32 temp, flags = 0;
  1081. temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
  1082. if (temp & TRANS_DDI_PHSYNC)
  1083. flags |= DRM_MODE_FLAG_PHSYNC;
  1084. else
  1085. flags |= DRM_MODE_FLAG_NHSYNC;
  1086. if (temp & TRANS_DDI_PVSYNC)
  1087. flags |= DRM_MODE_FLAG_PVSYNC;
  1088. else
  1089. flags |= DRM_MODE_FLAG_NVSYNC;
  1090. pipe_config->adjusted_mode.flags |= flags;
  1091. }
  1092. static void intel_ddi_destroy(struct drm_encoder *encoder)
  1093. {
  1094. /* HDMI has nothing special to destroy, so we can go with this. */
  1095. intel_dp_encoder_destroy(encoder);
  1096. }
  1097. static bool intel_ddi_compute_config(struct intel_encoder *encoder,
  1098. struct intel_crtc_config *pipe_config)
  1099. {
  1100. int type = encoder->type;
  1101. int port = intel_ddi_get_encoder_port(encoder);
  1102. WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n");
  1103. if (port == PORT_A)
  1104. pipe_config->cpu_transcoder = TRANSCODER_EDP;
  1105. if (type == INTEL_OUTPUT_HDMI)
  1106. return intel_hdmi_compute_config(encoder, pipe_config);
  1107. else
  1108. return intel_dp_compute_config(encoder, pipe_config);
  1109. }
  1110. static const struct drm_encoder_funcs intel_ddi_funcs = {
  1111. .destroy = intel_ddi_destroy,
  1112. };
  1113. static const struct drm_encoder_helper_funcs intel_ddi_helper_funcs = {
  1114. .mode_set = intel_ddi_mode_set,
  1115. };
  1116. void intel_ddi_init(struct drm_device *dev, enum port port)
  1117. {
  1118. struct drm_i915_private *dev_priv = dev->dev_private;
  1119. struct intel_digital_port *intel_dig_port;
  1120. struct intel_encoder *intel_encoder;
  1121. struct drm_encoder *encoder;
  1122. struct intel_connector *hdmi_connector = NULL;
  1123. struct intel_connector *dp_connector = NULL;
  1124. intel_dig_port = kzalloc(sizeof(struct intel_digital_port), GFP_KERNEL);
  1125. if (!intel_dig_port)
  1126. return;
  1127. dp_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
  1128. if (!dp_connector) {
  1129. kfree(intel_dig_port);
  1130. return;
  1131. }
  1132. intel_encoder = &intel_dig_port->base;
  1133. encoder = &intel_encoder->base;
  1134. drm_encoder_init(dev, encoder, &intel_ddi_funcs,
  1135. DRM_MODE_ENCODER_TMDS);
  1136. drm_encoder_helper_add(encoder, &intel_ddi_helper_funcs);
  1137. intel_encoder->compute_config = intel_ddi_compute_config;
  1138. intel_encoder->enable = intel_enable_ddi;
  1139. intel_encoder->pre_enable = intel_ddi_pre_enable;
  1140. intel_encoder->disable = intel_disable_ddi;
  1141. intel_encoder->post_disable = intel_ddi_post_disable;
  1142. intel_encoder->get_hw_state = intel_ddi_get_hw_state;
  1143. intel_encoder->get_config = intel_ddi_get_config;
  1144. intel_dig_port->port = port;
  1145. intel_dig_port->port_reversal = I915_READ(DDI_BUF_CTL(port)) &
  1146. DDI_BUF_PORT_REVERSAL;
  1147. intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
  1148. intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
  1149. intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
  1150. intel_encoder->cloneable = false;
  1151. intel_encoder->hot_plug = intel_ddi_hot_plug;
  1152. intel_dp_init_connector(intel_dig_port, dp_connector);
  1153. if (intel_encoder->type != INTEL_OUTPUT_EDP) {
  1154. hdmi_connector = kzalloc(sizeof(struct intel_connector),
  1155. GFP_KERNEL);
  1156. if (!hdmi_connector) {
  1157. return;
  1158. }
  1159. intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
  1160. intel_hdmi_init_connector(intel_dig_port, hdmi_connector);
  1161. }
  1162. }