intel_crt.c 22 KB

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  1. /*
  2. * Copyright © 2006-2007 Intel Corporation
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice (including the next
  12. * paragraph) shall be included in all copies or substantial portions of the
  13. * Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  18. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21. * DEALINGS IN THE SOFTWARE.
  22. *
  23. * Authors:
  24. * Eric Anholt <eric@anholt.net>
  25. */
  26. #include <linux/dmi.h>
  27. #include <linux/i2c.h>
  28. #include <linux/slab.h>
  29. #include <drm/drmP.h>
  30. #include <drm/drm_crtc.h>
  31. #include <drm/drm_crtc_helper.h>
  32. #include <drm/drm_edid.h>
  33. #include "intel_drv.h"
  34. #include <drm/i915_drm.h>
  35. #include "i915_drv.h"
  36. /* Here's the desired hotplug mode */
  37. #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 | \
  38. ADPA_CRT_HOTPLUG_WARMUP_10MS | \
  39. ADPA_CRT_HOTPLUG_SAMPLE_4S | \
  40. ADPA_CRT_HOTPLUG_VOLTAGE_50 | \
  41. ADPA_CRT_HOTPLUG_VOLREF_325MV | \
  42. ADPA_CRT_HOTPLUG_ENABLE)
  43. struct intel_crt {
  44. struct intel_encoder base;
  45. /* DPMS state is stored in the connector, which we need in the
  46. * encoder's enable/disable callbacks */
  47. struct intel_connector *connector;
  48. bool force_hotplug_required;
  49. u32 adpa_reg;
  50. };
  51. static struct intel_crt *intel_attached_crt(struct drm_connector *connector)
  52. {
  53. return container_of(intel_attached_encoder(connector),
  54. struct intel_crt, base);
  55. }
  56. static struct intel_crt *intel_encoder_to_crt(struct intel_encoder *encoder)
  57. {
  58. return container_of(encoder, struct intel_crt, base);
  59. }
  60. static bool intel_crt_get_hw_state(struct intel_encoder *encoder,
  61. enum pipe *pipe)
  62. {
  63. struct drm_device *dev = encoder->base.dev;
  64. struct drm_i915_private *dev_priv = dev->dev_private;
  65. struct intel_crt *crt = intel_encoder_to_crt(encoder);
  66. u32 tmp;
  67. tmp = I915_READ(crt->adpa_reg);
  68. if (!(tmp & ADPA_DAC_ENABLE))
  69. return false;
  70. if (HAS_PCH_CPT(dev))
  71. *pipe = PORT_TO_PIPE_CPT(tmp);
  72. else
  73. *pipe = PORT_TO_PIPE(tmp);
  74. return true;
  75. }
  76. static void intel_crt_get_config(struct intel_encoder *encoder,
  77. struct intel_crtc_config *pipe_config)
  78. {
  79. struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
  80. struct intel_crt *crt = intel_encoder_to_crt(encoder);
  81. u32 tmp, flags = 0;
  82. tmp = I915_READ(crt->adpa_reg);
  83. if (tmp & ADPA_HSYNC_ACTIVE_HIGH)
  84. flags |= DRM_MODE_FLAG_PHSYNC;
  85. else
  86. flags |= DRM_MODE_FLAG_NHSYNC;
  87. if (tmp & ADPA_VSYNC_ACTIVE_HIGH)
  88. flags |= DRM_MODE_FLAG_PVSYNC;
  89. else
  90. flags |= DRM_MODE_FLAG_NVSYNC;
  91. pipe_config->adjusted_mode.flags |= flags;
  92. }
  93. /* Note: The caller is required to filter out dpms modes not supported by the
  94. * platform. */
  95. static void intel_crt_set_dpms(struct intel_encoder *encoder, int mode)
  96. {
  97. struct drm_device *dev = encoder->base.dev;
  98. struct drm_i915_private *dev_priv = dev->dev_private;
  99. struct intel_crt *crt = intel_encoder_to_crt(encoder);
  100. u32 temp;
  101. temp = I915_READ(crt->adpa_reg);
  102. temp &= ~(ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE);
  103. temp &= ~ADPA_DAC_ENABLE;
  104. switch (mode) {
  105. case DRM_MODE_DPMS_ON:
  106. temp |= ADPA_DAC_ENABLE;
  107. break;
  108. case DRM_MODE_DPMS_STANDBY:
  109. temp |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE;
  110. break;
  111. case DRM_MODE_DPMS_SUSPEND:
  112. temp |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE;
  113. break;
  114. case DRM_MODE_DPMS_OFF:
  115. temp |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE;
  116. break;
  117. }
  118. I915_WRITE(crt->adpa_reg, temp);
  119. }
  120. static void intel_disable_crt(struct intel_encoder *encoder)
  121. {
  122. intel_crt_set_dpms(encoder, DRM_MODE_DPMS_OFF);
  123. }
  124. static void intel_enable_crt(struct intel_encoder *encoder)
  125. {
  126. struct intel_crt *crt = intel_encoder_to_crt(encoder);
  127. intel_crt_set_dpms(encoder, crt->connector->base.dpms);
  128. }
  129. /* Special dpms function to support cloning between dvo/sdvo/crt. */
  130. static void intel_crt_dpms(struct drm_connector *connector, int mode)
  131. {
  132. struct drm_device *dev = connector->dev;
  133. struct intel_encoder *encoder = intel_attached_encoder(connector);
  134. struct drm_crtc *crtc;
  135. int old_dpms;
  136. /* PCH platforms and VLV only support on/off. */
  137. if (INTEL_INFO(dev)->gen >= 5 && mode != DRM_MODE_DPMS_ON)
  138. mode = DRM_MODE_DPMS_OFF;
  139. if (mode == connector->dpms)
  140. return;
  141. old_dpms = connector->dpms;
  142. connector->dpms = mode;
  143. /* Only need to change hw state when actually enabled */
  144. crtc = encoder->base.crtc;
  145. if (!crtc) {
  146. encoder->connectors_active = false;
  147. return;
  148. }
  149. /* We need the pipe to run for anything but OFF. */
  150. if (mode == DRM_MODE_DPMS_OFF)
  151. encoder->connectors_active = false;
  152. else
  153. encoder->connectors_active = true;
  154. /* We call connector dpms manually below in case pipe dpms doesn't
  155. * change due to cloning. */
  156. if (mode < old_dpms) {
  157. /* From off to on, enable the pipe first. */
  158. intel_crtc_update_dpms(crtc);
  159. intel_crt_set_dpms(encoder, mode);
  160. } else {
  161. intel_crt_set_dpms(encoder, mode);
  162. intel_crtc_update_dpms(crtc);
  163. }
  164. intel_modeset_check_state(connector->dev);
  165. }
  166. static int intel_crt_mode_valid(struct drm_connector *connector,
  167. struct drm_display_mode *mode)
  168. {
  169. struct drm_device *dev = connector->dev;
  170. int max_clock = 0;
  171. if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
  172. return MODE_NO_DBLESCAN;
  173. if (mode->clock < 25000)
  174. return MODE_CLOCK_LOW;
  175. if (IS_GEN2(dev))
  176. max_clock = 350000;
  177. else
  178. max_clock = 400000;
  179. if (mode->clock > max_clock)
  180. return MODE_CLOCK_HIGH;
  181. /* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */
  182. if (HAS_PCH_LPT(dev) &&
  183. (ironlake_get_lanes_required(mode->clock, 270000, 24) > 2))
  184. return MODE_CLOCK_HIGH;
  185. return MODE_OK;
  186. }
  187. static bool intel_crt_compute_config(struct intel_encoder *encoder,
  188. struct intel_crtc_config *pipe_config)
  189. {
  190. struct drm_device *dev = encoder->base.dev;
  191. if (HAS_PCH_SPLIT(dev))
  192. pipe_config->has_pch_encoder = true;
  193. /* LPT FDI RX only supports 8bpc. */
  194. if (HAS_PCH_LPT(dev))
  195. pipe_config->pipe_bpp = 24;
  196. return true;
  197. }
  198. static void intel_crt_mode_set(struct drm_encoder *encoder,
  199. struct drm_display_mode *mode,
  200. struct drm_display_mode *adjusted_mode)
  201. {
  202. struct drm_device *dev = encoder->dev;
  203. struct drm_crtc *crtc = encoder->crtc;
  204. struct intel_crt *crt =
  205. intel_encoder_to_crt(to_intel_encoder(encoder));
  206. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  207. struct drm_i915_private *dev_priv = dev->dev_private;
  208. u32 adpa;
  209. if (HAS_PCH_SPLIT(dev))
  210. adpa = ADPA_HOTPLUG_BITS;
  211. else
  212. adpa = 0;
  213. if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
  214. adpa |= ADPA_HSYNC_ACTIVE_HIGH;
  215. if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
  216. adpa |= ADPA_VSYNC_ACTIVE_HIGH;
  217. /* For CPT allow 3 pipe config, for others just use A or B */
  218. if (HAS_PCH_LPT(dev))
  219. ; /* Those bits don't exist here */
  220. else if (HAS_PCH_CPT(dev))
  221. adpa |= PORT_TRANS_SEL_CPT(intel_crtc->pipe);
  222. else if (intel_crtc->pipe == 0)
  223. adpa |= ADPA_PIPE_A_SELECT;
  224. else
  225. adpa |= ADPA_PIPE_B_SELECT;
  226. if (!HAS_PCH_SPLIT(dev))
  227. I915_WRITE(BCLRPAT(intel_crtc->pipe), 0);
  228. I915_WRITE(crt->adpa_reg, adpa);
  229. }
  230. static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector)
  231. {
  232. struct drm_device *dev = connector->dev;
  233. struct intel_crt *crt = intel_attached_crt(connector);
  234. struct drm_i915_private *dev_priv = dev->dev_private;
  235. u32 adpa;
  236. bool ret;
  237. /* The first time through, trigger an explicit detection cycle */
  238. if (crt->force_hotplug_required) {
  239. bool turn_off_dac = HAS_PCH_SPLIT(dev);
  240. u32 save_adpa;
  241. crt->force_hotplug_required = 0;
  242. save_adpa = adpa = I915_READ(crt->adpa_reg);
  243. DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
  244. adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
  245. if (turn_off_dac)
  246. adpa &= ~ADPA_DAC_ENABLE;
  247. I915_WRITE(crt->adpa_reg, adpa);
  248. if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0,
  249. 1000))
  250. DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");
  251. if (turn_off_dac) {
  252. I915_WRITE(crt->adpa_reg, save_adpa);
  253. POSTING_READ(crt->adpa_reg);
  254. }
  255. }
  256. /* Check the status to see if both blue and green are on now */
  257. adpa = I915_READ(crt->adpa_reg);
  258. if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
  259. ret = true;
  260. else
  261. ret = false;
  262. DRM_DEBUG_KMS("ironlake hotplug adpa=0x%x, result %d\n", adpa, ret);
  263. return ret;
  264. }
  265. static bool valleyview_crt_detect_hotplug(struct drm_connector *connector)
  266. {
  267. struct drm_device *dev = connector->dev;
  268. struct intel_crt *crt = intel_attached_crt(connector);
  269. struct drm_i915_private *dev_priv = dev->dev_private;
  270. u32 adpa;
  271. bool ret;
  272. u32 save_adpa;
  273. save_adpa = adpa = I915_READ(crt->adpa_reg);
  274. DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
  275. adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
  276. I915_WRITE(crt->adpa_reg, adpa);
  277. if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0,
  278. 1000)) {
  279. DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");
  280. I915_WRITE(crt->adpa_reg, save_adpa);
  281. }
  282. /* Check the status to see if both blue and green are on now */
  283. adpa = I915_READ(crt->adpa_reg);
  284. if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
  285. ret = true;
  286. else
  287. ret = false;
  288. DRM_DEBUG_KMS("valleyview hotplug adpa=0x%x, result %d\n", adpa, ret);
  289. /* FIXME: debug force function and remove */
  290. ret = true;
  291. return ret;
  292. }
  293. /**
  294. * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect CRT presence.
  295. *
  296. * Not for i915G/i915GM
  297. *
  298. * \return true if CRT is connected.
  299. * \return false if CRT is disconnected.
  300. */
  301. static bool intel_crt_detect_hotplug(struct drm_connector *connector)
  302. {
  303. struct drm_device *dev = connector->dev;
  304. struct drm_i915_private *dev_priv = dev->dev_private;
  305. u32 hotplug_en, orig, stat;
  306. bool ret = false;
  307. int i, tries = 0;
  308. if (HAS_PCH_SPLIT(dev))
  309. return intel_ironlake_crt_detect_hotplug(connector);
  310. if (IS_VALLEYVIEW(dev))
  311. return valleyview_crt_detect_hotplug(connector);
  312. /*
  313. * On 4 series desktop, CRT detect sequence need to be done twice
  314. * to get a reliable result.
  315. */
  316. if (IS_G4X(dev) && !IS_GM45(dev))
  317. tries = 2;
  318. else
  319. tries = 1;
  320. hotplug_en = orig = I915_READ(PORT_HOTPLUG_EN);
  321. hotplug_en |= CRT_HOTPLUG_FORCE_DETECT;
  322. for (i = 0; i < tries ; i++) {
  323. /* turn on the FORCE_DETECT */
  324. I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
  325. /* wait for FORCE_DETECT to go off */
  326. if (wait_for((I915_READ(PORT_HOTPLUG_EN) &
  327. CRT_HOTPLUG_FORCE_DETECT) == 0,
  328. 1000))
  329. DRM_DEBUG_KMS("timed out waiting for FORCE_DETECT to go off");
  330. }
  331. stat = I915_READ(PORT_HOTPLUG_STAT);
  332. if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE)
  333. ret = true;
  334. /* clear the interrupt we just generated, if any */
  335. I915_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS);
  336. /* and put the bits back */
  337. I915_WRITE(PORT_HOTPLUG_EN, orig);
  338. return ret;
  339. }
  340. static struct edid *intel_crt_get_edid(struct drm_connector *connector,
  341. struct i2c_adapter *i2c)
  342. {
  343. struct edid *edid;
  344. edid = drm_get_edid(connector, i2c);
  345. if (!edid && !intel_gmbus_is_forced_bit(i2c)) {
  346. DRM_DEBUG_KMS("CRT GMBUS EDID read failed, retry using GPIO bit-banging\n");
  347. intel_gmbus_force_bit(i2c, true);
  348. edid = drm_get_edid(connector, i2c);
  349. intel_gmbus_force_bit(i2c, false);
  350. }
  351. return edid;
  352. }
  353. /* local version of intel_ddc_get_modes() to use intel_crt_get_edid() */
  354. static int intel_crt_ddc_get_modes(struct drm_connector *connector,
  355. struct i2c_adapter *adapter)
  356. {
  357. struct edid *edid;
  358. int ret;
  359. edid = intel_crt_get_edid(connector, adapter);
  360. if (!edid)
  361. return 0;
  362. ret = intel_connector_update_modes(connector, edid);
  363. kfree(edid);
  364. return ret;
  365. }
  366. static bool intel_crt_detect_ddc(struct drm_connector *connector)
  367. {
  368. struct intel_crt *crt = intel_attached_crt(connector);
  369. struct drm_i915_private *dev_priv = crt->base.base.dev->dev_private;
  370. struct edid *edid;
  371. struct i2c_adapter *i2c;
  372. BUG_ON(crt->base.type != INTEL_OUTPUT_ANALOG);
  373. i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin);
  374. edid = intel_crt_get_edid(connector, i2c);
  375. if (edid) {
  376. bool is_digital = edid->input & DRM_EDID_INPUT_DIGITAL;
  377. /*
  378. * This may be a DVI-I connector with a shared DDC
  379. * link between analog and digital outputs, so we
  380. * have to check the EDID input spec of the attached device.
  381. */
  382. if (!is_digital) {
  383. DRM_DEBUG_KMS("CRT detected via DDC:0x50 [EDID]\n");
  384. return true;
  385. }
  386. DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [EDID reports a digital panel]\n");
  387. } else {
  388. DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [no valid EDID found]\n");
  389. }
  390. kfree(edid);
  391. return false;
  392. }
  393. static enum drm_connector_status
  394. intel_crt_load_detect(struct intel_crt *crt)
  395. {
  396. struct drm_device *dev = crt->base.base.dev;
  397. struct drm_i915_private *dev_priv = dev->dev_private;
  398. uint32_t pipe = to_intel_crtc(crt->base.base.crtc)->pipe;
  399. uint32_t save_bclrpat;
  400. uint32_t save_vtotal;
  401. uint32_t vtotal, vactive;
  402. uint32_t vsample;
  403. uint32_t vblank, vblank_start, vblank_end;
  404. uint32_t dsl;
  405. uint32_t bclrpat_reg;
  406. uint32_t vtotal_reg;
  407. uint32_t vblank_reg;
  408. uint32_t vsync_reg;
  409. uint32_t pipeconf_reg;
  410. uint32_t pipe_dsl_reg;
  411. uint8_t st00;
  412. enum drm_connector_status status;
  413. DRM_DEBUG_KMS("starting load-detect on CRT\n");
  414. bclrpat_reg = BCLRPAT(pipe);
  415. vtotal_reg = VTOTAL(pipe);
  416. vblank_reg = VBLANK(pipe);
  417. vsync_reg = VSYNC(pipe);
  418. pipeconf_reg = PIPECONF(pipe);
  419. pipe_dsl_reg = PIPEDSL(pipe);
  420. save_bclrpat = I915_READ(bclrpat_reg);
  421. save_vtotal = I915_READ(vtotal_reg);
  422. vblank = I915_READ(vblank_reg);
  423. vtotal = ((save_vtotal >> 16) & 0xfff) + 1;
  424. vactive = (save_vtotal & 0x7ff) + 1;
  425. vblank_start = (vblank & 0xfff) + 1;
  426. vblank_end = ((vblank >> 16) & 0xfff) + 1;
  427. /* Set the border color to purple. */
  428. I915_WRITE(bclrpat_reg, 0x500050);
  429. if (!IS_GEN2(dev)) {
  430. uint32_t pipeconf = I915_READ(pipeconf_reg);
  431. I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER);
  432. POSTING_READ(pipeconf_reg);
  433. /* Wait for next Vblank to substitue
  434. * border color for Color info */
  435. intel_wait_for_vblank(dev, pipe);
  436. st00 = I915_READ8(VGA_MSR_WRITE);
  437. status = ((st00 & (1 << 4)) != 0) ?
  438. connector_status_connected :
  439. connector_status_disconnected;
  440. I915_WRITE(pipeconf_reg, pipeconf);
  441. } else {
  442. bool restore_vblank = false;
  443. int count, detect;
  444. /*
  445. * If there isn't any border, add some.
  446. * Yes, this will flicker
  447. */
  448. if (vblank_start <= vactive && vblank_end >= vtotal) {
  449. uint32_t vsync = I915_READ(vsync_reg);
  450. uint32_t vsync_start = (vsync & 0xffff) + 1;
  451. vblank_start = vsync_start;
  452. I915_WRITE(vblank_reg,
  453. (vblank_start - 1) |
  454. ((vblank_end - 1) << 16));
  455. restore_vblank = true;
  456. }
  457. /* sample in the vertical border, selecting the larger one */
  458. if (vblank_start - vactive >= vtotal - vblank_end)
  459. vsample = (vblank_start + vactive) >> 1;
  460. else
  461. vsample = (vtotal + vblank_end) >> 1;
  462. /*
  463. * Wait for the border to be displayed
  464. */
  465. while (I915_READ(pipe_dsl_reg) >= vactive)
  466. ;
  467. while ((dsl = I915_READ(pipe_dsl_reg)) <= vsample)
  468. ;
  469. /*
  470. * Watch ST00 for an entire scanline
  471. */
  472. detect = 0;
  473. count = 0;
  474. do {
  475. count++;
  476. /* Read the ST00 VGA status register */
  477. st00 = I915_READ8(VGA_MSR_WRITE);
  478. if (st00 & (1 << 4))
  479. detect++;
  480. } while ((I915_READ(pipe_dsl_reg) == dsl));
  481. /* restore vblank if necessary */
  482. if (restore_vblank)
  483. I915_WRITE(vblank_reg, vblank);
  484. /*
  485. * If more than 3/4 of the scanline detected a monitor,
  486. * then it is assumed to be present. This works even on i830,
  487. * where there isn't any way to force the border color across
  488. * the screen
  489. */
  490. status = detect * 4 > count * 3 ?
  491. connector_status_connected :
  492. connector_status_disconnected;
  493. }
  494. /* Restore previous settings */
  495. I915_WRITE(bclrpat_reg, save_bclrpat);
  496. return status;
  497. }
  498. static enum drm_connector_status
  499. intel_crt_detect(struct drm_connector *connector, bool force)
  500. {
  501. struct drm_device *dev = connector->dev;
  502. struct intel_crt *crt = intel_attached_crt(connector);
  503. enum drm_connector_status status;
  504. struct intel_load_detect_pipe tmp;
  505. if (I915_HAS_HOTPLUG(dev)) {
  506. /* We can not rely on the HPD pin always being correctly wired
  507. * up, for example many KVM do not pass it through, and so
  508. * only trust an assertion that the monitor is connected.
  509. */
  510. if (intel_crt_detect_hotplug(connector)) {
  511. DRM_DEBUG_KMS("CRT detected via hotplug\n");
  512. return connector_status_connected;
  513. } else
  514. DRM_DEBUG_KMS("CRT not detected via hotplug\n");
  515. }
  516. if (intel_crt_detect_ddc(connector))
  517. return connector_status_connected;
  518. /* Load detection is broken on HPD capable machines. Whoever wants a
  519. * broken monitor (without edid) to work behind a broken kvm (that fails
  520. * to have the right resistors for HP detection) needs to fix this up.
  521. * For now just bail out. */
  522. if (I915_HAS_HOTPLUG(dev))
  523. return connector_status_disconnected;
  524. if (!force)
  525. return connector->status;
  526. /* for pre-945g platforms use load detect */
  527. if (intel_get_load_detect_pipe(connector, NULL, &tmp)) {
  528. if (intel_crt_detect_ddc(connector))
  529. status = connector_status_connected;
  530. else
  531. status = intel_crt_load_detect(crt);
  532. intel_release_load_detect_pipe(connector, &tmp);
  533. } else
  534. status = connector_status_unknown;
  535. return status;
  536. }
  537. static void intel_crt_destroy(struct drm_connector *connector)
  538. {
  539. drm_sysfs_connector_remove(connector);
  540. drm_connector_cleanup(connector);
  541. kfree(connector);
  542. }
  543. static int intel_crt_get_modes(struct drm_connector *connector)
  544. {
  545. struct drm_device *dev = connector->dev;
  546. struct drm_i915_private *dev_priv = dev->dev_private;
  547. int ret;
  548. struct i2c_adapter *i2c;
  549. i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin);
  550. ret = intel_crt_ddc_get_modes(connector, i2c);
  551. if (ret || !IS_G4X(dev))
  552. return ret;
  553. /* Try to probe digital port for output in DVI-I -> VGA mode. */
  554. i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PORT_DPB);
  555. return intel_crt_ddc_get_modes(connector, i2c);
  556. }
  557. static int intel_crt_set_property(struct drm_connector *connector,
  558. struct drm_property *property,
  559. uint64_t value)
  560. {
  561. return 0;
  562. }
  563. static void intel_crt_reset(struct drm_connector *connector)
  564. {
  565. struct drm_device *dev = connector->dev;
  566. struct drm_i915_private *dev_priv = dev->dev_private;
  567. struct intel_crt *crt = intel_attached_crt(connector);
  568. if (HAS_PCH_SPLIT(dev)) {
  569. u32 adpa;
  570. adpa = I915_READ(crt->adpa_reg);
  571. adpa &= ~ADPA_CRT_HOTPLUG_MASK;
  572. adpa |= ADPA_HOTPLUG_BITS;
  573. I915_WRITE(crt->adpa_reg, adpa);
  574. POSTING_READ(crt->adpa_reg);
  575. DRM_DEBUG_KMS("pch crt adpa set to 0x%x\n", adpa);
  576. crt->force_hotplug_required = 1;
  577. }
  578. }
  579. /*
  580. * Routines for controlling stuff on the analog port
  581. */
  582. static const struct drm_encoder_helper_funcs crt_encoder_funcs = {
  583. .mode_set = intel_crt_mode_set,
  584. };
  585. static const struct drm_connector_funcs intel_crt_connector_funcs = {
  586. .reset = intel_crt_reset,
  587. .dpms = intel_crt_dpms,
  588. .detect = intel_crt_detect,
  589. .fill_modes = drm_helper_probe_single_connector_modes,
  590. .destroy = intel_crt_destroy,
  591. .set_property = intel_crt_set_property,
  592. };
  593. static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = {
  594. .mode_valid = intel_crt_mode_valid,
  595. .get_modes = intel_crt_get_modes,
  596. .best_encoder = intel_best_encoder,
  597. };
  598. static const struct drm_encoder_funcs intel_crt_enc_funcs = {
  599. .destroy = intel_encoder_destroy,
  600. };
  601. static int __init intel_no_crt_dmi_callback(const struct dmi_system_id *id)
  602. {
  603. DRM_INFO("Skipping CRT initialization for %s\n", id->ident);
  604. return 1;
  605. }
  606. static const struct dmi_system_id intel_no_crt[] = {
  607. {
  608. .callback = intel_no_crt_dmi_callback,
  609. .ident = "ACER ZGB",
  610. .matches = {
  611. DMI_MATCH(DMI_SYS_VENDOR, "ACER"),
  612. DMI_MATCH(DMI_PRODUCT_NAME, "ZGB"),
  613. },
  614. },
  615. { }
  616. };
  617. void intel_crt_init(struct drm_device *dev)
  618. {
  619. struct drm_connector *connector;
  620. struct intel_crt *crt;
  621. struct intel_connector *intel_connector;
  622. struct drm_i915_private *dev_priv = dev->dev_private;
  623. /* Skip machines without VGA that falsely report hotplug events */
  624. if (dmi_check_system(intel_no_crt))
  625. return;
  626. crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL);
  627. if (!crt)
  628. return;
  629. intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
  630. if (!intel_connector) {
  631. kfree(crt);
  632. return;
  633. }
  634. connector = &intel_connector->base;
  635. crt->connector = intel_connector;
  636. drm_connector_init(dev, &intel_connector->base,
  637. &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA);
  638. drm_encoder_init(dev, &crt->base.base, &intel_crt_enc_funcs,
  639. DRM_MODE_ENCODER_DAC);
  640. intel_connector_attach_encoder(intel_connector, &crt->base);
  641. crt->base.type = INTEL_OUTPUT_ANALOG;
  642. crt->base.cloneable = true;
  643. if (IS_I830(dev))
  644. crt->base.crtc_mask = (1 << 0);
  645. else
  646. crt->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
  647. if (IS_GEN2(dev))
  648. connector->interlace_allowed = 0;
  649. else
  650. connector->interlace_allowed = 1;
  651. connector->doublescan_allowed = 0;
  652. if (HAS_PCH_SPLIT(dev))
  653. crt->adpa_reg = PCH_ADPA;
  654. else if (IS_VALLEYVIEW(dev))
  655. crt->adpa_reg = VLV_ADPA;
  656. else
  657. crt->adpa_reg = ADPA;
  658. crt->base.compute_config = intel_crt_compute_config;
  659. crt->base.disable = intel_disable_crt;
  660. crt->base.enable = intel_enable_crt;
  661. crt->base.get_config = intel_crt_get_config;
  662. if (I915_HAS_HOTPLUG(dev))
  663. crt->base.hpd_pin = HPD_CRT;
  664. if (HAS_DDI(dev))
  665. crt->base.get_hw_state = intel_ddi_get_hw_state;
  666. else
  667. crt->base.get_hw_state = intel_crt_get_hw_state;
  668. intel_connector->get_hw_state = intel_connector_get_hw_state;
  669. drm_encoder_helper_add(&crt->base.base, &crt_encoder_funcs);
  670. drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs);
  671. drm_sysfs_connector_add(connector);
  672. if (!I915_HAS_HOTPLUG(dev))
  673. intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT;
  674. /*
  675. * Configure the automatic hotplug detection stuff
  676. */
  677. crt->force_hotplug_required = 0;
  678. /*
  679. * TODO: find a proper way to discover whether we need to set the the
  680. * polarity and link reversal bits or not, instead of relying on the
  681. * BIOS.
  682. */
  683. if (HAS_PCH_LPT(dev)) {
  684. u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT |
  685. FDI_RX_LINK_REVERSAL_OVERRIDE;
  686. dev_priv->fdi_rx_config = I915_READ(_FDI_RXA_CTL) & fdi_config;
  687. }
  688. }