i915_irq.c 103 KB

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  1. /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
  2. */
  3. /*
  4. * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
  5. * All Rights Reserved.
  6. *
  7. * Permission is hereby granted, free of charge, to any person obtaining a
  8. * copy of this software and associated documentation files (the
  9. * "Software"), to deal in the Software without restriction, including
  10. * without limitation the rights to use, copy, modify, merge, publish,
  11. * distribute, sub license, and/or sell copies of the Software, and to
  12. * permit persons to whom the Software is furnished to do so, subject to
  13. * the following conditions:
  14. *
  15. * The above copyright notice and this permission notice (including the
  16. * next paragraph) shall be included in all copies or substantial portions
  17. * of the Software.
  18. *
  19. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20. * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22. * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23. * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24. * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25. * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26. *
  27. */
  28. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  29. #include <linux/sysrq.h>
  30. #include <linux/slab.h>
  31. #include <drm/drmP.h>
  32. #include <drm/i915_drm.h>
  33. #include "i915_drv.h"
  34. #include "i915_trace.h"
  35. #include "intel_drv.h"
  36. static const u32 hpd_ibx[] = {
  37. [HPD_CRT] = SDE_CRT_HOTPLUG,
  38. [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
  39. [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
  40. [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
  41. [HPD_PORT_D] = SDE_PORTD_HOTPLUG
  42. };
  43. static const u32 hpd_cpt[] = {
  44. [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
  45. [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
  46. [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
  47. [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
  48. [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
  49. };
  50. static const u32 hpd_mask_i915[] = {
  51. [HPD_CRT] = CRT_HOTPLUG_INT_EN,
  52. [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
  53. [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
  54. [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
  55. [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
  56. [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
  57. };
  58. static const u32 hpd_status_gen4[] = {
  59. [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
  60. [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
  61. [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
  62. [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
  63. [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
  64. [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
  65. };
  66. static const u32 hpd_status_i965[] = {
  67. [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
  68. [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I965,
  69. [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I965,
  70. [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
  71. [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
  72. [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
  73. };
  74. static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */
  75. [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
  76. [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
  77. [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
  78. [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
  79. [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
  80. [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
  81. };
  82. static void ibx_hpd_irq_setup(struct drm_device *dev);
  83. static void i915_hpd_irq_setup(struct drm_device *dev);
  84. /* For display hotplug interrupt */
  85. static void
  86. ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  87. {
  88. if ((dev_priv->irq_mask & mask) != 0) {
  89. dev_priv->irq_mask &= ~mask;
  90. I915_WRITE(DEIMR, dev_priv->irq_mask);
  91. POSTING_READ(DEIMR);
  92. }
  93. }
  94. static void
  95. ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  96. {
  97. if ((dev_priv->irq_mask & mask) != mask) {
  98. dev_priv->irq_mask |= mask;
  99. I915_WRITE(DEIMR, dev_priv->irq_mask);
  100. POSTING_READ(DEIMR);
  101. }
  102. }
  103. static bool ivb_can_enable_err_int(struct drm_device *dev)
  104. {
  105. struct drm_i915_private *dev_priv = dev->dev_private;
  106. struct intel_crtc *crtc;
  107. enum pipe pipe;
  108. for_each_pipe(pipe) {
  109. crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
  110. if (crtc->cpu_fifo_underrun_disabled)
  111. return false;
  112. }
  113. return true;
  114. }
  115. static bool cpt_can_enable_serr_int(struct drm_device *dev)
  116. {
  117. struct drm_i915_private *dev_priv = dev->dev_private;
  118. enum pipe pipe;
  119. struct intel_crtc *crtc;
  120. for_each_pipe(pipe) {
  121. crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
  122. if (crtc->pch_fifo_underrun_disabled)
  123. return false;
  124. }
  125. return true;
  126. }
  127. static void ironlake_set_fifo_underrun_reporting(struct drm_device *dev,
  128. enum pipe pipe, bool enable)
  129. {
  130. struct drm_i915_private *dev_priv = dev->dev_private;
  131. uint32_t bit = (pipe == PIPE_A) ? DE_PIPEA_FIFO_UNDERRUN :
  132. DE_PIPEB_FIFO_UNDERRUN;
  133. if (enable)
  134. ironlake_enable_display_irq(dev_priv, bit);
  135. else
  136. ironlake_disable_display_irq(dev_priv, bit);
  137. }
  138. static void ivybridge_set_fifo_underrun_reporting(struct drm_device *dev,
  139. bool enable)
  140. {
  141. struct drm_i915_private *dev_priv = dev->dev_private;
  142. if (enable) {
  143. if (!ivb_can_enable_err_int(dev))
  144. return;
  145. I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN_A |
  146. ERR_INT_FIFO_UNDERRUN_B |
  147. ERR_INT_FIFO_UNDERRUN_C);
  148. ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB);
  149. } else {
  150. ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB);
  151. }
  152. }
  153. static void ibx_set_fifo_underrun_reporting(struct intel_crtc *crtc,
  154. bool enable)
  155. {
  156. struct drm_device *dev = crtc->base.dev;
  157. struct drm_i915_private *dev_priv = dev->dev_private;
  158. uint32_t bit = (crtc->pipe == PIPE_A) ? SDE_TRANSA_FIFO_UNDER :
  159. SDE_TRANSB_FIFO_UNDER;
  160. if (enable)
  161. I915_WRITE(SDEIMR, I915_READ(SDEIMR) & ~bit);
  162. else
  163. I915_WRITE(SDEIMR, I915_READ(SDEIMR) | bit);
  164. POSTING_READ(SDEIMR);
  165. }
  166. static void cpt_set_fifo_underrun_reporting(struct drm_device *dev,
  167. enum transcoder pch_transcoder,
  168. bool enable)
  169. {
  170. struct drm_i915_private *dev_priv = dev->dev_private;
  171. if (enable) {
  172. if (!cpt_can_enable_serr_int(dev))
  173. return;
  174. I915_WRITE(SERR_INT, SERR_INT_TRANS_A_FIFO_UNDERRUN |
  175. SERR_INT_TRANS_B_FIFO_UNDERRUN |
  176. SERR_INT_TRANS_C_FIFO_UNDERRUN);
  177. I915_WRITE(SDEIMR, I915_READ(SDEIMR) & ~SDE_ERROR_CPT);
  178. } else {
  179. I915_WRITE(SDEIMR, I915_READ(SDEIMR) | SDE_ERROR_CPT);
  180. }
  181. POSTING_READ(SDEIMR);
  182. }
  183. /**
  184. * intel_set_cpu_fifo_underrun_reporting - enable/disable FIFO underrun messages
  185. * @dev: drm device
  186. * @pipe: pipe
  187. * @enable: true if we want to report FIFO underrun errors, false otherwise
  188. *
  189. * This function makes us disable or enable CPU fifo underruns for a specific
  190. * pipe. Notice that on some Gens (e.g. IVB, HSW), disabling FIFO underrun
  191. * reporting for one pipe may also disable all the other CPU error interruts for
  192. * the other pipes, due to the fact that there's just one interrupt mask/enable
  193. * bit for all the pipes.
  194. *
  195. * Returns the previous state of underrun reporting.
  196. */
  197. bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
  198. enum pipe pipe, bool enable)
  199. {
  200. struct drm_i915_private *dev_priv = dev->dev_private;
  201. struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
  202. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  203. unsigned long flags;
  204. bool ret;
  205. spin_lock_irqsave(&dev_priv->irq_lock, flags);
  206. ret = !intel_crtc->cpu_fifo_underrun_disabled;
  207. if (enable == ret)
  208. goto done;
  209. intel_crtc->cpu_fifo_underrun_disabled = !enable;
  210. if (IS_GEN5(dev) || IS_GEN6(dev))
  211. ironlake_set_fifo_underrun_reporting(dev, pipe, enable);
  212. else if (IS_GEN7(dev))
  213. ivybridge_set_fifo_underrun_reporting(dev, enable);
  214. done:
  215. spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
  216. return ret;
  217. }
  218. /**
  219. * intel_set_pch_fifo_underrun_reporting - enable/disable FIFO underrun messages
  220. * @dev: drm device
  221. * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
  222. * @enable: true if we want to report FIFO underrun errors, false otherwise
  223. *
  224. * This function makes us disable or enable PCH fifo underruns for a specific
  225. * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO
  226. * underrun reporting for one transcoder may also disable all the other PCH
  227. * error interruts for the other transcoders, due to the fact that there's just
  228. * one interrupt mask/enable bit for all the transcoders.
  229. *
  230. * Returns the previous state of underrun reporting.
  231. */
  232. bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
  233. enum transcoder pch_transcoder,
  234. bool enable)
  235. {
  236. struct drm_i915_private *dev_priv = dev->dev_private;
  237. enum pipe p;
  238. struct drm_crtc *crtc;
  239. struct intel_crtc *intel_crtc;
  240. unsigned long flags;
  241. bool ret;
  242. if (HAS_PCH_LPT(dev)) {
  243. crtc = NULL;
  244. for_each_pipe(p) {
  245. struct drm_crtc *c = dev_priv->pipe_to_crtc_mapping[p];
  246. if (intel_pipe_has_type(c, INTEL_OUTPUT_ANALOG)) {
  247. crtc = c;
  248. break;
  249. }
  250. }
  251. if (!crtc) {
  252. DRM_ERROR("PCH FIFO underrun, but no CRTC using the PCH found\n");
  253. return false;
  254. }
  255. } else {
  256. crtc = dev_priv->pipe_to_crtc_mapping[pch_transcoder];
  257. }
  258. intel_crtc = to_intel_crtc(crtc);
  259. spin_lock_irqsave(&dev_priv->irq_lock, flags);
  260. ret = !intel_crtc->pch_fifo_underrun_disabled;
  261. if (enable == ret)
  262. goto done;
  263. intel_crtc->pch_fifo_underrun_disabled = !enable;
  264. if (HAS_PCH_IBX(dev))
  265. ibx_set_fifo_underrun_reporting(intel_crtc, enable);
  266. else
  267. cpt_set_fifo_underrun_reporting(dev, pch_transcoder, enable);
  268. done:
  269. spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
  270. return ret;
  271. }
  272. void
  273. i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
  274. {
  275. u32 reg = PIPESTAT(pipe);
  276. u32 pipestat = I915_READ(reg) & 0x7fff0000;
  277. if ((pipestat & mask) == mask)
  278. return;
  279. /* Enable the interrupt, clear any pending status */
  280. pipestat |= mask | (mask >> 16);
  281. I915_WRITE(reg, pipestat);
  282. POSTING_READ(reg);
  283. }
  284. void
  285. i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
  286. {
  287. u32 reg = PIPESTAT(pipe);
  288. u32 pipestat = I915_READ(reg) & 0x7fff0000;
  289. if ((pipestat & mask) == 0)
  290. return;
  291. pipestat &= ~mask;
  292. I915_WRITE(reg, pipestat);
  293. POSTING_READ(reg);
  294. }
  295. /**
  296. * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
  297. */
  298. static void i915_enable_asle_pipestat(struct drm_device *dev)
  299. {
  300. drm_i915_private_t *dev_priv = dev->dev_private;
  301. unsigned long irqflags;
  302. if (!dev_priv->opregion.asle || !IS_MOBILE(dev))
  303. return;
  304. spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  305. i915_enable_pipestat(dev_priv, 1, PIPE_LEGACY_BLC_EVENT_ENABLE);
  306. if (INTEL_INFO(dev)->gen >= 4)
  307. i915_enable_pipestat(dev_priv, 0, PIPE_LEGACY_BLC_EVENT_ENABLE);
  308. spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  309. }
  310. /**
  311. * i915_pipe_enabled - check if a pipe is enabled
  312. * @dev: DRM device
  313. * @pipe: pipe to check
  314. *
  315. * Reading certain registers when the pipe is disabled can hang the chip.
  316. * Use this routine to make sure the PLL is running and the pipe is active
  317. * before reading such registers if unsure.
  318. */
  319. static int
  320. i915_pipe_enabled(struct drm_device *dev, int pipe)
  321. {
  322. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  323. if (drm_core_check_feature(dev, DRIVER_MODESET)) {
  324. /* Locking is horribly broken here, but whatever. */
  325. struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
  326. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  327. return intel_crtc->active;
  328. } else {
  329. return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
  330. }
  331. }
  332. /* Called from drm generic code, passed a 'crtc', which
  333. * we use as a pipe index
  334. */
  335. static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
  336. {
  337. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  338. unsigned long high_frame;
  339. unsigned long low_frame;
  340. u32 high1, high2, low;
  341. if (!i915_pipe_enabled(dev, pipe)) {
  342. DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
  343. "pipe %c\n", pipe_name(pipe));
  344. return 0;
  345. }
  346. high_frame = PIPEFRAME(pipe);
  347. low_frame = PIPEFRAMEPIXEL(pipe);
  348. /*
  349. * High & low register fields aren't synchronized, so make sure
  350. * we get a low value that's stable across two reads of the high
  351. * register.
  352. */
  353. do {
  354. high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
  355. low = I915_READ(low_frame) & PIPE_FRAME_LOW_MASK;
  356. high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
  357. } while (high1 != high2);
  358. high1 >>= PIPE_FRAME_HIGH_SHIFT;
  359. low >>= PIPE_FRAME_LOW_SHIFT;
  360. return (high1 << 8) | low;
  361. }
  362. static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
  363. {
  364. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  365. int reg = PIPE_FRMCOUNT_GM45(pipe);
  366. if (!i915_pipe_enabled(dev, pipe)) {
  367. DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
  368. "pipe %c\n", pipe_name(pipe));
  369. return 0;
  370. }
  371. return I915_READ(reg);
  372. }
  373. static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
  374. int *vpos, int *hpos)
  375. {
  376. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  377. u32 vbl = 0, position = 0;
  378. int vbl_start, vbl_end, htotal, vtotal;
  379. bool in_vbl = true;
  380. int ret = 0;
  381. enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
  382. pipe);
  383. if (!i915_pipe_enabled(dev, pipe)) {
  384. DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
  385. "pipe %c\n", pipe_name(pipe));
  386. return 0;
  387. }
  388. /* Get vtotal. */
  389. vtotal = 1 + ((I915_READ(VTOTAL(cpu_transcoder)) >> 16) & 0x1fff);
  390. if (INTEL_INFO(dev)->gen >= 4) {
  391. /* No obvious pixelcount register. Only query vertical
  392. * scanout position from Display scan line register.
  393. */
  394. position = I915_READ(PIPEDSL(pipe));
  395. /* Decode into vertical scanout position. Don't have
  396. * horizontal scanout position.
  397. */
  398. *vpos = position & 0x1fff;
  399. *hpos = 0;
  400. } else {
  401. /* Have access to pixelcount since start of frame.
  402. * We can split this into vertical and horizontal
  403. * scanout position.
  404. */
  405. position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
  406. htotal = 1 + ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff);
  407. *vpos = position / htotal;
  408. *hpos = position - (*vpos * htotal);
  409. }
  410. /* Query vblank area. */
  411. vbl = I915_READ(VBLANK(cpu_transcoder));
  412. /* Test position against vblank region. */
  413. vbl_start = vbl & 0x1fff;
  414. vbl_end = (vbl >> 16) & 0x1fff;
  415. if ((*vpos < vbl_start) || (*vpos > vbl_end))
  416. in_vbl = false;
  417. /* Inside "upper part" of vblank area? Apply corrective offset: */
  418. if (in_vbl && (*vpos >= vbl_start))
  419. *vpos = *vpos - vtotal;
  420. /* Readouts valid? */
  421. if (vbl > 0)
  422. ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
  423. /* In vblank? */
  424. if (in_vbl)
  425. ret |= DRM_SCANOUTPOS_INVBL;
  426. return ret;
  427. }
  428. static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
  429. int *max_error,
  430. struct timeval *vblank_time,
  431. unsigned flags)
  432. {
  433. struct drm_crtc *crtc;
  434. if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) {
  435. DRM_ERROR("Invalid crtc %d\n", pipe);
  436. return -EINVAL;
  437. }
  438. /* Get drm_crtc to timestamp: */
  439. crtc = intel_get_crtc_for_pipe(dev, pipe);
  440. if (crtc == NULL) {
  441. DRM_ERROR("Invalid crtc %d\n", pipe);
  442. return -EINVAL;
  443. }
  444. if (!crtc->enabled) {
  445. DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
  446. return -EBUSY;
  447. }
  448. /* Helper routine in DRM core does all the work: */
  449. return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
  450. vblank_time, flags,
  451. crtc);
  452. }
  453. static int intel_hpd_irq_event(struct drm_device *dev, struct drm_connector *connector)
  454. {
  455. enum drm_connector_status old_status;
  456. WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
  457. old_status = connector->status;
  458. connector->status = connector->funcs->detect(connector, false);
  459. DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %d to %d\n",
  460. connector->base.id,
  461. drm_get_connector_name(connector),
  462. old_status, connector->status);
  463. return (old_status != connector->status);
  464. }
  465. /*
  466. * Handle hotplug events outside the interrupt handler proper.
  467. */
  468. #define I915_REENABLE_HOTPLUG_DELAY (2*60*1000)
  469. static void i915_hotplug_work_func(struct work_struct *work)
  470. {
  471. drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
  472. hotplug_work);
  473. struct drm_device *dev = dev_priv->dev;
  474. struct drm_mode_config *mode_config = &dev->mode_config;
  475. struct intel_connector *intel_connector;
  476. struct intel_encoder *intel_encoder;
  477. struct drm_connector *connector;
  478. unsigned long irqflags;
  479. bool hpd_disabled = false;
  480. bool changed = false;
  481. u32 hpd_event_bits;
  482. /* HPD irq before everything is fully set up. */
  483. if (!dev_priv->enable_hotplug_processing)
  484. return;
  485. mutex_lock(&mode_config->mutex);
  486. DRM_DEBUG_KMS("running encoder hotplug functions\n");
  487. spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  488. hpd_event_bits = dev_priv->hpd_event_bits;
  489. dev_priv->hpd_event_bits = 0;
  490. list_for_each_entry(connector, &mode_config->connector_list, head) {
  491. intel_connector = to_intel_connector(connector);
  492. intel_encoder = intel_connector->encoder;
  493. if (intel_encoder->hpd_pin > HPD_NONE &&
  494. dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_MARK_DISABLED &&
  495. connector->polled == DRM_CONNECTOR_POLL_HPD) {
  496. DRM_INFO("HPD interrupt storm detected on connector %s: "
  497. "switching from hotplug detection to polling\n",
  498. drm_get_connector_name(connector));
  499. dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark = HPD_DISABLED;
  500. connector->polled = DRM_CONNECTOR_POLL_CONNECT
  501. | DRM_CONNECTOR_POLL_DISCONNECT;
  502. hpd_disabled = true;
  503. }
  504. if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
  505. DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n",
  506. drm_get_connector_name(connector), intel_encoder->hpd_pin);
  507. }
  508. }
  509. /* if there were no outputs to poll, poll was disabled,
  510. * therefore make sure it's enabled when disabling HPD on
  511. * some connectors */
  512. if (hpd_disabled) {
  513. drm_kms_helper_poll_enable(dev);
  514. mod_timer(&dev_priv->hotplug_reenable_timer,
  515. jiffies + msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY));
  516. }
  517. spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  518. list_for_each_entry(connector, &mode_config->connector_list, head) {
  519. intel_connector = to_intel_connector(connector);
  520. intel_encoder = intel_connector->encoder;
  521. if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
  522. if (intel_encoder->hot_plug)
  523. intel_encoder->hot_plug(intel_encoder);
  524. if (intel_hpd_irq_event(dev, connector))
  525. changed = true;
  526. }
  527. }
  528. mutex_unlock(&mode_config->mutex);
  529. if (changed)
  530. drm_kms_helper_hotplug_event(dev);
  531. }
  532. static void ironlake_handle_rps_change(struct drm_device *dev)
  533. {
  534. drm_i915_private_t *dev_priv = dev->dev_private;
  535. u32 busy_up, busy_down, max_avg, min_avg;
  536. u8 new_delay;
  537. unsigned long flags;
  538. spin_lock_irqsave(&mchdev_lock, flags);
  539. I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
  540. new_delay = dev_priv->ips.cur_delay;
  541. I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
  542. busy_up = I915_READ(RCPREVBSYTUPAVG);
  543. busy_down = I915_READ(RCPREVBSYTDNAVG);
  544. max_avg = I915_READ(RCBMAXAVG);
  545. min_avg = I915_READ(RCBMINAVG);
  546. /* Handle RCS change request from hw */
  547. if (busy_up > max_avg) {
  548. if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
  549. new_delay = dev_priv->ips.cur_delay - 1;
  550. if (new_delay < dev_priv->ips.max_delay)
  551. new_delay = dev_priv->ips.max_delay;
  552. } else if (busy_down < min_avg) {
  553. if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
  554. new_delay = dev_priv->ips.cur_delay + 1;
  555. if (new_delay > dev_priv->ips.min_delay)
  556. new_delay = dev_priv->ips.min_delay;
  557. }
  558. if (ironlake_set_drps(dev, new_delay))
  559. dev_priv->ips.cur_delay = new_delay;
  560. spin_unlock_irqrestore(&mchdev_lock, flags);
  561. return;
  562. }
  563. static void notify_ring(struct drm_device *dev,
  564. struct intel_ring_buffer *ring)
  565. {
  566. struct drm_i915_private *dev_priv = dev->dev_private;
  567. if (ring->obj == NULL)
  568. return;
  569. trace_i915_gem_request_complete(ring, ring->get_seqno(ring, false));
  570. wake_up_all(&ring->irq_queue);
  571. if (i915_enable_hangcheck) {
  572. mod_timer(&dev_priv->gpu_error.hangcheck_timer,
  573. round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
  574. }
  575. }
  576. static void gen6_pm_rps_work(struct work_struct *work)
  577. {
  578. drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
  579. rps.work);
  580. u32 pm_iir, pm_imr;
  581. u8 new_delay;
  582. spin_lock_irq(&dev_priv->rps.lock);
  583. pm_iir = dev_priv->rps.pm_iir;
  584. dev_priv->rps.pm_iir = 0;
  585. pm_imr = I915_READ(GEN6_PMIMR);
  586. /* Make sure not to corrupt PMIMR state used by ringbuffer code */
  587. I915_WRITE(GEN6_PMIMR, pm_imr & ~GEN6_PM_RPS_EVENTS);
  588. spin_unlock_irq(&dev_priv->rps.lock);
  589. if ((pm_iir & GEN6_PM_RPS_EVENTS) == 0)
  590. return;
  591. mutex_lock(&dev_priv->rps.hw_lock);
  592. if (pm_iir & GEN6_PM_RP_UP_THRESHOLD)
  593. new_delay = dev_priv->rps.cur_delay + 1;
  594. else
  595. new_delay = dev_priv->rps.cur_delay - 1;
  596. /* sysfs frequency interfaces may have snuck in while servicing the
  597. * interrupt
  598. */
  599. if (!(new_delay > dev_priv->rps.max_delay ||
  600. new_delay < dev_priv->rps.min_delay)) {
  601. if (IS_VALLEYVIEW(dev_priv->dev))
  602. valleyview_set_rps(dev_priv->dev, new_delay);
  603. else
  604. gen6_set_rps(dev_priv->dev, new_delay);
  605. }
  606. if (IS_VALLEYVIEW(dev_priv->dev)) {
  607. /*
  608. * On VLV, when we enter RC6 we may not be at the minimum
  609. * voltage level, so arm a timer to check. It should only
  610. * fire when there's activity or once after we've entered
  611. * RC6, and then won't be re-armed until the next RPS interrupt.
  612. */
  613. mod_delayed_work(dev_priv->wq, &dev_priv->rps.vlv_work,
  614. msecs_to_jiffies(100));
  615. }
  616. mutex_unlock(&dev_priv->rps.hw_lock);
  617. }
  618. /**
  619. * ivybridge_parity_work - Workqueue called when a parity error interrupt
  620. * occurred.
  621. * @work: workqueue struct
  622. *
  623. * Doesn't actually do anything except notify userspace. As a consequence of
  624. * this event, userspace should try to remap the bad rows since statistically
  625. * it is likely the same row is more likely to go bad again.
  626. */
  627. static void ivybridge_parity_work(struct work_struct *work)
  628. {
  629. drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
  630. l3_parity.error_work);
  631. u32 error_status, row, bank, subbank;
  632. char *parity_event[5];
  633. uint32_t misccpctl;
  634. unsigned long flags;
  635. /* We must turn off DOP level clock gating to access the L3 registers.
  636. * In order to prevent a get/put style interface, acquire struct mutex
  637. * any time we access those registers.
  638. */
  639. mutex_lock(&dev_priv->dev->struct_mutex);
  640. misccpctl = I915_READ(GEN7_MISCCPCTL);
  641. I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
  642. POSTING_READ(GEN7_MISCCPCTL);
  643. error_status = I915_READ(GEN7_L3CDERRST1);
  644. row = GEN7_PARITY_ERROR_ROW(error_status);
  645. bank = GEN7_PARITY_ERROR_BANK(error_status);
  646. subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
  647. I915_WRITE(GEN7_L3CDERRST1, GEN7_PARITY_ERROR_VALID |
  648. GEN7_L3CDERRST1_ENABLE);
  649. POSTING_READ(GEN7_L3CDERRST1);
  650. I915_WRITE(GEN7_MISCCPCTL, misccpctl);
  651. spin_lock_irqsave(&dev_priv->irq_lock, flags);
  652. dev_priv->gt_irq_mask &= ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
  653. I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
  654. spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
  655. mutex_unlock(&dev_priv->dev->struct_mutex);
  656. parity_event[0] = "L3_PARITY_ERROR=1";
  657. parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
  658. parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
  659. parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
  660. parity_event[4] = NULL;
  661. kobject_uevent_env(&dev_priv->dev->primary->kdev.kobj,
  662. KOBJ_CHANGE, parity_event);
  663. DRM_DEBUG("Parity error: Row = %d, Bank = %d, Sub bank = %d.\n",
  664. row, bank, subbank);
  665. kfree(parity_event[3]);
  666. kfree(parity_event[2]);
  667. kfree(parity_event[1]);
  668. }
  669. static void ivybridge_handle_parity_error(struct drm_device *dev)
  670. {
  671. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  672. unsigned long flags;
  673. if (!HAS_L3_GPU_CACHE(dev))
  674. return;
  675. spin_lock_irqsave(&dev_priv->irq_lock, flags);
  676. dev_priv->gt_irq_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
  677. I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
  678. spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
  679. queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
  680. }
  681. static void snb_gt_irq_handler(struct drm_device *dev,
  682. struct drm_i915_private *dev_priv,
  683. u32 gt_iir)
  684. {
  685. if (gt_iir &
  686. (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
  687. notify_ring(dev, &dev_priv->ring[RCS]);
  688. if (gt_iir & GT_BSD_USER_INTERRUPT)
  689. notify_ring(dev, &dev_priv->ring[VCS]);
  690. if (gt_iir & GT_BLT_USER_INTERRUPT)
  691. notify_ring(dev, &dev_priv->ring[BCS]);
  692. if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
  693. GT_BSD_CS_ERROR_INTERRUPT |
  694. GT_RENDER_CS_MASTER_ERROR_INTERRUPT)) {
  695. DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir);
  696. i915_handle_error(dev, false);
  697. }
  698. if (gt_iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
  699. ivybridge_handle_parity_error(dev);
  700. }
  701. /* Legacy way of handling PM interrupts */
  702. static void gen6_queue_rps_work(struct drm_i915_private *dev_priv,
  703. u32 pm_iir)
  704. {
  705. unsigned long flags;
  706. /*
  707. * IIR bits should never already be set because IMR should
  708. * prevent an interrupt from being shown in IIR. The warning
  709. * displays a case where we've unsafely cleared
  710. * dev_priv->rps.pm_iir. Although missing an interrupt of the same
  711. * type is not a problem, it displays a problem in the logic.
  712. *
  713. * The mask bit in IMR is cleared by dev_priv->rps.work.
  714. */
  715. spin_lock_irqsave(&dev_priv->rps.lock, flags);
  716. dev_priv->rps.pm_iir |= pm_iir;
  717. I915_WRITE(GEN6_PMIMR, dev_priv->rps.pm_iir);
  718. POSTING_READ(GEN6_PMIMR);
  719. spin_unlock_irqrestore(&dev_priv->rps.lock, flags);
  720. queue_work(dev_priv->wq, &dev_priv->rps.work);
  721. }
  722. #define HPD_STORM_DETECT_PERIOD 1000
  723. #define HPD_STORM_THRESHOLD 5
  724. static inline bool hotplug_irq_storm_detect(struct drm_device *dev,
  725. u32 hotplug_trigger,
  726. const u32 *hpd)
  727. {
  728. drm_i915_private_t *dev_priv = dev->dev_private;
  729. unsigned long irqflags;
  730. int i;
  731. bool ret = false;
  732. spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  733. for (i = 1; i < HPD_NUM_PINS; i++) {
  734. if (!(hpd[i] & hotplug_trigger) ||
  735. dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED)
  736. continue;
  737. dev_priv->hpd_event_bits |= (1 << i);
  738. if (!time_in_range(jiffies, dev_priv->hpd_stats[i].hpd_last_jiffies,
  739. dev_priv->hpd_stats[i].hpd_last_jiffies
  740. + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD))) {
  741. dev_priv->hpd_stats[i].hpd_last_jiffies = jiffies;
  742. dev_priv->hpd_stats[i].hpd_cnt = 0;
  743. } else if (dev_priv->hpd_stats[i].hpd_cnt > HPD_STORM_THRESHOLD) {
  744. dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED;
  745. dev_priv->hpd_event_bits &= ~(1 << i);
  746. DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i);
  747. ret = true;
  748. } else {
  749. dev_priv->hpd_stats[i].hpd_cnt++;
  750. }
  751. }
  752. spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  753. return ret;
  754. }
  755. static void gmbus_irq_handler(struct drm_device *dev)
  756. {
  757. struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
  758. wake_up_all(&dev_priv->gmbus_wait_queue);
  759. }
  760. static void dp_aux_irq_handler(struct drm_device *dev)
  761. {
  762. struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
  763. wake_up_all(&dev_priv->gmbus_wait_queue);
  764. }
  765. /* Unlike gen6_queue_rps_work() from which this function is originally derived,
  766. * we must be able to deal with other PM interrupts. This is complicated because
  767. * of the way in which we use the masks to defer the RPS work (which for
  768. * posterity is necessary because of forcewake).
  769. */
  770. static void hsw_pm_irq_handler(struct drm_i915_private *dev_priv,
  771. u32 pm_iir)
  772. {
  773. unsigned long flags;
  774. spin_lock_irqsave(&dev_priv->rps.lock, flags);
  775. dev_priv->rps.pm_iir |= pm_iir & GEN6_PM_RPS_EVENTS;
  776. if (dev_priv->rps.pm_iir) {
  777. I915_WRITE(GEN6_PMIMR, dev_priv->rps.pm_iir);
  778. /* never want to mask useful interrupts. (also posting read) */
  779. WARN_ON(I915_READ_NOTRACE(GEN6_PMIMR) & ~GEN6_PM_RPS_EVENTS);
  780. /* TODO: if queue_work is slow, move it out of the spinlock */
  781. queue_work(dev_priv->wq, &dev_priv->rps.work);
  782. }
  783. spin_unlock_irqrestore(&dev_priv->rps.lock, flags);
  784. if (pm_iir & ~GEN6_PM_RPS_EVENTS) {
  785. if (pm_iir & PM_VEBOX_USER_INTERRUPT)
  786. notify_ring(dev_priv->dev, &dev_priv->ring[VECS]);
  787. if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) {
  788. DRM_ERROR("VEBOX CS error interrupt 0x%08x\n", pm_iir);
  789. i915_handle_error(dev_priv->dev, false);
  790. }
  791. }
  792. }
  793. static irqreturn_t valleyview_irq_handler(int irq, void *arg)
  794. {
  795. struct drm_device *dev = (struct drm_device *) arg;
  796. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  797. u32 iir, gt_iir, pm_iir;
  798. irqreturn_t ret = IRQ_NONE;
  799. unsigned long irqflags;
  800. int pipe;
  801. u32 pipe_stats[I915_MAX_PIPES];
  802. atomic_inc(&dev_priv->irq_received);
  803. while (true) {
  804. iir = I915_READ(VLV_IIR);
  805. gt_iir = I915_READ(GTIIR);
  806. pm_iir = I915_READ(GEN6_PMIIR);
  807. if (gt_iir == 0 && pm_iir == 0 && iir == 0)
  808. goto out;
  809. ret = IRQ_HANDLED;
  810. snb_gt_irq_handler(dev, dev_priv, gt_iir);
  811. spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  812. for_each_pipe(pipe) {
  813. int reg = PIPESTAT(pipe);
  814. pipe_stats[pipe] = I915_READ(reg);
  815. /*
  816. * Clear the PIPE*STAT regs before the IIR
  817. */
  818. if (pipe_stats[pipe] & 0x8000ffff) {
  819. if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
  820. DRM_DEBUG_DRIVER("pipe %c underrun\n",
  821. pipe_name(pipe));
  822. I915_WRITE(reg, pipe_stats[pipe]);
  823. }
  824. }
  825. spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  826. for_each_pipe(pipe) {
  827. if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
  828. drm_handle_vblank(dev, pipe);
  829. if (pipe_stats[pipe] & PLANE_FLIPDONE_INT_STATUS_VLV) {
  830. intel_prepare_page_flip(dev, pipe);
  831. intel_finish_page_flip(dev, pipe);
  832. }
  833. }
  834. /* Consume port. Then clear IIR or we'll miss events */
  835. if (iir & I915_DISPLAY_PORT_INTERRUPT) {
  836. u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
  837. u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
  838. DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
  839. hotplug_status);
  840. if (hotplug_trigger) {
  841. if (hotplug_irq_storm_detect(dev, hotplug_trigger, hpd_status_i915))
  842. i915_hpd_irq_setup(dev);
  843. queue_work(dev_priv->wq,
  844. &dev_priv->hotplug_work);
  845. }
  846. I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
  847. I915_READ(PORT_HOTPLUG_STAT);
  848. }
  849. if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
  850. gmbus_irq_handler(dev);
  851. if (pm_iir & GEN6_PM_RPS_EVENTS)
  852. gen6_queue_rps_work(dev_priv, pm_iir);
  853. I915_WRITE(GTIIR, gt_iir);
  854. I915_WRITE(GEN6_PMIIR, pm_iir);
  855. I915_WRITE(VLV_IIR, iir);
  856. }
  857. out:
  858. return ret;
  859. }
  860. static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
  861. {
  862. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  863. int pipe;
  864. u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
  865. if (hotplug_trigger) {
  866. if (hotplug_irq_storm_detect(dev, hotplug_trigger, hpd_ibx))
  867. ibx_hpd_irq_setup(dev);
  868. queue_work(dev_priv->wq, &dev_priv->hotplug_work);
  869. }
  870. if (pch_iir & SDE_AUDIO_POWER_MASK) {
  871. int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
  872. SDE_AUDIO_POWER_SHIFT);
  873. DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
  874. port_name(port));
  875. }
  876. if (pch_iir & SDE_AUX_MASK)
  877. dp_aux_irq_handler(dev);
  878. if (pch_iir & SDE_GMBUS)
  879. gmbus_irq_handler(dev);
  880. if (pch_iir & SDE_AUDIO_HDCP_MASK)
  881. DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
  882. if (pch_iir & SDE_AUDIO_TRANS_MASK)
  883. DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
  884. if (pch_iir & SDE_POISON)
  885. DRM_ERROR("PCH poison interrupt\n");
  886. if (pch_iir & SDE_FDI_MASK)
  887. for_each_pipe(pipe)
  888. DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
  889. pipe_name(pipe),
  890. I915_READ(FDI_RX_IIR(pipe)));
  891. if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
  892. DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
  893. if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
  894. DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
  895. if (pch_iir & SDE_TRANSA_FIFO_UNDER)
  896. if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
  897. false))
  898. DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
  899. if (pch_iir & SDE_TRANSB_FIFO_UNDER)
  900. if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
  901. false))
  902. DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
  903. }
  904. static void ivb_err_int_handler(struct drm_device *dev)
  905. {
  906. struct drm_i915_private *dev_priv = dev->dev_private;
  907. u32 err_int = I915_READ(GEN7_ERR_INT);
  908. if (err_int & ERR_INT_POISON)
  909. DRM_ERROR("Poison interrupt\n");
  910. if (err_int & ERR_INT_FIFO_UNDERRUN_A)
  911. if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_A, false))
  912. DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n");
  913. if (err_int & ERR_INT_FIFO_UNDERRUN_B)
  914. if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_B, false))
  915. DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n");
  916. if (err_int & ERR_INT_FIFO_UNDERRUN_C)
  917. if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_C, false))
  918. DRM_DEBUG_DRIVER("Pipe C FIFO underrun\n");
  919. I915_WRITE(GEN7_ERR_INT, err_int);
  920. }
  921. static void cpt_serr_int_handler(struct drm_device *dev)
  922. {
  923. struct drm_i915_private *dev_priv = dev->dev_private;
  924. u32 serr_int = I915_READ(SERR_INT);
  925. if (serr_int & SERR_INT_POISON)
  926. DRM_ERROR("PCH poison interrupt\n");
  927. if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
  928. if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
  929. false))
  930. DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
  931. if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
  932. if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
  933. false))
  934. DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
  935. if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
  936. if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_C,
  937. false))
  938. DRM_DEBUG_DRIVER("PCH transcoder C FIFO underrun\n");
  939. I915_WRITE(SERR_INT, serr_int);
  940. }
  941. static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
  942. {
  943. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  944. int pipe;
  945. u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
  946. if (hotplug_trigger) {
  947. if (hotplug_irq_storm_detect(dev, hotplug_trigger, hpd_cpt))
  948. ibx_hpd_irq_setup(dev);
  949. queue_work(dev_priv->wq, &dev_priv->hotplug_work);
  950. }
  951. if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
  952. int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
  953. SDE_AUDIO_POWER_SHIFT_CPT);
  954. DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
  955. port_name(port));
  956. }
  957. if (pch_iir & SDE_AUX_MASK_CPT)
  958. dp_aux_irq_handler(dev);
  959. if (pch_iir & SDE_GMBUS_CPT)
  960. gmbus_irq_handler(dev);
  961. if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
  962. DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
  963. if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
  964. DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
  965. if (pch_iir & SDE_FDI_MASK_CPT)
  966. for_each_pipe(pipe)
  967. DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
  968. pipe_name(pipe),
  969. I915_READ(FDI_RX_IIR(pipe)));
  970. if (pch_iir & SDE_ERROR_CPT)
  971. cpt_serr_int_handler(dev);
  972. }
  973. static irqreturn_t ivybridge_irq_handler(int irq, void *arg)
  974. {
  975. struct drm_device *dev = (struct drm_device *) arg;
  976. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  977. u32 de_iir, gt_iir, de_ier, pm_iir, sde_ier = 0;
  978. irqreturn_t ret = IRQ_NONE;
  979. int i;
  980. atomic_inc(&dev_priv->irq_received);
  981. /* We get interrupts on unclaimed registers, so check for this before we
  982. * do any I915_{READ,WRITE}. */
  983. if (IS_HASWELL(dev) &&
  984. (I915_READ_NOTRACE(FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) {
  985. DRM_ERROR("Unclaimed register before interrupt\n");
  986. I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
  987. }
  988. /* disable master interrupt before clearing iir */
  989. de_ier = I915_READ(DEIER);
  990. I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
  991. /* Disable south interrupts. We'll only write to SDEIIR once, so further
  992. * interrupts will will be stored on its back queue, and then we'll be
  993. * able to process them after we restore SDEIER (as soon as we restore
  994. * it, we'll get an interrupt if SDEIIR still has something to process
  995. * due to its back queue). */
  996. if (!HAS_PCH_NOP(dev)) {
  997. sde_ier = I915_READ(SDEIER);
  998. I915_WRITE(SDEIER, 0);
  999. POSTING_READ(SDEIER);
  1000. }
  1001. /* On Haswell, also mask ERR_INT because we don't want to risk
  1002. * generating "unclaimed register" interrupts from inside the interrupt
  1003. * handler. */
  1004. if (IS_HASWELL(dev))
  1005. ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB);
  1006. gt_iir = I915_READ(GTIIR);
  1007. if (gt_iir) {
  1008. snb_gt_irq_handler(dev, dev_priv, gt_iir);
  1009. I915_WRITE(GTIIR, gt_iir);
  1010. ret = IRQ_HANDLED;
  1011. }
  1012. de_iir = I915_READ(DEIIR);
  1013. if (de_iir) {
  1014. if (de_iir & DE_ERR_INT_IVB)
  1015. ivb_err_int_handler(dev);
  1016. if (de_iir & DE_AUX_CHANNEL_A_IVB)
  1017. dp_aux_irq_handler(dev);
  1018. if (de_iir & DE_GSE_IVB)
  1019. intel_opregion_asle_intr(dev);
  1020. for (i = 0; i < 3; i++) {
  1021. if (de_iir & (DE_PIPEA_VBLANK_IVB << (5 * i)))
  1022. drm_handle_vblank(dev, i);
  1023. if (de_iir & (DE_PLANEA_FLIP_DONE_IVB << (5 * i))) {
  1024. intel_prepare_page_flip(dev, i);
  1025. intel_finish_page_flip_plane(dev, i);
  1026. }
  1027. }
  1028. /* check event from PCH */
  1029. if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) {
  1030. u32 pch_iir = I915_READ(SDEIIR);
  1031. cpt_irq_handler(dev, pch_iir);
  1032. /* clear PCH hotplug event before clear CPU irq */
  1033. I915_WRITE(SDEIIR, pch_iir);
  1034. }
  1035. I915_WRITE(DEIIR, de_iir);
  1036. ret = IRQ_HANDLED;
  1037. }
  1038. pm_iir = I915_READ(GEN6_PMIIR);
  1039. if (pm_iir) {
  1040. if (IS_HASWELL(dev))
  1041. hsw_pm_irq_handler(dev_priv, pm_iir);
  1042. else if (pm_iir & GEN6_PM_RPS_EVENTS)
  1043. gen6_queue_rps_work(dev_priv, pm_iir);
  1044. I915_WRITE(GEN6_PMIIR, pm_iir);
  1045. ret = IRQ_HANDLED;
  1046. }
  1047. if (IS_HASWELL(dev) && ivb_can_enable_err_int(dev))
  1048. ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB);
  1049. I915_WRITE(DEIER, de_ier);
  1050. POSTING_READ(DEIER);
  1051. if (!HAS_PCH_NOP(dev)) {
  1052. I915_WRITE(SDEIER, sde_ier);
  1053. POSTING_READ(SDEIER);
  1054. }
  1055. return ret;
  1056. }
  1057. static void ilk_gt_irq_handler(struct drm_device *dev,
  1058. struct drm_i915_private *dev_priv,
  1059. u32 gt_iir)
  1060. {
  1061. if (gt_iir &
  1062. (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
  1063. notify_ring(dev, &dev_priv->ring[RCS]);
  1064. if (gt_iir & ILK_BSD_USER_INTERRUPT)
  1065. notify_ring(dev, &dev_priv->ring[VCS]);
  1066. }
  1067. static irqreturn_t ironlake_irq_handler(int irq, void *arg)
  1068. {
  1069. struct drm_device *dev = (struct drm_device *) arg;
  1070. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1071. int ret = IRQ_NONE;
  1072. u32 de_iir, gt_iir, de_ier, pm_iir, sde_ier;
  1073. atomic_inc(&dev_priv->irq_received);
  1074. /* disable master interrupt before clearing iir */
  1075. de_ier = I915_READ(DEIER);
  1076. I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
  1077. POSTING_READ(DEIER);
  1078. /* Disable south interrupts. We'll only write to SDEIIR once, so further
  1079. * interrupts will will be stored on its back queue, and then we'll be
  1080. * able to process them after we restore SDEIER (as soon as we restore
  1081. * it, we'll get an interrupt if SDEIIR still has something to process
  1082. * due to its back queue). */
  1083. sde_ier = I915_READ(SDEIER);
  1084. I915_WRITE(SDEIER, 0);
  1085. POSTING_READ(SDEIER);
  1086. de_iir = I915_READ(DEIIR);
  1087. gt_iir = I915_READ(GTIIR);
  1088. pm_iir = I915_READ(GEN6_PMIIR);
  1089. if (de_iir == 0 && gt_iir == 0 && (!IS_GEN6(dev) || pm_iir == 0))
  1090. goto done;
  1091. ret = IRQ_HANDLED;
  1092. if (IS_GEN5(dev))
  1093. ilk_gt_irq_handler(dev, dev_priv, gt_iir);
  1094. else
  1095. snb_gt_irq_handler(dev, dev_priv, gt_iir);
  1096. if (de_iir & DE_AUX_CHANNEL_A)
  1097. dp_aux_irq_handler(dev);
  1098. if (de_iir & DE_GSE)
  1099. intel_opregion_asle_intr(dev);
  1100. if (de_iir & DE_PIPEA_VBLANK)
  1101. drm_handle_vblank(dev, 0);
  1102. if (de_iir & DE_PIPEB_VBLANK)
  1103. drm_handle_vblank(dev, 1);
  1104. if (de_iir & DE_POISON)
  1105. DRM_ERROR("Poison interrupt\n");
  1106. if (de_iir & DE_PIPEA_FIFO_UNDERRUN)
  1107. if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_A, false))
  1108. DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n");
  1109. if (de_iir & DE_PIPEB_FIFO_UNDERRUN)
  1110. if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_B, false))
  1111. DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n");
  1112. if (de_iir & DE_PLANEA_FLIP_DONE) {
  1113. intel_prepare_page_flip(dev, 0);
  1114. intel_finish_page_flip_plane(dev, 0);
  1115. }
  1116. if (de_iir & DE_PLANEB_FLIP_DONE) {
  1117. intel_prepare_page_flip(dev, 1);
  1118. intel_finish_page_flip_plane(dev, 1);
  1119. }
  1120. /* check event from PCH */
  1121. if (de_iir & DE_PCH_EVENT) {
  1122. u32 pch_iir = I915_READ(SDEIIR);
  1123. if (HAS_PCH_CPT(dev))
  1124. cpt_irq_handler(dev, pch_iir);
  1125. else
  1126. ibx_irq_handler(dev, pch_iir);
  1127. /* should clear PCH hotplug event before clear CPU irq */
  1128. I915_WRITE(SDEIIR, pch_iir);
  1129. }
  1130. if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
  1131. ironlake_handle_rps_change(dev);
  1132. if (IS_GEN6(dev) && pm_iir & GEN6_PM_RPS_EVENTS)
  1133. gen6_queue_rps_work(dev_priv, pm_iir);
  1134. I915_WRITE(GTIIR, gt_iir);
  1135. I915_WRITE(DEIIR, de_iir);
  1136. I915_WRITE(GEN6_PMIIR, pm_iir);
  1137. done:
  1138. I915_WRITE(DEIER, de_ier);
  1139. POSTING_READ(DEIER);
  1140. I915_WRITE(SDEIER, sde_ier);
  1141. POSTING_READ(SDEIER);
  1142. return ret;
  1143. }
  1144. /**
  1145. * i915_error_work_func - do process context error handling work
  1146. * @work: work struct
  1147. *
  1148. * Fire an error uevent so userspace can see that a hang or error
  1149. * was detected.
  1150. */
  1151. static void i915_error_work_func(struct work_struct *work)
  1152. {
  1153. struct i915_gpu_error *error = container_of(work, struct i915_gpu_error,
  1154. work);
  1155. drm_i915_private_t *dev_priv = container_of(error, drm_i915_private_t,
  1156. gpu_error);
  1157. struct drm_device *dev = dev_priv->dev;
  1158. struct intel_ring_buffer *ring;
  1159. char *error_event[] = { "ERROR=1", NULL };
  1160. char *reset_event[] = { "RESET=1", NULL };
  1161. char *reset_done_event[] = { "ERROR=0", NULL };
  1162. int i, ret;
  1163. kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
  1164. /*
  1165. * Note that there's only one work item which does gpu resets, so we
  1166. * need not worry about concurrent gpu resets potentially incrementing
  1167. * error->reset_counter twice. We only need to take care of another
  1168. * racing irq/hangcheck declaring the gpu dead for a second time. A
  1169. * quick check for that is good enough: schedule_work ensures the
  1170. * correct ordering between hang detection and this work item, and since
  1171. * the reset in-progress bit is only ever set by code outside of this
  1172. * work we don't need to worry about any other races.
  1173. */
  1174. if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
  1175. DRM_DEBUG_DRIVER("resetting chip\n");
  1176. kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE,
  1177. reset_event);
  1178. ret = i915_reset(dev);
  1179. if (ret == 0) {
  1180. /*
  1181. * After all the gem state is reset, increment the reset
  1182. * counter and wake up everyone waiting for the reset to
  1183. * complete.
  1184. *
  1185. * Since unlock operations are a one-sided barrier only,
  1186. * we need to insert a barrier here to order any seqno
  1187. * updates before
  1188. * the counter increment.
  1189. */
  1190. smp_mb__before_atomic_inc();
  1191. atomic_inc(&dev_priv->gpu_error.reset_counter);
  1192. kobject_uevent_env(&dev->primary->kdev.kobj,
  1193. KOBJ_CHANGE, reset_done_event);
  1194. } else {
  1195. atomic_set(&error->reset_counter, I915_WEDGED);
  1196. }
  1197. for_each_ring(ring, dev_priv, i)
  1198. wake_up_all(&ring->irq_queue);
  1199. intel_display_handle_reset(dev);
  1200. wake_up_all(&dev_priv->gpu_error.reset_queue);
  1201. }
  1202. }
  1203. /* NB: please notice the memset */
  1204. static void i915_get_extra_instdone(struct drm_device *dev,
  1205. uint32_t *instdone)
  1206. {
  1207. struct drm_i915_private *dev_priv = dev->dev_private;
  1208. memset(instdone, 0, sizeof(*instdone) * I915_NUM_INSTDONE_REG);
  1209. switch(INTEL_INFO(dev)->gen) {
  1210. case 2:
  1211. case 3:
  1212. instdone[0] = I915_READ(INSTDONE);
  1213. break;
  1214. case 4:
  1215. case 5:
  1216. case 6:
  1217. instdone[0] = I915_READ(INSTDONE_I965);
  1218. instdone[1] = I915_READ(INSTDONE1);
  1219. break;
  1220. default:
  1221. WARN_ONCE(1, "Unsupported platform\n");
  1222. case 7:
  1223. instdone[0] = I915_READ(GEN7_INSTDONE_1);
  1224. instdone[1] = I915_READ(GEN7_SC_INSTDONE);
  1225. instdone[2] = I915_READ(GEN7_SAMPLER_INSTDONE);
  1226. instdone[3] = I915_READ(GEN7_ROW_INSTDONE);
  1227. break;
  1228. }
  1229. }
  1230. #ifdef CONFIG_DEBUG_FS
  1231. static struct drm_i915_error_object *
  1232. i915_error_object_create_sized(struct drm_i915_private *dev_priv,
  1233. struct drm_i915_gem_object *src,
  1234. const int num_pages)
  1235. {
  1236. struct drm_i915_error_object *dst;
  1237. int i;
  1238. u32 reloc_offset;
  1239. if (src == NULL || src->pages == NULL)
  1240. return NULL;
  1241. dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *), GFP_ATOMIC);
  1242. if (dst == NULL)
  1243. return NULL;
  1244. reloc_offset = src->gtt_offset;
  1245. for (i = 0; i < num_pages; i++) {
  1246. unsigned long flags;
  1247. void *d;
  1248. d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
  1249. if (d == NULL)
  1250. goto unwind;
  1251. local_irq_save(flags);
  1252. if (reloc_offset < dev_priv->gtt.mappable_end &&
  1253. src->has_global_gtt_mapping) {
  1254. void __iomem *s;
  1255. /* Simply ignore tiling or any overlapping fence.
  1256. * It's part of the error state, and this hopefully
  1257. * captures what the GPU read.
  1258. */
  1259. s = io_mapping_map_atomic_wc(dev_priv->gtt.mappable,
  1260. reloc_offset);
  1261. memcpy_fromio(d, s, PAGE_SIZE);
  1262. io_mapping_unmap_atomic(s);
  1263. } else if (src->stolen) {
  1264. unsigned long offset;
  1265. offset = dev_priv->mm.stolen_base;
  1266. offset += src->stolen->start;
  1267. offset += i << PAGE_SHIFT;
  1268. memcpy_fromio(d, (void __iomem *) offset, PAGE_SIZE);
  1269. } else {
  1270. struct page *page;
  1271. void *s;
  1272. page = i915_gem_object_get_page(src, i);
  1273. drm_clflush_pages(&page, 1);
  1274. s = kmap_atomic(page);
  1275. memcpy(d, s, PAGE_SIZE);
  1276. kunmap_atomic(s);
  1277. drm_clflush_pages(&page, 1);
  1278. }
  1279. local_irq_restore(flags);
  1280. dst->pages[i] = d;
  1281. reloc_offset += PAGE_SIZE;
  1282. }
  1283. dst->page_count = num_pages;
  1284. dst->gtt_offset = src->gtt_offset;
  1285. return dst;
  1286. unwind:
  1287. while (i--)
  1288. kfree(dst->pages[i]);
  1289. kfree(dst);
  1290. return NULL;
  1291. }
  1292. #define i915_error_object_create(dev_priv, src) \
  1293. i915_error_object_create_sized((dev_priv), (src), \
  1294. (src)->base.size>>PAGE_SHIFT)
  1295. static void
  1296. i915_error_object_free(struct drm_i915_error_object *obj)
  1297. {
  1298. int page;
  1299. if (obj == NULL)
  1300. return;
  1301. for (page = 0; page < obj->page_count; page++)
  1302. kfree(obj->pages[page]);
  1303. kfree(obj);
  1304. }
  1305. void
  1306. i915_error_state_free(struct kref *error_ref)
  1307. {
  1308. struct drm_i915_error_state *error = container_of(error_ref,
  1309. typeof(*error), ref);
  1310. int i;
  1311. for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
  1312. i915_error_object_free(error->ring[i].batchbuffer);
  1313. i915_error_object_free(error->ring[i].ringbuffer);
  1314. i915_error_object_free(error->ring[i].ctx);
  1315. kfree(error->ring[i].requests);
  1316. }
  1317. kfree(error->active_bo);
  1318. kfree(error->overlay);
  1319. kfree(error->display);
  1320. kfree(error);
  1321. }
  1322. static void capture_bo(struct drm_i915_error_buffer *err,
  1323. struct drm_i915_gem_object *obj)
  1324. {
  1325. err->size = obj->base.size;
  1326. err->name = obj->base.name;
  1327. err->rseqno = obj->last_read_seqno;
  1328. err->wseqno = obj->last_write_seqno;
  1329. err->gtt_offset = obj->gtt_offset;
  1330. err->read_domains = obj->base.read_domains;
  1331. err->write_domain = obj->base.write_domain;
  1332. err->fence_reg = obj->fence_reg;
  1333. err->pinned = 0;
  1334. if (obj->pin_count > 0)
  1335. err->pinned = 1;
  1336. if (obj->user_pin_count > 0)
  1337. err->pinned = -1;
  1338. err->tiling = obj->tiling_mode;
  1339. err->dirty = obj->dirty;
  1340. err->purgeable = obj->madv != I915_MADV_WILLNEED;
  1341. err->ring = obj->ring ? obj->ring->id : -1;
  1342. err->cache_level = obj->cache_level;
  1343. }
  1344. static u32 capture_active_bo(struct drm_i915_error_buffer *err,
  1345. int count, struct list_head *head)
  1346. {
  1347. struct drm_i915_gem_object *obj;
  1348. int i = 0;
  1349. list_for_each_entry(obj, head, mm_list) {
  1350. capture_bo(err++, obj);
  1351. if (++i == count)
  1352. break;
  1353. }
  1354. return i;
  1355. }
  1356. static u32 capture_pinned_bo(struct drm_i915_error_buffer *err,
  1357. int count, struct list_head *head)
  1358. {
  1359. struct drm_i915_gem_object *obj;
  1360. int i = 0;
  1361. list_for_each_entry(obj, head, global_list) {
  1362. if (obj->pin_count == 0)
  1363. continue;
  1364. capture_bo(err++, obj);
  1365. if (++i == count)
  1366. break;
  1367. }
  1368. return i;
  1369. }
  1370. static void i915_gem_record_fences(struct drm_device *dev,
  1371. struct drm_i915_error_state *error)
  1372. {
  1373. struct drm_i915_private *dev_priv = dev->dev_private;
  1374. int i;
  1375. /* Fences */
  1376. switch (INTEL_INFO(dev)->gen) {
  1377. case 7:
  1378. case 6:
  1379. for (i = 0; i < dev_priv->num_fence_regs; i++)
  1380. error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
  1381. break;
  1382. case 5:
  1383. case 4:
  1384. for (i = 0; i < 16; i++)
  1385. error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
  1386. break;
  1387. case 3:
  1388. if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
  1389. for (i = 0; i < 8; i++)
  1390. error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
  1391. case 2:
  1392. for (i = 0; i < 8; i++)
  1393. error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
  1394. break;
  1395. default:
  1396. BUG();
  1397. }
  1398. }
  1399. static struct drm_i915_error_object *
  1400. i915_error_first_batchbuffer(struct drm_i915_private *dev_priv,
  1401. struct intel_ring_buffer *ring)
  1402. {
  1403. struct drm_i915_gem_object *obj;
  1404. u32 seqno;
  1405. if (!ring->get_seqno)
  1406. return NULL;
  1407. if (HAS_BROKEN_CS_TLB(dev_priv->dev)) {
  1408. u32 acthd = I915_READ(ACTHD);
  1409. if (WARN_ON(ring->id != RCS))
  1410. return NULL;
  1411. obj = ring->private;
  1412. if (acthd >= obj->gtt_offset &&
  1413. acthd < obj->gtt_offset + obj->base.size)
  1414. return i915_error_object_create(dev_priv, obj);
  1415. }
  1416. seqno = ring->get_seqno(ring, false);
  1417. list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) {
  1418. if (obj->ring != ring)
  1419. continue;
  1420. if (i915_seqno_passed(seqno, obj->last_read_seqno))
  1421. continue;
  1422. if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0)
  1423. continue;
  1424. /* We need to copy these to an anonymous buffer as the simplest
  1425. * method to avoid being overwritten by userspace.
  1426. */
  1427. return i915_error_object_create(dev_priv, obj);
  1428. }
  1429. return NULL;
  1430. }
  1431. static void i915_record_ring_state(struct drm_device *dev,
  1432. struct drm_i915_error_state *error,
  1433. struct intel_ring_buffer *ring)
  1434. {
  1435. struct drm_i915_private *dev_priv = dev->dev_private;
  1436. if (INTEL_INFO(dev)->gen >= 6) {
  1437. error->rc_psmi[ring->id] = I915_READ(ring->mmio_base + 0x50);
  1438. error->fault_reg[ring->id] = I915_READ(RING_FAULT_REG(ring));
  1439. error->semaphore_mboxes[ring->id][0]
  1440. = I915_READ(RING_SYNC_0(ring->mmio_base));
  1441. error->semaphore_mboxes[ring->id][1]
  1442. = I915_READ(RING_SYNC_1(ring->mmio_base));
  1443. error->semaphore_seqno[ring->id][0] = ring->sync_seqno[0];
  1444. error->semaphore_seqno[ring->id][1] = ring->sync_seqno[1];
  1445. }
  1446. if (INTEL_INFO(dev)->gen >= 4) {
  1447. error->faddr[ring->id] = I915_READ(RING_DMA_FADD(ring->mmio_base));
  1448. error->ipeir[ring->id] = I915_READ(RING_IPEIR(ring->mmio_base));
  1449. error->ipehr[ring->id] = I915_READ(RING_IPEHR(ring->mmio_base));
  1450. error->instdone[ring->id] = I915_READ(RING_INSTDONE(ring->mmio_base));
  1451. error->instps[ring->id] = I915_READ(RING_INSTPS(ring->mmio_base));
  1452. if (ring->id == RCS)
  1453. error->bbaddr = I915_READ64(BB_ADDR);
  1454. } else {
  1455. error->faddr[ring->id] = I915_READ(DMA_FADD_I8XX);
  1456. error->ipeir[ring->id] = I915_READ(IPEIR);
  1457. error->ipehr[ring->id] = I915_READ(IPEHR);
  1458. error->instdone[ring->id] = I915_READ(INSTDONE);
  1459. }
  1460. error->waiting[ring->id] = waitqueue_active(&ring->irq_queue);
  1461. error->instpm[ring->id] = I915_READ(RING_INSTPM(ring->mmio_base));
  1462. error->seqno[ring->id] = ring->get_seqno(ring, false);
  1463. error->acthd[ring->id] = intel_ring_get_active_head(ring);
  1464. error->head[ring->id] = I915_READ_HEAD(ring);
  1465. error->tail[ring->id] = I915_READ_TAIL(ring);
  1466. error->ctl[ring->id] = I915_READ_CTL(ring);
  1467. error->cpu_ring_head[ring->id] = ring->head;
  1468. error->cpu_ring_tail[ring->id] = ring->tail;
  1469. }
  1470. static void i915_gem_record_active_context(struct intel_ring_buffer *ring,
  1471. struct drm_i915_error_state *error,
  1472. struct drm_i915_error_ring *ering)
  1473. {
  1474. struct drm_i915_private *dev_priv = ring->dev->dev_private;
  1475. struct drm_i915_gem_object *obj;
  1476. /* Currently render ring is the only HW context user */
  1477. if (ring->id != RCS || !error->ccid)
  1478. return;
  1479. list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
  1480. if ((error->ccid & PAGE_MASK) == obj->gtt_offset) {
  1481. ering->ctx = i915_error_object_create_sized(dev_priv,
  1482. obj, 1);
  1483. }
  1484. }
  1485. }
  1486. static void i915_gem_record_rings(struct drm_device *dev,
  1487. struct drm_i915_error_state *error)
  1488. {
  1489. struct drm_i915_private *dev_priv = dev->dev_private;
  1490. struct intel_ring_buffer *ring;
  1491. struct drm_i915_gem_request *request;
  1492. int i, count;
  1493. for_each_ring(ring, dev_priv, i) {
  1494. i915_record_ring_state(dev, error, ring);
  1495. error->ring[i].batchbuffer =
  1496. i915_error_first_batchbuffer(dev_priv, ring);
  1497. error->ring[i].ringbuffer =
  1498. i915_error_object_create(dev_priv, ring->obj);
  1499. i915_gem_record_active_context(ring, error, &error->ring[i]);
  1500. count = 0;
  1501. list_for_each_entry(request, &ring->request_list, list)
  1502. count++;
  1503. error->ring[i].num_requests = count;
  1504. error->ring[i].requests =
  1505. kmalloc(count*sizeof(struct drm_i915_error_request),
  1506. GFP_ATOMIC);
  1507. if (error->ring[i].requests == NULL) {
  1508. error->ring[i].num_requests = 0;
  1509. continue;
  1510. }
  1511. count = 0;
  1512. list_for_each_entry(request, &ring->request_list, list) {
  1513. struct drm_i915_error_request *erq;
  1514. erq = &error->ring[i].requests[count++];
  1515. erq->seqno = request->seqno;
  1516. erq->jiffies = request->emitted_jiffies;
  1517. erq->tail = request->tail;
  1518. }
  1519. }
  1520. }
  1521. /**
  1522. * i915_capture_error_state - capture an error record for later analysis
  1523. * @dev: drm device
  1524. *
  1525. * Should be called when an error is detected (either a hang or an error
  1526. * interrupt) to capture error state from the time of the error. Fills
  1527. * out a structure which becomes available in debugfs for user level tools
  1528. * to pick up.
  1529. */
  1530. static void i915_capture_error_state(struct drm_device *dev)
  1531. {
  1532. struct drm_i915_private *dev_priv = dev->dev_private;
  1533. struct drm_i915_gem_object *obj;
  1534. struct drm_i915_error_state *error;
  1535. unsigned long flags;
  1536. int i, pipe;
  1537. spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
  1538. error = dev_priv->gpu_error.first_error;
  1539. spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
  1540. if (error)
  1541. return;
  1542. /* Account for pipe specific data like PIPE*STAT */
  1543. error = kzalloc(sizeof(*error), GFP_ATOMIC);
  1544. if (!error) {
  1545. DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
  1546. return;
  1547. }
  1548. DRM_INFO("capturing error event; look for more information in "
  1549. "/sys/kernel/debug/dri/%d/i915_error_state\n",
  1550. dev->primary->index);
  1551. kref_init(&error->ref);
  1552. error->eir = I915_READ(EIR);
  1553. error->pgtbl_er = I915_READ(PGTBL_ER);
  1554. if (HAS_HW_CONTEXTS(dev))
  1555. error->ccid = I915_READ(CCID);
  1556. if (HAS_PCH_SPLIT(dev))
  1557. error->ier = I915_READ(DEIER) | I915_READ(GTIER);
  1558. else if (IS_VALLEYVIEW(dev))
  1559. error->ier = I915_READ(GTIER) | I915_READ(VLV_IER);
  1560. else if (IS_GEN2(dev))
  1561. error->ier = I915_READ16(IER);
  1562. else
  1563. error->ier = I915_READ(IER);
  1564. if (INTEL_INFO(dev)->gen >= 6)
  1565. error->derrmr = I915_READ(DERRMR);
  1566. if (IS_VALLEYVIEW(dev))
  1567. error->forcewake = I915_READ(FORCEWAKE_VLV);
  1568. else if (INTEL_INFO(dev)->gen >= 7)
  1569. error->forcewake = I915_READ(FORCEWAKE_MT);
  1570. else if (INTEL_INFO(dev)->gen == 6)
  1571. error->forcewake = I915_READ(FORCEWAKE);
  1572. if (!HAS_PCH_SPLIT(dev))
  1573. for_each_pipe(pipe)
  1574. error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
  1575. if (INTEL_INFO(dev)->gen >= 6) {
  1576. error->error = I915_READ(ERROR_GEN6);
  1577. error->done_reg = I915_READ(DONE_REG);
  1578. }
  1579. if (INTEL_INFO(dev)->gen == 7)
  1580. error->err_int = I915_READ(GEN7_ERR_INT);
  1581. i915_get_extra_instdone(dev, error->extra_instdone);
  1582. i915_gem_record_fences(dev, error);
  1583. i915_gem_record_rings(dev, error);
  1584. /* Record buffers on the active and pinned lists. */
  1585. error->active_bo = NULL;
  1586. error->pinned_bo = NULL;
  1587. i = 0;
  1588. list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list)
  1589. i++;
  1590. error->active_bo_count = i;
  1591. list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
  1592. if (obj->pin_count)
  1593. i++;
  1594. error->pinned_bo_count = i - error->active_bo_count;
  1595. error->active_bo = NULL;
  1596. error->pinned_bo = NULL;
  1597. if (i) {
  1598. error->active_bo = kmalloc(sizeof(*error->active_bo)*i,
  1599. GFP_ATOMIC);
  1600. if (error->active_bo)
  1601. error->pinned_bo =
  1602. error->active_bo + error->active_bo_count;
  1603. }
  1604. if (error->active_bo)
  1605. error->active_bo_count =
  1606. capture_active_bo(error->active_bo,
  1607. error->active_bo_count,
  1608. &dev_priv->mm.active_list);
  1609. if (error->pinned_bo)
  1610. error->pinned_bo_count =
  1611. capture_pinned_bo(error->pinned_bo,
  1612. error->pinned_bo_count,
  1613. &dev_priv->mm.bound_list);
  1614. do_gettimeofday(&error->time);
  1615. error->overlay = intel_overlay_capture_error_state(dev);
  1616. error->display = intel_display_capture_error_state(dev);
  1617. spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
  1618. if (dev_priv->gpu_error.first_error == NULL) {
  1619. dev_priv->gpu_error.first_error = error;
  1620. error = NULL;
  1621. }
  1622. spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
  1623. if (error)
  1624. i915_error_state_free(&error->ref);
  1625. }
  1626. void i915_destroy_error_state(struct drm_device *dev)
  1627. {
  1628. struct drm_i915_private *dev_priv = dev->dev_private;
  1629. struct drm_i915_error_state *error;
  1630. unsigned long flags;
  1631. spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
  1632. error = dev_priv->gpu_error.first_error;
  1633. dev_priv->gpu_error.first_error = NULL;
  1634. spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
  1635. if (error)
  1636. kref_put(&error->ref, i915_error_state_free);
  1637. }
  1638. #else
  1639. #define i915_capture_error_state(x)
  1640. #endif
  1641. static void i915_report_and_clear_eir(struct drm_device *dev)
  1642. {
  1643. struct drm_i915_private *dev_priv = dev->dev_private;
  1644. uint32_t instdone[I915_NUM_INSTDONE_REG];
  1645. u32 eir = I915_READ(EIR);
  1646. int pipe, i;
  1647. if (!eir)
  1648. return;
  1649. pr_err("render error detected, EIR: 0x%08x\n", eir);
  1650. i915_get_extra_instdone(dev, instdone);
  1651. if (IS_G4X(dev)) {
  1652. if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
  1653. u32 ipeir = I915_READ(IPEIR_I965);
  1654. pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
  1655. pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
  1656. for (i = 0; i < ARRAY_SIZE(instdone); i++)
  1657. pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
  1658. pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
  1659. pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
  1660. I915_WRITE(IPEIR_I965, ipeir);
  1661. POSTING_READ(IPEIR_I965);
  1662. }
  1663. if (eir & GM45_ERROR_PAGE_TABLE) {
  1664. u32 pgtbl_err = I915_READ(PGTBL_ER);
  1665. pr_err("page table error\n");
  1666. pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
  1667. I915_WRITE(PGTBL_ER, pgtbl_err);
  1668. POSTING_READ(PGTBL_ER);
  1669. }
  1670. }
  1671. if (!IS_GEN2(dev)) {
  1672. if (eir & I915_ERROR_PAGE_TABLE) {
  1673. u32 pgtbl_err = I915_READ(PGTBL_ER);
  1674. pr_err("page table error\n");
  1675. pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
  1676. I915_WRITE(PGTBL_ER, pgtbl_err);
  1677. POSTING_READ(PGTBL_ER);
  1678. }
  1679. }
  1680. if (eir & I915_ERROR_MEMORY_REFRESH) {
  1681. pr_err("memory refresh error:\n");
  1682. for_each_pipe(pipe)
  1683. pr_err("pipe %c stat: 0x%08x\n",
  1684. pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
  1685. /* pipestat has already been acked */
  1686. }
  1687. if (eir & I915_ERROR_INSTRUCTION) {
  1688. pr_err("instruction error\n");
  1689. pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM));
  1690. for (i = 0; i < ARRAY_SIZE(instdone); i++)
  1691. pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
  1692. if (INTEL_INFO(dev)->gen < 4) {
  1693. u32 ipeir = I915_READ(IPEIR);
  1694. pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR));
  1695. pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR));
  1696. pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD));
  1697. I915_WRITE(IPEIR, ipeir);
  1698. POSTING_READ(IPEIR);
  1699. } else {
  1700. u32 ipeir = I915_READ(IPEIR_I965);
  1701. pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
  1702. pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
  1703. pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
  1704. pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
  1705. I915_WRITE(IPEIR_I965, ipeir);
  1706. POSTING_READ(IPEIR_I965);
  1707. }
  1708. }
  1709. I915_WRITE(EIR, eir);
  1710. POSTING_READ(EIR);
  1711. eir = I915_READ(EIR);
  1712. if (eir) {
  1713. /*
  1714. * some errors might have become stuck,
  1715. * mask them.
  1716. */
  1717. DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
  1718. I915_WRITE(EMR, I915_READ(EMR) | eir);
  1719. I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
  1720. }
  1721. }
  1722. /**
  1723. * i915_handle_error - handle an error interrupt
  1724. * @dev: drm device
  1725. *
  1726. * Do some basic checking of regsiter state at error interrupt time and
  1727. * dump it to the syslog. Also call i915_capture_error_state() to make
  1728. * sure we get a record and make it available in debugfs. Fire a uevent
  1729. * so userspace knows something bad happened (should trigger collection
  1730. * of a ring dump etc.).
  1731. */
  1732. void i915_handle_error(struct drm_device *dev, bool wedged)
  1733. {
  1734. struct drm_i915_private *dev_priv = dev->dev_private;
  1735. struct intel_ring_buffer *ring;
  1736. int i;
  1737. i915_capture_error_state(dev);
  1738. i915_report_and_clear_eir(dev);
  1739. if (wedged) {
  1740. atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG,
  1741. &dev_priv->gpu_error.reset_counter);
  1742. /*
  1743. * Wakeup waiting processes so that the reset work item
  1744. * doesn't deadlock trying to grab various locks.
  1745. */
  1746. for_each_ring(ring, dev_priv, i)
  1747. wake_up_all(&ring->irq_queue);
  1748. }
  1749. queue_work(dev_priv->wq, &dev_priv->gpu_error.work);
  1750. }
  1751. static void __always_unused i915_pageflip_stall_check(struct drm_device *dev, int pipe)
  1752. {
  1753. drm_i915_private_t *dev_priv = dev->dev_private;
  1754. struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
  1755. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1756. struct drm_i915_gem_object *obj;
  1757. struct intel_unpin_work *work;
  1758. unsigned long flags;
  1759. bool stall_detected;
  1760. /* Ignore early vblank irqs */
  1761. if (intel_crtc == NULL)
  1762. return;
  1763. spin_lock_irqsave(&dev->event_lock, flags);
  1764. work = intel_crtc->unpin_work;
  1765. if (work == NULL ||
  1766. atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE ||
  1767. !work->enable_stall_check) {
  1768. /* Either the pending flip IRQ arrived, or we're too early. Don't check */
  1769. spin_unlock_irqrestore(&dev->event_lock, flags);
  1770. return;
  1771. }
  1772. /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
  1773. obj = work->pending_flip_obj;
  1774. if (INTEL_INFO(dev)->gen >= 4) {
  1775. int dspsurf = DSPSURF(intel_crtc->plane);
  1776. stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
  1777. obj->gtt_offset;
  1778. } else {
  1779. int dspaddr = DSPADDR(intel_crtc->plane);
  1780. stall_detected = I915_READ(dspaddr) == (obj->gtt_offset +
  1781. crtc->y * crtc->fb->pitches[0] +
  1782. crtc->x * crtc->fb->bits_per_pixel/8);
  1783. }
  1784. spin_unlock_irqrestore(&dev->event_lock, flags);
  1785. if (stall_detected) {
  1786. DRM_DEBUG_DRIVER("Pageflip stall detected\n");
  1787. intel_prepare_page_flip(dev, intel_crtc->plane);
  1788. }
  1789. }
  1790. /* Called from drm generic code, passed 'crtc' which
  1791. * we use as a pipe index
  1792. */
  1793. static int i915_enable_vblank(struct drm_device *dev, int pipe)
  1794. {
  1795. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1796. unsigned long irqflags;
  1797. if (!i915_pipe_enabled(dev, pipe))
  1798. return -EINVAL;
  1799. spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  1800. if (INTEL_INFO(dev)->gen >= 4)
  1801. i915_enable_pipestat(dev_priv, pipe,
  1802. PIPE_START_VBLANK_INTERRUPT_ENABLE);
  1803. else
  1804. i915_enable_pipestat(dev_priv, pipe,
  1805. PIPE_VBLANK_INTERRUPT_ENABLE);
  1806. /* maintain vblank delivery even in deep C-states */
  1807. if (dev_priv->info->gen == 3)
  1808. I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
  1809. spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  1810. return 0;
  1811. }
  1812. static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
  1813. {
  1814. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1815. unsigned long irqflags;
  1816. if (!i915_pipe_enabled(dev, pipe))
  1817. return -EINVAL;
  1818. spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  1819. ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
  1820. DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
  1821. spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  1822. return 0;
  1823. }
  1824. static int ivybridge_enable_vblank(struct drm_device *dev, int pipe)
  1825. {
  1826. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1827. unsigned long irqflags;
  1828. if (!i915_pipe_enabled(dev, pipe))
  1829. return -EINVAL;
  1830. spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  1831. ironlake_enable_display_irq(dev_priv,
  1832. DE_PIPEA_VBLANK_IVB << (5 * pipe));
  1833. spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  1834. return 0;
  1835. }
  1836. static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
  1837. {
  1838. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1839. unsigned long irqflags;
  1840. u32 imr;
  1841. if (!i915_pipe_enabled(dev, pipe))
  1842. return -EINVAL;
  1843. spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  1844. imr = I915_READ(VLV_IMR);
  1845. if (pipe == 0)
  1846. imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
  1847. else
  1848. imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
  1849. I915_WRITE(VLV_IMR, imr);
  1850. i915_enable_pipestat(dev_priv, pipe,
  1851. PIPE_START_VBLANK_INTERRUPT_ENABLE);
  1852. spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  1853. return 0;
  1854. }
  1855. /* Called from drm generic code, passed 'crtc' which
  1856. * we use as a pipe index
  1857. */
  1858. static void i915_disable_vblank(struct drm_device *dev, int pipe)
  1859. {
  1860. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1861. unsigned long irqflags;
  1862. spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  1863. if (dev_priv->info->gen == 3)
  1864. I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
  1865. i915_disable_pipestat(dev_priv, pipe,
  1866. PIPE_VBLANK_INTERRUPT_ENABLE |
  1867. PIPE_START_VBLANK_INTERRUPT_ENABLE);
  1868. spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  1869. }
  1870. static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
  1871. {
  1872. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1873. unsigned long irqflags;
  1874. spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  1875. ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
  1876. DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
  1877. spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  1878. }
  1879. static void ivybridge_disable_vblank(struct drm_device *dev, int pipe)
  1880. {
  1881. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1882. unsigned long irqflags;
  1883. spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  1884. ironlake_disable_display_irq(dev_priv,
  1885. DE_PIPEA_VBLANK_IVB << (pipe * 5));
  1886. spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  1887. }
  1888. static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
  1889. {
  1890. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1891. unsigned long irqflags;
  1892. u32 imr;
  1893. spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  1894. i915_disable_pipestat(dev_priv, pipe,
  1895. PIPE_START_VBLANK_INTERRUPT_ENABLE);
  1896. imr = I915_READ(VLV_IMR);
  1897. if (pipe == 0)
  1898. imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
  1899. else
  1900. imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
  1901. I915_WRITE(VLV_IMR, imr);
  1902. spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  1903. }
  1904. static u32
  1905. ring_last_seqno(struct intel_ring_buffer *ring)
  1906. {
  1907. return list_entry(ring->request_list.prev,
  1908. struct drm_i915_gem_request, list)->seqno;
  1909. }
  1910. static bool
  1911. ring_idle(struct intel_ring_buffer *ring, u32 seqno)
  1912. {
  1913. return (list_empty(&ring->request_list) ||
  1914. i915_seqno_passed(seqno, ring_last_seqno(ring)));
  1915. }
  1916. static struct intel_ring_buffer *
  1917. semaphore_waits_for(struct intel_ring_buffer *ring, u32 *seqno)
  1918. {
  1919. struct drm_i915_private *dev_priv = ring->dev->dev_private;
  1920. u32 cmd, ipehr, acthd, acthd_min;
  1921. ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
  1922. if ((ipehr & ~(0x3 << 16)) !=
  1923. (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE | MI_SEMAPHORE_REGISTER))
  1924. return NULL;
  1925. /* ACTHD is likely pointing to the dword after the actual command,
  1926. * so scan backwards until we find the MBOX.
  1927. */
  1928. acthd = intel_ring_get_active_head(ring) & HEAD_ADDR;
  1929. acthd_min = max((int)acthd - 3 * 4, 0);
  1930. do {
  1931. cmd = ioread32(ring->virtual_start + acthd);
  1932. if (cmd == ipehr)
  1933. break;
  1934. acthd -= 4;
  1935. if (acthd < acthd_min)
  1936. return NULL;
  1937. } while (1);
  1938. *seqno = ioread32(ring->virtual_start+acthd+4)+1;
  1939. return &dev_priv->ring[(ring->id + (((ipehr >> 17) & 1) + 1)) % 3];
  1940. }
  1941. static int semaphore_passed(struct intel_ring_buffer *ring)
  1942. {
  1943. struct drm_i915_private *dev_priv = ring->dev->dev_private;
  1944. struct intel_ring_buffer *signaller;
  1945. u32 seqno, ctl;
  1946. ring->hangcheck.deadlock = true;
  1947. signaller = semaphore_waits_for(ring, &seqno);
  1948. if (signaller == NULL || signaller->hangcheck.deadlock)
  1949. return -1;
  1950. /* cursory check for an unkickable deadlock */
  1951. ctl = I915_READ_CTL(signaller);
  1952. if (ctl & RING_WAIT_SEMAPHORE && semaphore_passed(signaller) < 0)
  1953. return -1;
  1954. return i915_seqno_passed(signaller->get_seqno(signaller, false), seqno);
  1955. }
  1956. static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv)
  1957. {
  1958. struct intel_ring_buffer *ring;
  1959. int i;
  1960. for_each_ring(ring, dev_priv, i)
  1961. ring->hangcheck.deadlock = false;
  1962. }
  1963. static enum intel_ring_hangcheck_action
  1964. ring_stuck(struct intel_ring_buffer *ring, u32 acthd)
  1965. {
  1966. struct drm_device *dev = ring->dev;
  1967. struct drm_i915_private *dev_priv = dev->dev_private;
  1968. u32 tmp;
  1969. if (ring->hangcheck.acthd != acthd)
  1970. return active;
  1971. if (IS_GEN2(dev))
  1972. return hung;
  1973. /* Is the chip hanging on a WAIT_FOR_EVENT?
  1974. * If so we can simply poke the RB_WAIT bit
  1975. * and break the hang. This should work on
  1976. * all but the second generation chipsets.
  1977. */
  1978. tmp = I915_READ_CTL(ring);
  1979. if (tmp & RING_WAIT) {
  1980. DRM_ERROR("Kicking stuck wait on %s\n",
  1981. ring->name);
  1982. I915_WRITE_CTL(ring, tmp);
  1983. return kick;
  1984. }
  1985. if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) {
  1986. switch (semaphore_passed(ring)) {
  1987. default:
  1988. return hung;
  1989. case 1:
  1990. DRM_ERROR("Kicking stuck semaphore on %s\n",
  1991. ring->name);
  1992. I915_WRITE_CTL(ring, tmp);
  1993. return kick;
  1994. case 0:
  1995. return wait;
  1996. }
  1997. }
  1998. return hung;
  1999. }
  2000. /**
  2001. * This is called when the chip hasn't reported back with completed
  2002. * batchbuffers in a long time. We keep track per ring seqno progress and
  2003. * if there are no progress, hangcheck score for that ring is increased.
  2004. * Further, acthd is inspected to see if the ring is stuck. On stuck case
  2005. * we kick the ring. If we see no progress on three subsequent calls
  2006. * we assume chip is wedged and try to fix it by resetting the chip.
  2007. */
  2008. void i915_hangcheck_elapsed(unsigned long data)
  2009. {
  2010. struct drm_device *dev = (struct drm_device *)data;
  2011. drm_i915_private_t *dev_priv = dev->dev_private;
  2012. struct intel_ring_buffer *ring;
  2013. int i;
  2014. int busy_count = 0, rings_hung = 0;
  2015. bool stuck[I915_NUM_RINGS] = { 0 };
  2016. #define BUSY 1
  2017. #define KICK 5
  2018. #define HUNG 20
  2019. #define FIRE 30
  2020. if (!i915_enable_hangcheck)
  2021. return;
  2022. for_each_ring(ring, dev_priv, i) {
  2023. u32 seqno, acthd;
  2024. bool busy = true;
  2025. semaphore_clear_deadlocks(dev_priv);
  2026. seqno = ring->get_seqno(ring, false);
  2027. acthd = intel_ring_get_active_head(ring);
  2028. if (ring->hangcheck.seqno == seqno) {
  2029. if (ring_idle(ring, seqno)) {
  2030. if (waitqueue_active(&ring->irq_queue)) {
  2031. /* Issue a wake-up to catch stuck h/w. */
  2032. DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
  2033. ring->name);
  2034. wake_up_all(&ring->irq_queue);
  2035. ring->hangcheck.score += HUNG;
  2036. } else
  2037. busy = false;
  2038. } else {
  2039. int score;
  2040. /* We always increment the hangcheck score
  2041. * if the ring is busy and still processing
  2042. * the same request, so that no single request
  2043. * can run indefinitely (such as a chain of
  2044. * batches). The only time we do not increment
  2045. * the hangcheck score on this ring, if this
  2046. * ring is in a legitimate wait for another
  2047. * ring. In that case the waiting ring is a
  2048. * victim and we want to be sure we catch the
  2049. * right culprit. Then every time we do kick
  2050. * the ring, add a small increment to the
  2051. * score so that we can catch a batch that is
  2052. * being repeatedly kicked and so responsible
  2053. * for stalling the machine.
  2054. */
  2055. ring->hangcheck.action = ring_stuck(ring,
  2056. acthd);
  2057. switch (ring->hangcheck.action) {
  2058. case wait:
  2059. score = 0;
  2060. break;
  2061. case active:
  2062. score = BUSY;
  2063. break;
  2064. case kick:
  2065. score = KICK;
  2066. break;
  2067. case hung:
  2068. score = HUNG;
  2069. stuck[i] = true;
  2070. break;
  2071. }
  2072. ring->hangcheck.score += score;
  2073. }
  2074. } else {
  2075. /* Gradually reduce the count so that we catch DoS
  2076. * attempts across multiple batches.
  2077. */
  2078. if (ring->hangcheck.score > 0)
  2079. ring->hangcheck.score--;
  2080. }
  2081. ring->hangcheck.seqno = seqno;
  2082. ring->hangcheck.acthd = acthd;
  2083. busy_count += busy;
  2084. }
  2085. for_each_ring(ring, dev_priv, i) {
  2086. if (ring->hangcheck.score > FIRE) {
  2087. DRM_ERROR("%s on %s\n",
  2088. stuck[i] ? "stuck" : "no progress",
  2089. ring->name);
  2090. rings_hung++;
  2091. }
  2092. }
  2093. if (rings_hung)
  2094. return i915_handle_error(dev, true);
  2095. if (busy_count)
  2096. /* Reset timer case chip hangs without another request
  2097. * being added */
  2098. mod_timer(&dev_priv->gpu_error.hangcheck_timer,
  2099. round_jiffies_up(jiffies +
  2100. DRM_I915_HANGCHECK_JIFFIES));
  2101. }
  2102. static void ibx_irq_preinstall(struct drm_device *dev)
  2103. {
  2104. struct drm_i915_private *dev_priv = dev->dev_private;
  2105. if (HAS_PCH_NOP(dev))
  2106. return;
  2107. /* south display irq */
  2108. I915_WRITE(SDEIMR, 0xffffffff);
  2109. /*
  2110. * SDEIER is also touched by the interrupt handler to work around missed
  2111. * PCH interrupts. Hence we can't update it after the interrupt handler
  2112. * is enabled - instead we unconditionally enable all PCH interrupt
  2113. * sources here, but then only unmask them as needed with SDEIMR.
  2114. */
  2115. I915_WRITE(SDEIER, 0xffffffff);
  2116. POSTING_READ(SDEIER);
  2117. }
  2118. /* drm_dma.h hooks
  2119. */
  2120. static void ironlake_irq_preinstall(struct drm_device *dev)
  2121. {
  2122. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  2123. atomic_set(&dev_priv->irq_received, 0);
  2124. I915_WRITE(HWSTAM, 0xeffe);
  2125. /* XXX hotplug from PCH */
  2126. I915_WRITE(DEIMR, 0xffffffff);
  2127. I915_WRITE(DEIER, 0x0);
  2128. POSTING_READ(DEIER);
  2129. /* and GT */
  2130. I915_WRITE(GTIMR, 0xffffffff);
  2131. I915_WRITE(GTIER, 0x0);
  2132. POSTING_READ(GTIER);
  2133. ibx_irq_preinstall(dev);
  2134. }
  2135. static void ivybridge_irq_preinstall(struct drm_device *dev)
  2136. {
  2137. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  2138. atomic_set(&dev_priv->irq_received, 0);
  2139. I915_WRITE(HWSTAM, 0xeffe);
  2140. /* XXX hotplug from PCH */
  2141. I915_WRITE(DEIMR, 0xffffffff);
  2142. I915_WRITE(DEIER, 0x0);
  2143. POSTING_READ(DEIER);
  2144. /* and GT */
  2145. I915_WRITE(GTIMR, 0xffffffff);
  2146. I915_WRITE(GTIER, 0x0);
  2147. POSTING_READ(GTIER);
  2148. /* Power management */
  2149. I915_WRITE(GEN6_PMIMR, 0xffffffff);
  2150. I915_WRITE(GEN6_PMIER, 0x0);
  2151. POSTING_READ(GEN6_PMIER);
  2152. ibx_irq_preinstall(dev);
  2153. }
  2154. static void valleyview_irq_preinstall(struct drm_device *dev)
  2155. {
  2156. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  2157. int pipe;
  2158. atomic_set(&dev_priv->irq_received, 0);
  2159. /* VLV magic */
  2160. I915_WRITE(VLV_IMR, 0);
  2161. I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
  2162. I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
  2163. I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
  2164. /* and GT */
  2165. I915_WRITE(GTIIR, I915_READ(GTIIR));
  2166. I915_WRITE(GTIIR, I915_READ(GTIIR));
  2167. I915_WRITE(GTIMR, 0xffffffff);
  2168. I915_WRITE(GTIER, 0x0);
  2169. POSTING_READ(GTIER);
  2170. I915_WRITE(DPINVGTT, 0xff);
  2171. I915_WRITE(PORT_HOTPLUG_EN, 0);
  2172. I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
  2173. for_each_pipe(pipe)
  2174. I915_WRITE(PIPESTAT(pipe), 0xffff);
  2175. I915_WRITE(VLV_IIR, 0xffffffff);
  2176. I915_WRITE(VLV_IMR, 0xffffffff);
  2177. I915_WRITE(VLV_IER, 0x0);
  2178. POSTING_READ(VLV_IER);
  2179. }
  2180. static void ibx_hpd_irq_setup(struct drm_device *dev)
  2181. {
  2182. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  2183. struct drm_mode_config *mode_config = &dev->mode_config;
  2184. struct intel_encoder *intel_encoder;
  2185. u32 mask = ~I915_READ(SDEIMR);
  2186. u32 hotplug;
  2187. if (HAS_PCH_IBX(dev)) {
  2188. mask &= ~SDE_HOTPLUG_MASK;
  2189. list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
  2190. if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
  2191. mask |= hpd_ibx[intel_encoder->hpd_pin];
  2192. } else {
  2193. mask &= ~SDE_HOTPLUG_MASK_CPT;
  2194. list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
  2195. if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
  2196. mask |= hpd_cpt[intel_encoder->hpd_pin];
  2197. }
  2198. I915_WRITE(SDEIMR, ~mask);
  2199. /*
  2200. * Enable digital hotplug on the PCH, and configure the DP short pulse
  2201. * duration to 2ms (which is the minimum in the Display Port spec)
  2202. *
  2203. * This register is the same on all known PCH chips.
  2204. */
  2205. hotplug = I915_READ(PCH_PORT_HOTPLUG);
  2206. hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
  2207. hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
  2208. hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
  2209. hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
  2210. I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
  2211. }
  2212. static void ibx_irq_postinstall(struct drm_device *dev)
  2213. {
  2214. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  2215. u32 mask;
  2216. if (HAS_PCH_NOP(dev))
  2217. return;
  2218. if (HAS_PCH_IBX(dev)) {
  2219. mask = SDE_GMBUS | SDE_AUX_MASK | SDE_TRANSB_FIFO_UNDER |
  2220. SDE_TRANSA_FIFO_UNDER | SDE_POISON;
  2221. } else {
  2222. mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT | SDE_ERROR_CPT;
  2223. I915_WRITE(SERR_INT, I915_READ(SERR_INT));
  2224. }
  2225. I915_WRITE(SDEIIR, I915_READ(SDEIIR));
  2226. I915_WRITE(SDEIMR, ~mask);
  2227. }
  2228. static int ironlake_irq_postinstall(struct drm_device *dev)
  2229. {
  2230. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  2231. /* enable kind of interrupts always enabled */
  2232. u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
  2233. DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
  2234. DE_AUX_CHANNEL_A | DE_PIPEB_FIFO_UNDERRUN |
  2235. DE_PIPEA_FIFO_UNDERRUN | DE_POISON;
  2236. u32 gt_irqs;
  2237. dev_priv->irq_mask = ~display_mask;
  2238. /* should always can generate irq */
  2239. I915_WRITE(DEIIR, I915_READ(DEIIR));
  2240. I915_WRITE(DEIMR, dev_priv->irq_mask);
  2241. I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK);
  2242. POSTING_READ(DEIER);
  2243. dev_priv->gt_irq_mask = ~0;
  2244. I915_WRITE(GTIIR, I915_READ(GTIIR));
  2245. I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
  2246. gt_irqs = GT_RENDER_USER_INTERRUPT;
  2247. if (IS_GEN6(dev))
  2248. gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
  2249. else
  2250. gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT |
  2251. ILK_BSD_USER_INTERRUPT;
  2252. I915_WRITE(GTIER, gt_irqs);
  2253. POSTING_READ(GTIER);
  2254. ibx_irq_postinstall(dev);
  2255. if (IS_IRONLAKE_M(dev)) {
  2256. /* Clear & enable PCU event interrupts */
  2257. I915_WRITE(DEIIR, DE_PCU_EVENT);
  2258. I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
  2259. ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
  2260. }
  2261. return 0;
  2262. }
  2263. static int ivybridge_irq_postinstall(struct drm_device *dev)
  2264. {
  2265. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  2266. /* enable kind of interrupts always enabled */
  2267. u32 display_mask =
  2268. DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | DE_PCH_EVENT_IVB |
  2269. DE_PLANEC_FLIP_DONE_IVB |
  2270. DE_PLANEB_FLIP_DONE_IVB |
  2271. DE_PLANEA_FLIP_DONE_IVB |
  2272. DE_AUX_CHANNEL_A_IVB |
  2273. DE_ERR_INT_IVB;
  2274. u32 pm_irqs = GEN6_PM_RPS_EVENTS;
  2275. u32 gt_irqs;
  2276. dev_priv->irq_mask = ~display_mask;
  2277. /* should always can generate irq */
  2278. I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT));
  2279. I915_WRITE(DEIIR, I915_READ(DEIIR));
  2280. I915_WRITE(DEIMR, dev_priv->irq_mask);
  2281. I915_WRITE(DEIER,
  2282. display_mask |
  2283. DE_PIPEC_VBLANK_IVB |
  2284. DE_PIPEB_VBLANK_IVB |
  2285. DE_PIPEA_VBLANK_IVB);
  2286. POSTING_READ(DEIER);
  2287. dev_priv->gt_irq_mask = ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
  2288. I915_WRITE(GTIIR, I915_READ(GTIIR));
  2289. I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
  2290. gt_irqs = GT_RENDER_USER_INTERRUPT | GT_BSD_USER_INTERRUPT |
  2291. GT_BLT_USER_INTERRUPT | GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
  2292. I915_WRITE(GTIER, gt_irqs);
  2293. POSTING_READ(GTIER);
  2294. I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
  2295. if (HAS_VEBOX(dev))
  2296. pm_irqs |= PM_VEBOX_USER_INTERRUPT |
  2297. PM_VEBOX_CS_ERROR_INTERRUPT;
  2298. /* Our enable/disable rps functions may touch these registers so
  2299. * make sure to set a known state for only the non-RPS bits.
  2300. * The RMW is extra paranoia since this should be called after being set
  2301. * to a known state in preinstall.
  2302. * */
  2303. I915_WRITE(GEN6_PMIMR,
  2304. (I915_READ(GEN6_PMIMR) | ~GEN6_PM_RPS_EVENTS) & ~pm_irqs);
  2305. I915_WRITE(GEN6_PMIER,
  2306. (I915_READ(GEN6_PMIER) & GEN6_PM_RPS_EVENTS) | pm_irqs);
  2307. POSTING_READ(GEN6_PMIER);
  2308. ibx_irq_postinstall(dev);
  2309. return 0;
  2310. }
  2311. static int valleyview_irq_postinstall(struct drm_device *dev)
  2312. {
  2313. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  2314. u32 gt_irqs;
  2315. u32 enable_mask;
  2316. u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV;
  2317. enable_mask = I915_DISPLAY_PORT_INTERRUPT;
  2318. enable_mask |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
  2319. I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
  2320. I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
  2321. I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
  2322. /*
  2323. *Leave vblank interrupts masked initially. enable/disable will
  2324. * toggle them based on usage.
  2325. */
  2326. dev_priv->irq_mask = (~enable_mask) |
  2327. I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
  2328. I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
  2329. I915_WRITE(PORT_HOTPLUG_EN, 0);
  2330. POSTING_READ(PORT_HOTPLUG_EN);
  2331. I915_WRITE(VLV_IMR, dev_priv->irq_mask);
  2332. I915_WRITE(VLV_IER, enable_mask);
  2333. I915_WRITE(VLV_IIR, 0xffffffff);
  2334. I915_WRITE(PIPESTAT(0), 0xffff);
  2335. I915_WRITE(PIPESTAT(1), 0xffff);
  2336. POSTING_READ(VLV_IER);
  2337. i915_enable_pipestat(dev_priv, 0, pipestat_enable);
  2338. i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
  2339. i915_enable_pipestat(dev_priv, 1, pipestat_enable);
  2340. I915_WRITE(VLV_IIR, 0xffffffff);
  2341. I915_WRITE(VLV_IIR, 0xffffffff);
  2342. I915_WRITE(GTIIR, I915_READ(GTIIR));
  2343. I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
  2344. gt_irqs = GT_RENDER_USER_INTERRUPT | GT_BSD_USER_INTERRUPT |
  2345. GT_BLT_USER_INTERRUPT;
  2346. I915_WRITE(GTIER, gt_irqs);
  2347. POSTING_READ(GTIER);
  2348. /* ack & enable invalid PTE error interrupts */
  2349. #if 0 /* FIXME: add support to irq handler for checking these bits */
  2350. I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
  2351. I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
  2352. #endif
  2353. I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
  2354. return 0;
  2355. }
  2356. static void valleyview_irq_uninstall(struct drm_device *dev)
  2357. {
  2358. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  2359. int pipe;
  2360. if (!dev_priv)
  2361. return;
  2362. del_timer_sync(&dev_priv->hotplug_reenable_timer);
  2363. for_each_pipe(pipe)
  2364. I915_WRITE(PIPESTAT(pipe), 0xffff);
  2365. I915_WRITE(HWSTAM, 0xffffffff);
  2366. I915_WRITE(PORT_HOTPLUG_EN, 0);
  2367. I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
  2368. for_each_pipe(pipe)
  2369. I915_WRITE(PIPESTAT(pipe), 0xffff);
  2370. I915_WRITE(VLV_IIR, 0xffffffff);
  2371. I915_WRITE(VLV_IMR, 0xffffffff);
  2372. I915_WRITE(VLV_IER, 0x0);
  2373. POSTING_READ(VLV_IER);
  2374. }
  2375. static void ironlake_irq_uninstall(struct drm_device *dev)
  2376. {
  2377. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  2378. if (!dev_priv)
  2379. return;
  2380. del_timer_sync(&dev_priv->hotplug_reenable_timer);
  2381. I915_WRITE(HWSTAM, 0xffffffff);
  2382. I915_WRITE(DEIMR, 0xffffffff);
  2383. I915_WRITE(DEIER, 0x0);
  2384. I915_WRITE(DEIIR, I915_READ(DEIIR));
  2385. if (IS_GEN7(dev))
  2386. I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT));
  2387. I915_WRITE(GTIMR, 0xffffffff);
  2388. I915_WRITE(GTIER, 0x0);
  2389. I915_WRITE(GTIIR, I915_READ(GTIIR));
  2390. if (HAS_PCH_NOP(dev))
  2391. return;
  2392. I915_WRITE(SDEIMR, 0xffffffff);
  2393. I915_WRITE(SDEIER, 0x0);
  2394. I915_WRITE(SDEIIR, I915_READ(SDEIIR));
  2395. if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
  2396. I915_WRITE(SERR_INT, I915_READ(SERR_INT));
  2397. }
  2398. static void i8xx_irq_preinstall(struct drm_device * dev)
  2399. {
  2400. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  2401. int pipe;
  2402. atomic_set(&dev_priv->irq_received, 0);
  2403. for_each_pipe(pipe)
  2404. I915_WRITE(PIPESTAT(pipe), 0);
  2405. I915_WRITE16(IMR, 0xffff);
  2406. I915_WRITE16(IER, 0x0);
  2407. POSTING_READ16(IER);
  2408. }
  2409. static int i8xx_irq_postinstall(struct drm_device *dev)
  2410. {
  2411. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  2412. I915_WRITE16(EMR,
  2413. ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
  2414. /* Unmask the interrupts that we always want on. */
  2415. dev_priv->irq_mask =
  2416. ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
  2417. I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
  2418. I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
  2419. I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
  2420. I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
  2421. I915_WRITE16(IMR, dev_priv->irq_mask);
  2422. I915_WRITE16(IER,
  2423. I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
  2424. I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
  2425. I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
  2426. I915_USER_INTERRUPT);
  2427. POSTING_READ16(IER);
  2428. return 0;
  2429. }
  2430. /*
  2431. * Returns true when a page flip has completed.
  2432. */
  2433. static bool i8xx_handle_vblank(struct drm_device *dev,
  2434. int pipe, u16 iir)
  2435. {
  2436. drm_i915_private_t *dev_priv = dev->dev_private;
  2437. u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(pipe);
  2438. if (!drm_handle_vblank(dev, pipe))
  2439. return false;
  2440. if ((iir & flip_pending) == 0)
  2441. return false;
  2442. intel_prepare_page_flip(dev, pipe);
  2443. /* We detect FlipDone by looking for the change in PendingFlip from '1'
  2444. * to '0' on the following vblank, i.e. IIR has the Pendingflip
  2445. * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
  2446. * the flip is completed (no longer pending). Since this doesn't raise
  2447. * an interrupt per se, we watch for the change at vblank.
  2448. */
  2449. if (I915_READ16(ISR) & flip_pending)
  2450. return false;
  2451. intel_finish_page_flip(dev, pipe);
  2452. return true;
  2453. }
  2454. static irqreturn_t i8xx_irq_handler(int irq, void *arg)
  2455. {
  2456. struct drm_device *dev = (struct drm_device *) arg;
  2457. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  2458. u16 iir, new_iir;
  2459. u32 pipe_stats[2];
  2460. unsigned long irqflags;
  2461. int irq_received;
  2462. int pipe;
  2463. u16 flip_mask =
  2464. I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
  2465. I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
  2466. atomic_inc(&dev_priv->irq_received);
  2467. iir = I915_READ16(IIR);
  2468. if (iir == 0)
  2469. return IRQ_NONE;
  2470. while (iir & ~flip_mask) {
  2471. /* Can't rely on pipestat interrupt bit in iir as it might
  2472. * have been cleared after the pipestat interrupt was received.
  2473. * It doesn't set the bit in iir again, but it still produces
  2474. * interrupts (for non-MSI).
  2475. */
  2476. spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  2477. if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
  2478. i915_handle_error(dev, false);
  2479. for_each_pipe(pipe) {
  2480. int reg = PIPESTAT(pipe);
  2481. pipe_stats[pipe] = I915_READ(reg);
  2482. /*
  2483. * Clear the PIPE*STAT regs before the IIR
  2484. */
  2485. if (pipe_stats[pipe] & 0x8000ffff) {
  2486. if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
  2487. DRM_DEBUG_DRIVER("pipe %c underrun\n",
  2488. pipe_name(pipe));
  2489. I915_WRITE(reg, pipe_stats[pipe]);
  2490. irq_received = 1;
  2491. }
  2492. }
  2493. spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  2494. I915_WRITE16(IIR, iir & ~flip_mask);
  2495. new_iir = I915_READ16(IIR); /* Flush posted writes */
  2496. i915_update_dri1_breadcrumb(dev);
  2497. if (iir & I915_USER_INTERRUPT)
  2498. notify_ring(dev, &dev_priv->ring[RCS]);
  2499. if (pipe_stats[0] & PIPE_VBLANK_INTERRUPT_STATUS &&
  2500. i8xx_handle_vblank(dev, 0, iir))
  2501. flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(0);
  2502. if (pipe_stats[1] & PIPE_VBLANK_INTERRUPT_STATUS &&
  2503. i8xx_handle_vblank(dev, 1, iir))
  2504. flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(1);
  2505. iir = new_iir;
  2506. }
  2507. return IRQ_HANDLED;
  2508. }
  2509. static void i8xx_irq_uninstall(struct drm_device * dev)
  2510. {
  2511. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  2512. int pipe;
  2513. for_each_pipe(pipe) {
  2514. /* Clear enable bits; then clear status bits */
  2515. I915_WRITE(PIPESTAT(pipe), 0);
  2516. I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
  2517. }
  2518. I915_WRITE16(IMR, 0xffff);
  2519. I915_WRITE16(IER, 0x0);
  2520. I915_WRITE16(IIR, I915_READ16(IIR));
  2521. }
  2522. static void i915_irq_preinstall(struct drm_device * dev)
  2523. {
  2524. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  2525. int pipe;
  2526. atomic_set(&dev_priv->irq_received, 0);
  2527. if (I915_HAS_HOTPLUG(dev)) {
  2528. I915_WRITE(PORT_HOTPLUG_EN, 0);
  2529. I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
  2530. }
  2531. I915_WRITE16(HWSTAM, 0xeffe);
  2532. for_each_pipe(pipe)
  2533. I915_WRITE(PIPESTAT(pipe), 0);
  2534. I915_WRITE(IMR, 0xffffffff);
  2535. I915_WRITE(IER, 0x0);
  2536. POSTING_READ(IER);
  2537. }
  2538. static int i915_irq_postinstall(struct drm_device *dev)
  2539. {
  2540. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  2541. u32 enable_mask;
  2542. I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
  2543. /* Unmask the interrupts that we always want on. */
  2544. dev_priv->irq_mask =
  2545. ~(I915_ASLE_INTERRUPT |
  2546. I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
  2547. I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
  2548. I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
  2549. I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
  2550. I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
  2551. enable_mask =
  2552. I915_ASLE_INTERRUPT |
  2553. I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
  2554. I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
  2555. I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
  2556. I915_USER_INTERRUPT;
  2557. if (I915_HAS_HOTPLUG(dev)) {
  2558. I915_WRITE(PORT_HOTPLUG_EN, 0);
  2559. POSTING_READ(PORT_HOTPLUG_EN);
  2560. /* Enable in IER... */
  2561. enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
  2562. /* and unmask in IMR */
  2563. dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
  2564. }
  2565. I915_WRITE(IMR, dev_priv->irq_mask);
  2566. I915_WRITE(IER, enable_mask);
  2567. POSTING_READ(IER);
  2568. i915_enable_asle_pipestat(dev);
  2569. return 0;
  2570. }
  2571. /*
  2572. * Returns true when a page flip has completed.
  2573. */
  2574. static bool i915_handle_vblank(struct drm_device *dev,
  2575. int plane, int pipe, u32 iir)
  2576. {
  2577. drm_i915_private_t *dev_priv = dev->dev_private;
  2578. u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
  2579. if (!drm_handle_vblank(dev, pipe))
  2580. return false;
  2581. if ((iir & flip_pending) == 0)
  2582. return false;
  2583. intel_prepare_page_flip(dev, plane);
  2584. /* We detect FlipDone by looking for the change in PendingFlip from '1'
  2585. * to '0' on the following vblank, i.e. IIR has the Pendingflip
  2586. * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
  2587. * the flip is completed (no longer pending). Since this doesn't raise
  2588. * an interrupt per se, we watch for the change at vblank.
  2589. */
  2590. if (I915_READ(ISR) & flip_pending)
  2591. return false;
  2592. intel_finish_page_flip(dev, pipe);
  2593. return true;
  2594. }
  2595. static irqreturn_t i915_irq_handler(int irq, void *arg)
  2596. {
  2597. struct drm_device *dev = (struct drm_device *) arg;
  2598. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  2599. u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
  2600. unsigned long irqflags;
  2601. u32 flip_mask =
  2602. I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
  2603. I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
  2604. int pipe, ret = IRQ_NONE;
  2605. atomic_inc(&dev_priv->irq_received);
  2606. iir = I915_READ(IIR);
  2607. do {
  2608. bool irq_received = (iir & ~flip_mask) != 0;
  2609. bool blc_event = false;
  2610. /* Can't rely on pipestat interrupt bit in iir as it might
  2611. * have been cleared after the pipestat interrupt was received.
  2612. * It doesn't set the bit in iir again, but it still produces
  2613. * interrupts (for non-MSI).
  2614. */
  2615. spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  2616. if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
  2617. i915_handle_error(dev, false);
  2618. for_each_pipe(pipe) {
  2619. int reg = PIPESTAT(pipe);
  2620. pipe_stats[pipe] = I915_READ(reg);
  2621. /* Clear the PIPE*STAT regs before the IIR */
  2622. if (pipe_stats[pipe] & 0x8000ffff) {
  2623. if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
  2624. DRM_DEBUG_DRIVER("pipe %c underrun\n",
  2625. pipe_name(pipe));
  2626. I915_WRITE(reg, pipe_stats[pipe]);
  2627. irq_received = true;
  2628. }
  2629. }
  2630. spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  2631. if (!irq_received)
  2632. break;
  2633. /* Consume port. Then clear IIR or we'll miss events */
  2634. if ((I915_HAS_HOTPLUG(dev)) &&
  2635. (iir & I915_DISPLAY_PORT_INTERRUPT)) {
  2636. u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
  2637. u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
  2638. DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
  2639. hotplug_status);
  2640. if (hotplug_trigger) {
  2641. if (hotplug_irq_storm_detect(dev, hotplug_trigger, hpd_status_i915))
  2642. i915_hpd_irq_setup(dev);
  2643. queue_work(dev_priv->wq,
  2644. &dev_priv->hotplug_work);
  2645. }
  2646. I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
  2647. POSTING_READ(PORT_HOTPLUG_STAT);
  2648. }
  2649. I915_WRITE(IIR, iir & ~flip_mask);
  2650. new_iir = I915_READ(IIR); /* Flush posted writes */
  2651. if (iir & I915_USER_INTERRUPT)
  2652. notify_ring(dev, &dev_priv->ring[RCS]);
  2653. for_each_pipe(pipe) {
  2654. int plane = pipe;
  2655. if (IS_MOBILE(dev))
  2656. plane = !plane;
  2657. if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
  2658. i915_handle_vblank(dev, plane, pipe, iir))
  2659. flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
  2660. if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
  2661. blc_event = true;
  2662. }
  2663. if (blc_event || (iir & I915_ASLE_INTERRUPT))
  2664. intel_opregion_asle_intr(dev);
  2665. /* With MSI, interrupts are only generated when iir
  2666. * transitions from zero to nonzero. If another bit got
  2667. * set while we were handling the existing iir bits, then
  2668. * we would never get another interrupt.
  2669. *
  2670. * This is fine on non-MSI as well, as if we hit this path
  2671. * we avoid exiting the interrupt handler only to generate
  2672. * another one.
  2673. *
  2674. * Note that for MSI this could cause a stray interrupt report
  2675. * if an interrupt landed in the time between writing IIR and
  2676. * the posting read. This should be rare enough to never
  2677. * trigger the 99% of 100,000 interrupts test for disabling
  2678. * stray interrupts.
  2679. */
  2680. ret = IRQ_HANDLED;
  2681. iir = new_iir;
  2682. } while (iir & ~flip_mask);
  2683. i915_update_dri1_breadcrumb(dev);
  2684. return ret;
  2685. }
  2686. static void i915_irq_uninstall(struct drm_device * dev)
  2687. {
  2688. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  2689. int pipe;
  2690. del_timer_sync(&dev_priv->hotplug_reenable_timer);
  2691. if (I915_HAS_HOTPLUG(dev)) {
  2692. I915_WRITE(PORT_HOTPLUG_EN, 0);
  2693. I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
  2694. }
  2695. I915_WRITE16(HWSTAM, 0xffff);
  2696. for_each_pipe(pipe) {
  2697. /* Clear enable bits; then clear status bits */
  2698. I915_WRITE(PIPESTAT(pipe), 0);
  2699. I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
  2700. }
  2701. I915_WRITE(IMR, 0xffffffff);
  2702. I915_WRITE(IER, 0x0);
  2703. I915_WRITE(IIR, I915_READ(IIR));
  2704. }
  2705. static void i965_irq_preinstall(struct drm_device * dev)
  2706. {
  2707. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  2708. int pipe;
  2709. atomic_set(&dev_priv->irq_received, 0);
  2710. I915_WRITE(PORT_HOTPLUG_EN, 0);
  2711. I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
  2712. I915_WRITE(HWSTAM, 0xeffe);
  2713. for_each_pipe(pipe)
  2714. I915_WRITE(PIPESTAT(pipe), 0);
  2715. I915_WRITE(IMR, 0xffffffff);
  2716. I915_WRITE(IER, 0x0);
  2717. POSTING_READ(IER);
  2718. }
  2719. static int i965_irq_postinstall(struct drm_device *dev)
  2720. {
  2721. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  2722. u32 enable_mask;
  2723. u32 error_mask;
  2724. /* Unmask the interrupts that we always want on. */
  2725. dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
  2726. I915_DISPLAY_PORT_INTERRUPT |
  2727. I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
  2728. I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
  2729. I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
  2730. I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
  2731. I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
  2732. enable_mask = ~dev_priv->irq_mask;
  2733. enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
  2734. I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
  2735. enable_mask |= I915_USER_INTERRUPT;
  2736. if (IS_G4X(dev))
  2737. enable_mask |= I915_BSD_USER_INTERRUPT;
  2738. i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
  2739. /*
  2740. * Enable some error detection, note the instruction error mask
  2741. * bit is reserved, so we leave it masked.
  2742. */
  2743. if (IS_G4X(dev)) {
  2744. error_mask = ~(GM45_ERROR_PAGE_TABLE |
  2745. GM45_ERROR_MEM_PRIV |
  2746. GM45_ERROR_CP_PRIV |
  2747. I915_ERROR_MEMORY_REFRESH);
  2748. } else {
  2749. error_mask = ~(I915_ERROR_PAGE_TABLE |
  2750. I915_ERROR_MEMORY_REFRESH);
  2751. }
  2752. I915_WRITE(EMR, error_mask);
  2753. I915_WRITE(IMR, dev_priv->irq_mask);
  2754. I915_WRITE(IER, enable_mask);
  2755. POSTING_READ(IER);
  2756. I915_WRITE(PORT_HOTPLUG_EN, 0);
  2757. POSTING_READ(PORT_HOTPLUG_EN);
  2758. i915_enable_asle_pipestat(dev);
  2759. return 0;
  2760. }
  2761. static void i915_hpd_irq_setup(struct drm_device *dev)
  2762. {
  2763. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  2764. struct drm_mode_config *mode_config = &dev->mode_config;
  2765. struct intel_encoder *intel_encoder;
  2766. u32 hotplug_en;
  2767. if (I915_HAS_HOTPLUG(dev)) {
  2768. hotplug_en = I915_READ(PORT_HOTPLUG_EN);
  2769. hotplug_en &= ~HOTPLUG_INT_EN_MASK;
  2770. /* Note HDMI and DP share hotplug bits */
  2771. /* enable bits are the same for all generations */
  2772. list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
  2773. if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
  2774. hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin];
  2775. /* Programming the CRT detection parameters tends
  2776. to generate a spurious hotplug event about three
  2777. seconds later. So just do it once.
  2778. */
  2779. if (IS_G4X(dev))
  2780. hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
  2781. hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK;
  2782. hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
  2783. /* Ignore TV since it's buggy */
  2784. I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
  2785. }
  2786. }
  2787. static irqreturn_t i965_irq_handler(int irq, void *arg)
  2788. {
  2789. struct drm_device *dev = (struct drm_device *) arg;
  2790. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  2791. u32 iir, new_iir;
  2792. u32 pipe_stats[I915_MAX_PIPES];
  2793. unsigned long irqflags;
  2794. int irq_received;
  2795. int ret = IRQ_NONE, pipe;
  2796. u32 flip_mask =
  2797. I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
  2798. I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
  2799. atomic_inc(&dev_priv->irq_received);
  2800. iir = I915_READ(IIR);
  2801. for (;;) {
  2802. bool blc_event = false;
  2803. irq_received = (iir & ~flip_mask) != 0;
  2804. /* Can't rely on pipestat interrupt bit in iir as it might
  2805. * have been cleared after the pipestat interrupt was received.
  2806. * It doesn't set the bit in iir again, but it still produces
  2807. * interrupts (for non-MSI).
  2808. */
  2809. spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  2810. if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
  2811. i915_handle_error(dev, false);
  2812. for_each_pipe(pipe) {
  2813. int reg = PIPESTAT(pipe);
  2814. pipe_stats[pipe] = I915_READ(reg);
  2815. /*
  2816. * Clear the PIPE*STAT regs before the IIR
  2817. */
  2818. if (pipe_stats[pipe] & 0x8000ffff) {
  2819. if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
  2820. DRM_DEBUG_DRIVER("pipe %c underrun\n",
  2821. pipe_name(pipe));
  2822. I915_WRITE(reg, pipe_stats[pipe]);
  2823. irq_received = 1;
  2824. }
  2825. }
  2826. spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  2827. if (!irq_received)
  2828. break;
  2829. ret = IRQ_HANDLED;
  2830. /* Consume port. Then clear IIR or we'll miss events */
  2831. if (iir & I915_DISPLAY_PORT_INTERRUPT) {
  2832. u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
  2833. u32 hotplug_trigger = hotplug_status & (IS_G4X(dev) ?
  2834. HOTPLUG_INT_STATUS_G4X :
  2835. HOTPLUG_INT_STATUS_I965);
  2836. DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
  2837. hotplug_status);
  2838. if (hotplug_trigger) {
  2839. if (hotplug_irq_storm_detect(dev, hotplug_trigger,
  2840. IS_G4X(dev) ? hpd_status_gen4 : hpd_status_i965))
  2841. i915_hpd_irq_setup(dev);
  2842. queue_work(dev_priv->wq,
  2843. &dev_priv->hotplug_work);
  2844. }
  2845. I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
  2846. I915_READ(PORT_HOTPLUG_STAT);
  2847. }
  2848. I915_WRITE(IIR, iir & ~flip_mask);
  2849. new_iir = I915_READ(IIR); /* Flush posted writes */
  2850. if (iir & I915_USER_INTERRUPT)
  2851. notify_ring(dev, &dev_priv->ring[RCS]);
  2852. if (iir & I915_BSD_USER_INTERRUPT)
  2853. notify_ring(dev, &dev_priv->ring[VCS]);
  2854. for_each_pipe(pipe) {
  2855. if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
  2856. i915_handle_vblank(dev, pipe, pipe, iir))
  2857. flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
  2858. if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
  2859. blc_event = true;
  2860. }
  2861. if (blc_event || (iir & I915_ASLE_INTERRUPT))
  2862. intel_opregion_asle_intr(dev);
  2863. if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
  2864. gmbus_irq_handler(dev);
  2865. /* With MSI, interrupts are only generated when iir
  2866. * transitions from zero to nonzero. If another bit got
  2867. * set while we were handling the existing iir bits, then
  2868. * we would never get another interrupt.
  2869. *
  2870. * This is fine on non-MSI as well, as if we hit this path
  2871. * we avoid exiting the interrupt handler only to generate
  2872. * another one.
  2873. *
  2874. * Note that for MSI this could cause a stray interrupt report
  2875. * if an interrupt landed in the time between writing IIR and
  2876. * the posting read. This should be rare enough to never
  2877. * trigger the 99% of 100,000 interrupts test for disabling
  2878. * stray interrupts.
  2879. */
  2880. iir = new_iir;
  2881. }
  2882. i915_update_dri1_breadcrumb(dev);
  2883. return ret;
  2884. }
  2885. static void i965_irq_uninstall(struct drm_device * dev)
  2886. {
  2887. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  2888. int pipe;
  2889. if (!dev_priv)
  2890. return;
  2891. del_timer_sync(&dev_priv->hotplug_reenable_timer);
  2892. I915_WRITE(PORT_HOTPLUG_EN, 0);
  2893. I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
  2894. I915_WRITE(HWSTAM, 0xffffffff);
  2895. for_each_pipe(pipe)
  2896. I915_WRITE(PIPESTAT(pipe), 0);
  2897. I915_WRITE(IMR, 0xffffffff);
  2898. I915_WRITE(IER, 0x0);
  2899. for_each_pipe(pipe)
  2900. I915_WRITE(PIPESTAT(pipe),
  2901. I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
  2902. I915_WRITE(IIR, I915_READ(IIR));
  2903. }
  2904. static void i915_reenable_hotplug_timer_func(unsigned long data)
  2905. {
  2906. drm_i915_private_t *dev_priv = (drm_i915_private_t *)data;
  2907. struct drm_device *dev = dev_priv->dev;
  2908. struct drm_mode_config *mode_config = &dev->mode_config;
  2909. unsigned long irqflags;
  2910. int i;
  2911. spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  2912. for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) {
  2913. struct drm_connector *connector;
  2914. if (dev_priv->hpd_stats[i].hpd_mark != HPD_DISABLED)
  2915. continue;
  2916. dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
  2917. list_for_each_entry(connector, &mode_config->connector_list, head) {
  2918. struct intel_connector *intel_connector = to_intel_connector(connector);
  2919. if (intel_connector->encoder->hpd_pin == i) {
  2920. if (connector->polled != intel_connector->polled)
  2921. DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
  2922. drm_get_connector_name(connector));
  2923. connector->polled = intel_connector->polled;
  2924. if (!connector->polled)
  2925. connector->polled = DRM_CONNECTOR_POLL_HPD;
  2926. }
  2927. }
  2928. }
  2929. if (dev_priv->display.hpd_irq_setup)
  2930. dev_priv->display.hpd_irq_setup(dev);
  2931. spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  2932. }
  2933. void intel_irq_init(struct drm_device *dev)
  2934. {
  2935. struct drm_i915_private *dev_priv = dev->dev_private;
  2936. INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
  2937. INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func);
  2938. INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
  2939. INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
  2940. setup_timer(&dev_priv->gpu_error.hangcheck_timer,
  2941. i915_hangcheck_elapsed,
  2942. (unsigned long) dev);
  2943. setup_timer(&dev_priv->hotplug_reenable_timer, i915_reenable_hotplug_timer_func,
  2944. (unsigned long) dev_priv);
  2945. pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
  2946. dev->driver->get_vblank_counter = i915_get_vblank_counter;
  2947. dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
  2948. if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
  2949. dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
  2950. dev->driver->get_vblank_counter = gm45_get_vblank_counter;
  2951. }
  2952. if (drm_core_check_feature(dev, DRIVER_MODESET))
  2953. dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
  2954. else
  2955. dev->driver->get_vblank_timestamp = NULL;
  2956. dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
  2957. if (IS_VALLEYVIEW(dev)) {
  2958. dev->driver->irq_handler = valleyview_irq_handler;
  2959. dev->driver->irq_preinstall = valleyview_irq_preinstall;
  2960. dev->driver->irq_postinstall = valleyview_irq_postinstall;
  2961. dev->driver->irq_uninstall = valleyview_irq_uninstall;
  2962. dev->driver->enable_vblank = valleyview_enable_vblank;
  2963. dev->driver->disable_vblank = valleyview_disable_vblank;
  2964. dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
  2965. } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
  2966. /* Share uninstall handlers with ILK/SNB */
  2967. dev->driver->irq_handler = ivybridge_irq_handler;
  2968. dev->driver->irq_preinstall = ivybridge_irq_preinstall;
  2969. dev->driver->irq_postinstall = ivybridge_irq_postinstall;
  2970. dev->driver->irq_uninstall = ironlake_irq_uninstall;
  2971. dev->driver->enable_vblank = ivybridge_enable_vblank;
  2972. dev->driver->disable_vblank = ivybridge_disable_vblank;
  2973. dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
  2974. } else if (HAS_PCH_SPLIT(dev)) {
  2975. dev->driver->irq_handler = ironlake_irq_handler;
  2976. dev->driver->irq_preinstall = ironlake_irq_preinstall;
  2977. dev->driver->irq_postinstall = ironlake_irq_postinstall;
  2978. dev->driver->irq_uninstall = ironlake_irq_uninstall;
  2979. dev->driver->enable_vblank = ironlake_enable_vblank;
  2980. dev->driver->disable_vblank = ironlake_disable_vblank;
  2981. dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
  2982. } else {
  2983. if (INTEL_INFO(dev)->gen == 2) {
  2984. dev->driver->irq_preinstall = i8xx_irq_preinstall;
  2985. dev->driver->irq_postinstall = i8xx_irq_postinstall;
  2986. dev->driver->irq_handler = i8xx_irq_handler;
  2987. dev->driver->irq_uninstall = i8xx_irq_uninstall;
  2988. } else if (INTEL_INFO(dev)->gen == 3) {
  2989. dev->driver->irq_preinstall = i915_irq_preinstall;
  2990. dev->driver->irq_postinstall = i915_irq_postinstall;
  2991. dev->driver->irq_uninstall = i915_irq_uninstall;
  2992. dev->driver->irq_handler = i915_irq_handler;
  2993. dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
  2994. } else {
  2995. dev->driver->irq_preinstall = i965_irq_preinstall;
  2996. dev->driver->irq_postinstall = i965_irq_postinstall;
  2997. dev->driver->irq_uninstall = i965_irq_uninstall;
  2998. dev->driver->irq_handler = i965_irq_handler;
  2999. dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
  3000. }
  3001. dev->driver->enable_vblank = i915_enable_vblank;
  3002. dev->driver->disable_vblank = i915_disable_vblank;
  3003. }
  3004. }
  3005. void intel_hpd_init(struct drm_device *dev)
  3006. {
  3007. struct drm_i915_private *dev_priv = dev->dev_private;
  3008. struct drm_mode_config *mode_config = &dev->mode_config;
  3009. struct drm_connector *connector;
  3010. int i;
  3011. for (i = 1; i < HPD_NUM_PINS; i++) {
  3012. dev_priv->hpd_stats[i].hpd_cnt = 0;
  3013. dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
  3014. }
  3015. list_for_each_entry(connector, &mode_config->connector_list, head) {
  3016. struct intel_connector *intel_connector = to_intel_connector(connector);
  3017. connector->polled = intel_connector->polled;
  3018. if (!connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE)
  3019. connector->polled = DRM_CONNECTOR_POLL_HPD;
  3020. }
  3021. if (dev_priv->display.hpd_irq_setup)
  3022. dev_priv->display.hpd_irq_setup(dev);
  3023. }