i915_gem_execbuffer.c 33 KB

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  1. /*
  2. * Copyright © 2008,2010 Intel Corporation
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice (including the next
  12. * paragraph) shall be included in all copies or substantial portions of the
  13. * Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  18. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21. * IN THE SOFTWARE.
  22. *
  23. * Authors:
  24. * Eric Anholt <eric@anholt.net>
  25. * Chris Wilson <chris@chris-wilson.co.uk>
  26. *
  27. */
  28. #include <drm/drmP.h>
  29. #include <drm/i915_drm.h>
  30. #include "i915_drv.h"
  31. #include "i915_trace.h"
  32. #include "intel_drv.h"
  33. #include <linux/dma_remapping.h>
  34. struct eb_objects {
  35. struct list_head objects;
  36. int and;
  37. union {
  38. struct drm_i915_gem_object *lut[0];
  39. struct hlist_head buckets[0];
  40. };
  41. };
  42. static struct eb_objects *
  43. eb_create(struct drm_i915_gem_execbuffer2 *args)
  44. {
  45. struct eb_objects *eb = NULL;
  46. if (args->flags & I915_EXEC_HANDLE_LUT) {
  47. int size = args->buffer_count;
  48. size *= sizeof(struct drm_i915_gem_object *);
  49. size += sizeof(struct eb_objects);
  50. eb = kmalloc(size, GFP_TEMPORARY | __GFP_NOWARN | __GFP_NORETRY);
  51. }
  52. if (eb == NULL) {
  53. int size = args->buffer_count;
  54. int count = PAGE_SIZE / sizeof(struct hlist_head) / 2;
  55. BUILD_BUG_ON_NOT_POWER_OF_2(PAGE_SIZE / sizeof(struct hlist_head));
  56. while (count > 2*size)
  57. count >>= 1;
  58. eb = kzalloc(count*sizeof(struct hlist_head) +
  59. sizeof(struct eb_objects),
  60. GFP_TEMPORARY);
  61. if (eb == NULL)
  62. return eb;
  63. eb->and = count - 1;
  64. } else
  65. eb->and = -args->buffer_count;
  66. INIT_LIST_HEAD(&eb->objects);
  67. return eb;
  68. }
  69. static void
  70. eb_reset(struct eb_objects *eb)
  71. {
  72. if (eb->and >= 0)
  73. memset(eb->buckets, 0, (eb->and+1)*sizeof(struct hlist_head));
  74. }
  75. static int
  76. eb_lookup_objects(struct eb_objects *eb,
  77. struct drm_i915_gem_exec_object2 *exec,
  78. const struct drm_i915_gem_execbuffer2 *args,
  79. struct drm_file *file)
  80. {
  81. int i;
  82. spin_lock(&file->table_lock);
  83. for (i = 0; i < args->buffer_count; i++) {
  84. struct drm_i915_gem_object *obj;
  85. obj = to_intel_bo(idr_find(&file->object_idr, exec[i].handle));
  86. if (obj == NULL) {
  87. spin_unlock(&file->table_lock);
  88. DRM_DEBUG("Invalid object handle %d at index %d\n",
  89. exec[i].handle, i);
  90. return -ENOENT;
  91. }
  92. if (!list_empty(&obj->exec_list)) {
  93. spin_unlock(&file->table_lock);
  94. DRM_DEBUG("Object %p [handle %d, index %d] appears more than once in object list\n",
  95. obj, exec[i].handle, i);
  96. return -EINVAL;
  97. }
  98. drm_gem_object_reference(&obj->base);
  99. list_add_tail(&obj->exec_list, &eb->objects);
  100. obj->exec_entry = &exec[i];
  101. if (eb->and < 0) {
  102. eb->lut[i] = obj;
  103. } else {
  104. uint32_t handle = args->flags & I915_EXEC_HANDLE_LUT ? i : exec[i].handle;
  105. obj->exec_handle = handle;
  106. hlist_add_head(&obj->exec_node,
  107. &eb->buckets[handle & eb->and]);
  108. }
  109. }
  110. spin_unlock(&file->table_lock);
  111. return 0;
  112. }
  113. static struct drm_i915_gem_object *
  114. eb_get_object(struct eb_objects *eb, unsigned long handle)
  115. {
  116. if (eb->and < 0) {
  117. if (handle >= -eb->and)
  118. return NULL;
  119. return eb->lut[handle];
  120. } else {
  121. struct hlist_head *head;
  122. struct hlist_node *node;
  123. head = &eb->buckets[handle & eb->and];
  124. hlist_for_each(node, head) {
  125. struct drm_i915_gem_object *obj;
  126. obj = hlist_entry(node, struct drm_i915_gem_object, exec_node);
  127. if (obj->exec_handle == handle)
  128. return obj;
  129. }
  130. return NULL;
  131. }
  132. }
  133. static void
  134. eb_destroy(struct eb_objects *eb)
  135. {
  136. while (!list_empty(&eb->objects)) {
  137. struct drm_i915_gem_object *obj;
  138. obj = list_first_entry(&eb->objects,
  139. struct drm_i915_gem_object,
  140. exec_list);
  141. list_del_init(&obj->exec_list);
  142. drm_gem_object_unreference(&obj->base);
  143. }
  144. kfree(eb);
  145. }
  146. static inline int use_cpu_reloc(struct drm_i915_gem_object *obj)
  147. {
  148. return (obj->base.write_domain == I915_GEM_DOMAIN_CPU ||
  149. !obj->map_and_fenceable ||
  150. obj->cache_level != I915_CACHE_NONE);
  151. }
  152. static int
  153. i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj,
  154. struct eb_objects *eb,
  155. struct drm_i915_gem_relocation_entry *reloc)
  156. {
  157. struct drm_device *dev = obj->base.dev;
  158. struct drm_gem_object *target_obj;
  159. struct drm_i915_gem_object *target_i915_obj;
  160. uint32_t target_offset;
  161. int ret = -EINVAL;
  162. /* we've already hold a reference to all valid objects */
  163. target_obj = &eb_get_object(eb, reloc->target_handle)->base;
  164. if (unlikely(target_obj == NULL))
  165. return -ENOENT;
  166. target_i915_obj = to_intel_bo(target_obj);
  167. target_offset = target_i915_obj->gtt_offset;
  168. /* Sandybridge PPGTT errata: We need a global gtt mapping for MI and
  169. * pipe_control writes because the gpu doesn't properly redirect them
  170. * through the ppgtt for non_secure batchbuffers. */
  171. if (unlikely(IS_GEN6(dev) &&
  172. reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION &&
  173. !target_i915_obj->has_global_gtt_mapping)) {
  174. i915_gem_gtt_bind_object(target_i915_obj,
  175. target_i915_obj->cache_level);
  176. }
  177. /* Validate that the target is in a valid r/w GPU domain */
  178. if (unlikely(reloc->write_domain & (reloc->write_domain - 1))) {
  179. DRM_DEBUG("reloc with multiple write domains: "
  180. "obj %p target %d offset %d "
  181. "read %08x write %08x",
  182. obj, reloc->target_handle,
  183. (int) reloc->offset,
  184. reloc->read_domains,
  185. reloc->write_domain);
  186. return ret;
  187. }
  188. if (unlikely((reloc->write_domain | reloc->read_domains)
  189. & ~I915_GEM_GPU_DOMAINS)) {
  190. DRM_DEBUG("reloc with read/write non-GPU domains: "
  191. "obj %p target %d offset %d "
  192. "read %08x write %08x",
  193. obj, reloc->target_handle,
  194. (int) reloc->offset,
  195. reloc->read_domains,
  196. reloc->write_domain);
  197. return ret;
  198. }
  199. target_obj->pending_read_domains |= reloc->read_domains;
  200. target_obj->pending_write_domain |= reloc->write_domain;
  201. /* If the relocation already has the right value in it, no
  202. * more work needs to be done.
  203. */
  204. if (target_offset == reloc->presumed_offset)
  205. return 0;
  206. /* Check that the relocation address is valid... */
  207. if (unlikely(reloc->offset > obj->base.size - 4)) {
  208. DRM_DEBUG("Relocation beyond object bounds: "
  209. "obj %p target %d offset %d size %d.\n",
  210. obj, reloc->target_handle,
  211. (int) reloc->offset,
  212. (int) obj->base.size);
  213. return ret;
  214. }
  215. if (unlikely(reloc->offset & 3)) {
  216. DRM_DEBUG("Relocation not 4-byte aligned: "
  217. "obj %p target %d offset %d.\n",
  218. obj, reloc->target_handle,
  219. (int) reloc->offset);
  220. return ret;
  221. }
  222. /* We can't wait for rendering with pagefaults disabled */
  223. if (obj->active && in_atomic())
  224. return -EFAULT;
  225. reloc->delta += target_offset;
  226. if (use_cpu_reloc(obj)) {
  227. uint32_t page_offset = reloc->offset & ~PAGE_MASK;
  228. char *vaddr;
  229. ret = i915_gem_object_set_to_cpu_domain(obj, 1);
  230. if (ret)
  231. return ret;
  232. vaddr = kmap_atomic(i915_gem_object_get_page(obj,
  233. reloc->offset >> PAGE_SHIFT));
  234. *(uint32_t *)(vaddr + page_offset) = reloc->delta;
  235. kunmap_atomic(vaddr);
  236. } else {
  237. struct drm_i915_private *dev_priv = dev->dev_private;
  238. uint32_t __iomem *reloc_entry;
  239. void __iomem *reloc_page;
  240. ret = i915_gem_object_set_to_gtt_domain(obj, true);
  241. if (ret)
  242. return ret;
  243. ret = i915_gem_object_put_fence(obj);
  244. if (ret)
  245. return ret;
  246. /* Map the page containing the relocation we're going to perform. */
  247. reloc->offset += obj->gtt_offset;
  248. reloc_page = io_mapping_map_atomic_wc(dev_priv->gtt.mappable,
  249. reloc->offset & PAGE_MASK);
  250. reloc_entry = (uint32_t __iomem *)
  251. (reloc_page + (reloc->offset & ~PAGE_MASK));
  252. iowrite32(reloc->delta, reloc_entry);
  253. io_mapping_unmap_atomic(reloc_page);
  254. }
  255. /* and update the user's relocation entry */
  256. reloc->presumed_offset = target_offset;
  257. return 0;
  258. }
  259. static int
  260. i915_gem_execbuffer_relocate_object(struct drm_i915_gem_object *obj,
  261. struct eb_objects *eb)
  262. {
  263. #define N_RELOC(x) ((x) / sizeof(struct drm_i915_gem_relocation_entry))
  264. struct drm_i915_gem_relocation_entry stack_reloc[N_RELOC(512)];
  265. struct drm_i915_gem_relocation_entry __user *user_relocs;
  266. struct drm_i915_gem_exec_object2 *entry = obj->exec_entry;
  267. int remain, ret;
  268. user_relocs = to_user_ptr(entry->relocs_ptr);
  269. remain = entry->relocation_count;
  270. while (remain) {
  271. struct drm_i915_gem_relocation_entry *r = stack_reloc;
  272. int count = remain;
  273. if (count > ARRAY_SIZE(stack_reloc))
  274. count = ARRAY_SIZE(stack_reloc);
  275. remain -= count;
  276. if (__copy_from_user_inatomic(r, user_relocs, count*sizeof(r[0])))
  277. return -EFAULT;
  278. do {
  279. u64 offset = r->presumed_offset;
  280. ret = i915_gem_execbuffer_relocate_entry(obj, eb, r);
  281. if (ret)
  282. return ret;
  283. if (r->presumed_offset != offset &&
  284. __copy_to_user_inatomic(&user_relocs->presumed_offset,
  285. &r->presumed_offset,
  286. sizeof(r->presumed_offset))) {
  287. return -EFAULT;
  288. }
  289. user_relocs++;
  290. r++;
  291. } while (--count);
  292. }
  293. return 0;
  294. #undef N_RELOC
  295. }
  296. static int
  297. i915_gem_execbuffer_relocate_object_slow(struct drm_i915_gem_object *obj,
  298. struct eb_objects *eb,
  299. struct drm_i915_gem_relocation_entry *relocs)
  300. {
  301. const struct drm_i915_gem_exec_object2 *entry = obj->exec_entry;
  302. int i, ret;
  303. for (i = 0; i < entry->relocation_count; i++) {
  304. ret = i915_gem_execbuffer_relocate_entry(obj, eb, &relocs[i]);
  305. if (ret)
  306. return ret;
  307. }
  308. return 0;
  309. }
  310. static int
  311. i915_gem_execbuffer_relocate(struct eb_objects *eb)
  312. {
  313. struct drm_i915_gem_object *obj;
  314. int ret = 0;
  315. /* This is the fast path and we cannot handle a pagefault whilst
  316. * holding the struct mutex lest the user pass in the relocations
  317. * contained within a mmaped bo. For in such a case we, the page
  318. * fault handler would call i915_gem_fault() and we would try to
  319. * acquire the struct mutex again. Obviously this is bad and so
  320. * lockdep complains vehemently.
  321. */
  322. pagefault_disable();
  323. list_for_each_entry(obj, &eb->objects, exec_list) {
  324. ret = i915_gem_execbuffer_relocate_object(obj, eb);
  325. if (ret)
  326. break;
  327. }
  328. pagefault_enable();
  329. return ret;
  330. }
  331. #define __EXEC_OBJECT_HAS_PIN (1<<31)
  332. #define __EXEC_OBJECT_HAS_FENCE (1<<30)
  333. static int
  334. need_reloc_mappable(struct drm_i915_gem_object *obj)
  335. {
  336. struct drm_i915_gem_exec_object2 *entry = obj->exec_entry;
  337. return entry->relocation_count && !use_cpu_reloc(obj);
  338. }
  339. static int
  340. i915_gem_execbuffer_reserve_object(struct drm_i915_gem_object *obj,
  341. struct intel_ring_buffer *ring,
  342. bool *need_reloc)
  343. {
  344. struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
  345. struct drm_i915_gem_exec_object2 *entry = obj->exec_entry;
  346. bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4;
  347. bool need_fence, need_mappable;
  348. int ret;
  349. need_fence =
  350. has_fenced_gpu_access &&
  351. entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
  352. obj->tiling_mode != I915_TILING_NONE;
  353. need_mappable = need_fence || need_reloc_mappable(obj);
  354. ret = i915_gem_object_pin(obj, entry->alignment, need_mappable, false);
  355. if (ret)
  356. return ret;
  357. entry->flags |= __EXEC_OBJECT_HAS_PIN;
  358. if (has_fenced_gpu_access) {
  359. if (entry->flags & EXEC_OBJECT_NEEDS_FENCE) {
  360. ret = i915_gem_object_get_fence(obj);
  361. if (ret)
  362. return ret;
  363. if (i915_gem_object_pin_fence(obj))
  364. entry->flags |= __EXEC_OBJECT_HAS_FENCE;
  365. obj->pending_fenced_gpu_access = true;
  366. }
  367. }
  368. /* Ensure ppgtt mapping exists if needed */
  369. if (dev_priv->mm.aliasing_ppgtt && !obj->has_aliasing_ppgtt_mapping) {
  370. i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt,
  371. obj, obj->cache_level);
  372. obj->has_aliasing_ppgtt_mapping = 1;
  373. }
  374. if (entry->offset != obj->gtt_offset) {
  375. entry->offset = obj->gtt_offset;
  376. *need_reloc = true;
  377. }
  378. if (entry->flags & EXEC_OBJECT_WRITE) {
  379. obj->base.pending_read_domains = I915_GEM_DOMAIN_RENDER;
  380. obj->base.pending_write_domain = I915_GEM_DOMAIN_RENDER;
  381. }
  382. if (entry->flags & EXEC_OBJECT_NEEDS_GTT &&
  383. !obj->has_global_gtt_mapping)
  384. i915_gem_gtt_bind_object(obj, obj->cache_level);
  385. return 0;
  386. }
  387. static void
  388. i915_gem_execbuffer_unreserve_object(struct drm_i915_gem_object *obj)
  389. {
  390. struct drm_i915_gem_exec_object2 *entry;
  391. if (!obj->gtt_space)
  392. return;
  393. entry = obj->exec_entry;
  394. if (entry->flags & __EXEC_OBJECT_HAS_FENCE)
  395. i915_gem_object_unpin_fence(obj);
  396. if (entry->flags & __EXEC_OBJECT_HAS_PIN)
  397. i915_gem_object_unpin(obj);
  398. entry->flags &= ~(__EXEC_OBJECT_HAS_FENCE | __EXEC_OBJECT_HAS_PIN);
  399. }
  400. static int
  401. i915_gem_execbuffer_reserve(struct intel_ring_buffer *ring,
  402. struct list_head *objects,
  403. bool *need_relocs)
  404. {
  405. struct drm_i915_gem_object *obj;
  406. struct list_head ordered_objects;
  407. bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4;
  408. int retry;
  409. INIT_LIST_HEAD(&ordered_objects);
  410. while (!list_empty(objects)) {
  411. struct drm_i915_gem_exec_object2 *entry;
  412. bool need_fence, need_mappable;
  413. obj = list_first_entry(objects,
  414. struct drm_i915_gem_object,
  415. exec_list);
  416. entry = obj->exec_entry;
  417. need_fence =
  418. has_fenced_gpu_access &&
  419. entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
  420. obj->tiling_mode != I915_TILING_NONE;
  421. need_mappable = need_fence || need_reloc_mappable(obj);
  422. if (need_mappable)
  423. list_move(&obj->exec_list, &ordered_objects);
  424. else
  425. list_move_tail(&obj->exec_list, &ordered_objects);
  426. obj->base.pending_read_domains = I915_GEM_GPU_DOMAINS & ~I915_GEM_DOMAIN_COMMAND;
  427. obj->base.pending_write_domain = 0;
  428. obj->pending_fenced_gpu_access = false;
  429. }
  430. list_splice(&ordered_objects, objects);
  431. /* Attempt to pin all of the buffers into the GTT.
  432. * This is done in 3 phases:
  433. *
  434. * 1a. Unbind all objects that do not match the GTT constraints for
  435. * the execbuffer (fenceable, mappable, alignment etc).
  436. * 1b. Increment pin count for already bound objects.
  437. * 2. Bind new objects.
  438. * 3. Decrement pin count.
  439. *
  440. * This avoid unnecessary unbinding of later objects in order to make
  441. * room for the earlier objects *unless* we need to defragment.
  442. */
  443. retry = 0;
  444. do {
  445. int ret = 0;
  446. /* Unbind any ill-fitting objects or pin. */
  447. list_for_each_entry(obj, objects, exec_list) {
  448. struct drm_i915_gem_exec_object2 *entry = obj->exec_entry;
  449. bool need_fence, need_mappable;
  450. if (!obj->gtt_space)
  451. continue;
  452. need_fence =
  453. has_fenced_gpu_access &&
  454. entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
  455. obj->tiling_mode != I915_TILING_NONE;
  456. need_mappable = need_fence || need_reloc_mappable(obj);
  457. if ((entry->alignment && obj->gtt_offset & (entry->alignment - 1)) ||
  458. (need_mappable && !obj->map_and_fenceable))
  459. ret = i915_gem_object_unbind(obj);
  460. else
  461. ret = i915_gem_execbuffer_reserve_object(obj, ring, need_relocs);
  462. if (ret)
  463. goto err;
  464. }
  465. /* Bind fresh objects */
  466. list_for_each_entry(obj, objects, exec_list) {
  467. if (obj->gtt_space)
  468. continue;
  469. ret = i915_gem_execbuffer_reserve_object(obj, ring, need_relocs);
  470. if (ret)
  471. goto err;
  472. }
  473. err: /* Decrement pin count for bound objects */
  474. list_for_each_entry(obj, objects, exec_list)
  475. i915_gem_execbuffer_unreserve_object(obj);
  476. if (ret != -ENOSPC || retry++)
  477. return ret;
  478. ret = i915_gem_evict_everything(ring->dev);
  479. if (ret)
  480. return ret;
  481. } while (1);
  482. }
  483. static int
  484. i915_gem_execbuffer_relocate_slow(struct drm_device *dev,
  485. struct drm_i915_gem_execbuffer2 *args,
  486. struct drm_file *file,
  487. struct intel_ring_buffer *ring,
  488. struct eb_objects *eb,
  489. struct drm_i915_gem_exec_object2 *exec)
  490. {
  491. struct drm_i915_gem_relocation_entry *reloc;
  492. struct drm_i915_gem_object *obj;
  493. bool need_relocs;
  494. int *reloc_offset;
  495. int i, total, ret;
  496. int count = args->buffer_count;
  497. /* We may process another execbuffer during the unlock... */
  498. while (!list_empty(&eb->objects)) {
  499. obj = list_first_entry(&eb->objects,
  500. struct drm_i915_gem_object,
  501. exec_list);
  502. list_del_init(&obj->exec_list);
  503. drm_gem_object_unreference(&obj->base);
  504. }
  505. mutex_unlock(&dev->struct_mutex);
  506. total = 0;
  507. for (i = 0; i < count; i++)
  508. total += exec[i].relocation_count;
  509. reloc_offset = drm_malloc_ab(count, sizeof(*reloc_offset));
  510. reloc = drm_malloc_ab(total, sizeof(*reloc));
  511. if (reloc == NULL || reloc_offset == NULL) {
  512. drm_free_large(reloc);
  513. drm_free_large(reloc_offset);
  514. mutex_lock(&dev->struct_mutex);
  515. return -ENOMEM;
  516. }
  517. total = 0;
  518. for (i = 0; i < count; i++) {
  519. struct drm_i915_gem_relocation_entry __user *user_relocs;
  520. u64 invalid_offset = (u64)-1;
  521. int j;
  522. user_relocs = to_user_ptr(exec[i].relocs_ptr);
  523. if (copy_from_user(reloc+total, user_relocs,
  524. exec[i].relocation_count * sizeof(*reloc))) {
  525. ret = -EFAULT;
  526. mutex_lock(&dev->struct_mutex);
  527. goto err;
  528. }
  529. /* As we do not update the known relocation offsets after
  530. * relocating (due to the complexities in lock handling),
  531. * we need to mark them as invalid now so that we force the
  532. * relocation processing next time. Just in case the target
  533. * object is evicted and then rebound into its old
  534. * presumed_offset before the next execbuffer - if that
  535. * happened we would make the mistake of assuming that the
  536. * relocations were valid.
  537. */
  538. for (j = 0; j < exec[i].relocation_count; j++) {
  539. if (copy_to_user(&user_relocs[j].presumed_offset,
  540. &invalid_offset,
  541. sizeof(invalid_offset))) {
  542. ret = -EFAULT;
  543. mutex_lock(&dev->struct_mutex);
  544. goto err;
  545. }
  546. }
  547. reloc_offset[i] = total;
  548. total += exec[i].relocation_count;
  549. }
  550. ret = i915_mutex_lock_interruptible(dev);
  551. if (ret) {
  552. mutex_lock(&dev->struct_mutex);
  553. goto err;
  554. }
  555. /* reacquire the objects */
  556. eb_reset(eb);
  557. ret = eb_lookup_objects(eb, exec, args, file);
  558. if (ret)
  559. goto err;
  560. need_relocs = (args->flags & I915_EXEC_NO_RELOC) == 0;
  561. ret = i915_gem_execbuffer_reserve(ring, &eb->objects, &need_relocs);
  562. if (ret)
  563. goto err;
  564. list_for_each_entry(obj, &eb->objects, exec_list) {
  565. int offset = obj->exec_entry - exec;
  566. ret = i915_gem_execbuffer_relocate_object_slow(obj, eb,
  567. reloc + reloc_offset[offset]);
  568. if (ret)
  569. goto err;
  570. }
  571. /* Leave the user relocations as are, this is the painfully slow path,
  572. * and we want to avoid the complication of dropping the lock whilst
  573. * having buffers reserved in the aperture and so causing spurious
  574. * ENOSPC for random operations.
  575. */
  576. err:
  577. drm_free_large(reloc);
  578. drm_free_large(reloc_offset);
  579. return ret;
  580. }
  581. static int
  582. i915_gem_execbuffer_move_to_gpu(struct intel_ring_buffer *ring,
  583. struct list_head *objects)
  584. {
  585. struct drm_i915_gem_object *obj;
  586. uint32_t flush_domains = 0;
  587. int ret;
  588. list_for_each_entry(obj, objects, exec_list) {
  589. ret = i915_gem_object_sync(obj, ring);
  590. if (ret)
  591. return ret;
  592. if (obj->base.write_domain & I915_GEM_DOMAIN_CPU)
  593. i915_gem_clflush_object(obj);
  594. flush_domains |= obj->base.write_domain;
  595. }
  596. if (flush_domains & I915_GEM_DOMAIN_CPU)
  597. i915_gem_chipset_flush(ring->dev);
  598. if (flush_domains & I915_GEM_DOMAIN_GTT)
  599. wmb();
  600. /* Unconditionally invalidate gpu caches and ensure that we do flush
  601. * any residual writes from the previous batch.
  602. */
  603. return intel_ring_invalidate_all_caches(ring);
  604. }
  605. static bool
  606. i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec)
  607. {
  608. if (exec->flags & __I915_EXEC_UNKNOWN_FLAGS)
  609. return false;
  610. return ((exec->batch_start_offset | exec->batch_len) & 0x7) == 0;
  611. }
  612. static int
  613. validate_exec_list(struct drm_i915_gem_exec_object2 *exec,
  614. int count)
  615. {
  616. int i;
  617. int relocs_total = 0;
  618. int relocs_max = INT_MAX / sizeof(struct drm_i915_gem_relocation_entry);
  619. for (i = 0; i < count; i++) {
  620. char __user *ptr = to_user_ptr(exec[i].relocs_ptr);
  621. int length; /* limited by fault_in_pages_readable() */
  622. if (exec[i].flags & __EXEC_OBJECT_UNKNOWN_FLAGS)
  623. return -EINVAL;
  624. /* First check for malicious input causing overflow in
  625. * the worst case where we need to allocate the entire
  626. * relocation tree as a single array.
  627. */
  628. if (exec[i].relocation_count > relocs_max - relocs_total)
  629. return -EINVAL;
  630. relocs_total += exec[i].relocation_count;
  631. length = exec[i].relocation_count *
  632. sizeof(struct drm_i915_gem_relocation_entry);
  633. /*
  634. * We must check that the entire relocation array is safe
  635. * to read, but since we may need to update the presumed
  636. * offsets during execution, check for full write access.
  637. */
  638. if (!access_ok(VERIFY_WRITE, ptr, length))
  639. return -EFAULT;
  640. if (fault_in_multipages_readable(ptr, length))
  641. return -EFAULT;
  642. }
  643. return 0;
  644. }
  645. static void
  646. i915_gem_execbuffer_move_to_active(struct list_head *objects,
  647. struct intel_ring_buffer *ring)
  648. {
  649. struct drm_i915_gem_object *obj;
  650. list_for_each_entry(obj, objects, exec_list) {
  651. u32 old_read = obj->base.read_domains;
  652. u32 old_write = obj->base.write_domain;
  653. obj->base.write_domain = obj->base.pending_write_domain;
  654. if (obj->base.write_domain == 0)
  655. obj->base.pending_read_domains |= obj->base.read_domains;
  656. obj->base.read_domains = obj->base.pending_read_domains;
  657. obj->fenced_gpu_access = obj->pending_fenced_gpu_access;
  658. i915_gem_object_move_to_active(obj, ring);
  659. if (obj->base.write_domain) {
  660. obj->dirty = 1;
  661. obj->last_write_seqno = intel_ring_get_seqno(ring);
  662. if (obj->pin_count) /* check for potential scanout */
  663. intel_mark_fb_busy(obj, ring);
  664. }
  665. trace_i915_gem_object_change_domain(obj, old_read, old_write);
  666. }
  667. }
  668. static void
  669. i915_gem_execbuffer_retire_commands(struct drm_device *dev,
  670. struct drm_file *file,
  671. struct intel_ring_buffer *ring,
  672. struct drm_i915_gem_object *obj)
  673. {
  674. /* Unconditionally force add_request to emit a full flush. */
  675. ring->gpu_caches_dirty = true;
  676. /* Add a breadcrumb for the completion of the batch buffer */
  677. (void)__i915_add_request(ring, file, obj, NULL);
  678. }
  679. static int
  680. i915_reset_gen7_sol_offsets(struct drm_device *dev,
  681. struct intel_ring_buffer *ring)
  682. {
  683. drm_i915_private_t *dev_priv = dev->dev_private;
  684. int ret, i;
  685. if (!IS_GEN7(dev) || ring != &dev_priv->ring[RCS])
  686. return 0;
  687. ret = intel_ring_begin(ring, 4 * 3);
  688. if (ret)
  689. return ret;
  690. for (i = 0; i < 4; i++) {
  691. intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
  692. intel_ring_emit(ring, GEN7_SO_WRITE_OFFSET(i));
  693. intel_ring_emit(ring, 0);
  694. }
  695. intel_ring_advance(ring);
  696. return 0;
  697. }
  698. static int
  699. i915_gem_do_execbuffer(struct drm_device *dev, void *data,
  700. struct drm_file *file,
  701. struct drm_i915_gem_execbuffer2 *args,
  702. struct drm_i915_gem_exec_object2 *exec)
  703. {
  704. drm_i915_private_t *dev_priv = dev->dev_private;
  705. struct eb_objects *eb;
  706. struct drm_i915_gem_object *batch_obj;
  707. struct drm_clip_rect *cliprects = NULL;
  708. struct intel_ring_buffer *ring;
  709. u32 ctx_id = i915_execbuffer2_get_context_id(*args);
  710. u32 exec_start, exec_len;
  711. u32 mask, flags;
  712. int ret, mode, i;
  713. bool need_relocs;
  714. if (!i915_gem_check_execbuffer(args))
  715. return -EINVAL;
  716. ret = validate_exec_list(exec, args->buffer_count);
  717. if (ret)
  718. return ret;
  719. flags = 0;
  720. if (args->flags & I915_EXEC_SECURE) {
  721. if (!file->is_master || !capable(CAP_SYS_ADMIN))
  722. return -EPERM;
  723. flags |= I915_DISPATCH_SECURE;
  724. }
  725. if (args->flags & I915_EXEC_IS_PINNED)
  726. flags |= I915_DISPATCH_PINNED;
  727. switch (args->flags & I915_EXEC_RING_MASK) {
  728. case I915_EXEC_DEFAULT:
  729. case I915_EXEC_RENDER:
  730. ring = &dev_priv->ring[RCS];
  731. break;
  732. case I915_EXEC_BSD:
  733. ring = &dev_priv->ring[VCS];
  734. if (ctx_id != 0) {
  735. DRM_DEBUG("Ring %s doesn't support contexts\n",
  736. ring->name);
  737. return -EPERM;
  738. }
  739. break;
  740. case I915_EXEC_BLT:
  741. ring = &dev_priv->ring[BCS];
  742. if (ctx_id != 0) {
  743. DRM_DEBUG("Ring %s doesn't support contexts\n",
  744. ring->name);
  745. return -EPERM;
  746. }
  747. break;
  748. case I915_EXEC_VEBOX:
  749. ring = &dev_priv->ring[VECS];
  750. if (ctx_id != 0) {
  751. DRM_DEBUG("Ring %s doesn't support contexts\n",
  752. ring->name);
  753. return -EPERM;
  754. }
  755. break;
  756. default:
  757. DRM_DEBUG("execbuf with unknown ring: %d\n",
  758. (int)(args->flags & I915_EXEC_RING_MASK));
  759. return -EINVAL;
  760. }
  761. if (!intel_ring_initialized(ring)) {
  762. DRM_DEBUG("execbuf with invalid ring: %d\n",
  763. (int)(args->flags & I915_EXEC_RING_MASK));
  764. return -EINVAL;
  765. }
  766. mode = args->flags & I915_EXEC_CONSTANTS_MASK;
  767. mask = I915_EXEC_CONSTANTS_MASK;
  768. switch (mode) {
  769. case I915_EXEC_CONSTANTS_REL_GENERAL:
  770. case I915_EXEC_CONSTANTS_ABSOLUTE:
  771. case I915_EXEC_CONSTANTS_REL_SURFACE:
  772. if (ring == &dev_priv->ring[RCS] &&
  773. mode != dev_priv->relative_constants_mode) {
  774. if (INTEL_INFO(dev)->gen < 4)
  775. return -EINVAL;
  776. if (INTEL_INFO(dev)->gen > 5 &&
  777. mode == I915_EXEC_CONSTANTS_REL_SURFACE)
  778. return -EINVAL;
  779. /* The HW changed the meaning on this bit on gen6 */
  780. if (INTEL_INFO(dev)->gen >= 6)
  781. mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE;
  782. }
  783. break;
  784. default:
  785. DRM_DEBUG("execbuf with unknown constants: %d\n", mode);
  786. return -EINVAL;
  787. }
  788. if (args->buffer_count < 1) {
  789. DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count);
  790. return -EINVAL;
  791. }
  792. if (args->num_cliprects != 0) {
  793. if (ring != &dev_priv->ring[RCS]) {
  794. DRM_DEBUG("clip rectangles are only valid with the render ring\n");
  795. return -EINVAL;
  796. }
  797. if (INTEL_INFO(dev)->gen >= 5) {
  798. DRM_DEBUG("clip rectangles are only valid on pre-gen5\n");
  799. return -EINVAL;
  800. }
  801. if (args->num_cliprects > UINT_MAX / sizeof(*cliprects)) {
  802. DRM_DEBUG("execbuf with %u cliprects\n",
  803. args->num_cliprects);
  804. return -EINVAL;
  805. }
  806. cliprects = kmalloc(args->num_cliprects * sizeof(*cliprects),
  807. GFP_KERNEL);
  808. if (cliprects == NULL) {
  809. ret = -ENOMEM;
  810. goto pre_mutex_err;
  811. }
  812. if (copy_from_user(cliprects,
  813. to_user_ptr(args->cliprects_ptr),
  814. sizeof(*cliprects)*args->num_cliprects)) {
  815. ret = -EFAULT;
  816. goto pre_mutex_err;
  817. }
  818. }
  819. ret = i915_mutex_lock_interruptible(dev);
  820. if (ret)
  821. goto pre_mutex_err;
  822. if (dev_priv->mm.suspended) {
  823. mutex_unlock(&dev->struct_mutex);
  824. ret = -EBUSY;
  825. goto pre_mutex_err;
  826. }
  827. eb = eb_create(args);
  828. if (eb == NULL) {
  829. mutex_unlock(&dev->struct_mutex);
  830. ret = -ENOMEM;
  831. goto pre_mutex_err;
  832. }
  833. /* Look up object handles */
  834. ret = eb_lookup_objects(eb, exec, args, file);
  835. if (ret)
  836. goto err;
  837. /* take note of the batch buffer before we might reorder the lists */
  838. batch_obj = list_entry(eb->objects.prev,
  839. struct drm_i915_gem_object,
  840. exec_list);
  841. /* Move the objects en-masse into the GTT, evicting if necessary. */
  842. need_relocs = (args->flags & I915_EXEC_NO_RELOC) == 0;
  843. ret = i915_gem_execbuffer_reserve(ring, &eb->objects, &need_relocs);
  844. if (ret)
  845. goto err;
  846. /* The objects are in their final locations, apply the relocations. */
  847. if (need_relocs)
  848. ret = i915_gem_execbuffer_relocate(eb);
  849. if (ret) {
  850. if (ret == -EFAULT) {
  851. ret = i915_gem_execbuffer_relocate_slow(dev, args, file, ring,
  852. eb, exec);
  853. BUG_ON(!mutex_is_locked(&dev->struct_mutex));
  854. }
  855. if (ret)
  856. goto err;
  857. }
  858. /* Set the pending read domains for the batch buffer to COMMAND */
  859. if (batch_obj->base.pending_write_domain) {
  860. DRM_DEBUG("Attempting to use self-modifying batch buffer\n");
  861. ret = -EINVAL;
  862. goto err;
  863. }
  864. batch_obj->base.pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
  865. /* snb/ivb/vlv conflate the "batch in ppgtt" bit with the "non-secure
  866. * batch" bit. Hence we need to pin secure batches into the global gtt.
  867. * hsw should have this fixed, but let's be paranoid and do it
  868. * unconditionally for now. */
  869. if (flags & I915_DISPATCH_SECURE && !batch_obj->has_global_gtt_mapping)
  870. i915_gem_gtt_bind_object(batch_obj, batch_obj->cache_level);
  871. ret = i915_gem_execbuffer_move_to_gpu(ring, &eb->objects);
  872. if (ret)
  873. goto err;
  874. ret = i915_switch_context(ring, file, ctx_id);
  875. if (ret)
  876. goto err;
  877. if (ring == &dev_priv->ring[RCS] &&
  878. mode != dev_priv->relative_constants_mode) {
  879. ret = intel_ring_begin(ring, 4);
  880. if (ret)
  881. goto err;
  882. intel_ring_emit(ring, MI_NOOP);
  883. intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
  884. intel_ring_emit(ring, INSTPM);
  885. intel_ring_emit(ring, mask << 16 | mode);
  886. intel_ring_advance(ring);
  887. dev_priv->relative_constants_mode = mode;
  888. }
  889. if (args->flags & I915_EXEC_GEN7_SOL_RESET) {
  890. ret = i915_reset_gen7_sol_offsets(dev, ring);
  891. if (ret)
  892. goto err;
  893. }
  894. exec_start = batch_obj->gtt_offset + args->batch_start_offset;
  895. exec_len = args->batch_len;
  896. if (cliprects) {
  897. for (i = 0; i < args->num_cliprects; i++) {
  898. ret = i915_emit_box(dev, &cliprects[i],
  899. args->DR1, args->DR4);
  900. if (ret)
  901. goto err;
  902. ret = ring->dispatch_execbuffer(ring,
  903. exec_start, exec_len,
  904. flags);
  905. if (ret)
  906. goto err;
  907. }
  908. } else {
  909. ret = ring->dispatch_execbuffer(ring,
  910. exec_start, exec_len,
  911. flags);
  912. if (ret)
  913. goto err;
  914. }
  915. trace_i915_gem_ring_dispatch(ring, intel_ring_get_seqno(ring), flags);
  916. i915_gem_execbuffer_move_to_active(&eb->objects, ring);
  917. i915_gem_execbuffer_retire_commands(dev, file, ring, batch_obj);
  918. err:
  919. eb_destroy(eb);
  920. mutex_unlock(&dev->struct_mutex);
  921. pre_mutex_err:
  922. kfree(cliprects);
  923. return ret;
  924. }
  925. /*
  926. * Legacy execbuffer just creates an exec2 list from the original exec object
  927. * list array and passes it to the real function.
  928. */
  929. int
  930. i915_gem_execbuffer(struct drm_device *dev, void *data,
  931. struct drm_file *file)
  932. {
  933. struct drm_i915_gem_execbuffer *args = data;
  934. struct drm_i915_gem_execbuffer2 exec2;
  935. struct drm_i915_gem_exec_object *exec_list = NULL;
  936. struct drm_i915_gem_exec_object2 *exec2_list = NULL;
  937. int ret, i;
  938. if (args->buffer_count < 1) {
  939. DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count);
  940. return -EINVAL;
  941. }
  942. /* Copy in the exec list from userland */
  943. exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count);
  944. exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
  945. if (exec_list == NULL || exec2_list == NULL) {
  946. DRM_DEBUG("Failed to allocate exec list for %d buffers\n",
  947. args->buffer_count);
  948. drm_free_large(exec_list);
  949. drm_free_large(exec2_list);
  950. return -ENOMEM;
  951. }
  952. ret = copy_from_user(exec_list,
  953. to_user_ptr(args->buffers_ptr),
  954. sizeof(*exec_list) * args->buffer_count);
  955. if (ret != 0) {
  956. DRM_DEBUG("copy %d exec entries failed %d\n",
  957. args->buffer_count, ret);
  958. drm_free_large(exec_list);
  959. drm_free_large(exec2_list);
  960. return -EFAULT;
  961. }
  962. for (i = 0; i < args->buffer_count; i++) {
  963. exec2_list[i].handle = exec_list[i].handle;
  964. exec2_list[i].relocation_count = exec_list[i].relocation_count;
  965. exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr;
  966. exec2_list[i].alignment = exec_list[i].alignment;
  967. exec2_list[i].offset = exec_list[i].offset;
  968. if (INTEL_INFO(dev)->gen < 4)
  969. exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE;
  970. else
  971. exec2_list[i].flags = 0;
  972. }
  973. exec2.buffers_ptr = args->buffers_ptr;
  974. exec2.buffer_count = args->buffer_count;
  975. exec2.batch_start_offset = args->batch_start_offset;
  976. exec2.batch_len = args->batch_len;
  977. exec2.DR1 = args->DR1;
  978. exec2.DR4 = args->DR4;
  979. exec2.num_cliprects = args->num_cliprects;
  980. exec2.cliprects_ptr = args->cliprects_ptr;
  981. exec2.flags = I915_EXEC_RENDER;
  982. i915_execbuffer2_set_context_id(exec2, 0);
  983. ret = i915_gem_do_execbuffer(dev, data, file, &exec2, exec2_list);
  984. if (!ret) {
  985. /* Copy the new buffer offsets back to the user's exec list. */
  986. for (i = 0; i < args->buffer_count; i++)
  987. exec_list[i].offset = exec2_list[i].offset;
  988. /* ... and back out to userspace */
  989. ret = copy_to_user(to_user_ptr(args->buffers_ptr),
  990. exec_list,
  991. sizeof(*exec_list) * args->buffer_count);
  992. if (ret) {
  993. ret = -EFAULT;
  994. DRM_DEBUG("failed to copy %d exec entries "
  995. "back to user (%d)\n",
  996. args->buffer_count, ret);
  997. }
  998. }
  999. drm_free_large(exec_list);
  1000. drm_free_large(exec2_list);
  1001. return ret;
  1002. }
  1003. int
  1004. i915_gem_execbuffer2(struct drm_device *dev, void *data,
  1005. struct drm_file *file)
  1006. {
  1007. struct drm_i915_gem_execbuffer2 *args = data;
  1008. struct drm_i915_gem_exec_object2 *exec2_list = NULL;
  1009. int ret;
  1010. if (args->buffer_count < 1 ||
  1011. args->buffer_count > UINT_MAX / sizeof(*exec2_list)) {
  1012. DRM_DEBUG("execbuf2 with %d buffers\n", args->buffer_count);
  1013. return -EINVAL;
  1014. }
  1015. exec2_list = kmalloc(sizeof(*exec2_list)*args->buffer_count,
  1016. GFP_TEMPORARY | __GFP_NOWARN | __GFP_NORETRY);
  1017. if (exec2_list == NULL)
  1018. exec2_list = drm_malloc_ab(sizeof(*exec2_list),
  1019. args->buffer_count);
  1020. if (exec2_list == NULL) {
  1021. DRM_DEBUG("Failed to allocate exec list for %d buffers\n",
  1022. args->buffer_count);
  1023. return -ENOMEM;
  1024. }
  1025. ret = copy_from_user(exec2_list,
  1026. to_user_ptr(args->buffers_ptr),
  1027. sizeof(*exec2_list) * args->buffer_count);
  1028. if (ret != 0) {
  1029. DRM_DEBUG("copy %d exec entries failed %d\n",
  1030. args->buffer_count, ret);
  1031. drm_free_large(exec2_list);
  1032. return -EFAULT;
  1033. }
  1034. ret = i915_gem_do_execbuffer(dev, data, file, args, exec2_list);
  1035. if (!ret) {
  1036. /* Copy the new buffer offsets back to the user's exec list. */
  1037. ret = copy_to_user(to_user_ptr(args->buffers_ptr),
  1038. exec2_list,
  1039. sizeof(*exec2_list) * args->buffer_count);
  1040. if (ret) {
  1041. ret = -EFAULT;
  1042. DRM_DEBUG("failed to copy %d exec entries "
  1043. "back to user (%d)\n",
  1044. args->buffer_count, ret);
  1045. }
  1046. }
  1047. drm_free_large(exec2_list);
  1048. return ret;
  1049. }