at91sam9n12.dtsi 11 KB

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  1. /*
  2. * at91sam9n12.dtsi - Device Tree include file for AT91SAM9N12 SoC
  3. *
  4. * Copyright (C) 2012 Atmel,
  5. * 2012 Hong Xu <hong.xu@atmel.com>
  6. *
  7. * Licensed under GPLv2 or later.
  8. */
  9. /include/ "skeleton.dtsi"
  10. / {
  11. model = "Atmel AT91SAM9N12 SoC";
  12. compatible = "atmel,at91sam9n12";
  13. interrupt-parent = <&aic>;
  14. aliases {
  15. serial0 = &dbgu;
  16. serial1 = &usart0;
  17. serial2 = &usart1;
  18. serial3 = &usart2;
  19. serial4 = &usart3;
  20. gpio0 = &pioA;
  21. gpio1 = &pioB;
  22. gpio2 = &pioC;
  23. gpio3 = &pioD;
  24. tcb0 = &tcb0;
  25. tcb1 = &tcb1;
  26. i2c0 = &i2c0;
  27. i2c1 = &i2c1;
  28. ssc0 = &ssc0;
  29. };
  30. cpus {
  31. cpu@0 {
  32. compatible = "arm,arm926ejs";
  33. };
  34. };
  35. memory {
  36. reg = <0x20000000 0x10000000>;
  37. };
  38. ahb {
  39. compatible = "simple-bus";
  40. #address-cells = <1>;
  41. #size-cells = <1>;
  42. ranges;
  43. apb {
  44. compatible = "simple-bus";
  45. #address-cells = <1>;
  46. #size-cells = <1>;
  47. ranges;
  48. aic: interrupt-controller@fffff000 {
  49. #interrupt-cells = <3>;
  50. compatible = "atmel,at91rm9200-aic";
  51. interrupt-controller;
  52. reg = <0xfffff000 0x200>;
  53. atmel,external-irqs = <31>;
  54. };
  55. ramc0: ramc@ffffe800 {
  56. compatible = "atmel,at91sam9g45-ddramc";
  57. reg = <0xffffe800 0x200>;
  58. };
  59. pmc: pmc@fffffc00 {
  60. compatible = "atmel,at91rm9200-pmc";
  61. reg = <0xfffffc00 0x100>;
  62. };
  63. rstc@fffffe00 {
  64. compatible = "atmel,at91sam9g45-rstc";
  65. reg = <0xfffffe00 0x10>;
  66. };
  67. pit: timer@fffffe30 {
  68. compatible = "atmel,at91sam9260-pit";
  69. reg = <0xfffffe30 0xf>;
  70. interrupts = <1 4 7>;
  71. };
  72. shdwc@fffffe10 {
  73. compatible = "atmel,at91sam9x5-shdwc";
  74. reg = <0xfffffe10 0x10>;
  75. };
  76. mmc0: mmc@f0008000 {
  77. compatible = "atmel,hsmci";
  78. reg = <0xf0008000 0x600>;
  79. interrupts = <12 4 0>;
  80. dmas = <&dma 1 0>;
  81. dma-names = "rxtx";
  82. #address-cells = <1>;
  83. #size-cells = <0>;
  84. status = "disabled";
  85. };
  86. tcb0: timer@f8008000 {
  87. compatible = "atmel,at91sam9x5-tcb";
  88. reg = <0xf8008000 0x100>;
  89. interrupts = <17 4 0>;
  90. };
  91. tcb1: timer@f800c000 {
  92. compatible = "atmel,at91sam9x5-tcb";
  93. reg = <0xf800c000 0x100>;
  94. interrupts = <17 4 0>;
  95. };
  96. dma: dma-controller@ffffec00 {
  97. compatible = "atmel,at91sam9g45-dma";
  98. reg = <0xffffec00 0x200>;
  99. interrupts = <20 4 0>;
  100. #dma-cells = <2>;
  101. };
  102. pinctrl@fffff400 {
  103. #address-cells = <1>;
  104. #size-cells = <1>;
  105. compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
  106. ranges = <0xfffff400 0xfffff400 0x800>;
  107. atmel,mux-mask = <
  108. /* A B C */
  109. 0xffffffff 0xffe07983 0x00000000 /* pioA */
  110. 0x00040000 0x00047e0f 0x00000000 /* pioB */
  111. 0xfdffffff 0x07c00000 0xb83fffff /* pioC */
  112. 0x003fffff 0x003f8000 0x00000000 /* pioD */
  113. >;
  114. /* shared pinctrl settings */
  115. dbgu {
  116. pinctrl_dbgu: dbgu-0 {
  117. atmel,pins =
  118. <0 9 0x1 0x0 /* PA9 periph A */
  119. 0 10 0x1 0x1>; /* PA10 periph with pullup */
  120. };
  121. };
  122. usart0 {
  123. pinctrl_usart0: usart0-0 {
  124. atmel,pins =
  125. <0 1 0x1 0x1 /* PA1 periph A with pullup */
  126. 0 0 0x1 0x0>; /* PA0 periph A */
  127. };
  128. pinctrl_usart0_rts: usart0_rts-0 {
  129. atmel,pins =
  130. <0 2 0x1 0x0>; /* PA2 periph A */
  131. };
  132. pinctrl_usart0_cts: usart0_cts-0 {
  133. atmel,pins =
  134. <0 3 0x1 0x0>; /* PA3 periph A */
  135. };
  136. };
  137. usart1 {
  138. pinctrl_usart1: usart1-0 {
  139. atmel,pins =
  140. <0 6 0x1 0x1 /* PA6 periph A with pullup */
  141. 0 5 0x1 0x0>; /* PA5 periph A */
  142. };
  143. };
  144. usart2 {
  145. pinctrl_usart2: usart2-0 {
  146. atmel,pins =
  147. <0 8 0x1 0x1 /* PA8 periph A with pullup */
  148. 0 7 0x1 0x0>; /* PA7 periph A */
  149. };
  150. pinctrl_usart2_rts: usart2_rts-0 {
  151. atmel,pins =
  152. <1 0 0x2 0x0>; /* PB0 periph B */
  153. };
  154. pinctrl_usart2_cts: usart2_cts-0 {
  155. atmel,pins =
  156. <1 1 0x2 0x0>; /* PB1 periph B */
  157. };
  158. };
  159. usart3 {
  160. pinctrl_usart3: usart3-0 {
  161. atmel,pins =
  162. <2 23 0x2 0x1 /* PC23 periph B with pullup */
  163. 2 22 0x2 0x0>; /* PC22 periph B */
  164. };
  165. pinctrl_usart3_rts: usart3_rts-0 {
  166. atmel,pins =
  167. <2 24 0x2 0x0>; /* PC24 periph B */
  168. };
  169. pinctrl_usart3_cts: usart3_cts-0 {
  170. atmel,pins =
  171. <2 25 0x2 0x0>; /* PC25 periph B */
  172. };
  173. };
  174. uart0 {
  175. pinctrl_uart0: uart0-0 {
  176. atmel,pins =
  177. <2 9 0x3 0x1 /* PC9 periph C with pullup */
  178. 2 8 0x3 0x0>; /* PC8 periph C */
  179. };
  180. };
  181. uart1 {
  182. pinctrl_uart1: uart1-0 {
  183. atmel,pins =
  184. <2 16 0x3 0x1 /* PC17 periph C with pullup */
  185. 2 17 0x3 0x0>; /* PC16 periph C */
  186. };
  187. };
  188. nand {
  189. pinctrl_nand: nand-0 {
  190. atmel,pins =
  191. <3 5 0x0 0x1 /* PD5 gpio RDY pin pull_up*/
  192. 3 4 0x0 0x1>; /* PD4 gpio enable pin pull_up */
  193. };
  194. };
  195. mmc0 {
  196. pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {
  197. atmel,pins =
  198. <0 17 0x1 0x0 /* PA17 periph A */
  199. 0 16 0x1 0x1 /* PA16 periph A with pullup */
  200. 0 15 0x1 0x1>; /* PA15 periph A with pullup */
  201. };
  202. pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
  203. atmel,pins =
  204. <0 18 0x1 0x1 /* PA18 periph A with pullup */
  205. 0 19 0x1 0x1 /* PA19 periph A with pullup */
  206. 0 20 0x1 0x1>; /* PA20 periph A with pullup */
  207. };
  208. pinctrl_mmc0_slot0_dat4_7: mmc0_slot0_dat4_7-0 {
  209. atmel,pins =
  210. <0 11 0x2 0x1 /* PA11 periph B with pullup */
  211. 0 12 0x2 0x1 /* PA12 periph B with pullup */
  212. 0 13 0x2 0x1 /* PA13 periph B with pullup */
  213. 0 14 0x2 0x1>; /* PA14 periph B with pullup */
  214. };
  215. };
  216. ssc0 {
  217. pinctrl_ssc0_tx: ssc0_tx-0 {
  218. atmel,pins =
  219. <0 24 0x2 0x0 /* PA24 periph B */
  220. 0 25 0x2 0x0 /* PA25 periph B */
  221. 0 26 0x2 0x0>; /* PA26 periph B */
  222. };
  223. pinctrl_ssc0_rx: ssc0_rx-0 {
  224. atmel,pins =
  225. <0 27 0x2 0x0 /* PA27 periph B */
  226. 0 28 0x2 0x0 /* PA28 periph B */
  227. 0 29 0x2 0x0>; /* PA29 periph B */
  228. };
  229. };
  230. spi0 {
  231. pinctrl_spi0: spi0-0 {
  232. atmel,pins =
  233. <0 11 0x1 0x0 /* PA11 periph A SPI0_MISO pin */
  234. 0 12 0x1 0x0 /* PA12 periph A SPI0_MOSI pin */
  235. 0 13 0x1 0x0>; /* PA13 periph A SPI0_SPCK pin */
  236. };
  237. };
  238. spi1 {
  239. pinctrl_spi1: spi1-0 {
  240. atmel,pins =
  241. <0 21 0x2 0x0 /* PA21 periph B SPI1_MISO pin */
  242. 0 22 0x2 0x0 /* PA22 periph B SPI1_MOSI pin */
  243. 0 23 0x2 0x0>; /* PA23 periph B SPI1_SPCK pin */
  244. };
  245. };
  246. pioA: gpio@fffff400 {
  247. compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
  248. reg = <0xfffff400 0x200>;
  249. interrupts = <2 4 1>;
  250. #gpio-cells = <2>;
  251. gpio-controller;
  252. interrupt-controller;
  253. #interrupt-cells = <2>;
  254. };
  255. pioB: gpio@fffff600 {
  256. compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
  257. reg = <0xfffff600 0x200>;
  258. interrupts = <2 4 1>;
  259. #gpio-cells = <2>;
  260. gpio-controller;
  261. interrupt-controller;
  262. #interrupt-cells = <2>;
  263. };
  264. pioC: gpio@fffff800 {
  265. compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
  266. reg = <0xfffff800 0x200>;
  267. interrupts = <3 4 1>;
  268. #gpio-cells = <2>;
  269. gpio-controller;
  270. interrupt-controller;
  271. #interrupt-cells = <2>;
  272. };
  273. pioD: gpio@fffffa00 {
  274. compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
  275. reg = <0xfffffa00 0x200>;
  276. interrupts = <3 4 1>;
  277. #gpio-cells = <2>;
  278. gpio-controller;
  279. interrupt-controller;
  280. #interrupt-cells = <2>;
  281. };
  282. };
  283. dbgu: serial@fffff200 {
  284. compatible = "atmel,at91sam9260-usart";
  285. reg = <0xfffff200 0x200>;
  286. interrupts = <1 4 7>;
  287. pinctrl-names = "default";
  288. pinctrl-0 = <&pinctrl_dbgu>;
  289. status = "disabled";
  290. };
  291. ssc0: ssc@f0010000 {
  292. compatible = "atmel,at91sam9g45-ssc";
  293. reg = <0xf0010000 0x4000>;
  294. interrupts = <28 4 5>;
  295. pinctrl-names = "default";
  296. pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
  297. status = "disabled";
  298. };
  299. usart0: serial@f801c000 {
  300. compatible = "atmel,at91sam9260-usart";
  301. reg = <0xf801c000 0x4000>;
  302. interrupts = <5 4 5>;
  303. pinctrl-names = "default";
  304. pinctrl-0 = <&pinctrl_usart0>;
  305. status = "disabled";
  306. };
  307. usart1: serial@f8020000 {
  308. compatible = "atmel,at91sam9260-usart";
  309. reg = <0xf8020000 0x4000>;
  310. interrupts = <6 4 5>;
  311. pinctrl-names = "default";
  312. pinctrl-0 = <&pinctrl_usart1>;
  313. status = "disabled";
  314. };
  315. usart2: serial@f8024000 {
  316. compatible = "atmel,at91sam9260-usart";
  317. reg = <0xf8024000 0x4000>;
  318. interrupts = <7 4 5>;
  319. pinctrl-names = "default";
  320. pinctrl-0 = <&pinctrl_usart2>;
  321. status = "disabled";
  322. };
  323. usart3: serial@f8028000 {
  324. compatible = "atmel,at91sam9260-usart";
  325. reg = <0xf8028000 0x4000>;
  326. interrupts = <8 4 5>;
  327. pinctrl-names = "default";
  328. pinctrl-0 = <&pinctrl_usart3>;
  329. status = "disabled";
  330. };
  331. i2c0: i2c@f8010000 {
  332. compatible = "atmel,at91sam9x5-i2c";
  333. reg = <0xf8010000 0x100>;
  334. interrupts = <9 4 6>;
  335. dmas = <&dma 1 13>,
  336. <&dma 1 14>;
  337. dma-names = "tx", "rx";
  338. #address-cells = <1>;
  339. #size-cells = <0>;
  340. status = "disabled";
  341. };
  342. i2c1: i2c@f8014000 {
  343. compatible = "atmel,at91sam9x5-i2c";
  344. reg = <0xf8014000 0x100>;
  345. interrupts = <10 4 6>;
  346. dmas = <&dma 1 15>,
  347. <&dma 1 16>;
  348. dma-names = "tx", "rx";
  349. #address-cells = <1>;
  350. #size-cells = <0>;
  351. status = "disabled";
  352. };
  353. spi0: spi@f0000000 {
  354. #address-cells = <1>;
  355. #size-cells = <0>;
  356. compatible = "atmel,at91rm9200-spi";
  357. reg = <0xf0000000 0x100>;
  358. interrupts = <13 4 3>;
  359. pinctrl-names = "default";
  360. pinctrl-0 = <&pinctrl_spi0>;
  361. status = "disabled";
  362. };
  363. spi1: spi@f0004000 {
  364. #address-cells = <1>;
  365. #size-cells = <0>;
  366. compatible = "atmel,at91rm9200-spi";
  367. reg = <0xf0004000 0x100>;
  368. interrupts = <14 4 3>;
  369. pinctrl-names = "default";
  370. pinctrl-0 = <&pinctrl_spi1>;
  371. status = "disabled";
  372. };
  373. };
  374. nand0: nand@40000000 {
  375. compatible = "atmel,at91rm9200-nand";
  376. #address-cells = <1>;
  377. #size-cells = <1>;
  378. reg = < 0x40000000 0x10000000
  379. 0xffffe000 0x00000600
  380. 0xffffe600 0x00000200
  381. 0x00108000 0x00018000
  382. >;
  383. atmel,pmecc-lookup-table-offset = <0x0 0x8000>;
  384. atmel,nand-addr-offset = <21>;
  385. atmel,nand-cmd-offset = <22>;
  386. pinctrl-names = "default";
  387. pinctrl-0 = <&pinctrl_nand>;
  388. gpios = <&pioD 5 0
  389. &pioD 4 0
  390. 0
  391. >;
  392. status = "disabled";
  393. };
  394. usb0: ohci@00500000 {
  395. compatible = "atmel,at91rm9200-ohci", "usb-ohci";
  396. reg = <0x00500000 0x00100000>;
  397. interrupts = <22 4 2>;
  398. status = "disabled";
  399. };
  400. };
  401. i2c@0 {
  402. compatible = "i2c-gpio";
  403. gpios = <&pioA 30 0 /* sda */
  404. &pioA 31 0 /* scl */
  405. >;
  406. i2c-gpio,sda-open-drain;
  407. i2c-gpio,scl-open-drain;
  408. i2c-gpio,delay-us = <2>; /* ~100 kHz */
  409. #address-cells = <1>;
  410. #size-cells = <0>;
  411. status = "disabled";
  412. };
  413. };