events.c 38 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498149915001501150215031504150515061507150815091510151115121513151415151516151715181519152015211522152315241525152615271528152915301531153215331534153515361537153815391540154115421543154415451546154715481549155015511552155315541555155615571558155915601561156215631564156515661567156815691570157115721573157415751576157715781579158015811582158315841585158615871588158915901591159215931594159515961597159815991600160116021603160416051606160716081609161016111612161316141615161616171618161916201621162216231624162516261627162816291630163116321633163416351636163716381639164016411642164316441645164616471648164916501651165216531654165516561657165816591660
  1. /*
  2. * Xen event channels
  3. *
  4. * Xen models interrupts with abstract event channels. Because each
  5. * domain gets 1024 event channels, but NR_IRQ is not that large, we
  6. * must dynamically map irqs<->event channels. The event channels
  7. * interface with the rest of the kernel by defining a xen interrupt
  8. * chip. When an event is received, it is mapped to an irq and sent
  9. * through the normal interrupt processing path.
  10. *
  11. * There are four kinds of events which can be mapped to an event
  12. * channel:
  13. *
  14. * 1. Inter-domain notifications. This includes all the virtual
  15. * device events, since they're driven by front-ends in another domain
  16. * (typically dom0).
  17. * 2. VIRQs, typically used for timers. These are per-cpu events.
  18. * 3. IPIs.
  19. * 4. PIRQs - Hardware interrupts.
  20. *
  21. * Jeremy Fitzhardinge <jeremy@xensource.com>, XenSource Inc, 2007
  22. */
  23. #include <linux/linkage.h>
  24. #include <linux/interrupt.h>
  25. #include <linux/irq.h>
  26. #include <linux/module.h>
  27. #include <linux/string.h>
  28. #include <linux/bootmem.h>
  29. #include <linux/slab.h>
  30. #include <linux/irqnr.h>
  31. #include <linux/pci.h>
  32. #include <asm/desc.h>
  33. #include <asm/ptrace.h>
  34. #include <asm/irq.h>
  35. #include <asm/idle.h>
  36. #include <asm/io_apic.h>
  37. #include <asm/sync_bitops.h>
  38. #include <asm/xen/pci.h>
  39. #include <asm/xen/hypercall.h>
  40. #include <asm/xen/hypervisor.h>
  41. #include <xen/xen.h>
  42. #include <xen/hvm.h>
  43. #include <xen/xen-ops.h>
  44. #include <xen/events.h>
  45. #include <xen/interface/xen.h>
  46. #include <xen/interface/event_channel.h>
  47. #include <xen/interface/hvm/hvm_op.h>
  48. #include <xen/interface/hvm/params.h>
  49. /*
  50. * This lock protects updates to the following mapping and reference-count
  51. * arrays. The lock does not need to be acquired to read the mapping tables.
  52. */
  53. static DEFINE_SPINLOCK(irq_mapping_update_lock);
  54. static LIST_HEAD(xen_irq_list_head);
  55. /* IRQ <-> VIRQ mapping. */
  56. static DEFINE_PER_CPU(int [NR_VIRQS], virq_to_irq) = {[0 ... NR_VIRQS-1] = -1};
  57. /* IRQ <-> IPI mapping */
  58. static DEFINE_PER_CPU(int [XEN_NR_IPIS], ipi_to_irq) = {[0 ... XEN_NR_IPIS-1] = -1};
  59. /* Interrupt types. */
  60. enum xen_irq_type {
  61. IRQT_UNBOUND = 0,
  62. IRQT_PIRQ,
  63. IRQT_VIRQ,
  64. IRQT_IPI,
  65. IRQT_EVTCHN
  66. };
  67. /*
  68. * Packed IRQ information:
  69. * type - enum xen_irq_type
  70. * event channel - irq->event channel mapping
  71. * cpu - cpu this event channel is bound to
  72. * index - type-specific information:
  73. * PIRQ - vector, with MSB being "needs EIO", or physical IRQ of the HVM
  74. * guest, or GSI (real passthrough IRQ) of the device.
  75. * VIRQ - virq number
  76. * IPI - IPI vector
  77. * EVTCHN -
  78. */
  79. struct irq_info
  80. {
  81. struct list_head list;
  82. enum xen_irq_type type; /* type */
  83. unsigned irq;
  84. unsigned short evtchn; /* event channel */
  85. unsigned short cpu; /* cpu bound */
  86. union {
  87. unsigned short virq;
  88. enum ipi_vector ipi;
  89. struct {
  90. unsigned short pirq;
  91. unsigned short gsi;
  92. unsigned char vector;
  93. unsigned char flags;
  94. uint16_t domid;
  95. } pirq;
  96. } u;
  97. };
  98. #define PIRQ_NEEDS_EOI (1 << 0)
  99. #define PIRQ_SHAREABLE (1 << 1)
  100. static int *evtchn_to_irq;
  101. static DEFINE_PER_CPU(unsigned long [NR_EVENT_CHANNELS/BITS_PER_LONG],
  102. cpu_evtchn_mask);
  103. /* Xen will never allocate port zero for any purpose. */
  104. #define VALID_EVTCHN(chn) ((chn) != 0)
  105. static struct irq_chip xen_dynamic_chip;
  106. static struct irq_chip xen_percpu_chip;
  107. static struct irq_chip xen_pirq_chip;
  108. /* Get info for IRQ */
  109. static struct irq_info *info_for_irq(unsigned irq)
  110. {
  111. return irq_get_handler_data(irq);
  112. }
  113. /* Constructors for packed IRQ information. */
  114. static void xen_irq_info_common_init(struct irq_info *info,
  115. unsigned irq,
  116. enum xen_irq_type type,
  117. unsigned short evtchn,
  118. unsigned short cpu)
  119. {
  120. BUG_ON(info->type != IRQT_UNBOUND && info->type != type);
  121. info->type = type;
  122. info->irq = irq;
  123. info->evtchn = evtchn;
  124. info->cpu = cpu;
  125. evtchn_to_irq[evtchn] = irq;
  126. }
  127. static void xen_irq_info_evtchn_init(unsigned irq,
  128. unsigned short evtchn)
  129. {
  130. struct irq_info *info = info_for_irq(irq);
  131. xen_irq_info_common_init(info, irq, IRQT_EVTCHN, evtchn, 0);
  132. }
  133. static void xen_irq_info_ipi_init(unsigned cpu,
  134. unsigned irq,
  135. unsigned short evtchn,
  136. enum ipi_vector ipi)
  137. {
  138. struct irq_info *info = info_for_irq(irq);
  139. xen_irq_info_common_init(info, irq, IRQT_IPI, evtchn, 0);
  140. info->u.ipi = ipi;
  141. per_cpu(ipi_to_irq, cpu)[ipi] = irq;
  142. }
  143. static void xen_irq_info_virq_init(unsigned cpu,
  144. unsigned irq,
  145. unsigned short evtchn,
  146. unsigned short virq)
  147. {
  148. struct irq_info *info = info_for_irq(irq);
  149. xen_irq_info_common_init(info, irq, IRQT_VIRQ, evtchn, 0);
  150. info->u.virq = virq;
  151. per_cpu(virq_to_irq, cpu)[virq] = irq;
  152. }
  153. static void xen_irq_info_pirq_init(unsigned irq,
  154. unsigned short evtchn,
  155. unsigned short pirq,
  156. unsigned short gsi,
  157. unsigned short vector,
  158. uint16_t domid,
  159. unsigned char flags)
  160. {
  161. struct irq_info *info = info_for_irq(irq);
  162. xen_irq_info_common_init(info, irq, IRQT_PIRQ, evtchn, 0);
  163. info->u.pirq.pirq = pirq;
  164. info->u.pirq.gsi = gsi;
  165. info->u.pirq.vector = vector;
  166. info->u.pirq.domid = domid;
  167. info->u.pirq.flags = flags;
  168. }
  169. /*
  170. * Accessors for packed IRQ information.
  171. */
  172. static unsigned int evtchn_from_irq(unsigned irq)
  173. {
  174. if (unlikely(WARN(irq < 0 || irq >= nr_irqs, "Invalid irq %d!\n", irq)))
  175. return 0;
  176. return info_for_irq(irq)->evtchn;
  177. }
  178. unsigned irq_from_evtchn(unsigned int evtchn)
  179. {
  180. return evtchn_to_irq[evtchn];
  181. }
  182. EXPORT_SYMBOL_GPL(irq_from_evtchn);
  183. static enum ipi_vector ipi_from_irq(unsigned irq)
  184. {
  185. struct irq_info *info = info_for_irq(irq);
  186. BUG_ON(info == NULL);
  187. BUG_ON(info->type != IRQT_IPI);
  188. return info->u.ipi;
  189. }
  190. static unsigned virq_from_irq(unsigned irq)
  191. {
  192. struct irq_info *info = info_for_irq(irq);
  193. BUG_ON(info == NULL);
  194. BUG_ON(info->type != IRQT_VIRQ);
  195. return info->u.virq;
  196. }
  197. static unsigned pirq_from_irq(unsigned irq)
  198. {
  199. struct irq_info *info = info_for_irq(irq);
  200. BUG_ON(info == NULL);
  201. BUG_ON(info->type != IRQT_PIRQ);
  202. return info->u.pirq.pirq;
  203. }
  204. static enum xen_irq_type type_from_irq(unsigned irq)
  205. {
  206. return info_for_irq(irq)->type;
  207. }
  208. static unsigned cpu_from_irq(unsigned irq)
  209. {
  210. return info_for_irq(irq)->cpu;
  211. }
  212. static unsigned int cpu_from_evtchn(unsigned int evtchn)
  213. {
  214. int irq = evtchn_to_irq[evtchn];
  215. unsigned ret = 0;
  216. if (irq != -1)
  217. ret = cpu_from_irq(irq);
  218. return ret;
  219. }
  220. static bool pirq_needs_eoi(unsigned irq)
  221. {
  222. struct irq_info *info = info_for_irq(irq);
  223. BUG_ON(info->type != IRQT_PIRQ);
  224. return info->u.pirq.flags & PIRQ_NEEDS_EOI;
  225. }
  226. static inline unsigned long active_evtchns(unsigned int cpu,
  227. struct shared_info *sh,
  228. unsigned int idx)
  229. {
  230. return (sh->evtchn_pending[idx] &
  231. per_cpu(cpu_evtchn_mask, cpu)[idx] &
  232. ~sh->evtchn_mask[idx]);
  233. }
  234. static void bind_evtchn_to_cpu(unsigned int chn, unsigned int cpu)
  235. {
  236. int irq = evtchn_to_irq[chn];
  237. BUG_ON(irq == -1);
  238. #ifdef CONFIG_SMP
  239. cpumask_copy(irq_to_desc(irq)->irq_data.affinity, cpumask_of(cpu));
  240. #endif
  241. clear_bit(chn, per_cpu(cpu_evtchn_mask, cpu_from_irq(irq)));
  242. set_bit(chn, per_cpu(cpu_evtchn_mask, cpu));
  243. info_for_irq(irq)->cpu = cpu;
  244. }
  245. static void init_evtchn_cpu_bindings(void)
  246. {
  247. int i;
  248. #ifdef CONFIG_SMP
  249. struct irq_info *info;
  250. /* By default all event channels notify CPU#0. */
  251. list_for_each_entry(info, &xen_irq_list_head, list) {
  252. struct irq_desc *desc = irq_to_desc(info->irq);
  253. cpumask_copy(desc->irq_data.affinity, cpumask_of(0));
  254. }
  255. #endif
  256. for_each_possible_cpu(i)
  257. memset(per_cpu(cpu_evtchn_mask, i),
  258. (i == 0) ? ~0 : 0, sizeof(*per_cpu(cpu_evtchn_mask, i)));
  259. }
  260. static inline void clear_evtchn(int port)
  261. {
  262. struct shared_info *s = HYPERVISOR_shared_info;
  263. sync_clear_bit(port, &s->evtchn_pending[0]);
  264. }
  265. static inline void set_evtchn(int port)
  266. {
  267. struct shared_info *s = HYPERVISOR_shared_info;
  268. sync_set_bit(port, &s->evtchn_pending[0]);
  269. }
  270. static inline int test_evtchn(int port)
  271. {
  272. struct shared_info *s = HYPERVISOR_shared_info;
  273. return sync_test_bit(port, &s->evtchn_pending[0]);
  274. }
  275. /**
  276. * notify_remote_via_irq - send event to remote end of event channel via irq
  277. * @irq: irq of event channel to send event to
  278. *
  279. * Unlike notify_remote_via_evtchn(), this is safe to use across
  280. * save/restore. Notifications on a broken connection are silently
  281. * dropped.
  282. */
  283. void notify_remote_via_irq(int irq)
  284. {
  285. int evtchn = evtchn_from_irq(irq);
  286. if (VALID_EVTCHN(evtchn))
  287. notify_remote_via_evtchn(evtchn);
  288. }
  289. EXPORT_SYMBOL_GPL(notify_remote_via_irq);
  290. static void mask_evtchn(int port)
  291. {
  292. struct shared_info *s = HYPERVISOR_shared_info;
  293. sync_set_bit(port, &s->evtchn_mask[0]);
  294. }
  295. static void unmask_evtchn(int port)
  296. {
  297. struct shared_info *s = HYPERVISOR_shared_info;
  298. unsigned int cpu = get_cpu();
  299. BUG_ON(!irqs_disabled());
  300. /* Slow path (hypercall) if this is a non-local port. */
  301. if (unlikely(cpu != cpu_from_evtchn(port))) {
  302. struct evtchn_unmask unmask = { .port = port };
  303. (void)HYPERVISOR_event_channel_op(EVTCHNOP_unmask, &unmask);
  304. } else {
  305. struct vcpu_info *vcpu_info = __this_cpu_read(xen_vcpu);
  306. sync_clear_bit(port, &s->evtchn_mask[0]);
  307. /*
  308. * The following is basically the equivalent of
  309. * 'hw_resend_irq'. Just like a real IO-APIC we 'lose
  310. * the interrupt edge' if the channel is masked.
  311. */
  312. if (sync_test_bit(port, &s->evtchn_pending[0]) &&
  313. !sync_test_and_set_bit(port / BITS_PER_LONG,
  314. &vcpu_info->evtchn_pending_sel))
  315. vcpu_info->evtchn_upcall_pending = 1;
  316. }
  317. put_cpu();
  318. }
  319. static void xen_irq_init(unsigned irq)
  320. {
  321. struct irq_info *info;
  322. struct irq_desc *desc = irq_to_desc(irq);
  323. #ifdef CONFIG_SMP
  324. /* By default all event channels notify CPU#0. */
  325. cpumask_copy(desc->irq_data.affinity, cpumask_of(0));
  326. #endif
  327. info = kzalloc(sizeof(*info), GFP_KERNEL);
  328. if (info == NULL)
  329. panic("Unable to allocate metadata for IRQ%d\n", irq);
  330. info->type = IRQT_UNBOUND;
  331. irq_set_handler_data(irq, info);
  332. list_add_tail(&info->list, &xen_irq_list_head);
  333. }
  334. static int __must_check xen_allocate_irq_dynamic(void)
  335. {
  336. int first = 0;
  337. int irq;
  338. #ifdef CONFIG_X86_IO_APIC
  339. /*
  340. * For an HVM guest or domain 0 which see "real" (emulated or
  341. * actual respectively) GSIs we allocate dynamic IRQs
  342. * e.g. those corresponding to event channels or MSIs
  343. * etc. from the range above those "real" GSIs to avoid
  344. * collisions.
  345. */
  346. if (xen_initial_domain() || xen_hvm_domain())
  347. first = get_nr_irqs_gsi();
  348. #endif
  349. irq = irq_alloc_desc_from(first, -1);
  350. xen_irq_init(irq);
  351. return irq;
  352. }
  353. static int __must_check xen_allocate_irq_gsi(unsigned gsi)
  354. {
  355. int irq;
  356. /*
  357. * A PV guest has no concept of a GSI (since it has no ACPI
  358. * nor access to/knowledge of the physical APICs). Therefore
  359. * all IRQs are dynamically allocated from the entire IRQ
  360. * space.
  361. */
  362. if (xen_pv_domain() && !xen_initial_domain())
  363. return xen_allocate_irq_dynamic();
  364. /* Legacy IRQ descriptors are already allocated by the arch. */
  365. if (gsi < NR_IRQS_LEGACY)
  366. irq = gsi;
  367. else
  368. irq = irq_alloc_desc_at(gsi, -1);
  369. xen_irq_init(irq);
  370. return irq;
  371. }
  372. static void xen_free_irq(unsigned irq)
  373. {
  374. struct irq_info *info = irq_get_handler_data(irq);
  375. list_del(&info->list);
  376. irq_set_handler_data(irq, NULL);
  377. kfree(info);
  378. /* Legacy IRQ descriptors are managed by the arch. */
  379. if (irq < NR_IRQS_LEGACY)
  380. return;
  381. irq_free_desc(irq);
  382. }
  383. static void pirq_unmask_notify(int irq)
  384. {
  385. struct physdev_eoi eoi = { .irq = pirq_from_irq(irq) };
  386. if (unlikely(pirq_needs_eoi(irq))) {
  387. int rc = HYPERVISOR_physdev_op(PHYSDEVOP_eoi, &eoi);
  388. WARN_ON(rc);
  389. }
  390. }
  391. static void pirq_query_unmask(int irq)
  392. {
  393. struct physdev_irq_status_query irq_status;
  394. struct irq_info *info = info_for_irq(irq);
  395. BUG_ON(info->type != IRQT_PIRQ);
  396. irq_status.irq = pirq_from_irq(irq);
  397. if (HYPERVISOR_physdev_op(PHYSDEVOP_irq_status_query, &irq_status))
  398. irq_status.flags = 0;
  399. info->u.pirq.flags &= ~PIRQ_NEEDS_EOI;
  400. if (irq_status.flags & XENIRQSTAT_needs_eoi)
  401. info->u.pirq.flags |= PIRQ_NEEDS_EOI;
  402. }
  403. static bool probing_irq(int irq)
  404. {
  405. struct irq_desc *desc = irq_to_desc(irq);
  406. return desc && desc->action == NULL;
  407. }
  408. static unsigned int __startup_pirq(unsigned int irq)
  409. {
  410. struct evtchn_bind_pirq bind_pirq;
  411. struct irq_info *info = info_for_irq(irq);
  412. int evtchn = evtchn_from_irq(irq);
  413. int rc;
  414. BUG_ON(info->type != IRQT_PIRQ);
  415. if (VALID_EVTCHN(evtchn))
  416. goto out;
  417. bind_pirq.pirq = pirq_from_irq(irq);
  418. /* NB. We are happy to share unless we are probing. */
  419. bind_pirq.flags = info->u.pirq.flags & PIRQ_SHAREABLE ?
  420. BIND_PIRQ__WILL_SHARE : 0;
  421. rc = HYPERVISOR_event_channel_op(EVTCHNOP_bind_pirq, &bind_pirq);
  422. if (rc != 0) {
  423. if (!probing_irq(irq))
  424. printk(KERN_INFO "Failed to obtain physical IRQ %d\n",
  425. irq);
  426. return 0;
  427. }
  428. evtchn = bind_pirq.port;
  429. pirq_query_unmask(irq);
  430. evtchn_to_irq[evtchn] = irq;
  431. bind_evtchn_to_cpu(evtchn, 0);
  432. info->evtchn = evtchn;
  433. out:
  434. unmask_evtchn(evtchn);
  435. pirq_unmask_notify(irq);
  436. return 0;
  437. }
  438. static unsigned int startup_pirq(struct irq_data *data)
  439. {
  440. return __startup_pirq(data->irq);
  441. }
  442. static void shutdown_pirq(struct irq_data *data)
  443. {
  444. struct evtchn_close close;
  445. unsigned int irq = data->irq;
  446. struct irq_info *info = info_for_irq(irq);
  447. int evtchn = evtchn_from_irq(irq);
  448. BUG_ON(info->type != IRQT_PIRQ);
  449. if (!VALID_EVTCHN(evtchn))
  450. return;
  451. mask_evtchn(evtchn);
  452. close.port = evtchn;
  453. if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0)
  454. BUG();
  455. bind_evtchn_to_cpu(evtchn, 0);
  456. evtchn_to_irq[evtchn] = -1;
  457. info->evtchn = 0;
  458. }
  459. static void enable_pirq(struct irq_data *data)
  460. {
  461. startup_pirq(data);
  462. }
  463. static void disable_pirq(struct irq_data *data)
  464. {
  465. }
  466. static void ack_pirq(struct irq_data *data)
  467. {
  468. int evtchn = evtchn_from_irq(data->irq);
  469. irq_move_irq(data);
  470. if (VALID_EVTCHN(evtchn)) {
  471. mask_evtchn(evtchn);
  472. clear_evtchn(evtchn);
  473. }
  474. }
  475. static int find_irq_by_gsi(unsigned gsi)
  476. {
  477. struct irq_info *info;
  478. list_for_each_entry(info, &xen_irq_list_head, list) {
  479. if (info->type != IRQT_PIRQ)
  480. continue;
  481. if (info->u.pirq.gsi == gsi)
  482. return info->irq;
  483. }
  484. return -1;
  485. }
  486. int xen_allocate_pirq_gsi(unsigned gsi)
  487. {
  488. return gsi;
  489. }
  490. /*
  491. * Do not make any assumptions regarding the relationship between the
  492. * IRQ number returned here and the Xen pirq argument.
  493. *
  494. * Note: We don't assign an event channel until the irq actually started
  495. * up. Return an existing irq if we've already got one for the gsi.
  496. */
  497. int xen_bind_pirq_gsi_to_irq(unsigned gsi,
  498. unsigned pirq, int shareable, char *name)
  499. {
  500. int irq = -1;
  501. struct physdev_irq irq_op;
  502. spin_lock(&irq_mapping_update_lock);
  503. irq = find_irq_by_gsi(gsi);
  504. if (irq != -1) {
  505. printk(KERN_INFO "xen_map_pirq_gsi: returning irq %d for gsi %u\n",
  506. irq, gsi);
  507. goto out; /* XXX need refcount? */
  508. }
  509. irq = xen_allocate_irq_gsi(gsi);
  510. if (irq < 0)
  511. goto out;
  512. irq_set_chip_and_handler_name(irq, &xen_pirq_chip, handle_level_irq,
  513. name);
  514. irq_op.irq = irq;
  515. irq_op.vector = 0;
  516. /* Only the privileged domain can do this. For non-priv, the pcifront
  517. * driver provides a PCI bus that does the call to do exactly
  518. * this in the priv domain. */
  519. if (xen_initial_domain() &&
  520. HYPERVISOR_physdev_op(PHYSDEVOP_alloc_irq_vector, &irq_op)) {
  521. xen_free_irq(irq);
  522. irq = -ENOSPC;
  523. goto out;
  524. }
  525. xen_irq_info_pirq_init(irq, 0, pirq, gsi, irq_op.vector, DOMID_SELF,
  526. shareable ? PIRQ_SHAREABLE : 0);
  527. out:
  528. spin_unlock(&irq_mapping_update_lock);
  529. return irq;
  530. }
  531. #ifdef CONFIG_PCI_MSI
  532. int xen_allocate_pirq_msi(struct pci_dev *dev, struct msi_desc *msidesc)
  533. {
  534. int rc;
  535. struct physdev_get_free_pirq op_get_free_pirq;
  536. op_get_free_pirq.type = MAP_PIRQ_TYPE_MSI;
  537. rc = HYPERVISOR_physdev_op(PHYSDEVOP_get_free_pirq, &op_get_free_pirq);
  538. WARN_ONCE(rc == -ENOSYS,
  539. "hypervisor does not support the PHYSDEVOP_get_free_pirq interface\n");
  540. return rc ? -1 : op_get_free_pirq.pirq;
  541. }
  542. int xen_bind_pirq_msi_to_irq(struct pci_dev *dev, struct msi_desc *msidesc,
  543. int pirq, int vector, const char *name,
  544. domid_t domid)
  545. {
  546. int irq, ret;
  547. spin_lock(&irq_mapping_update_lock);
  548. irq = xen_allocate_irq_dynamic();
  549. if (irq == -1)
  550. goto out;
  551. irq_set_chip_and_handler_name(irq, &xen_pirq_chip, handle_level_irq,
  552. name);
  553. xen_irq_info_pirq_init(irq, 0, pirq, 0, vector, domid, 0);
  554. ret = irq_set_msi_desc(irq, msidesc);
  555. if (ret < 0)
  556. goto error_irq;
  557. out:
  558. spin_unlock(&irq_mapping_update_lock);
  559. return irq;
  560. error_irq:
  561. spin_unlock(&irq_mapping_update_lock);
  562. xen_free_irq(irq);
  563. return -1;
  564. }
  565. #endif
  566. int xen_destroy_irq(int irq)
  567. {
  568. struct irq_desc *desc;
  569. struct physdev_unmap_pirq unmap_irq;
  570. struct irq_info *info = info_for_irq(irq);
  571. int rc = -ENOENT;
  572. spin_lock(&irq_mapping_update_lock);
  573. desc = irq_to_desc(irq);
  574. if (!desc)
  575. goto out;
  576. if (xen_initial_domain()) {
  577. unmap_irq.pirq = info->u.pirq.pirq;
  578. unmap_irq.domid = info->u.pirq.domid;
  579. rc = HYPERVISOR_physdev_op(PHYSDEVOP_unmap_pirq, &unmap_irq);
  580. if (rc) {
  581. printk(KERN_WARNING "unmap irq failed %d\n", rc);
  582. goto out;
  583. }
  584. }
  585. xen_free_irq(irq);
  586. out:
  587. spin_unlock(&irq_mapping_update_lock);
  588. return rc;
  589. }
  590. int xen_irq_from_pirq(unsigned pirq)
  591. {
  592. int irq;
  593. struct irq_info *info;
  594. spin_lock(&irq_mapping_update_lock);
  595. list_for_each_entry(info, &xen_irq_list_head, list) {
  596. if (info == NULL || info->type != IRQT_PIRQ)
  597. continue;
  598. irq = info->irq;
  599. if (info->u.pirq.pirq == pirq)
  600. goto out;
  601. }
  602. irq = -1;
  603. out:
  604. spin_unlock(&irq_mapping_update_lock);
  605. return irq;
  606. }
  607. int xen_pirq_from_irq(unsigned irq)
  608. {
  609. return pirq_from_irq(irq);
  610. }
  611. EXPORT_SYMBOL_GPL(xen_pirq_from_irq);
  612. int bind_evtchn_to_irq(unsigned int evtchn)
  613. {
  614. int irq;
  615. spin_lock(&irq_mapping_update_lock);
  616. irq = evtchn_to_irq[evtchn];
  617. if (irq == -1) {
  618. irq = xen_allocate_irq_dynamic();
  619. if (irq == -1)
  620. goto out;
  621. irq_set_chip_and_handler_name(irq, &xen_dynamic_chip,
  622. handle_fasteoi_irq, "event");
  623. xen_irq_info_evtchn_init(irq, evtchn);
  624. }
  625. out:
  626. spin_unlock(&irq_mapping_update_lock);
  627. return irq;
  628. }
  629. EXPORT_SYMBOL_GPL(bind_evtchn_to_irq);
  630. static int bind_ipi_to_irq(unsigned int ipi, unsigned int cpu)
  631. {
  632. struct evtchn_bind_ipi bind_ipi;
  633. int evtchn, irq;
  634. spin_lock(&irq_mapping_update_lock);
  635. irq = per_cpu(ipi_to_irq, cpu)[ipi];
  636. if (irq == -1) {
  637. irq = xen_allocate_irq_dynamic();
  638. if (irq < 0)
  639. goto out;
  640. irq_set_chip_and_handler_name(irq, &xen_percpu_chip,
  641. handle_percpu_irq, "ipi");
  642. bind_ipi.vcpu = cpu;
  643. if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi,
  644. &bind_ipi) != 0)
  645. BUG();
  646. evtchn = bind_ipi.port;
  647. xen_irq_info_ipi_init(cpu, irq, evtchn, ipi);
  648. bind_evtchn_to_cpu(evtchn, cpu);
  649. }
  650. out:
  651. spin_unlock(&irq_mapping_update_lock);
  652. return irq;
  653. }
  654. static int bind_interdomain_evtchn_to_irq(unsigned int remote_domain,
  655. unsigned int remote_port)
  656. {
  657. struct evtchn_bind_interdomain bind_interdomain;
  658. int err;
  659. bind_interdomain.remote_dom = remote_domain;
  660. bind_interdomain.remote_port = remote_port;
  661. err = HYPERVISOR_event_channel_op(EVTCHNOP_bind_interdomain,
  662. &bind_interdomain);
  663. return err ? : bind_evtchn_to_irq(bind_interdomain.local_port);
  664. }
  665. int bind_virq_to_irq(unsigned int virq, unsigned int cpu)
  666. {
  667. struct evtchn_bind_virq bind_virq;
  668. int evtchn, irq;
  669. spin_lock(&irq_mapping_update_lock);
  670. irq = per_cpu(virq_to_irq, cpu)[virq];
  671. if (irq == -1) {
  672. irq = xen_allocate_irq_dynamic();
  673. if (irq == -1)
  674. goto out;
  675. irq_set_chip_and_handler_name(irq, &xen_percpu_chip,
  676. handle_percpu_irq, "virq");
  677. bind_virq.virq = virq;
  678. bind_virq.vcpu = cpu;
  679. if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq,
  680. &bind_virq) != 0)
  681. BUG();
  682. evtchn = bind_virq.port;
  683. xen_irq_info_virq_init(cpu, irq, evtchn, virq);
  684. bind_evtchn_to_cpu(evtchn, cpu);
  685. }
  686. out:
  687. spin_unlock(&irq_mapping_update_lock);
  688. return irq;
  689. }
  690. static void unbind_from_irq(unsigned int irq)
  691. {
  692. struct evtchn_close close;
  693. int evtchn = evtchn_from_irq(irq);
  694. spin_lock(&irq_mapping_update_lock);
  695. if (VALID_EVTCHN(evtchn)) {
  696. close.port = evtchn;
  697. if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0)
  698. BUG();
  699. switch (type_from_irq(irq)) {
  700. case IRQT_VIRQ:
  701. per_cpu(virq_to_irq, cpu_from_evtchn(evtchn))
  702. [virq_from_irq(irq)] = -1;
  703. break;
  704. case IRQT_IPI:
  705. per_cpu(ipi_to_irq, cpu_from_evtchn(evtchn))
  706. [ipi_from_irq(irq)] = -1;
  707. break;
  708. default:
  709. break;
  710. }
  711. /* Closed ports are implicitly re-bound to VCPU0. */
  712. bind_evtchn_to_cpu(evtchn, 0);
  713. evtchn_to_irq[evtchn] = -1;
  714. }
  715. BUG_ON(info_for_irq(irq)->type == IRQT_UNBOUND);
  716. xen_free_irq(irq);
  717. spin_unlock(&irq_mapping_update_lock);
  718. }
  719. int bind_evtchn_to_irqhandler(unsigned int evtchn,
  720. irq_handler_t handler,
  721. unsigned long irqflags,
  722. const char *devname, void *dev_id)
  723. {
  724. unsigned int irq;
  725. int retval;
  726. irq = bind_evtchn_to_irq(evtchn);
  727. if (irq < 0)
  728. return irq;
  729. retval = request_irq(irq, handler, irqflags, devname, dev_id);
  730. if (retval != 0) {
  731. unbind_from_irq(irq);
  732. return retval;
  733. }
  734. return irq;
  735. }
  736. EXPORT_SYMBOL_GPL(bind_evtchn_to_irqhandler);
  737. int bind_interdomain_evtchn_to_irqhandler(unsigned int remote_domain,
  738. unsigned int remote_port,
  739. irq_handler_t handler,
  740. unsigned long irqflags,
  741. const char *devname,
  742. void *dev_id)
  743. {
  744. int irq, retval;
  745. irq = bind_interdomain_evtchn_to_irq(remote_domain, remote_port);
  746. if (irq < 0)
  747. return irq;
  748. retval = request_irq(irq, handler, irqflags, devname, dev_id);
  749. if (retval != 0) {
  750. unbind_from_irq(irq);
  751. return retval;
  752. }
  753. return irq;
  754. }
  755. EXPORT_SYMBOL_GPL(bind_interdomain_evtchn_to_irqhandler);
  756. int bind_virq_to_irqhandler(unsigned int virq, unsigned int cpu,
  757. irq_handler_t handler,
  758. unsigned long irqflags, const char *devname, void *dev_id)
  759. {
  760. unsigned int irq;
  761. int retval;
  762. irq = bind_virq_to_irq(virq, cpu);
  763. if (irq < 0)
  764. return irq;
  765. retval = request_irq(irq, handler, irqflags, devname, dev_id);
  766. if (retval != 0) {
  767. unbind_from_irq(irq);
  768. return retval;
  769. }
  770. return irq;
  771. }
  772. EXPORT_SYMBOL_GPL(bind_virq_to_irqhandler);
  773. int bind_ipi_to_irqhandler(enum ipi_vector ipi,
  774. unsigned int cpu,
  775. irq_handler_t handler,
  776. unsigned long irqflags,
  777. const char *devname,
  778. void *dev_id)
  779. {
  780. int irq, retval;
  781. irq = bind_ipi_to_irq(ipi, cpu);
  782. if (irq < 0)
  783. return irq;
  784. irqflags |= IRQF_NO_SUSPEND | IRQF_FORCE_RESUME;
  785. retval = request_irq(irq, handler, irqflags, devname, dev_id);
  786. if (retval != 0) {
  787. unbind_from_irq(irq);
  788. return retval;
  789. }
  790. return irq;
  791. }
  792. void unbind_from_irqhandler(unsigned int irq, void *dev_id)
  793. {
  794. free_irq(irq, dev_id);
  795. unbind_from_irq(irq);
  796. }
  797. EXPORT_SYMBOL_GPL(unbind_from_irqhandler);
  798. void xen_send_IPI_one(unsigned int cpu, enum ipi_vector vector)
  799. {
  800. int irq = per_cpu(ipi_to_irq, cpu)[vector];
  801. BUG_ON(irq < 0);
  802. notify_remote_via_irq(irq);
  803. }
  804. irqreturn_t xen_debug_interrupt(int irq, void *dev_id)
  805. {
  806. struct shared_info *sh = HYPERVISOR_shared_info;
  807. int cpu = smp_processor_id();
  808. unsigned long *cpu_evtchn = per_cpu(cpu_evtchn_mask, cpu);
  809. int i;
  810. unsigned long flags;
  811. static DEFINE_SPINLOCK(debug_lock);
  812. struct vcpu_info *v;
  813. spin_lock_irqsave(&debug_lock, flags);
  814. printk("\nvcpu %d\n ", cpu);
  815. for_each_online_cpu(i) {
  816. int pending;
  817. v = per_cpu(xen_vcpu, i);
  818. pending = (get_irq_regs() && i == cpu)
  819. ? xen_irqs_disabled(get_irq_regs())
  820. : v->evtchn_upcall_mask;
  821. printk("%d: masked=%d pending=%d event_sel %0*lx\n ", i,
  822. pending, v->evtchn_upcall_pending,
  823. (int)(sizeof(v->evtchn_pending_sel)*2),
  824. v->evtchn_pending_sel);
  825. }
  826. v = per_cpu(xen_vcpu, cpu);
  827. printk("\npending:\n ");
  828. for (i = ARRAY_SIZE(sh->evtchn_pending)-1; i >= 0; i--)
  829. printk("%0*lx%s", (int)sizeof(sh->evtchn_pending[0])*2,
  830. sh->evtchn_pending[i],
  831. i % 8 == 0 ? "\n " : " ");
  832. printk("\nglobal mask:\n ");
  833. for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--)
  834. printk("%0*lx%s",
  835. (int)(sizeof(sh->evtchn_mask[0])*2),
  836. sh->evtchn_mask[i],
  837. i % 8 == 0 ? "\n " : " ");
  838. printk("\nglobally unmasked:\n ");
  839. for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--)
  840. printk("%0*lx%s", (int)(sizeof(sh->evtchn_mask[0])*2),
  841. sh->evtchn_pending[i] & ~sh->evtchn_mask[i],
  842. i % 8 == 0 ? "\n " : " ");
  843. printk("\nlocal cpu%d mask:\n ", cpu);
  844. for (i = (NR_EVENT_CHANNELS/BITS_PER_LONG)-1; i >= 0; i--)
  845. printk("%0*lx%s", (int)(sizeof(cpu_evtchn[0])*2),
  846. cpu_evtchn[i],
  847. i % 8 == 0 ? "\n " : " ");
  848. printk("\nlocally unmasked:\n ");
  849. for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--) {
  850. unsigned long pending = sh->evtchn_pending[i]
  851. & ~sh->evtchn_mask[i]
  852. & cpu_evtchn[i];
  853. printk("%0*lx%s", (int)(sizeof(sh->evtchn_mask[0])*2),
  854. pending, i % 8 == 0 ? "\n " : " ");
  855. }
  856. printk("\npending list:\n");
  857. for (i = 0; i < NR_EVENT_CHANNELS; i++) {
  858. if (sync_test_bit(i, sh->evtchn_pending)) {
  859. int word_idx = i / BITS_PER_LONG;
  860. printk(" %d: event %d -> irq %d%s%s%s\n",
  861. cpu_from_evtchn(i), i,
  862. evtchn_to_irq[i],
  863. sync_test_bit(word_idx, &v->evtchn_pending_sel)
  864. ? "" : " l2-clear",
  865. !sync_test_bit(i, sh->evtchn_mask)
  866. ? "" : " globally-masked",
  867. sync_test_bit(i, cpu_evtchn)
  868. ? "" : " locally-masked");
  869. }
  870. }
  871. spin_unlock_irqrestore(&debug_lock, flags);
  872. return IRQ_HANDLED;
  873. }
  874. static DEFINE_PER_CPU(unsigned, xed_nesting_count);
  875. static DEFINE_PER_CPU(unsigned int, current_word_idx);
  876. static DEFINE_PER_CPU(unsigned int, current_bit_idx);
  877. /*
  878. * Mask out the i least significant bits of w
  879. */
  880. #define MASK_LSBS(w, i) (w & ((~0UL) << i))
  881. /*
  882. * Search the CPUs pending events bitmasks. For each one found, map
  883. * the event number to an irq, and feed it into do_IRQ() for
  884. * handling.
  885. *
  886. * Xen uses a two-level bitmap to speed searching. The first level is
  887. * a bitset of words which contain pending event bits. The second
  888. * level is a bitset of pending events themselves.
  889. */
  890. static void __xen_evtchn_do_upcall(void)
  891. {
  892. int start_word_idx, start_bit_idx;
  893. int word_idx, bit_idx;
  894. int i;
  895. int cpu = get_cpu();
  896. struct shared_info *s = HYPERVISOR_shared_info;
  897. struct vcpu_info *vcpu_info = __this_cpu_read(xen_vcpu);
  898. unsigned count;
  899. do {
  900. unsigned long pending_words;
  901. vcpu_info->evtchn_upcall_pending = 0;
  902. if (__this_cpu_inc_return(xed_nesting_count) - 1)
  903. goto out;
  904. #ifndef CONFIG_X86 /* No need for a barrier -- XCHG is a barrier on x86. */
  905. /* Clear master flag /before/ clearing selector flag. */
  906. wmb();
  907. #endif
  908. pending_words = xchg(&vcpu_info->evtchn_pending_sel, 0);
  909. start_word_idx = __this_cpu_read(current_word_idx);
  910. start_bit_idx = __this_cpu_read(current_bit_idx);
  911. word_idx = start_word_idx;
  912. for (i = 0; pending_words != 0; i++) {
  913. unsigned long pending_bits;
  914. unsigned long words;
  915. words = MASK_LSBS(pending_words, word_idx);
  916. /*
  917. * If we masked out all events, wrap to beginning.
  918. */
  919. if (words == 0) {
  920. word_idx = 0;
  921. bit_idx = 0;
  922. continue;
  923. }
  924. word_idx = __ffs(words);
  925. pending_bits = active_evtchns(cpu, s, word_idx);
  926. bit_idx = 0; /* usually scan entire word from start */
  927. if (word_idx == start_word_idx) {
  928. /* We scan the starting word in two parts */
  929. if (i == 0)
  930. /* 1st time: start in the middle */
  931. bit_idx = start_bit_idx;
  932. else
  933. /* 2nd time: mask bits done already */
  934. bit_idx &= (1UL << start_bit_idx) - 1;
  935. }
  936. do {
  937. unsigned long bits;
  938. int port, irq;
  939. struct irq_desc *desc;
  940. bits = MASK_LSBS(pending_bits, bit_idx);
  941. /* If we masked out all events, move on. */
  942. if (bits == 0)
  943. break;
  944. bit_idx = __ffs(bits);
  945. /* Process port. */
  946. port = (word_idx * BITS_PER_LONG) + bit_idx;
  947. irq = evtchn_to_irq[port];
  948. mask_evtchn(port);
  949. clear_evtchn(port);
  950. if (irq != -1) {
  951. desc = irq_to_desc(irq);
  952. if (desc)
  953. generic_handle_irq_desc(irq, desc);
  954. }
  955. bit_idx = (bit_idx + 1) % BITS_PER_LONG;
  956. /* Next caller starts at last processed + 1 */
  957. __this_cpu_write(current_word_idx,
  958. bit_idx ? word_idx :
  959. (word_idx+1) % BITS_PER_LONG);
  960. __this_cpu_write(current_bit_idx, bit_idx);
  961. } while (bit_idx != 0);
  962. /* Scan start_l1i twice; all others once. */
  963. if ((word_idx != start_word_idx) || (i != 0))
  964. pending_words &= ~(1UL << word_idx);
  965. word_idx = (word_idx + 1) % BITS_PER_LONG;
  966. }
  967. BUG_ON(!irqs_disabled());
  968. count = __this_cpu_read(xed_nesting_count);
  969. __this_cpu_write(xed_nesting_count, 0);
  970. } while (count != 1 || vcpu_info->evtchn_upcall_pending);
  971. out:
  972. put_cpu();
  973. }
  974. void xen_evtchn_do_upcall(struct pt_regs *regs)
  975. {
  976. struct pt_regs *old_regs = set_irq_regs(regs);
  977. exit_idle();
  978. irq_enter();
  979. __xen_evtchn_do_upcall();
  980. irq_exit();
  981. set_irq_regs(old_regs);
  982. }
  983. void xen_hvm_evtchn_do_upcall(void)
  984. {
  985. __xen_evtchn_do_upcall();
  986. }
  987. EXPORT_SYMBOL_GPL(xen_hvm_evtchn_do_upcall);
  988. /* Rebind a new event channel to an existing irq. */
  989. void rebind_evtchn_irq(int evtchn, int irq)
  990. {
  991. struct irq_info *info = info_for_irq(irq);
  992. /* Make sure the irq is masked, since the new event channel
  993. will also be masked. */
  994. disable_irq(irq);
  995. spin_lock(&irq_mapping_update_lock);
  996. /* After resume the irq<->evtchn mappings are all cleared out */
  997. BUG_ON(evtchn_to_irq[evtchn] != -1);
  998. /* Expect irq to have been bound before,
  999. so there should be a proper type */
  1000. BUG_ON(info->type == IRQT_UNBOUND);
  1001. xen_irq_info_evtchn_init(irq, evtchn);
  1002. spin_unlock(&irq_mapping_update_lock);
  1003. /* new event channels are always bound to cpu 0 */
  1004. irq_set_affinity(irq, cpumask_of(0));
  1005. /* Unmask the event channel. */
  1006. enable_irq(irq);
  1007. }
  1008. /* Rebind an evtchn so that it gets delivered to a specific cpu */
  1009. static int rebind_irq_to_cpu(unsigned irq, unsigned tcpu)
  1010. {
  1011. struct evtchn_bind_vcpu bind_vcpu;
  1012. int evtchn = evtchn_from_irq(irq);
  1013. if (!VALID_EVTCHN(evtchn))
  1014. return -1;
  1015. /*
  1016. * Events delivered via platform PCI interrupts are always
  1017. * routed to vcpu 0 and hence cannot be rebound.
  1018. */
  1019. if (xen_hvm_domain() && !xen_have_vector_callback)
  1020. return -1;
  1021. /* Send future instances of this interrupt to other vcpu. */
  1022. bind_vcpu.port = evtchn;
  1023. bind_vcpu.vcpu = tcpu;
  1024. /*
  1025. * If this fails, it usually just indicates that we're dealing with a
  1026. * virq or IPI channel, which don't actually need to be rebound. Ignore
  1027. * it, but don't do the xenlinux-level rebind in that case.
  1028. */
  1029. if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_vcpu, &bind_vcpu) >= 0)
  1030. bind_evtchn_to_cpu(evtchn, tcpu);
  1031. return 0;
  1032. }
  1033. static int set_affinity_irq(struct irq_data *data, const struct cpumask *dest,
  1034. bool force)
  1035. {
  1036. unsigned tcpu = cpumask_first(dest);
  1037. return rebind_irq_to_cpu(data->irq, tcpu);
  1038. }
  1039. int resend_irq_on_evtchn(unsigned int irq)
  1040. {
  1041. int masked, evtchn = evtchn_from_irq(irq);
  1042. struct shared_info *s = HYPERVISOR_shared_info;
  1043. if (!VALID_EVTCHN(evtchn))
  1044. return 1;
  1045. masked = sync_test_and_set_bit(evtchn, s->evtchn_mask);
  1046. sync_set_bit(evtchn, s->evtchn_pending);
  1047. if (!masked)
  1048. unmask_evtchn(evtchn);
  1049. return 1;
  1050. }
  1051. static void enable_dynirq(struct irq_data *data)
  1052. {
  1053. int evtchn = evtchn_from_irq(data->irq);
  1054. if (VALID_EVTCHN(evtchn))
  1055. unmask_evtchn(evtchn);
  1056. }
  1057. static void disable_dynirq(struct irq_data *data)
  1058. {
  1059. int evtchn = evtchn_from_irq(data->irq);
  1060. if (VALID_EVTCHN(evtchn))
  1061. mask_evtchn(evtchn);
  1062. }
  1063. static void ack_dynirq(struct irq_data *data)
  1064. {
  1065. int evtchn = evtchn_from_irq(data->irq);
  1066. irq_move_masked_irq(data);
  1067. if (VALID_EVTCHN(evtchn))
  1068. unmask_evtchn(evtchn);
  1069. }
  1070. static int retrigger_dynirq(struct irq_data *data)
  1071. {
  1072. int evtchn = evtchn_from_irq(data->irq);
  1073. struct shared_info *sh = HYPERVISOR_shared_info;
  1074. int ret = 0;
  1075. if (VALID_EVTCHN(evtchn)) {
  1076. int masked;
  1077. masked = sync_test_and_set_bit(evtchn, sh->evtchn_mask);
  1078. sync_set_bit(evtchn, sh->evtchn_pending);
  1079. if (!masked)
  1080. unmask_evtchn(evtchn);
  1081. ret = 1;
  1082. }
  1083. return ret;
  1084. }
  1085. static void restore_pirqs(void)
  1086. {
  1087. int pirq, rc, irq, gsi;
  1088. struct physdev_map_pirq map_irq;
  1089. struct irq_info *info;
  1090. list_for_each_entry(info, &xen_irq_list_head, list) {
  1091. if (info->type != IRQT_PIRQ)
  1092. continue;
  1093. pirq = info->u.pirq.pirq;
  1094. gsi = info->u.pirq.gsi;
  1095. irq = info->irq;
  1096. /* save/restore of PT devices doesn't work, so at this point the
  1097. * only devices present are GSI based emulated devices */
  1098. if (!gsi)
  1099. continue;
  1100. map_irq.domid = DOMID_SELF;
  1101. map_irq.type = MAP_PIRQ_TYPE_GSI;
  1102. map_irq.index = gsi;
  1103. map_irq.pirq = pirq;
  1104. rc = HYPERVISOR_physdev_op(PHYSDEVOP_map_pirq, &map_irq);
  1105. if (rc) {
  1106. printk(KERN_WARNING "xen map irq failed gsi=%d irq=%d pirq=%d rc=%d\n",
  1107. gsi, irq, pirq, rc);
  1108. xen_free_irq(irq);
  1109. continue;
  1110. }
  1111. printk(KERN_DEBUG "xen: --> irq=%d, pirq=%d\n", irq, map_irq.pirq);
  1112. __startup_pirq(irq);
  1113. }
  1114. }
  1115. static void restore_cpu_virqs(unsigned int cpu)
  1116. {
  1117. struct evtchn_bind_virq bind_virq;
  1118. int virq, irq, evtchn;
  1119. for (virq = 0; virq < NR_VIRQS; virq++) {
  1120. if ((irq = per_cpu(virq_to_irq, cpu)[virq]) == -1)
  1121. continue;
  1122. BUG_ON(virq_from_irq(irq) != virq);
  1123. /* Get a new binding from Xen. */
  1124. bind_virq.virq = virq;
  1125. bind_virq.vcpu = cpu;
  1126. if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq,
  1127. &bind_virq) != 0)
  1128. BUG();
  1129. evtchn = bind_virq.port;
  1130. /* Record the new mapping. */
  1131. xen_irq_info_virq_init(cpu, irq, evtchn, virq);
  1132. bind_evtchn_to_cpu(evtchn, cpu);
  1133. }
  1134. }
  1135. static void restore_cpu_ipis(unsigned int cpu)
  1136. {
  1137. struct evtchn_bind_ipi bind_ipi;
  1138. int ipi, irq, evtchn;
  1139. for (ipi = 0; ipi < XEN_NR_IPIS; ipi++) {
  1140. if ((irq = per_cpu(ipi_to_irq, cpu)[ipi]) == -1)
  1141. continue;
  1142. BUG_ON(ipi_from_irq(irq) != ipi);
  1143. /* Get a new binding from Xen. */
  1144. bind_ipi.vcpu = cpu;
  1145. if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi,
  1146. &bind_ipi) != 0)
  1147. BUG();
  1148. evtchn = bind_ipi.port;
  1149. /* Record the new mapping. */
  1150. xen_irq_info_ipi_init(cpu, irq, evtchn, ipi);
  1151. bind_evtchn_to_cpu(evtchn, cpu);
  1152. }
  1153. }
  1154. /* Clear an irq's pending state, in preparation for polling on it */
  1155. void xen_clear_irq_pending(int irq)
  1156. {
  1157. int evtchn = evtchn_from_irq(irq);
  1158. if (VALID_EVTCHN(evtchn))
  1159. clear_evtchn(evtchn);
  1160. }
  1161. EXPORT_SYMBOL(xen_clear_irq_pending);
  1162. void xen_set_irq_pending(int irq)
  1163. {
  1164. int evtchn = evtchn_from_irq(irq);
  1165. if (VALID_EVTCHN(evtchn))
  1166. set_evtchn(evtchn);
  1167. }
  1168. bool xen_test_irq_pending(int irq)
  1169. {
  1170. int evtchn = evtchn_from_irq(irq);
  1171. bool ret = false;
  1172. if (VALID_EVTCHN(evtchn))
  1173. ret = test_evtchn(evtchn);
  1174. return ret;
  1175. }
  1176. /* Poll waiting for an irq to become pending with timeout. In the usual case,
  1177. * the irq will be disabled so it won't deliver an interrupt. */
  1178. void xen_poll_irq_timeout(int irq, u64 timeout)
  1179. {
  1180. evtchn_port_t evtchn = evtchn_from_irq(irq);
  1181. if (VALID_EVTCHN(evtchn)) {
  1182. struct sched_poll poll;
  1183. poll.nr_ports = 1;
  1184. poll.timeout = timeout;
  1185. set_xen_guest_handle(poll.ports, &evtchn);
  1186. if (HYPERVISOR_sched_op(SCHEDOP_poll, &poll) != 0)
  1187. BUG();
  1188. }
  1189. }
  1190. EXPORT_SYMBOL(xen_poll_irq_timeout);
  1191. /* Poll waiting for an irq to become pending. In the usual case, the
  1192. * irq will be disabled so it won't deliver an interrupt. */
  1193. void xen_poll_irq(int irq)
  1194. {
  1195. xen_poll_irq_timeout(irq, 0 /* no timeout */);
  1196. }
  1197. /* Check whether the IRQ line is shared with other guests. */
  1198. int xen_test_irq_shared(int irq)
  1199. {
  1200. struct irq_info *info = info_for_irq(irq);
  1201. struct physdev_irq_status_query irq_status = { .irq = info->u.pirq.pirq };
  1202. if (HYPERVISOR_physdev_op(PHYSDEVOP_irq_status_query, &irq_status))
  1203. return 0;
  1204. return !(irq_status.flags & XENIRQSTAT_shared);
  1205. }
  1206. EXPORT_SYMBOL_GPL(xen_test_irq_shared);
  1207. void xen_irq_resume(void)
  1208. {
  1209. unsigned int cpu, evtchn;
  1210. struct irq_info *info;
  1211. init_evtchn_cpu_bindings();
  1212. /* New event-channel space is not 'live' yet. */
  1213. for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++)
  1214. mask_evtchn(evtchn);
  1215. /* No IRQ <-> event-channel mappings. */
  1216. list_for_each_entry(info, &xen_irq_list_head, list)
  1217. info->evtchn = 0; /* zap event-channel binding */
  1218. for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++)
  1219. evtchn_to_irq[evtchn] = -1;
  1220. for_each_possible_cpu(cpu) {
  1221. restore_cpu_virqs(cpu);
  1222. restore_cpu_ipis(cpu);
  1223. }
  1224. restore_pirqs();
  1225. }
  1226. static struct irq_chip xen_dynamic_chip __read_mostly = {
  1227. .name = "xen-dyn",
  1228. .irq_disable = disable_dynirq,
  1229. .irq_mask = disable_dynirq,
  1230. .irq_unmask = enable_dynirq,
  1231. .irq_eoi = ack_dynirq,
  1232. .irq_set_affinity = set_affinity_irq,
  1233. .irq_retrigger = retrigger_dynirq,
  1234. };
  1235. static struct irq_chip xen_pirq_chip __read_mostly = {
  1236. .name = "xen-pirq",
  1237. .irq_startup = startup_pirq,
  1238. .irq_shutdown = shutdown_pirq,
  1239. .irq_enable = enable_pirq,
  1240. .irq_unmask = enable_pirq,
  1241. .irq_disable = disable_pirq,
  1242. .irq_mask = disable_pirq,
  1243. .irq_ack = ack_pirq,
  1244. .irq_set_affinity = set_affinity_irq,
  1245. .irq_retrigger = retrigger_dynirq,
  1246. };
  1247. static struct irq_chip xen_percpu_chip __read_mostly = {
  1248. .name = "xen-percpu",
  1249. .irq_disable = disable_dynirq,
  1250. .irq_mask = disable_dynirq,
  1251. .irq_unmask = enable_dynirq,
  1252. .irq_ack = ack_dynirq,
  1253. };
  1254. int xen_set_callback_via(uint64_t via)
  1255. {
  1256. struct xen_hvm_param a;
  1257. a.domid = DOMID_SELF;
  1258. a.index = HVM_PARAM_CALLBACK_IRQ;
  1259. a.value = via;
  1260. return HYPERVISOR_hvm_op(HVMOP_set_param, &a);
  1261. }
  1262. EXPORT_SYMBOL_GPL(xen_set_callback_via);
  1263. #ifdef CONFIG_XEN_PVHVM
  1264. /* Vector callbacks are better than PCI interrupts to receive event
  1265. * channel notifications because we can receive vector callbacks on any
  1266. * vcpu and we don't need PCI support or APIC interactions. */
  1267. void xen_callback_vector(void)
  1268. {
  1269. int rc;
  1270. uint64_t callback_via;
  1271. if (xen_have_vector_callback) {
  1272. callback_via = HVM_CALLBACK_VECTOR(XEN_HVM_EVTCHN_CALLBACK);
  1273. rc = xen_set_callback_via(callback_via);
  1274. if (rc) {
  1275. printk(KERN_ERR "Request for Xen HVM callback vector"
  1276. " failed.\n");
  1277. xen_have_vector_callback = 0;
  1278. return;
  1279. }
  1280. printk(KERN_INFO "Xen HVM callback vector for event delivery is "
  1281. "enabled\n");
  1282. /* in the restore case the vector has already been allocated */
  1283. if (!test_bit(XEN_HVM_EVTCHN_CALLBACK, used_vectors))
  1284. alloc_intr_gate(XEN_HVM_EVTCHN_CALLBACK, xen_hvm_callback_vector);
  1285. }
  1286. }
  1287. #else
  1288. void xen_callback_vector(void) {}
  1289. #endif
  1290. void __init xen_init_IRQ(void)
  1291. {
  1292. int i;
  1293. evtchn_to_irq = kcalloc(NR_EVENT_CHANNELS, sizeof(*evtchn_to_irq),
  1294. GFP_KERNEL);
  1295. for (i = 0; i < NR_EVENT_CHANNELS; i++)
  1296. evtchn_to_irq[i] = -1;
  1297. init_evtchn_cpu_bindings();
  1298. /* No event channels are 'live' right now. */
  1299. for (i = 0; i < NR_EVENT_CHANNELS; i++)
  1300. mask_evtchn(i);
  1301. if (xen_hvm_domain()) {
  1302. xen_callback_vector();
  1303. native_init_IRQ();
  1304. /* pci_xen_hvm_init must be called after native_init_IRQ so that
  1305. * __acpi_register_gsi can point at the right function */
  1306. pci_xen_hvm_init();
  1307. } else {
  1308. irq_ctx_init(smp_processor_id());
  1309. if (xen_initial_domain())
  1310. xen_setup_pirqs();
  1311. }
  1312. }